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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   Copyright (C) 2009 David Brownell                                     *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "etm.h"
  30 #include "breakpoints.h"
  31 #include "arm11_dbgtap.h"
  32 #include "arm_simulator.h"
  33 #include <helper/time_support.h>
  34 #include "target_type.h"
  35 #include "algorithm.h"
  36 #include "register.h"
  37 #include "arm_opcodes.h"
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43
  44 static int arm11_step(struct target *target, int current,
  45                 target_addr_t address, int handle_breakpoints);
  46
  47
  48 /** Check and if necessary take control of the system
  49  *
  50  * \param arm11         Target state variable.
  51  */
  52 static int arm11_check_init(struct arm11_common *arm11)
  53 {
  54         CHECK_RETVAL(arm11_read_dscr(arm11));
  55
  56         if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) {
  57                 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
  58                 LOG_DEBUG("Bringing target into debug mode");
  59
  60                 arm11->dscr |= DSCR_HALT_DBG_MODE;
  61                 CHECK_RETVAL(arm11_write_dscr(arm11, arm11->dscr));
  62
  63                 /* add further reset initialization here */
  64
  65                 arm11->simulate_reset_on_next_halt = true;
  66
  67                 if (arm11->dscr & DSCR_CORE_HALTED) {
  68                         /** \todo TODO: this needs further scrutiny because
  69                           * arm11_debug_entry() never gets called.  (WHY NOT?)
  70                           * As a result we don't read the actual register states from
  71                           * the target.
  72                           */
  73
  74                         arm11->arm.target->state = TARGET_HALTED;
  75                         arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
  76                 } else {
  77                         arm11->arm.target->state = TARGET_RUNNING;
  78                         arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
  79                 }
  80
  81                 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
  82         }
  83
  84         return ERROR_OK;
  85 }
  86
  87 /**
  88  * Save processor state.  This is called after a HALT instruction
  89  * succeeds, and on other occasions the processor enters debug mode
  90  * (breakpoint, watchpoint, etc).  Caller has updated arm11->dscr.
  91  */
  92 static int arm11_debug_entry(struct arm11_common *arm11)
  93 {
  94         int retval;
  95
  96         arm11->arm.target->state = TARGET_HALTED;
  97         arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
  98
  99         /* REVISIT entire cache should already be invalid !!! */
 100         register_cache_invalidate(arm11->arm.core_cache);
 101
 102         /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
 103
 104         /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
 105         arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
 106         if (arm11->is_wdtr_saved) {
 107                 arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT);
 108
 109                 arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 110
 111                 struct scan_field chain5_fields[3];
 112
 113                 arm11_setup_field(arm11, 32, NULL,
 114                         &arm11->saved_wdtr, chain5_fields + 0);
 115                 arm11_setup_field(arm11,  1, NULL, NULL, chain5_fields + 1);
 116                 arm11_setup_field(arm11,  1, NULL, NULL, chain5_fields + 2);
 117
 118                 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
 119                                 chain5_fields), chain5_fields, TAP_DRPAUSE);
 120
 121         }
 122
 123         /* DSCR: set the Execute ARM instruction enable bit.
 124          *
 125          * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
 126          * but not to issue ITRs(?).  The ARMv7 arch spec says it's required
 127          * for executing instructions via ITR.
 128          */
 129         CHECK_RETVAL(arm11_write_dscr(arm11, DSCR_ITR_EN | arm11->dscr));
 130
 131
 132         /* From the spec:
 133            Before executing any instruction in debug state you have to drain the write buffer.
 134            This ensures that no imprecise Data Aborts can return at a later point:*/
 135
 136         /** \todo TODO: Test drain write buffer. */
 137
 138 #if 0
 139         while (1) {
 140                 /* MRC p14,0,R0,c5,c10,0 */
 141                 /*      arm11_run_instr_no_data1(arm11, / *0xee150e1a* /0xe320f000); */
 142
 143                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 144                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 145
 146                 uint32_t dscr = arm11_read_dscr(arm11);
 147
 148                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 149
 150                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) {
 151                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 152
 153                         dscr = arm11_read_dscr(arm11);
 154
 155                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 156
 157                         break;
 158                 }
 159         }
 160 #endif
 161
 162         /* Save registers.
 163          *
 164          * NOTE:  ARM1136 TRM suggests saving just R0 here now, then
 165          * CPSR and PC after the rDTR stuff.  We do it all at once.
 166          */
 167         retval = arm_dpm_read_current_registers(&arm11->dpm);
 168         if (retval != ERROR_OK)
 169                 LOG_ERROR("DPM REG READ -- fail");
 170
 171         retval = arm11_run_instr_data_prepare(arm11);
 172         if (retval != ERROR_OK)
 173                 return retval;
 174
 175         /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
 176         arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
 177         if (arm11->is_rdtr_saved) {
 178                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 179                 retval = arm11_run_instr_data_from_core_via_r0(arm11,
 180                                 0xEE100E15, &arm11->saved_rdtr);
 181                 if (retval != ERROR_OK)
 182                         return retval;
 183         }
 184
 185         /* REVISIT Now that we've saved core state, there's may also
 186          * be MMU and cache state to care about ...
 187          */
 188
 189         if (arm11->simulate_reset_on_next_halt) {
 190                 arm11->simulate_reset_on_next_halt = false;
 191
 192                 LOG_DEBUG("Reset c1 Control Register");
 193
 194                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 195
 196                 /* MCR p15,0,R0,c1,c0,0 */
 197                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 198                 if (retval != ERROR_OK)
 199                         return retval;
 200
 201         }
 202
 203         if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
 204                 uint32_t wfar;
 205
 206                 /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
 207                 retval = arm11_run_instr_data_from_core_via_r0(arm11,
 208                                 ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
 209                                 &wfar);
 210                 if (retval != ERROR_OK)
 211                         return retval;
 212                 arm_dpm_report_wfar(arm11->arm.dpm, wfar);
 213         }
 214
 215
 216         retval = arm11_run_instr_data_finish(arm11);
 217         if (retval != ERROR_OK)
 218                 return retval;
 219
 220         return ERROR_OK;
 221 }
 222
 223 /**
 224  * Restore processor state.  This is called in preparation for
 225  * the RESTART function.
 226  */
 227 static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 228 {
 229         int retval;
 230
 231         /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
 232
 233         /* NOTE:  the ARM1136 TRM suggests restoring all registers
 234          * except R0/PC/CPSR right now.  Instead, we do them all
 235          * at once, just a bit later on.
 236          */
 237
 238         /* REVISIT once we start caring about MMU and cache state,
 239          * address it here ...
 240          */
 241
 242         /* spec says clear wDTR and rDTR; we assume they are clear as
 243            otherwise our programming would be sloppy */
 244         {
 245                 CHECK_RETVAL(arm11_read_dscr(arm11));
 246
 247                 if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) {
 248                         /*
 249                         The wDTR/rDTR two registers that are used to send/receive data to/from
 250                         the core in tandem with corresponding instruction codes that are
 251                         written into the core. The RDTR FULL/WDTR FULL flag indicates that the
 252                         registers hold data that was written by one side (CPU or JTAG) and not
 253                         read out by the other side.
 254                         */
 255                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
 256                                 (unsigned) arm11->dscr);
 257                         return ERROR_FAIL;
 258                 }
 259         }
 260
 261         /* maybe restore original wDTR */
 262         if (arm11->is_wdtr_saved) {
 263                 retval = arm11_run_instr_data_prepare(arm11);
 264                 if (retval != ERROR_OK)
 265                         return retval;
 266
 267                 /* MCR p14,0,R0,c0,c5,0 */
 268                 retval = arm11_run_instr_data_to_core_via_r0(arm11,
 269                                 0xee000e15, arm11->saved_wdtr);
 270                 if (retval != ERROR_OK)
 271                         return retval;
 272
 273                 retval = arm11_run_instr_data_finish(arm11);
 274                 if (retval != ERROR_OK)
 275                         return retval;
 276         }
 277
 278         /* restore CPSR, PC, and R0 ... after flushing any modified
 279          * registers.
 280          */
 281         CHECK_RETVAL(arm_dpm_write_dirty_registers(&arm11->dpm, bpwp));
 282
 283         CHECK_RETVAL(arm11_bpwp_flush(arm11));
 284
 285         register_cache_invalidate(arm11->arm.core_cache);
 286
 287         /* restore DSCR */
 288         CHECK_RETVAL(arm11_write_dscr(arm11, arm11->dscr));
 289
 290         /* maybe restore rDTR */
 291         if (arm11->is_rdtr_saved) {
 292                 arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT);
 293
 294                 arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 295
 296                 struct scan_field chain5_fields[3];
 297
 298                 uint8_t ready           = 0;                    /* ignored */
 299                 uint8_t valid           = 0;                    /* ignored */
 300
 301                 arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
 302                         NULL, chain5_fields + 0);
 303                 arm11_setup_field(arm11,  1, &ready,    NULL, chain5_fields + 1);
 304                 arm11_setup_field(arm11,  1, &valid,    NULL, chain5_fields + 2);
 305
 306                 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
 307                                 chain5_fields), chain5_fields, TAP_DRPAUSE);
 308         }
 309
 310         /* now processor is ready to RESTART */
 311
 312         return ERROR_OK;
 313 }
 314
 315 /* poll current target status */
 316 static int arm11_poll(struct target *target)
 317 {
 318         int retval;
 319         struct arm11_common *arm11 = target_to_arm11(target);
 320
 321         CHECK_RETVAL(arm11_check_init(arm11));
 322
 323         if (arm11->dscr & DSCR_CORE_HALTED) {
 324                 if (target->state != TARGET_HALTED) {
 325                         enum target_state old_state = target->state;
 326
 327                         LOG_DEBUG("enter TARGET_HALTED");
 328                         retval = arm11_debug_entry(arm11);
 329                         if (retval != ERROR_OK)
 330                                 return retval;
 331
 332                         target_call_event_callbacks(target,
 333                                 (old_state == TARGET_DEBUG_RUNNING)
 334                                 ? TARGET_EVENT_DEBUG_HALTED
 335                                 : TARGET_EVENT_HALTED);
 336                 }
 337         } else {
 338                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) {
 339                         LOG_DEBUG("enter TARGET_RUNNING");
 340                         target->state                   = TARGET_RUNNING;
 341                         target->debug_reason    = DBG_REASON_NOTHALTED;
 342                 }
 343         }
 344
 345         return ERROR_OK;
 346 }
 347 /* architecture specific status reply */
 348 static int arm11_arch_state(struct target *target)
 349 {
 350         struct arm11_common *arm11 = target_to_arm11(target);
 351         int retval;
 352
 353         retval = arm_arch_state(target);
 354
 355         /* REVISIT also display ARM11-specific MMU and cache status ... */
 356
 357         if (target->debug_reason == DBG_REASON_WATCHPOINT)
 358                 LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, arm11->dpm.wp_addr);
 359
 360         return retval;
 361 }
 362
 363 /* target execution control */
 364 static int arm11_halt(struct target *target)
 365 {
 366         struct arm11_common *arm11 = target_to_arm11(target);
 367
 368         LOG_DEBUG("target->state: %s",
 369                 target_state_name(target));
 370
 371         if (target->state == TARGET_UNKNOWN)
 372                 arm11->simulate_reset_on_next_halt = true;
 373
 374         if (target->state == TARGET_HALTED) {
 375                 LOG_DEBUG("target was already halted");
 376                 return ERROR_OK;
 377         }
 378
 379         arm11_add_ir(arm11, ARM11_HALT, TAP_IDLE);
 380
 381         CHECK_RETVAL(jtag_execute_queue());
 382
 383         int i = 0;
 384
 385         while (1) {
 386                 CHECK_RETVAL(arm11_read_dscr(arm11));
 387
 388                 if (arm11->dscr & DSCR_CORE_HALTED)
 389                         break;
 390
 391
 392                 int64_t then = 0;
 393                 if (i == 1000)
 394                         then = timeval_ms();
 395                 if (i >= 1000) {
 396                         if ((timeval_ms()-then) > 1000) {
 397                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 398                                 return ERROR_FAIL;
 399                         }
 400                 }
 401                 i++;
 402         }
 403
 404         enum target_state old_state     = target->state;
 405
 406         CHECK_RETVAL(arm11_debug_entry(arm11));
 407
 408         CHECK_RETVAL(
 409                 target_call_event_callbacks(target,
 410                         old_state ==
 411                         TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 412
 413         return ERROR_OK;
 414 }
 415
 416 static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
 417 {
 418         void *value = arm11->arm.pc->value;
 419
 420         /* use the current program counter */
 421         if (current)
 422                 address = buf_get_u32(value, 0, 32);
 423
 424         /* Make sure that the gdb thumb fixup does not
 425          * kill the return address
 426          */
 427         switch (arm11->arm.core_state) {
 428                 case ARM_STATE_ARM:
 429                         address &= 0xFFFFFFFC;
 430                         break;
 431                 case ARM_STATE_THUMB:
 432                         /* When the return address is loaded into PC
 433                          * bit 0 must be 1 to stay in Thumb state
 434                          */
 435                         address |= 0x1;
 436                         break;
 437
 438                 /* catch-all for JAZELLE and THUMB_EE */
 439                 default:
 440                         break;
 441         }
 442
 443         buf_set_u32(value, 0, 32, address);
 444         arm11->arm.pc->dirty = true;
 445         arm11->arm.pc->valid = true;
 446
 447         return address;
 448 }
 449
 450 static int arm11_resume(struct target *target, int current,
 451         target_addr_t address, int handle_breakpoints, int debug_execution)
 452 {
 453         /*        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d", */
 454         /*      current, address, handle_breakpoints, debug_execution); */
 455
 456         struct arm11_common *arm11 = target_to_arm11(target);
 457
 458         LOG_DEBUG("target->state: %s",
 459                 target_state_name(target));
 460
 461
 462         if (target->state != TARGET_HALTED) {
 463                 LOG_ERROR("Target not halted");
 464                 return ERROR_TARGET_NOT_HALTED;
 465         }
 466
 467         address = arm11_nextpc(arm11, current, address);
 468
 469         LOG_DEBUG("RESUME PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
 470
 471         /* clear breakpoints/watchpoints and VCR*/
 472         CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
 473
 474         if (!debug_execution)
 475                 target_free_all_working_areas(target);
 476
 477         /* Should we skip over breakpoints matching the PC? */
 478         if (handle_breakpoints) {
 479                 struct breakpoint *bp;
 480
 481                 for (bp = target->breakpoints; bp; bp = bp->next) {
 482                         if (bp->address == address) {
 483                                 LOG_DEBUG("must step over %08" TARGET_PRIxADDR "", bp->address);
 484                                 arm11_step(target, 1, 0, 0);
 485                                 break;
 486                         }
 487                 }
 488         }
 489
 490         /* activate all breakpoints */
 491         if (true) {
 492                 struct breakpoint *bp;
 493                 unsigned brp_num = 0;
 494
 495                 for (bp = target->breakpoints; bp; bp = bp->next) {
 496                         struct arm11_sc7_action brp[2];
 497
 498                         brp[0].write    = 1;
 499                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 500                         brp[0].value    = bp->address;
 501                         brp[1].write    = 1;
 502                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 503                         brp[1].value    = 0x1 |
 504                                 (3 <<
 505                                  1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 506
 507                         CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
 508
 509                         LOG_DEBUG("Add BP %d at %08" TARGET_PRIxADDR, brp_num,
 510                                 bp->address);
 511
 512                         brp_num++;
 513                 }
 514
 515                 if (arm11->vcr)
 516                         CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
 517         }
 518
 519         /* activate all watchpoints and breakpoints */
 520         CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
 521
 522         arm11_add_ir(arm11, ARM11_RESTART, TAP_IDLE);
 523
 524         CHECK_RETVAL(jtag_execute_queue());
 525
 526         int i = 0;
 527         while (1) {
 528                 CHECK_RETVAL(arm11_read_dscr(arm11));
 529
 530                 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
 531
 532                 if (arm11->dscr & DSCR_CORE_RESTARTED)
 533                         break;
 534
 535
 536                 int64_t then = 0;
 537                 if (i == 1000)
 538                         then = timeval_ms();
 539                 if (i >= 1000) {
 540                         if ((timeval_ms()-then) > 1000) {
 541                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 542                                 return ERROR_FAIL;
 543                         }
 544                 }
 545                 i++;
 546         }
 547
 548         target->debug_reason = DBG_REASON_NOTHALTED;
 549         if (!debug_execution)
 550                 target->state = TARGET_RUNNING;
 551         else
 552                 target->state = TARGET_DEBUG_RUNNING;
 553         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 554
 555         return ERROR_OK;
 556 }
 557
 558 static int arm11_step(struct target *target, int current,
 559         target_addr_t address, int handle_breakpoints)
 560 {
 561         LOG_DEBUG("target->state: %s",
 562                 target_state_name(target));
 563
 564         if (target->state != TARGET_HALTED) {
 565                 LOG_WARNING("target was not halted");
 566                 return ERROR_TARGET_NOT_HALTED;
 567         }
 568
 569         struct arm11_common *arm11 = target_to_arm11(target);
 570
 571         address = arm11_nextpc(arm11, current, address);
 572
 573         LOG_DEBUG("STEP PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
 574
 575
 576         /** \todo TODO: Thumb not supported here */
 577
 578         uint32_t next_instruction;
 579
 580         CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
 581
 582         /* skip over BKPT */
 583         if ((next_instruction & 0xFFF00070) == 0xe1200070) {
 584                 address = arm11_nextpc(arm11, 0, address + 4);
 585                 LOG_DEBUG("Skipping BKPT %08" TARGET_PRIxADDR, address);
 586         }
 587         /* skip over Wait for interrupt / Standby
 588          * mcr  15, 0, r?, cr7, cr0, {4} */
 589         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) {
 590                 address = arm11_nextpc(arm11, 0, address + 4);
 591                 LOG_DEBUG("Skipping WFI %08" TARGET_PRIxADDR, address);
 592         }
 593         /* ignore B to self */
 594         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
 595                 LOG_DEBUG("Not stepping jump to self");
 596         else {
 597                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
 598                 * with this. */
 599
 600                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
 601                 * the VCR might be something worth looking into. */
 602
 603
 604                 /* Set up breakpoint for stepping */
 605
 606                 struct arm11_sc7_action brp[2];
 607
 608                 brp[0].write    = 1;
 609                 brp[0].address  = ARM11_SC7_BVR0;
 610                 brp[1].write    = 1;
 611                 brp[1].address  = ARM11_SC7_BCR0;
 612
 613                 if (arm11->hardware_step) {
 614                         /* Hardware single stepping ("instruction address
 615                          * mismatch") is used if enabled.  It's not quite
 616                          * exactly "run one instruction"; "branch to here"
 617                          * loops won't break, neither will some other cases,
 618                          * but it's probably the best default.
 619                          *
 620                          * Hardware single stepping isn't supported on v6
 621                          * debug modules.  ARM1176 and v7 can support it...
 622                          *
 623                          * FIXME Thumb stepping likely needs to use 0x03
 624                          * or 0xc0 byte masks, not 0x0f.
 625                          */
 626                         brp[0].value   = address;
 627                         brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5)
 628                                 | (0 << 14) | (0 << 16) | (0 << 20)
 629                                 | (2 << 21);
 630                 } else {
 631                         /* Sets a breakpoint on the next PC, as calculated
 632                          * by instruction set simulation.
 633                          *
 634                          * REVISIT stepping Thumb on ARM1156 requires Thumb2
 635                          * support from the simulator.
 636                          */
 637                         uint32_t next_pc;
 638                         int retval;
 639
 640                         retval = arm_simulate_step(target, &next_pc);
 641                         if (retval != ERROR_OK)
 642                                 return retval;
 643
 644                         brp[0].value    = next_pc;
 645                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5)
 646                                 | (0 << 14) | (0 << 16) | (0 << 20)
 647                                 | (0 << 21);
 648                 }
 649
 650                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
 651
 652                 /* resume */
 653
 654
 655                 if (arm11->step_irq_enable)
 656                         /* this disable should be redundant ... */
 657                         arm11->dscr &= ~DSCR_INT_DIS;
 658                 else
 659                         arm11->dscr |= DSCR_INT_DIS;
 660
 661
 662                 CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
 663
 664                 arm11_add_ir(arm11, ARM11_RESTART, TAP_IDLE);
 665
 666                 CHECK_RETVAL(jtag_execute_queue());
 667
 668                 /* wait for halt */
 669                 int i = 0;
 670
 671                 while (1) {
 672                         const uint32_t mask = DSCR_CORE_RESTARTED
 673                                 | DSCR_CORE_HALTED;
 674
 675                         CHECK_RETVAL(arm11_read_dscr(arm11));
 676                         LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
 677
 678                         if ((arm11->dscr & mask) == mask)
 679                                 break;
 680
 681                         long long then = 0;
 682                         if (i == 1000)
 683                                 then = timeval_ms();
 684                         if (i >= 1000) {
 685                                 if ((timeval_ms()-then) > 1000) {
 686                                         LOG_WARNING(
 687                                                 "Timeout (1000ms) waiting for instructions to complete");
 688                                         return ERROR_FAIL;
 689                                 }
 690                         }
 691                         i++;
 692                 }
 693
 694                 /* clear breakpoint */
 695                 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
 696
 697                 /* save state */
 698                 CHECK_RETVAL(arm11_debug_entry(arm11));
 699
 700                 /* restore default state */
 701                 arm11->dscr &= ~DSCR_INT_DIS;
 702
 703         }
 704
 705         target->debug_reason = DBG_REASON_SINGLESTEP;
 706
 707         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 708
 709         return ERROR_OK;
 710 }
 711
 712 static int arm11_assert_reset(struct target *target)
 713 {
 714         struct arm11_common *arm11 = target_to_arm11(target);
 715
 716         if (!(target_was_examined(target))) {
 717                 if (jtag_get_reset_config() & RESET_HAS_SRST)
 718                         jtag_add_reset(0, 1);
 719                 else {
 720                         LOG_WARNING("Reset is not asserted because the target is not examined.");
 721                         LOG_WARNING("Use a reset button or power cycle the target.");
 722                         return ERROR_TARGET_NOT_EXAMINED;
 723                 }
 724         } else {
 725
 726                 /* optionally catch reset vector */
 727                 if (target->reset_halt && !(arm11->vcr & 1))
 728                         CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
 729
 730                 /* Issue some kind of warm reset. */
 731                 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
 732                         target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
 733                 else if (jtag_get_reset_config() & RESET_HAS_SRST) {
 734                         /* REVISIT handle "pulls" cases, if there's
 735                          * hardware that needs them to work.
 736                          */
 737                         jtag_add_reset(0, 1);
 738                 } else {
 739                         LOG_ERROR("%s: how to reset?", target_name(target));
 740                         return ERROR_FAIL;
 741                 }
 742         }
 743
 744         /* registers are now invalid */
 745         register_cache_invalidate(arm11->arm.core_cache);
 746
 747         target->state = TARGET_RESET;
 748
 749         return ERROR_OK;
 750 }
 751
 752 /*
 753  * - There is another bug in the arm11 core.  (iMX31 specific again?)
 754  *   When you generate an access to external logic (for example DDR
 755  *   controller via AHB bus) and that block is not configured (perhaps
 756  *   it is still held in reset), that transaction will never complete.
 757  *   This will hang arm11 core but it will also hang JTAG controller.
 758  *   Nothing short of srst assertion will bring it out of this.
 759  */
 760
 761 static int arm11_deassert_reset(struct target *target)
 762 {
 763         struct arm11_common *arm11 = target_to_arm11(target);
 764         int retval;
 765
 766         /* be certain SRST is off */
 767         jtag_add_reset(0, 0);
 768
 769         /* WORKAROUND i.MX31 problems:  SRST goofs the TAP, and resets
 770          * at least DSCR.  OMAP24xx doesn't show that problem, though
 771          * SRST-only reset seems to be problematic for other reasons.
 772          * (Secure boot sequences being one likelihood!)
 773          */
 774         jtag_add_tlr();
 775
 776         CHECK_RETVAL(arm11_poll(target));
 777
 778         if (target->reset_halt) {
 779                 if (target->state != TARGET_HALTED) {
 780                         LOG_WARNING("%s: ran after reset and before halt ...",
 781                                 target_name(target));
 782                         retval = target_halt(target);
 783                         if (retval != ERROR_OK)
 784                                 return retval;
 785                 }
 786         }
 787
 788         /* maybe restore vector catch config */
 789         if (target->reset_halt && !(arm11->vcr & 1))
 790                 CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
 791
 792         return ERROR_OK;
 793 }
 794
 795 /* target memory access
 796  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 797  * count: number of items of <size>
 798  *
 799  * arm11_config_memrw_no_increment - in the future we may want to be able
 800  * to read/write a range of data to a "port". a "port" is an action on
 801  * read memory address for some peripheral.
 802  */
 803 static int arm11_read_memory_inner(struct target *target,
 804         uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
 805         bool arm11_config_memrw_no_increment)
 806 {
 807         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment
 808          *problems */
 809         int retval;
 810
 811         if (target->state != TARGET_HALTED) {
 812                 LOG_WARNING("target was not halted");
 813                 return ERROR_TARGET_NOT_HALTED;
 814         }
 815
 816         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "",
 817                 address,
 818                 size,
 819                 count);
 820
 821         struct arm11_common *arm11 = target_to_arm11(target);
 822
 823         retval = arm11_run_instr_data_prepare(arm11);
 824         if (retval != ERROR_OK)
 825                 return retval;
 826
 827         /* MRC p14,0,r0,c0,c5,0 */
 828         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
 829         if (retval != ERROR_OK)
 830                 return retval;
 831
 832         switch (size) {
 833                 case 1:
 834                         arm11->arm.core_cache->reg_list[1].dirty = true;
 835
 836                         for (size_t i = 0; i < count; i++) {
 837                                 /* ldrb    r1, [r0], #1 */
 838                                 /* ldrb    r1, [r0] */
 839                                 CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
 840                                                 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
 841
 842                                 uint32_t res;
 843                                 /* MCR p14,0,R1,c0,c5,0 */
 844                                 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
 845
 846                                 *buffer++ = res;
 847                         }
 848
 849                         break;
 850
 851                 case 2:
 852                 {
 853                         arm11->arm.core_cache->reg_list[1].dirty = true;
 854
 855                         for (size_t i = 0; i < count; i++) {
 856                                 /* ldrh    r1, [r0], #2 */
 857                                 CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
 858                                                 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
 859
 860                                 uint32_t res;
 861
 862                                 /* MCR p14,0,R1,c0,c5,0 */
 863                                 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
 864
 865                                 uint16_t svalue = res;
 866                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
 867                         }
 868
 869                         break;
 870                 }
 871
 872                 case 4:
 873                 {
 874                         uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
 875                         /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
 876                         uint32_t *words = (uint32_t *)(void *)buffer;
 877
 878                         /* LDC p14,c5,[R0],#4 */
 879                         /* LDC p14,c5,[R0] */
 880                         CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
 881                         break;
 882                 }
 883         }
 884
 885         return arm11_run_instr_data_finish(arm11);
 886 }
 887
 888 static int arm11_read_memory(struct target *target,
 889         target_addr_t address,
 890         uint32_t size,
 891         uint32_t count,
 892         uint8_t *buffer)
 893 {
 894         return arm11_read_memory_inner(target, address, size, count, buffer, false);
 895 }
 896
 897 /*
 898 * no_increment - in the future we may want to be able
 899 * to read/write a range of data to a "port". a "port" is an action on
 900 * read memory address for some peripheral.
 901 */
 902 static int arm11_write_memory_inner(struct target *target,
 903         uint32_t address, uint32_t size,
 904         uint32_t count, const uint8_t *buffer,
 905         bool no_increment)
 906 {
 907         int retval;
 908
 909         if (target->state != TARGET_HALTED) {
 910                 LOG_WARNING("target was not halted");
 911                 return ERROR_TARGET_NOT_HALTED;
 912         }
 913
 914         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "",
 915                 address,
 916                 size,
 917                 count);
 918
 919         struct arm11_common *arm11 = target_to_arm11(target);
 920
 921         retval = arm11_run_instr_data_prepare(arm11);
 922         if (retval != ERROR_OK)
 923                 return retval;
 924
 925         /* load r0 with buffer address
 926          * MRC p14,0,r0,c0,c5,0 */
 927         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
 928         if (retval != ERROR_OK)
 929                 return retval;
 930
 931         /* burst writes are not used for single words as those may well be
 932          * reset init script writes.
 933          *
 934          * The other advantage is that as burst writes are default, we'll
 935          * now exercise both burst and non-burst code paths with the
 936          * default settings, increasing code coverage.
 937          */
 938         bool burst = arm11->memwrite_burst && (count > 1);
 939
 940         switch (size) {
 941                 case 1:
 942                 {
 943                         arm11->arm.core_cache->reg_list[1].dirty = true;
 944
 945                         for (size_t i = 0; i < count; i++) {
 946                                 /* load r1 from DCC with byte data */
 947                                 /* MRC p14,0,r1,c0,c5,0 */
 948                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
 949                                 if (retval != ERROR_OK)
 950                                         return retval;
 951
 952                                 /* write r1 to memory */
 953                                 /* strb    r1, [r0], #1 */
 954                                 /* strb    r1, [r0] */
 955                                 retval = arm11_run_instr_no_data1(arm11,
 956                                                 !no_increment ? 0xe4c01001 : 0xe5c01000);
 957                                 if (retval != ERROR_OK)
 958                                         return retval;
 959                         }
 960
 961                         break;
 962                 }
 963
 964                 case 2:
 965                 {
 966                         arm11->arm.core_cache->reg_list[1].dirty = true;
 967
 968                         for (size_t i = 0; i < count; i++) {
 969                                 uint16_t value;
 970                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
 971
 972                                 /* load r1 from DCC with halfword data */
 973                                 /* MRC p14,0,r1,c0,c5,0 */
 974                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
 975                                 if (retval != ERROR_OK)
 976                                         return retval;
 977
 978                                 /* write r1 to memory */
 979                                 /* strh    r1, [r0], #2 */
 980                                 /* strh    r1, [r0] */
 981                                 retval = arm11_run_instr_no_data1(arm11,
 982                                                 !no_increment ? 0xe0c010b2 : 0xe1c010b0);
 983                                 if (retval != ERROR_OK)
 984                                         return retval;
 985                         }
 986
 987                         break;
 988                 }
 989
 990                 case 4: {
 991                         /* stream word data through DCC directly to memory */
 992                         /* increment:           STC p14,c5,[R0],#4 */
 993                         /* no increment:        STC p14,c5,[R0]*/
 994                         uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
 995
 996                         /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
 997                         uint32_t *words = (uint32_t *)(void *)buffer;
 998
 999                         /* "burst" here just means trusting each instruction executes
1000                          * fully before we run the next one:  per-word roundtrips, to
1001                          * check the Ready flag, are not used.
1002                          */
1003                         if (!burst)
1004                                 retval = arm11_run_instr_data_to_core(arm11,
1005                                                 instr, words, count);
1006                         else
1007                                 retval = arm11_run_instr_data_to_core_noack(arm11,
1008                                                 instr, words, count);
1009                         if (retval != ERROR_OK)
1010                                 return retval;
1011
1012                         break;
1013                 }
1014         }
1015
1016         /* r0 verification */
1017         if (!no_increment) {
1018                 uint32_t r0;
1019
1020                 /* MCR p14,0,R0,c0,c5,0 */
1021                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1022                 if (retval != ERROR_OK)
1023                         return retval;
1024
1025                 if (address + size * count != r0) {
1026                         LOG_ERROR("Data transfer failed. Expected end "
1027                                 "address 0x%08x, got 0x%08x",
1028                                 (unsigned) (address + size * count),
1029                                 (unsigned) r0);
1030
1031                         if (burst)
1032                                 LOG_ERROR(
1033                                         "use 'arm11 memwrite burst disable' to disable fast burst mode");
1034
1035
1036                         if (arm11->memwrite_error_fatal)
1037                                 return ERROR_FAIL;
1038                 }
1039         }
1040
1041         return arm11_run_instr_data_finish(arm11);
1042 }
1043
1044 static int arm11_write_memory(struct target *target,
1045         target_addr_t address, uint32_t size,
1046         uint32_t count, const uint8_t *buffer)
1047 {
1048         /* pointer increment matters only for multi-unit writes ...
1049          * not e.g. to a "reset the chip" controller.
1050          */
1051         return arm11_write_memory_inner(target, address, size,
1052                 count, buffer, count == 1);
1053 }
1054
1055 /* target break-/watchpoint control
1056 * rw: 0 = write, 1 = read, 2 = access
1057 */
1058 static int arm11_add_breakpoint(struct target *target,
1059         struct breakpoint *breakpoint)
1060 {
1061         struct arm11_common *arm11 = target_to_arm11(target);
1062
1063 #if 0
1064         if (breakpoint->type == BKPT_SOFT) {
1065                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1066                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1067         }
1068 #endif
1069
1070         if (!arm11->free_brps) {
1071                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1072                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1073         }
1074
1075         if (breakpoint->length != 4) {
1076                 LOG_DEBUG("only breakpoints of four bytes length supported");
1077                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1078         }
1079
1080         arm11->free_brps--;
1081
1082         return ERROR_OK;
1083 }
1084
1085 static int arm11_remove_breakpoint(struct target *target,
1086         struct breakpoint *breakpoint)
1087 {
1088         struct arm11_common *arm11 = target_to_arm11(target);
1089
1090         arm11->free_brps++;
1091
1092         return ERROR_OK;
1093 }
1094
1095 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1096 {
1097         struct arm11_common *arm11;
1098
1099         if (!target->tap)
1100                 return ERROR_FAIL;
1101
1102         if (target->tap->ir_length != 5) {
1103                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1104                 return ERROR_COMMAND_SYNTAX_ERROR;
1105         }
1106
1107         arm11 = calloc(1, sizeof(*arm11));
1108         if (!arm11)
1109                 return ERROR_FAIL;
1110
1111         arm11->arm.core_type = ARM_CORE_TYPE_STD;
1112         arm_init_arch_info(target, &arm11->arm);
1113
1114         arm11->jtag_info.tap = target->tap;
1115         arm11->jtag_info.scann_size = 5;
1116         arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1117         arm11->jtag_info.cur_scan_chain = ~0;   /* invalid/unknown */
1118         arm11->jtag_info.intest_instr = ARM11_INTEST;
1119
1120         arm11->memwrite_burst = true;
1121         arm11->memwrite_error_fatal = true;
1122
1123         return ERROR_OK;
1124 }
1125
1126 static int arm11_init_target(struct command_context *cmd_ctx,
1127         struct target *target)
1128 {
1129         /* Initialize anything we can set up without talking to the target */
1130         return ERROR_OK;
1131 }
1132
1133 static void arm11_deinit_target(struct target *target)
1134 {
1135         struct arm11_common *arm11 = target_to_arm11(target);
1136
1137         arm11_dpm_deinit(arm11);
1138         free(arm11);
1139 }
1140
1141 /* talk to the target and set things up */
1142 static int arm11_examine(struct target *target)
1143 {
1144         int retval;
1145         char *type;
1146         struct arm11_common *arm11 = target_to_arm11(target);
1147         uint32_t didr, device_id;
1148         uint8_t implementor;
1149
1150         /* FIXME split into do-first-time and do-every-time logic ... */
1151
1152         /* check IDCODE */
1153
1154         arm11_add_ir(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1155
1156         struct scan_field idcode_field;
1157
1158         arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1159
1160         arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &idcode_field, TAP_DRPAUSE);
1161
1162         /* check DIDR */
1163
1164         arm11_add_debug_scan_n(arm11, 0x00, ARM11_TAP_DEFAULT);
1165
1166         arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1167
1168         struct scan_field chain0_fields[2];
1169
1170         arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1171         arm11_setup_field(arm11,  8, NULL, &implementor, chain0_fields + 1);
1172
1173         arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
1174                         chain0_fields), chain0_fields, TAP_IDLE);
1175
1176         CHECK_RETVAL(jtag_execute_queue());
1177
1178         /* assume the manufacturer id is ok; check the part # */
1179         switch ((device_id >> 12) & 0xFFFF) {
1180                 case 0x7B36:
1181                         type = "ARM1136";
1182                         break;
1183                 case 0x7B37:
1184                         type = "ARM11 MPCore";
1185                         break;
1186                 case 0x7B56:
1187                         type = "ARM1156";
1188                         break;
1189                 case 0x7B76:
1190                         arm11->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
1191                         /* NOTE: could default arm11->hardware_step to true */
1192                         type = "ARM1176";
1193                         break;
1194                 default:
1195                         LOG_ERROR("unexpected ARM11 ID code");
1196                         return ERROR_FAIL;
1197         }
1198         LOG_INFO("found %s", type);
1199
1200         /* unlikely this could ever fail, but ... */
1201         switch ((didr >> 16) & 0x0F) {
1202                 case ARM11_DEBUG_V6:
1203                 case ARM11_DEBUG_V61:   /* supports security extensions */
1204                         break;
1205                 default:
1206                         LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1207                         return ERROR_FAIL;
1208         }
1209
1210         arm11->brp = ((didr >> 24) & 0x0F) + 1;
1211
1212         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1213         arm11->free_brps = arm11->brp;
1214
1215         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1216                 device_id, implementor, didr);
1217
1218         /* Build register cache "late", after target_init(), since we
1219          * want to know if this core supports Secure Monitor mode.
1220          */
1221         if (!target_was_examined(target))
1222                 CHECK_RETVAL(arm11_dpm_init(arm11, didr));
1223
1224         /* as a side-effect this reads DSCR and thus
1225          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1226          * as suggested by the spec.
1227          */
1228
1229         retval = arm11_check_init(arm11);
1230         if (retval != ERROR_OK)
1231                 return retval;
1232
1233         /* ETM on ARM11 still uses original scanchain 6 access mode */
1234         if (arm11->arm.etm && !target_was_examined(target)) {
1235                 *register_get_last_cache_p(&target->reg_cache) =
1236                         etm_build_reg_cache(target, &arm11->jtag_info,
1237                                 arm11->arm.etm);
1238                 CHECK_RETVAL(etm_setup(target));
1239         }
1240
1241         target_set_examined(target);
1242
1243         return ERROR_OK;
1244 }
1245
1246 #define ARM11_BOOL_WRAPPER(name, print_name)    \
1247         COMMAND_HANDLER(arm11_handle_bool_ ## name) \
1248         { \
1249                 struct target *target = get_current_target(CMD_CTX); \
1250                 struct arm11_common *arm11 = target_to_arm11(target); \
1251                 \
1252                 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1253                         &arm11->name, print_name); \
1254         }
1255
1256 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1257 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1258 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1259 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1260
1261 /* REVISIT handle the VCR bits like other ARMs:  use symbols for
1262  * input and output values.
1263  */
1264
1265 COMMAND_HANDLER(arm11_handle_vcr)
1266 {
1267         struct target *target = get_current_target(CMD_CTX);
1268         struct arm11_common *arm11 = target_to_arm11(target);
1269
1270         switch (CMD_ARGC) {
1271                 case 0:
1272                         break;
1273                 case 1:
1274                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr);
1275                         break;
1276                 default:
1277                         return ERROR_COMMAND_SYNTAX_ERROR;
1278         }
1279
1280         LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr);
1281         return ERROR_OK;
1282 }
1283
1284 static const struct command_registration arm11_mw_command_handlers[] = {
1285         {
1286                 .name = "burst",
1287                 .handler = arm11_handle_bool_memwrite_burst,
1288                 .mode = COMMAND_ANY,
1289                 .help = "Display or modify flag controlling potentially "
1290                         "risky fast burst mode (default: enabled)",
1291                 .usage = "['enable'|'disable']",
1292         },
1293         {
1294                 .name = "error_fatal",
1295                 .handler = arm11_handle_bool_memwrite_error_fatal,
1296                 .mode = COMMAND_ANY,
1297                 .help = "Display or modify flag controlling transfer "
1298                         "termination on transfer errors"
1299                         " (default: enabled)",
1300                 .usage = "['enable'|'disable']",
1301         },
1302         COMMAND_REGISTRATION_DONE
1303 };
1304 static const struct command_registration arm11_any_command_handlers[] = {
1305         {
1306                 /* "hardware_step" is only here to check if the default
1307                  * simulate + breakpoint implementation is broken.
1308                  * TEMPORARY! NOT DOCUMENTED! */
1309                 .name = "hardware_step",
1310                 .handler = arm11_handle_bool_hardware_step,
1311                 .mode = COMMAND_ANY,
1312                 .help = "DEBUG ONLY - Hardware single stepping"
1313                         " (default: disabled)",
1314                 .usage = "['enable'|'disable']",
1315         },
1316         {
1317                 .name = "memwrite",
1318                 .mode = COMMAND_ANY,
1319                 .help = "memwrite command group",
1320                 .usage = "",
1321                 .chain = arm11_mw_command_handlers,
1322         },
1323         {
1324                 .name = "step_irq_enable",
1325                 .handler = arm11_handle_bool_step_irq_enable,
1326                 .mode = COMMAND_ANY,
1327                 .help = "Display or modify flag controlling interrupt "
1328                         "enable while stepping (default: disabled)",
1329                 .usage = "['enable'|'disable']",
1330         },
1331         {
1332                 .name = "vcr",
1333                 .handler = arm11_handle_vcr,
1334                 .mode = COMMAND_ANY,
1335                 .help = "Display or modify Vector Catch Register",
1336                 .usage = "[value]",
1337         },
1338         COMMAND_REGISTRATION_DONE
1339 };
1340
1341 static const struct command_registration arm11_command_handlers[] = {
1342         {
1343                 .chain = arm_command_handlers,
1344         },
1345         {
1346                 .chain = etm_command_handlers,
1347         },
1348         {
1349                 .name = "arm11",
1350                 .mode = COMMAND_ANY,
1351                 .help = "ARM11 command group",
1352                 .usage = "",
1353                 .chain = arm11_any_command_handlers,
1354         },
1355         COMMAND_REGISTRATION_DONE
1356 };
1357
1358 /** Holds methods for ARM11xx targets. */
1359 struct target_type arm11_target = {
1360         .name = "arm11",
1361
1362         .poll = arm11_poll,
1363         .arch_state = arm11_arch_state,
1364
1365         .halt = arm11_halt,
1366         .resume = arm11_resume,
1367         .step = arm11_step,
1368
1369         .assert_reset = arm11_assert_reset,
1370         .deassert_reset = arm11_deassert_reset,
1371
1372         .get_gdb_arch = arm_get_gdb_arch,
1373         .get_gdb_reg_list = arm_get_gdb_reg_list,
1374
1375         .read_memory = arm11_read_memory,
1376         .write_memory = arm11_write_memory,
1377
1378         .checksum_memory = arm_checksum_memory,
1379         .blank_check_memory = arm_blank_check_memory,
1380
1381         .add_breakpoint = arm11_add_breakpoint,
1382         .remove_breakpoint = arm11_remove_breakpoint,
1383
1384         .run_algorithm = armv4_5_run_algorithm,
1385
1386         .commands = arm11_command_handlers,
1387         .target_create = arm11_target_create,
1388         .init_target = arm11_init_target,
1389         .deinit_target = arm11_deinit_target,
1390         .examine = arm11_examine,
1391 };