1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2005 by Dominic Rath
7 * Copyright (C) 2008 by Spencer Oliver
10 * Copyright (C) 2009 by Øyvind Harboe
11 * oyvind.harboe@zylin.com
13 * Copyright (C) 2018 by Liviu Ionescu
17 #ifndef OPENOCD_TARGET_ARM_H
18 #define OPENOCD_TARGET_ARM_H
20 #include <helper/command.h>
25 * Holds the interface to ARM cores.
27 * At this writing, only "classic ARM" cores built on the ARMv4 register
28 * and mode model are supported. The Thumb2-only microcontroller profile
29 * support has not yet been integrated, affecting Cortex-M parts.
33 * Indicates what registers are in the ARM state core register set.
35 * - ARM_CORE_TYPE_STD indicates the standard set of 37 registers, seen
36 * on for example ARM7TDMI cores.
37 * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
38 * three more registers are shadowed for "Secure Monitor" mode.
39 * - ARM_CORE_TYPE_VIRT_EXT indicates core has virtualization extensions
40 * and also security extensions. Additional shadowed registers for
41 * "Secure Monitor" and "Hypervisor" modes.
42 * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
43 * which only shadows SP.
46 ARM_CORE_TYPE_STD = -1,
47 ARM_CORE_TYPE_SEC_EXT = 1,
48 ARM_CORE_TYPE_VIRT_EXT,
49 ARM_CORE_TYPE_M_PROFILE,
52 /** ARM Architecture specifying the version and the profile */
62 * Represent state of an ARM core.
64 * Most numbers match the five low bits of the *PSR registers on
65 * "classic ARM" processors, which build on the ARMv4 processor
66 * modes and register set.
68 * ARM_MODE_ANY is a magic value, often used as a wildcard.
70 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
71 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
83 ARM_MODE_1176_MON = 28,
87 ARM_MODE_USER_THREAD = 1,
101 /* VFPv3 internal register numbers mapping to d0:31 */
138 const char *arm_mode_name(unsigned psr_mode);
139 bool is_arm_mode(unsigned psr_mode);
141 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
150 /** ARM vector floating point enabled, if yes which version. */
151 enum arm_vfp_version {
158 #define ARM_COMMON_MAGIC 0x0A450A45U
161 * Represents a generic ARM core, with standard application registers.
163 * There are sixteen application registers (including PC, SP, LR) and a PSR.
164 * Cortex-M series cores do not support as many core states or shadowed
165 * registers as traditional ARM cores, and only support Thumb2 instructions.
168 unsigned int common_magic;
170 struct reg_cache *core_cache;
172 /** Handle to the PC; valid in all core modes. */
175 /** Handle to the CPSR/xPSR; valid in all core modes. */
178 /** Handle to the SPSR; valid only in core modes with an SPSR. */
181 /** Support for arm_reg_current() */
184 /** Indicates what registers are in the ARM state core register set. */
185 enum arm_core_type core_type;
187 /** Record the current core mode: SVC, USR, or some other mode. */
188 enum arm_mode core_mode;
190 /** Record the current core state: ARM, Thumb, or otherwise. */
191 enum arm_state core_state;
193 /** ARM architecture version */
196 /** Floating point or VFP version, 0 if disabled. */
199 int (*setup_semihosting)(struct target *target, int enable);
201 /** Backpointer to the target. */
202 struct target *target;
204 /** Handle for the debug module, if one is present. */
207 /** Handle for the Embedded Trace Module, if one is present. */
208 struct etm_context *etm;
210 /* FIXME all these methods should take "struct arm *" not target */
212 /** Retrieve all core registers, for display. */
213 int (*full_context)(struct target *target);
215 /** Retrieve a single core register. */
216 int (*read_core_reg)(struct target *target, struct reg *reg,
217 int num, enum arm_mode mode);
218 int (*write_core_reg)(struct target *target, struct reg *reg,
219 int num, enum arm_mode mode, uint8_t *value);
221 /** Read coprocessor register. */
222 int (*mrc)(struct target *target, int cpnum,
223 uint32_t op1, uint32_t op2,
224 uint32_t crn, uint32_t crm,
227 /** Write coprocessor register. */
228 int (*mcr)(struct target *target, int cpnum,
229 uint32_t op1, uint32_t op2,
230 uint32_t crn, uint32_t crm,
235 /** For targets conforming to ARM Debug Interface v5,
236 * this handle references the Debug Access Port (DAP)
237 * used to make requests to the target.
239 struct adiv5_dap *dap;
242 /** Convert target handle to generic ARM target state handle. */
243 static inline struct arm *target_to_arm(struct target *target)
246 return target->arch_info;
249 static inline bool is_arm(struct arm *arm)
252 return arm->common_magic == ARM_COMMON_MAGIC;
255 struct arm_algorithm {
256 unsigned int common_magic;
258 enum arm_mode core_mode;
259 enum arm_state core_state;
265 struct target *target;
270 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
271 void arm_free_reg_cache(struct arm *arm);
273 struct reg_cache *armv8_build_reg_cache(struct target *target);
275 extern const struct command_registration arm_command_handlers[];
276 extern const struct command_registration arm_all_profiles_command_handlers[];
278 int arm_arch_state(struct target *target);
279 const char *arm_get_gdb_arch(struct target *target);
280 int arm_get_gdb_reg_list(struct target *target,
281 struct reg **reg_list[], int *reg_list_size,
282 enum target_register_class reg_class);
283 const char *armv8_get_gdb_arch(struct target *target);
284 int armv8_get_gdb_reg_list(struct target *target,
285 struct reg **reg_list[], int *reg_list_size,
286 enum target_register_class reg_class);
288 int arm_init_arch_info(struct target *target, struct arm *arm);
290 /* REVISIT rename this once it's usable by ARMv7-M */
291 int armv4_5_run_algorithm(struct target *target,
292 int num_mem_params, struct mem_param *mem_params,
293 int num_reg_params, struct reg_param *reg_params,
294 target_addr_t entry_point, target_addr_t exit_point,
295 int timeout_ms, void *arch_info);
296 int armv4_5_run_algorithm_inner(struct target *target,
297 int num_mem_params, struct mem_param *mem_params,
298 int num_reg_params, struct reg_param *reg_params,
299 uint32_t entry_point, uint32_t exit_point,
300 int timeout_ms, void *arch_info,
301 int (*run_it)(struct target *target, uint32_t exit_point,
302 int timeout_ms, void *arch_info));
304 int arm_checksum_memory(struct target *target,
305 target_addr_t address, uint32_t count, uint32_t *checksum);
306 int arm_blank_check_memory(struct target *target,
307 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
309 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
310 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
311 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
313 #endif /* OPENOCD_TARGET_ARM_H */