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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2013-2015,2019-2020 Synopsys, Inc.                      *
   5  *   Frank Dols <frank.dols@synopsys.com>                                  *
   6  *   Mischa Jonker <mischa.jonker@synopsys.com>                            *
   7  *   Anton Kolesov <anton.kolesov@synopsys.com>                            *
   8  *   Evgeniy Didin <didin@synopsys.com>                                    *
   9  ***************************************************************************/
  10
  11
  12 #ifdef HAVE_CONFIG_H
  13 #include "config.h"
  14 #endif
  15
  16 #include "arc.h"
  17
  18
  19
  20 /*
  21  * ARC architecture specific details.
  22  *
  23  * ARC has two types of registers:
  24  *  1) core registers(e.g. r0,r1..) [is_core = true]
  25  *  2) Auxiliary registers [is_core = false]..
  26  *
  27  * Auxiliary registers at the same time can be divided into
  28  * read-only BCR(build configuration regs, e.g. isa_config, mpu_build) and
  29  * R/RW non-BCR ("control" register, e.g. pc, status32_t, debug).
  30  *
  31  * The way of accessing to Core and AUX registers differs on Jtag level.
  32  * BCR/non-BCR describes if the register is immutable and that reading
  33  * unexisting register is safe RAZ, rather then an error.
  34  * Note, core registers cannot be BCR.
  35  *
  36  * In arc/cpu/ tcl files all registers are defined as core, non-BCR aux
  37  * and BCR aux, in "add-reg" command they are passed to three lists
  38  * respectively:  core_reg_descriptions, aux_reg_descriptions,
  39  * bcr_reg_descriptions.
  40  *
  41  * Due to the specifics of accessing to BCR/non-BCR registers there are two
  42  * register caches:
  43  *  1) core_and_aux_cache - includes registers described in
  44  *     core_reg_descriptions and aux_reg_descriptions lists.
  45  *     Used during save/restore context step.
  46  *  2) bcr_cache - includes registers described bcr_reg_descriptions.
  47  *     Currently used internally during configure step.
  48  */
  49
  50
  51 static int arc_remove_watchpoint(struct target *target,
  52         struct watchpoint *watchpoint);
  53
  54 void arc_reg_data_type_add(struct target *target,
  55                 struct arc_reg_data_type *data_type)
  56 {
  57         LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id);
  58         struct arc_common *arc = target_to_arc(target);
  59         assert(arc);
  60
  61         list_add_tail(&data_type->list, &arc->reg_data_types);
  62 }
  63
  64 /**
  65  * Private implementation of register_get_by_name() for ARC that
  66  * doesn't skip not [yet] existing registers. Used in many places
  67  * for iteration through registers and even for marking required registers as
  68  * existing.
  69  */
  70 struct reg *arc_reg_get_by_name(struct reg_cache *first,
  71                 const char *name, bool search_all)
  72 {
  73         unsigned int i;
  74         struct reg_cache *cache = first;
  75
  76         while (cache) {
  77                 for (i = 0; i < cache->num_regs; i++) {
  78                         if (!strcmp(cache->reg_list[i].name, name))
  79                                 return &(cache->reg_list[i]);
  80                 }
  81
  82                 if (search_all)
  83                         cache = cache->next;
  84                 else
  85                         break;
  86         }
  87
  88         return NULL;
  89 }
  90
  91 /**
  92  * Reset internal states of caches. Must be called when entering debugging.
  93  *
  94  * @param target Target for which to reset caches states.
  95  */
  96 static int arc_reset_caches_states(struct target *target)
  97 {
  98         struct arc_common *arc = target_to_arc(target);
  99
 100         LOG_DEBUG("Resetting internal variables of caches states");
 101
 102         /* Reset caches states. */
 103         arc->dcache_flushed = false;
 104         arc->l2cache_flushed = false;
 105         arc->icache_invalidated = false;
 106         arc->dcache_invalidated = false;
 107         arc->l2cache_invalidated = false;
 108
 109         return ERROR_OK;
 110 }
 111
 112 /* Initialize arc_common structure, which passes to openocd target instance */
 113 static int arc_init_arch_info(struct target *target, struct arc_common *arc,
 114         struct jtag_tap *tap)
 115 {
 116         arc->common_magic = ARC_COMMON_MAGIC;
 117         target->arch_info = arc;
 118
 119         arc->jtag_info.tap = tap;
 120
 121         /* The only allowed ir_length is 4 for ARC jtag. */
 122         if (tap->ir_length != 4) {
 123                 LOG_ERROR("ARC jtag instruction length should be equal to 4");
 124                 return ERROR_FAIL;
 125         }
 126
 127         /* On most ARC targets there is a dcache, so we enable its flushing
 128          * by default. If there no dcache, there will be no error, just a slight
 129          * performance penalty from unnecessary JTAG operations. */
 130         arc->has_dcache = true;
 131         arc->has_icache = true;
 132         /* L2$ is not available in a target by default. */
 133         arc->has_l2cache = false;
 134         arc_reset_caches_states(target);
 135
 136         /* Add standard GDB data types */
 137         INIT_LIST_HEAD(&arc->reg_data_types);
 138         struct arc_reg_data_type *std_types = calloc(ARRAY_SIZE(standard_gdb_types),
 139                 sizeof(*std_types));
 140
 141         if (!std_types) {
 142                 LOG_ERROR("Unable to allocate memory");
 143                 return ERROR_FAIL;
 144         }
 145
 146         for (unsigned int i = 0; i < ARRAY_SIZE(standard_gdb_types); i++) {
 147                 std_types[i].data_type.type = standard_gdb_types[i].type;
 148                 std_types[i].data_type.id = standard_gdb_types[i].id;
 149                 arc_reg_data_type_add(target, &(std_types[i]));
 150         }
 151
 152         /* Fields related to target descriptions */
 153         INIT_LIST_HEAD(&arc->core_reg_descriptions);
 154         INIT_LIST_HEAD(&arc->aux_reg_descriptions);
 155         INIT_LIST_HEAD(&arc->bcr_reg_descriptions);
 156         arc->num_regs = 0;
 157         arc->num_core_regs = 0;
 158         arc->num_aux_regs = 0;
 159         arc->num_bcr_regs = 0;
 160         arc->last_general_reg = ULONG_MAX;
 161         arc->pc_index_in_cache = ULONG_MAX;
 162         arc->debug_index_in_cache = ULONG_MAX;
 163
 164         return ERROR_OK;
 165 }
 166
 167 int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
 168                 const char * const type_name, const size_t type_name_len)
 169 {
 170         assert(target);
 171         assert(arc_reg);
 172
 173         struct arc_common *arc = target_to_arc(target);
 174         assert(arc);
 175
 176         /* Find register type */
 177         {
 178                 struct arc_reg_data_type *type;
 179                 list_for_each_entry(type, &arc->reg_data_types, list)
 180                         if (!strncmp(type->data_type.id, type_name, type_name_len)) {
 181                                 arc_reg->data_type = &(type->data_type);
 182                                 break;
 183                         }
 184
 185                 if (!arc_reg->data_type)
 186                         return ERROR_ARC_REGTYPE_NOT_FOUND;
 187         }
 188
 189         if (arc_reg->is_core) {
 190                 list_add_tail(&arc_reg->list, &arc->core_reg_descriptions);
 191                 arc->num_core_regs += 1;
 192         } else if (arc_reg->is_bcr) {
 193                 list_add_tail(&arc_reg->list, &arc->bcr_reg_descriptions);
 194                 arc->num_bcr_regs += 1;
 195         } else {
 196                 list_add_tail(&arc_reg->list, &arc->aux_reg_descriptions);
 197                 arc->num_aux_regs += 1;
 198         }
 199         arc->num_regs += 1;
 200
 201         LOG_DEBUG(
 202                         "added register {name=%s, num=0x%" PRIx32 ", type=%s%s%s%s}",
 203                         arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id,
 204                         arc_reg->is_core ? ", core" : "",  arc_reg->is_bcr ? ", bcr" : "",
 205                         arc_reg->is_general ? ", general" : ""
 206                 );
 207
 208         return ERROR_OK;
 209 }
 210
 211 /* Reading core or aux register */
 212 static int arc_get_register(struct reg *reg)
 213 {
 214         assert(reg);
 215
 216         struct arc_reg_desc *desc = reg->arch_info;
 217         struct target *target = desc->target;
 218         struct arc_common *arc = target_to_arc(target);
 219
 220         uint32_t value;
 221
 222         if (reg->valid) {
 223                 LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
 224                                 reg->number, desc->name, target_buffer_get_u32(target, reg->value));
 225                 return ERROR_OK;
 226         }
 227
 228         if (desc->is_core) {
 229                 /* Accessing to R61/R62 registers causes Jtag hang */
 230                 if (desc->arch_num == ARC_R61 || desc->arch_num == ARC_R62) {
 231                         LOG_ERROR("It is forbidden to read core registers 61 and 62.");
 232                         return ERROR_FAIL;
 233                 }
 234                 CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, desc->arch_num,
 235                                         &value));
 236         } else {
 237                 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, desc->arch_num,
 238                         &value));
 239         }
 240
 241         target_buffer_set_u32(target, reg->value, value);
 242
 243         /* If target is unhalted all register reads should be uncached. */
 244         if (target->state == TARGET_HALTED)
 245                 reg->valid = true;
 246         else
 247                 reg->valid = false;
 248
 249         reg->dirty = false;
 250
 251         LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
 252                         reg->number, desc->name, value);
 253
 254
 255         return ERROR_OK;
 256 }
 257
 258 /* Writing core or aux register */
 259 static int arc_set_register(struct reg *reg, uint8_t *buf)
 260 {
 261         struct arc_reg_desc *desc = reg->arch_info;
 262         struct target *target = desc->target;
 263         uint32_t value = target_buffer_get_u32(target, buf);
 264         /* Unlike "get" function "set" is supported only if target
 265         * is in halt mode. Async writes are not supported yet. */
 266         if (target->state != TARGET_HALTED)
 267                 return ERROR_TARGET_NOT_HALTED;
 268
 269         /* Accessing to R61/R62 registers causes Jtag hang */
 270         if (desc->is_core && (desc->arch_num == ARC_R61 ||
 271                         desc->arch_num == ARC_R62)) {
 272                 LOG_ERROR("It is forbidden to write core registers 61 and 62.");
 273                 return ERROR_FAIL;
 274         }
 275         target_buffer_set_u32(target, reg->value, value);
 276
 277         LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
 278                         reg->number, desc->name, value);
 279
 280         reg->valid = true;
 281         reg->dirty = true;
 282
 283         return ERROR_OK;
 284 }
 285
 286 static const struct reg_arch_type arc_reg_type = {
 287         .get = arc_get_register,
 288         .set = arc_set_register,
 289 };
 290
 291 /* GDB register groups. For now we support only general and "empty" */
 292 static const char * const reg_group_general = "general";
 293 static const char * const reg_group_other = "";
 294
 295 /* Common code to initialize `struct reg` for different registers: core, aux, bcr. */
 296 static int arc_init_reg(struct target *target, struct reg *reg,
 297                         struct arc_reg_desc *reg_desc, unsigned long number)
 298 {
 299         assert(target);
 300         assert(reg);
 301         assert(reg_desc);
 302
 303         struct arc_common *arc = target_to_arc(target);
 304
 305         /* Initialize struct reg */
 306         reg->name = reg_desc->name;
 307         reg->size = 32; /* All register in ARC are 32-bit */
 308         reg->value = reg_desc->reg_value;
 309         reg->type = &arc_reg_type;
 310         reg->arch_info = reg_desc;
 311         reg->caller_save = true; /* @todo should be configurable. */
 312         reg->reg_data_type = reg_desc->data_type;
 313         reg->feature = &reg_desc->feature;
 314
 315         reg->feature->name = reg_desc->gdb_xml_feature;
 316
 317         /* reg->number is used by OpenOCD as value for @regnum. Thus when setting
 318          * value of a register GDB will use it as a number of register in
 319          * P-packet. OpenOCD gdbserver will then use number of register in
 320          * P-packet as an array index in the reg_list returned by
 321          * arc_regs_get_gdb_reg_list. So to ensure that registers are assigned
 322          * correctly it would be required to either sort registers in
 323          * arc_regs_get_gdb_reg_list or to assign numbers sequentially here and
 324          * according to how registers will be sorted in
 325          * arc_regs_get_gdb_reg_list. Second options is much more simpler. */
 326         reg->number = number;
 327
 328         if (reg_desc->is_general) {
 329                 arc->last_general_reg = reg->number;
 330                 reg->group = reg_group_general;
 331         } else {
 332                 reg->group = reg_group_other;
 333         }
 334
 335         return ERROR_OK;
 336 }
 337
 338 /* Building aux/core reg_cache */
 339 static int arc_build_reg_cache(struct target *target)
 340 {
 341         unsigned long i = 0;
 342         struct arc_reg_desc *reg_desc;
 343         /* get pointers to arch-specific information */
 344         struct arc_common *arc = target_to_arc(target);
 345         const unsigned long num_regs = arc->num_core_regs + arc->num_aux_regs;
 346         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 347         struct reg_cache *cache = calloc(1, sizeof(*cache));
 348         struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
 349
 350         if (!cache || !reg_list)  {
 351                 LOG_ERROR("Not enough memory");
 352                 goto fail;
 353         }
 354
 355         /* Build the process context cache */
 356         cache->name = "arc registers";
 357         cache->next = NULL;
 358         cache->reg_list = reg_list;
 359         cache->num_regs = num_regs;
 360         arc->core_and_aux_cache = cache;
 361         (*cache_p) = cache;
 362
 363         if (list_empty(&arc->core_reg_descriptions)) {
 364                 LOG_ERROR("No core registers were defined");
 365                 goto fail;
 366         }
 367
 368         list_for_each_entry(reg_desc, &arc->core_reg_descriptions, list) {
 369                 CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
 370
 371                 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
 372                         reg_list[i].name, reg_list[i].group,
 373                         reg_list[i].feature->name);
 374
 375                 i += 1;
 376         }
 377
 378         if (list_empty(&arc->aux_reg_descriptions)) {
 379                 LOG_ERROR("No aux registers were defined");
 380                 goto fail;
 381         }
 382
 383         list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
 384                  CHECK_RETVAL(arc_init_reg(target, &reg_list[i],  reg_desc, i));
 385
 386                 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
 387                         reg_list[i].name, reg_list[i].group,
 388                         reg_list[i].feature->name);
 389
 390                 /* PC and DEBUG are essential so we search for them. */
 391                 if (!strcmp("pc", reg_desc->name)) {
 392                         if (arc->pc_index_in_cache != ULONG_MAX) {
 393                                 LOG_ERROR("Double definition of PC in configuration");
 394                                 goto fail;
 395                         }
 396                         arc->pc_index_in_cache = i;
 397                 } else if (!strcmp("debug", reg_desc->name)) {
 398                         if (arc->debug_index_in_cache != ULONG_MAX) {
 399                                 LOG_ERROR("Double definition of DEBUG in configuration");
 400                                 goto fail;
 401                         }
 402                         arc->debug_index_in_cache = i;
 403                 }
 404                 i += 1;
 405         }
 406
 407         if (arc->pc_index_in_cache == ULONG_MAX
 408                         || arc->debug_index_in_cache == ULONG_MAX) {
 409                 LOG_ERROR("`pc' and `debug' registers must be present in target description.");
 410                 goto fail;
 411         }
 412
 413         assert(i == (arc->num_core_regs + arc->num_aux_regs));
 414
 415         arc->core_aux_cache_built = true;
 416
 417         return ERROR_OK;
 418
 419 fail:
 420         free(cache);
 421         free(reg_list);
 422
 423         return ERROR_FAIL;
 424 }
 425
 426 /* Build bcr reg_cache.
 427  * This function must be called only after arc_build_reg_cache */
 428 static int arc_build_bcr_reg_cache(struct target *target)
 429 {
 430         /* get pointers to arch-specific information */
 431         struct arc_common *arc = target_to_arc(target);
 432         const unsigned long num_regs = arc->num_bcr_regs;
 433         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 434         struct reg_cache *cache = malloc(sizeof(*cache));
 435         struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
 436
 437         struct arc_reg_desc *reg_desc;
 438         unsigned long i = 0;
 439         unsigned long gdb_regnum = arc->core_and_aux_cache->num_regs;
 440
 441         if (!cache || !reg_list)  {
 442                 LOG_ERROR("Unable to allocate memory");
 443                 goto fail;
 444         }
 445
 446         /* Build the process context cache */
 447         cache->name = "arc.bcr";
 448         cache->next = NULL;
 449         cache->reg_list = reg_list;
 450         cache->num_regs = num_regs;
 451         arc->bcr_cache = cache;
 452         (*cache_p) = cache;
 453
 454         if (list_empty(&arc->bcr_reg_descriptions)) {
 455                 LOG_ERROR("No BCR registers are defined");
 456                 goto fail;
 457         }
 458
 459         list_for_each_entry(reg_desc, &arc->bcr_reg_descriptions, list) {
 460                  CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, gdb_regnum));
 461                 /* BCRs always semantically, they are just read-as-zero, if there is
 462                  * not real register. */
 463                 reg_list[i].exist = true;
 464
 465                 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
 466                         reg_list[i].name, reg_list[i].group,
 467                         reg_list[i].feature->name);
 468                 i += 1;
 469                 gdb_regnum += 1;
 470         }
 471
 472         assert(i == arc->num_bcr_regs);
 473
 474         arc->bcr_cache_built = true;
 475
 476
 477         return ERROR_OK;
 478 fail:
 479         free(cache);
 480         free(reg_list);
 481
 482         return ERROR_FAIL;
 483 }
 484
 485
 486 static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 487         int *reg_list_size, enum target_register_class reg_class)
 488 {
 489         assert(target->reg_cache);
 490         struct arc_common *arc = target_to_arc(target);
 491
 492         /* get pointers to arch-specific information storage */
 493         *reg_list_size = arc->num_regs;
 494         *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
 495
 496         if (!*reg_list) {
 497                 LOG_ERROR("Unable to allocate memory");
 498                 return ERROR_FAIL;
 499         }
 500
 501         /* OpenOCD gdb_server API seems to be inconsistent here: when it generates
 502          * XML tdesc it filters out !exist registers, however when creating a
 503          * g-packet it doesn't do so. REG_CLASS_ALL is used in first case, and
 504          * REG_CLASS_GENERAL used in the latter one. Due to this we had to filter
 505          * out !exist register for "general", but not for "all". Attempts to filter out
 506          * !exist for "all" as well will cause a failed check in OpenOCD GDB
 507          * server. */
 508         if (reg_class == REG_CLASS_ALL) {
 509                 unsigned long i = 0;
 510                 struct reg_cache *reg_cache = target->reg_cache;
 511                 while (reg_cache) {
 512                         for (unsigned j = 0; j < reg_cache->num_regs; j++, i++)
 513                                 (*reg_list)[i] =  &reg_cache->reg_list[j];
 514                         reg_cache = reg_cache->next;
 515                 }
 516                 assert(i == arc->num_regs);
 517                 LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size);
 518         } else {
 519                 unsigned long i = 0;
 520                 unsigned long gdb_reg_number = 0;
 521                 struct reg_cache *reg_cache = target->reg_cache;
 522                 while (reg_cache) {
 523                         for (unsigned j = 0;
 524                                  j < reg_cache->num_regs && gdb_reg_number <= arc->last_general_reg;
 525                                  j++) {
 526                                 if (reg_cache->reg_list[j].exist) {
 527                                         (*reg_list)[i] =  &reg_cache->reg_list[j];
 528                                         i++;
 529                                 }
 530                                 gdb_reg_number += 1;
 531                         }
 532                         reg_cache = reg_cache->next;
 533                 }
 534                 *reg_list_size = i;
 535                 LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
 536         }
 537
 538         return ERROR_OK;
 539 }
 540
 541 /* Reading field of struct_type register */
 542 int arc_reg_get_field(struct target *target, const char *reg_name,
 543                 const char *field_name, uint32_t *value_ptr)
 544 {
 545         struct reg_data_type_struct_field *field;
 546
 547         LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
 548
 549         /* Get register */
 550         struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
 551
 552         if (!reg) {
 553                 LOG_ERROR("Requested register `%s' doesn't exist.", reg_name);
 554                 return ERROR_ARC_REGISTER_NOT_FOUND;
 555         }
 556
 557         if (reg->reg_data_type->type != REG_TYPE_ARCH_DEFINED
 558             || reg->reg_data_type->type_class != REG_TYPE_CLASS_STRUCT)
 559                 return ERROR_ARC_REGISTER_IS_NOT_STRUCT;
 560
 561         /* Get field in a register */
 562         struct reg_data_type_struct *reg_struct =
 563                 reg->reg_data_type->reg_type_struct;
 564         for (field = reg_struct->fields;
 565              field;
 566              field = field->next) {
 567                 if (!strcmp(field->name, field_name))
 568                         break;
 569         }
 570
 571         if (!field)
 572                 return ERROR_ARC_REGISTER_FIELD_NOT_FOUND;
 573
 574         if (!field->use_bitfields)
 575                 return ERROR_ARC_FIELD_IS_NOT_BITFIELD;
 576
 577         if (!reg->valid)
 578                 CHECK_RETVAL(reg->type->get(reg));
 579
 580         /* First do endianness-safe read of register value
 581          * then convert it to binary buffer for further
 582          * field extraction */
 583
 584         *value_ptr = buf_get_u32(reg->value, field->bitfield->start,
 585                 field->bitfield->end - field->bitfield->start + 1);
 586
 587         return ERROR_OK;
 588 }
 589
 590 static int arc_get_register_value(struct target *target, const char *reg_name,
 591                 uint32_t *value_ptr)
 592 {
 593         LOG_DEBUG("reg_name=%s", reg_name);
 594
 595         struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
 596
 597         if (!reg)
 598                 return ERROR_ARC_REGISTER_NOT_FOUND;
 599
 600         if (!reg->valid)
 601                 CHECK_RETVAL(reg->type->get(reg));
 602
 603         *value_ptr = target_buffer_get_u32(target, reg->value);
 604
 605         return ERROR_OK;
 606 }
 607
 608 static int arc_set_register_value(struct target *target, const char *reg_name,
 609                 uint32_t value)
 610 {
 611         LOG_DEBUG("reg_name=%s value=0x%08" PRIx32, reg_name, value);
 612
 613         if (!(target && reg_name)) {
 614                 LOG_ERROR("Arguments cannot be NULL.");
 615                 return ERROR_FAIL;
 616         }
 617
 618         struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
 619
 620         if (!reg)
 621                 return ERROR_ARC_REGISTER_NOT_FOUND;
 622
 623         uint8_t value_buf[4];
 624         buf_set_u32(value_buf, 0, 32, value);
 625         CHECK_RETVAL(reg->type->set(reg, value_buf));
 626
 627         return ERROR_OK;
 628 }
 629
 630 /* Configure DCCM's */
 631 static int arc_configure_dccm(struct target  *target)
 632 {
 633         struct arc_common *arc = target_to_arc(target);
 634
 635         uint32_t dccm_build_version, dccm_build_size0, dccm_build_size1;
 636         CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "version",
 637                 &dccm_build_version));
 638         CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size0",
 639                 &dccm_build_size0));
 640         CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size1",
 641                 &dccm_build_size1));
 642         /* There is no yet support of configurable number of cycles,
 643          * So there is no difference between v3 and v4 */
 644         if ((dccm_build_version == 3 || dccm_build_version == 4) && dccm_build_size0 > 0) {
 645                 CHECK_RETVAL(arc_get_register_value(target, "aux_dccm", &(arc->dccm_start)));
 646                 uint32_t dccm_size = 0x100;
 647                 dccm_size <<= dccm_build_size0;
 648                 if (dccm_build_size0 == 0xF)
 649                         dccm_size <<= dccm_build_size1;
 650                 arc->dccm_end = arc->dccm_start + dccm_size;
 651                 LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
 652                                 arc->dccm_start, arc->dccm_end);
 653
 654         }
 655         return ERROR_OK;
 656 }
 657
 658
 659 /* Configure ICCM's */
 660
 661 static int arc_configure_iccm(struct target  *target)
 662 {
 663         struct arc_common *arc = target_to_arc(target);
 664
 665         /* ICCM0 */
 666         uint32_t iccm_build_version, iccm_build_size00, iccm_build_size01;
 667         uint32_t aux_iccm = 0;
 668         CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "version",
 669                 &iccm_build_version));
 670         CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size0",
 671                 &iccm_build_size00));
 672         CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size1",
 673                 &iccm_build_size01));
 674         if (iccm_build_version == 4 && iccm_build_size00 > 0) {
 675                 CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
 676                 uint32_t iccm0_size = 0x100;
 677                 iccm0_size <<= iccm_build_size00;
 678                 if (iccm_build_size00 == 0xF)
 679                         iccm0_size <<= iccm_build_size01;
 680                 /* iccm0 start is located in highest 4 bits of aux_iccm */
 681                 arc->iccm0_start = aux_iccm & 0xF0000000;
 682                 arc->iccm0_end = arc->iccm0_start + iccm0_size;
 683                 LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
 684                                 arc->iccm0_start, arc->iccm0_end);
 685         }
 686
 687         /* ICCM1 */
 688         uint32_t iccm_build_size10, iccm_build_size11;
 689         CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size0",
 690                 &iccm_build_size10));
 691         CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size1",
 692                 &iccm_build_size11));
 693         if (iccm_build_version == 4 && iccm_build_size10 > 0) {
 694                 /* Use value read for ICCM0 */
 695                 if (!aux_iccm)
 696                         CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
 697                 uint32_t iccm1_size = 0x100;
 698                 iccm1_size <<= iccm_build_size10;
 699                 if (iccm_build_size10 == 0xF)
 700                         iccm1_size <<= iccm_build_size11;
 701                 arc->iccm1_start = aux_iccm & 0x0F000000;
 702                 arc->iccm1_end = arc->iccm1_start + iccm1_size;
 703                 LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
 704                                 arc->iccm1_start, arc->iccm1_end);
 705         }
 706         return ERROR_OK;
 707 }
 708
 709 /* Configure some core features, depending on BCRs. */
 710 static int arc_configure(struct target *target)
 711 {
 712         LOG_DEBUG("Configuring ARC ICCM and DCCM");
 713
 714         /* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
 715         if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
 716             arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
 717                                 CHECK_RETVAL(arc_configure_dccm(target));
 718
 719         /* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
 720         if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) &&
 721             arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
 722                                 CHECK_RETVAL(arc_configure_iccm(target));
 723
 724         return ERROR_OK;
 725 }
 726
 727 /* arc_examine is function, which is used for all arc targets*/
 728 static int arc_examine(struct target *target)
 729 {
 730         uint32_t status;
 731         struct arc_common *arc = target_to_arc(target);
 732
 733         CHECK_RETVAL(arc_jtag_startup(&arc->jtag_info));
 734
 735         if (!target_was_examined(target)) {
 736                 CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
 737                 if (status & ARC_JTAG_STAT_RU)
 738                         target->state = TARGET_RUNNING;
 739                 else
 740                         target->state = TARGET_HALTED;
 741
 742                 /* Read BCRs and configure optional registers. */
 743                 CHECK_RETVAL(arc_configure(target));
 744
 745                 target_set_examined(target);
 746         }
 747
 748         return ERROR_OK;
 749 }
 750
 751 static int arc_halt(struct target *target)
 752 {
 753         uint32_t value, irq_state;
 754         struct arc_common *arc = target_to_arc(target);
 755
 756         LOG_DEBUG("target->state: %s", target_state_name(target));
 757
 758         if (target->state == TARGET_HALTED) {
 759                 LOG_DEBUG("target was already halted");
 760                 return ERROR_OK;
 761         }
 762
 763         if (target->state == TARGET_UNKNOWN)
 764                 LOG_WARNING("target was in unknown state when halt was requested");
 765
 766         if (target->state == TARGET_RESET) {
 767                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 768                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 769                         return ERROR_TARGET_FAILURE;
 770                 } else {
 771                         target->debug_reason = DBG_REASON_DBGRQ;
 772                 }
 773         }
 774
 775         /* Break (stop) processor.
 776          * Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally.
 777          * We do not use here arc_get/set_core_reg functions here because they imply
 778          * that the processor is already halted. */
 779         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, &value));
 780         value |= SET_CORE_FORCE_HALT; /* set the HALT bit */
 781         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value));
 782         alive_sleep(1);
 783
 784         /* Save current IRQ state */
 785         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &irq_state));
 786
 787         if (irq_state & AUX_STATUS32_REG_IE_BIT)
 788                 arc->irq_state = 1;
 789         else
 790                 arc->irq_state = 0;
 791
 792         /* update state and notify gdb*/
 793         target->state = TARGET_HALTED;
 794         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 795
 796         /* some more debug information */
 797         if (debug_level >= LOG_LVL_DEBUG) {
 798                 LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
 799                 CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
 800                 LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
 801         }
 802
 803         return ERROR_OK;
 804 }
 805
 806 /**
 807  * Read registers that are used in GDB g-packet. We don't read them one-by-one,
 808  * but do that in one batch operation to improve speed. Calls to JTAG layer are
 809  * expensive so it is better to make one big call that reads all necessary
 810  * registers, instead of many calls, one for one register.
 811  */
 812 static int arc_save_context(struct target *target)
 813 {
 814         int retval = ERROR_OK;
 815         unsigned int i;
 816         struct arc_common *arc = target_to_arc(target);
 817         struct reg *reg_list = arc->core_and_aux_cache->reg_list;
 818
 819         LOG_DEBUG("Saving aux and core registers values");
 820         assert(reg_list);
 821
 822         /* It is assumed that there is at least one AUX register in the list, for
 823          * example PC. */
 824         const uint32_t core_regs_size = arc->num_core_regs * sizeof(uint32_t);
 825         /* last_general_reg is inclusive number. To get count of registers it is
 826          * required to do +1. */
 827         const uint32_t regs_to_scan =
 828                 MIN(arc->last_general_reg + 1, arc->num_regs);
 829         const uint32_t aux_regs_size = arc->num_aux_regs * sizeof(uint32_t);
 830         uint32_t *core_values = malloc(core_regs_size);
 831         uint32_t *aux_values = malloc(aux_regs_size);
 832         uint32_t *core_addrs = malloc(core_regs_size);
 833         uint32_t *aux_addrs = malloc(aux_regs_size);
 834         unsigned int core_cnt = 0;
 835         unsigned int aux_cnt = 0;
 836
 837         if (!core_values || !core_addrs || !aux_values || !aux_addrs)  {
 838                 LOG_ERROR("Unable to allocate memory");
 839                 retval = ERROR_FAIL;
 840                 goto exit;
 841         }
 842
 843         memset(core_values, 0xff, core_regs_size);
 844         memset(core_addrs, 0xff, core_regs_size);
 845         memset(aux_values, 0xff, aux_regs_size);
 846         memset(aux_addrs, 0xff, aux_regs_size);
 847
 848         for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) {
 849                 struct reg *reg = &(reg_list[i]);
 850                 struct arc_reg_desc *arc_reg = reg->arch_info;
 851                 if (!reg->valid && reg->exist) {
 852                         core_addrs[core_cnt] = arc_reg->arch_num;
 853                         core_cnt += 1;
 854                 }
 855         }
 856
 857         for (i = arc->num_core_regs; i < regs_to_scan; i++) {
 858                 struct reg *reg = &(reg_list[i]);
 859                 struct arc_reg_desc *arc_reg = reg->arch_info;
 860                 if (!reg->valid && reg->exist) {
 861                         aux_addrs[aux_cnt] = arc_reg->arch_num;
 862                         aux_cnt += 1;
 863                 }
 864         }
 865
 866         /* Read data from target. */
 867         if (core_cnt > 0) {
 868                 retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
 869                 if (retval != ERROR_OK) {
 870                         LOG_ERROR("Attempt to read core registers failed.");
 871                         retval = ERROR_FAIL;
 872                         goto exit;
 873                 }
 874         }
 875         if (aux_cnt > 0) {
 876                 retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
 877                 if (retval != ERROR_OK) {
 878                         LOG_ERROR("Attempt to read aux registers failed.");
 879                         retval = ERROR_FAIL;
 880                         goto exit;
 881                 }
 882         }
 883
 884         /* Parse core regs */
 885         core_cnt = 0;
 886         for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) {
 887                 struct reg *reg = &(reg_list[i]);
 888                 struct arc_reg_desc *arc_reg = reg->arch_info;
 889                 if (!reg->valid && reg->exist) {
 890                         target_buffer_set_u32(target, reg->value, core_values[core_cnt]);
 891                         core_cnt += 1;
 892                         reg->valid = true;
 893                         reg->dirty = false;
 894                         LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
 895                                 i, arc_reg->name, core_values[core_cnt]);
 896                 }
 897         }
 898
 899         /* Parse aux regs */
 900         aux_cnt = 0;
 901         for (i = arc->num_core_regs; i < regs_to_scan; i++) {
 902                 struct reg *reg = &(reg_list[i]);
 903                 struct arc_reg_desc *arc_reg = reg->arch_info;
 904                 if (!reg->valid && reg->exist) {
 905                         target_buffer_set_u32(target, reg->value, aux_values[aux_cnt]);
 906                         aux_cnt += 1;
 907                         reg->valid = true;
 908                         reg->dirty = false;
 909                         LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
 910                                 i, arc_reg->name, aux_values[aux_cnt]);
 911                 }
 912         }
 913
 914 exit:
 915         free(core_values);
 916         free(core_addrs);
 917         free(aux_values);
 918         free(aux_addrs);
 919
 920         return retval;
 921 }
 922
 923 /**
 924  * Finds an actionpoint that triggered last actionpoint event, as specified by
 925  * DEBUG.ASR.
 926  *
 927  * @param target
 928  * @param actionpoint Pointer to be set to last active actionpoint. Pointer
 929  *                    will be set to NULL if DEBUG.AH is 0.
 930  */
 931 static int get_current_actionpoint(struct target *target,
 932                 struct arc_actionpoint **actionpoint)
 933 {
 934         assert(target);
 935         assert(actionpoint);
 936
 937         uint32_t debug_ah;
 938         /* Check if actionpoint caused halt */
 939         CHECK_RETVAL(arc_reg_get_field(target, "debug", "ah",
 940                                 &debug_ah));
 941
 942         if (debug_ah) {
 943                 struct arc_common *arc = target_to_arc(target);
 944                 unsigned int ap;
 945                 uint32_t debug_asr;
 946                 CHECK_RETVAL(arc_reg_get_field(target, "debug",
 947                                         "asr", &debug_asr));
 948
 949                 for (ap = 0; debug_asr > 1; debug_asr >>= 1)
 950                         ap += 1;
 951
 952                 assert(ap < arc->actionpoints_num);
 953
 954                 *actionpoint = &(arc->actionpoints_list[ap]);
 955         } else {
 956                 *actionpoint = NULL;
 957         }
 958
 959         return ERROR_OK;
 960 }
 961
 962 static int arc_examine_debug_reason(struct target *target)
 963 {
 964         uint32_t debug_bh;
 965
 966         /* Only check for reason if don't know it already. */
 967         /* BTW After singlestep at this point core is not marked as halted, so
 968          * reading from memory to get current instruction wouldn't work anyway.  */
 969         if (target->debug_reason == DBG_REASON_DBGRQ ||
 970             target->debug_reason == DBG_REASON_SINGLESTEP) {
 971                 return ERROR_OK;
 972         }
 973
 974         CHECK_RETVAL(arc_reg_get_field(target, "debug", "bh",
 975                                 &debug_bh));
 976
 977         if (debug_bh) {
 978                 /* DEBUG.BH is set if core halted due to BRK instruction.  */
 979                 target->debug_reason = DBG_REASON_BREAKPOINT;
 980         } else {
 981                 struct arc_actionpoint *actionpoint = NULL;
 982                 CHECK_RETVAL(get_current_actionpoint(target, &actionpoint));
 983
 984                 if (actionpoint) {
 985                         if (!actionpoint->used)
 986                                 LOG_WARNING("Target halted by an unused actionpoint.");
 987
 988                         if (actionpoint->type == ARC_AP_BREAKPOINT)
 989                                 target->debug_reason = DBG_REASON_BREAKPOINT;
 990                         else if (actionpoint->type == ARC_AP_WATCHPOINT)
 991                                 target->debug_reason = DBG_REASON_WATCHPOINT;
 992                         else
 993                                 LOG_WARNING("Unknown type of actionpoint.");
 994                 }
 995         }
 996
 997         return ERROR_OK;
 998 }
 999
1000 static int arc_debug_entry(struct target *target)
1001 {
1002         CHECK_RETVAL(arc_save_context(target));
1003
1004         /* TODO: reset internal indicators of caches states, otherwise D$/I$
1005          * will not be flushed/invalidated when required. */
1006         CHECK_RETVAL(arc_reset_caches_states(target));
1007         CHECK_RETVAL(arc_examine_debug_reason(target));
1008
1009         return ERROR_OK;
1010 }
1011
1012 static int arc_poll(struct target *target)
1013 {
1014         uint32_t status, value;
1015         struct arc_common *arc = target_to_arc(target);
1016
1017         /* gdb calls continuously through this arc_poll() function  */
1018         CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
1019
1020         /* check for processor halted */
1021         if (status & ARC_JTAG_STAT_RU) {
1022                 if (target->state != TARGET_RUNNING) {
1023                         LOG_WARNING("target is still running!");
1024                         target->state = TARGET_RUNNING;
1025                 }
1026                 return ERROR_OK;
1027         }
1028         /* In some cases JTAG status register indicates that
1029          *  processor is in halt mode, but processor is still running.
1030          *  We check halt bit of AUX STATUS32 register for setting correct state. */
1031         if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
1032                 CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
1033                 if (value & AUX_STATUS32_REG_HALT_BIT) {
1034                         LOG_DEBUG("ARC core in halt or reset state.");
1035                         /* Save context if target was not in reset state */
1036                         if (target->state == TARGET_RUNNING)
1037                                 CHECK_RETVAL(arc_debug_entry(target));
1038                         target->state = TARGET_HALTED;
1039                         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1040                 } else {
1041                 LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
1042                                                 "target is still running");
1043                 }
1044
1045         } else if (target->state == TARGET_DEBUG_RUNNING) {
1046
1047                 target->state = TARGET_HALTED;
1048                 LOG_DEBUG("ARC core is in debug running mode");
1049
1050                 CHECK_RETVAL(arc_debug_entry(target));
1051
1052                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED));
1053         }
1054
1055         return ERROR_OK;
1056 }
1057
1058 static int arc_assert_reset(struct target *target)
1059 {
1060         struct arc_common *arc = target_to_arc(target);
1061         enum reset_types jtag_reset_config = jtag_get_reset_config();
1062         bool srst_asserted = false;
1063
1064         LOG_DEBUG("target->state: %s", target_state_name(target));
1065
1066         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1067                 /* allow scripts to override the reset event */
1068
1069                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1070                 register_cache_invalidate(arc->core_and_aux_cache);
1071                  /* An ARC target might be in halt state after reset, so
1072                  * if script requested processor to resume, then it must
1073                  * be manually started to ensure that this request
1074                  * is satisfied. */
1075                 if (target->state == TARGET_HALTED && !target->reset_halt) {
1076                         /* Resume the target and continue from the current
1077                          * PC register value. */
1078                         LOG_DEBUG("Starting CPU execution after reset");
1079                         CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
1080                 }
1081                 target->state = TARGET_RESET;
1082
1083                 return ERROR_OK;
1084         }
1085
1086         /* some cores support connecting while srst is asserted
1087          * use that mode if it has been configured */
1088         if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
1089                         (jtag_reset_config & RESET_SRST_NO_GATING)) {
1090                 jtag_add_reset(0, 1);
1091                 srst_asserted = true;
1092         }
1093
1094         if (jtag_reset_config & RESET_HAS_SRST) {
1095                 /* should issue a srst only, but we may have to assert trst as well */
1096                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1097                         jtag_add_reset(1, 1);
1098                 else if (!srst_asserted)
1099                         jtag_add_reset(0, 1);
1100         }
1101
1102         target->state = TARGET_RESET;
1103         jtag_add_sleep(50000);
1104
1105         register_cache_invalidate(arc->core_and_aux_cache);
1106
1107         if (target->reset_halt)
1108                 CHECK_RETVAL(target_halt(target));
1109
1110         return ERROR_OK;
1111 }
1112
1113 static int arc_deassert_reset(struct target *target)
1114 {
1115         LOG_DEBUG("target->state: %s", target_state_name(target));
1116
1117         /* deassert reset lines */
1118         jtag_add_reset(0, 0);
1119
1120         return ERROR_OK;
1121 }
1122
1123 static int arc_arch_state(struct target *target)
1124 {
1125         uint32_t pc_value;
1126
1127         if (debug_level < LOG_LVL_DEBUG)
1128                 return ERROR_OK;
1129
1130         CHECK_RETVAL(arc_get_register_value(target, "pc", &pc_value));
1131
1132         LOG_DEBUG("target state: %s;  PC at: 0x%08" PRIx32,
1133                 target_state_name(target),
1134                 pc_value);
1135
1136         return ERROR_OK;
1137 }
1138
1139 /**
1140  * See arc_save_context() for reason why we want to dump all regs at once.
1141  * This however means that if there are dependencies between registers they
1142  * will not be observable until target will be resumed.
1143  */
1144 static int arc_restore_context(struct target *target)
1145 {
1146         int retval = ERROR_OK;
1147         unsigned int i;
1148         struct arc_common *arc = target_to_arc(target);
1149         struct reg *reg_list = arc->core_and_aux_cache->reg_list;
1150
1151         LOG_DEBUG("Restoring registers values");
1152         assert(reg_list);
1153
1154         const uint32_t core_regs_size = arc->num_core_regs  * sizeof(uint32_t);
1155         const uint32_t aux_regs_size =  arc->num_aux_regs * sizeof(uint32_t);
1156         uint32_t *core_values = malloc(core_regs_size);
1157         uint32_t *aux_values = malloc(aux_regs_size);
1158         uint32_t *core_addrs = malloc(core_regs_size);
1159         uint32_t *aux_addrs = malloc(aux_regs_size);
1160         unsigned int core_cnt = 0;
1161         unsigned int aux_cnt = 0;
1162
1163         if (!core_values || !core_addrs || !aux_values || !aux_addrs)  {
1164                 LOG_ERROR("Unable to allocate memory");
1165                 retval = ERROR_FAIL;
1166                 goto exit;
1167         }
1168
1169         memset(core_values, 0xff, core_regs_size);
1170         memset(core_addrs, 0xff, core_regs_size);
1171         memset(aux_values, 0xff, aux_regs_size);
1172         memset(aux_addrs, 0xff, aux_regs_size);
1173
1174         for (i = 0; i < arc->num_core_regs; i++) {
1175                 struct reg *reg = &(reg_list[i]);
1176                 struct arc_reg_desc *arc_reg = reg->arch_info;
1177                 if (reg->valid && reg->exist && reg->dirty) {
1178                         LOG_DEBUG("Will write regnum=%u", i);
1179                         core_addrs[core_cnt] = arc_reg->arch_num;
1180                         core_values[core_cnt] = target_buffer_get_u32(target, reg->value);
1181                         core_cnt += 1;
1182                 }
1183         }
1184
1185         for (i = 0; i < arc->num_aux_regs; i++) {
1186                 struct reg *reg = &(reg_list[arc->num_core_regs + i]);
1187                 struct arc_reg_desc *arc_reg = reg->arch_info;
1188                 if (reg->valid && reg->exist && reg->dirty) {
1189                         LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i);
1190                         aux_addrs[aux_cnt] = arc_reg->arch_num;
1191                         aux_values[aux_cnt] = target_buffer_get_u32(target, reg->value);
1192                         aux_cnt += 1;
1193                 }
1194         }
1195
1196         /* Write data to target.
1197          * Check before write, if aux and core count is greater than 0. */
1198         if (core_cnt > 0) {
1199                 retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
1200                 if (retval != ERROR_OK) {
1201                         LOG_ERROR("Attempt to write to core registers failed.");
1202                         retval = ERROR_FAIL;
1203                         goto exit;
1204                 }
1205         }
1206
1207         if (aux_cnt > 0) {
1208                 retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
1209                 if (retval != ERROR_OK) {
1210                         LOG_ERROR("Attempt to write to aux registers failed.");
1211                         retval = ERROR_FAIL;
1212                         goto exit;
1213                 }
1214         }
1215
1216 exit:
1217         free(core_values);
1218         free(core_addrs);
1219         free(aux_values);
1220         free(aux_addrs);
1221
1222         return retval;
1223 }
1224
1225 static int arc_enable_interrupts(struct target *target, int enable)
1226 {
1227         uint32_t value;
1228
1229         struct arc_common *arc = target_to_arc(target);
1230
1231         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
1232
1233         if (enable) {
1234                 /* enable interrupts */
1235                 value |= SET_CORE_ENABLE_INTERRUPTS;
1236                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1237                 LOG_DEBUG("interrupts enabled");
1238         } else {
1239                 /* disable interrupts */
1240                 value &= ~SET_CORE_ENABLE_INTERRUPTS;
1241                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1242                 LOG_DEBUG("interrupts disabled");
1243         }
1244
1245         return ERROR_OK;
1246 }
1247
1248 static int arc_resume(struct target *target, int current, target_addr_t address,
1249         int handle_breakpoints, int debug_execution)
1250 {
1251         struct arc_common *arc = target_to_arc(target);
1252         uint32_t resume_pc = 0;
1253         uint32_t value;
1254         struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache];
1255
1256         LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints(not supported yet):%i,"
1257                 " debug_execution:%i", current, address, handle_breakpoints, debug_execution);
1258
1259         /* We need to reset ARC cache variables so caches
1260          * would be invalidated and actual data
1261          * would be fetched from memory. */
1262         CHECK_RETVAL(arc_reset_caches_states(target));
1263
1264         if (target->state != TARGET_HALTED) {
1265                 LOG_WARNING("target not halted");
1266                 return ERROR_TARGET_NOT_HALTED;
1267         }
1268
1269         /* current = 1: continue on current PC, otherwise continue at <address> */
1270         if (!current) {
1271                 target_buffer_set_u32(target, pc->value, address);
1272                 pc->dirty = 1;
1273                 pc->valid = 1;
1274                 LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
1275         }
1276
1277         if (!current)
1278                 resume_pc = address;
1279         else
1280                 resume_pc = target_buffer_get_u32(target, pc->value);
1281
1282         CHECK_RETVAL(arc_restore_context(target));
1283
1284         LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
1285                 resume_pc, pc->dirty, pc->valid);
1286
1287         /* check if GDB tells to set our PC where to continue from */
1288         if ((pc->valid == 1) && (resume_pc == target_buffer_get_u32(target, pc->value))) {
1289                 value = target_buffer_get_u32(target, pc->value);
1290                 LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
1291                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
1292         }
1293
1294         /* Restore IRQ state if not in debug_execution*/
1295         if (!debug_execution)
1296                 CHECK_RETVAL(arc_enable_interrupts(target, arc->irq_state));
1297         else
1298                 CHECK_RETVAL(arc_enable_interrupts(target, !debug_execution));
1299
1300         target->debug_reason = DBG_REASON_NOTHALTED;
1301
1302         /* ready to get us going again */
1303         target->state = TARGET_RUNNING;
1304         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
1305         value &= ~SET_CORE_HALT_BIT;        /* clear the HALT bit */
1306         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1307         LOG_DEBUG("Core started to run");
1308
1309         /* registers are now invalid */
1310         register_cache_invalidate(arc->core_and_aux_cache);
1311
1312         if (!debug_execution) {
1313                 target->state = TARGET_RUNNING;
1314                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
1315                 LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc);
1316         } else {
1317                 target->state = TARGET_DEBUG_RUNNING;
1318                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED));
1319                 LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc);
1320         }
1321
1322         return ERROR_OK;
1323 }
1324
1325 static int arc_init_target(struct command_context *cmd_ctx, struct target *target)
1326 {
1327         CHECK_RETVAL(arc_build_reg_cache(target));
1328         CHECK_RETVAL(arc_build_bcr_reg_cache(target));
1329         target->debug_reason = DBG_REASON_DBGRQ;
1330         return ERROR_OK;
1331 }
1332
1333 static void arc_free_reg_cache(struct reg_cache *cache)
1334 {
1335         free(cache->reg_list);
1336         free(cache);
1337 }
1338
1339 static void arc_deinit_target(struct target *target)
1340 {
1341         struct arc_common *arc = target_to_arc(target);
1342
1343         LOG_DEBUG("deinitialization of target");
1344         if (arc->core_aux_cache_built)
1345                 arc_free_reg_cache(arc->core_and_aux_cache);
1346         if (arc->bcr_cache_built)
1347                 arc_free_reg_cache(arc->bcr_cache);
1348
1349         struct arc_reg_data_type *type, *n;
1350         struct arc_reg_desc *desc, *k;
1351
1352         /* Free arc-specific reg_data_types allocations*/
1353         list_for_each_entry_safe_reverse(type, n, &arc->reg_data_types, list) {
1354                 if (type->data_type.type_class == REG_TYPE_CLASS_STRUCT) {
1355                         free(type->reg_type_struct_field);
1356                         free(type->bitfields);
1357                         free(type);
1358                 }       else if (type->data_type.type_class == REG_TYPE_CLASS_FLAGS) {
1359                         free(type->reg_type_flags_field);
1360                         free(type->bitfields);
1361                         free(type);
1362                 }
1363         }
1364
1365         /* Free standard_gdb_types reg_data_types allocations */
1366         type = list_first_entry(&arc->reg_data_types, struct arc_reg_data_type, list);
1367         free(type);
1368
1369         list_for_each_entry_safe(desc, k, &arc->aux_reg_descriptions, list)
1370                 free_reg_desc(desc);
1371
1372         list_for_each_entry_safe(desc, k, &arc->core_reg_descriptions, list)
1373                 free_reg_desc(desc);
1374
1375         list_for_each_entry_safe(desc, k, &arc->bcr_reg_descriptions, list)
1376                 free_reg_desc(desc);
1377
1378         free(arc->actionpoints_list);
1379         free(arc);
1380 }
1381
1382
1383 static int arc_target_create(struct target *target, Jim_Interp *interp)
1384 {
1385         struct arc_common *arc = calloc(1, sizeof(*arc));
1386
1387         if (!arc) {
1388                 LOG_ERROR("Unable to allocate memory");
1389                 return ERROR_FAIL;
1390         }
1391
1392         LOG_DEBUG("Entering");
1393         CHECK_RETVAL(arc_init_arch_info(target, arc, target->tap));
1394
1395         return ERROR_OK;
1396 }
1397
1398 /**
1399  * Write 4-byte instruction to memory. This is like target_write_u32, however
1400  * in case of little endian ARC instructions are in middle endian format, not
1401  * little endian, so different type of conversion should be done.
1402  * Middle endian: instruction "aabbccdd", stored as "bbaaddcc"
1403  */
1404 static int arc_write_instruction_u32(struct target *target, uint32_t address,
1405         uint32_t instr)
1406 {
1407         uint8_t value_buf[4];
1408         if (!target_was_examined(target)) {
1409                 LOG_ERROR("Target not examined yet");
1410                 return ERROR_FAIL;
1411         }
1412
1413         LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
1414                 instr);
1415
1416         if (target->endianness == TARGET_LITTLE_ENDIAN)
1417                 arc_h_u32_to_me(value_buf, instr);
1418         else
1419                 h_u32_to_be(value_buf, instr);
1420
1421         CHECK_RETVAL(target_write_buffer(target, address, 4, value_buf));
1422
1423         return ERROR_OK;
1424 }
1425
1426 /**
1427  * Read 32-bit instruction from memory. It is like target_read_u32, however in
1428  * case of little endian ARC instructions are in middle endian format, so
1429  * different type of conversion should be done.
1430  */
1431 static int arc_read_instruction_u32(struct target *target, uint32_t address,
1432                 uint32_t *value)
1433 {
1434         uint8_t value_buf[4];
1435
1436         if (!target_was_examined(target)) {
1437                 LOG_ERROR("Target not examined yet");
1438                 return ERROR_FAIL;
1439         }
1440
1441         *value = 0;
1442         CHECK_RETVAL(target_read_buffer(target, address, 4, value_buf));
1443
1444         if (target->endianness == TARGET_LITTLE_ENDIAN)
1445                 *value = arc_me_to_h_u32(value_buf);
1446         else
1447                 *value = be_to_h_u32(value_buf);
1448
1449         LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
1450                 *value);
1451
1452         return ERROR_OK;
1453 }
1454
1455 /* Actionpoint mechanism allows to setup HW breakpoints
1456  * and watchpoints. Each actionpoint is controlled by
1457  * 3 aux registers: Actionpoint(AP) match mask(AP_AMM), AP match value(AP_AMV)
1458  * and AP control(AC).
1459  * This function is for setting/unsetting actionpoints:
1460  * at - actionpoint target: trigger on mem/reg access
1461  * tt - transaction type : trigger on r/w. */
1462 static int arc_configure_actionpoint(struct target *target, uint32_t ap_num,
1463         uint32_t match_value, uint32_t control_tt, uint32_t control_at)
1464 {
1465         struct arc_common *arc = target_to_arc(target);
1466
1467         if (control_tt != AP_AC_TT_DISABLE) {
1468
1469                 if (arc->actionpoints_num_avail < 1) {
1470                         LOG_ERROR("No free actionpoints, maximum amount is %u",
1471                                         arc->actionpoints_num);
1472                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1473                 }
1474
1475                 /* Names of register to set - 24 chars should be enough. Looks a little
1476                  * bit out-of-place for C code, but makes it aligned to the bigger
1477                  * concept of "ARC registers are defined in TCL" as far as possible.
1478                  */
1479                 char ap_amv_reg_name[24], ap_amm_reg_name[24], ap_ac_reg_name[24];
1480                 snprintf(ap_amv_reg_name, 24, "ap_amv%" PRIu32, ap_num);
1481                 snprintf(ap_amm_reg_name, 24, "ap_amm%" PRIu32, ap_num);
1482                 snprintf(ap_ac_reg_name, 24, "ap_ac%" PRIu32, ap_num);
1483                 CHECK_RETVAL(arc_set_register_value(target, ap_amv_reg_name,
1484                                          match_value));
1485                 CHECK_RETVAL(arc_set_register_value(target, ap_amm_reg_name, 0));
1486                 CHECK_RETVAL(arc_set_register_value(target, ap_ac_reg_name,
1487                                          control_tt | control_at));
1488                 arc->actionpoints_num_avail--;
1489         } else {
1490                 char ap_ac_reg_name[24];
1491                 snprintf(ap_ac_reg_name, 24, "ap_ac%" PRIu32, ap_num);
1492                 CHECK_RETVAL(arc_set_register_value(target, ap_ac_reg_name,
1493                                          AP_AC_TT_DISABLE));
1494                 arc->actionpoints_num_avail++;
1495         }
1496
1497         return ERROR_OK;
1498 }
1499
1500 static int arc_set_breakpoint(struct target *target,
1501                 struct breakpoint *breakpoint)
1502 {
1503         if (breakpoint->is_set) {
1504                 LOG_WARNING("breakpoint already set");
1505                 return ERROR_OK;
1506         }
1507
1508         if (breakpoint->type == BKPT_SOFT) {
1509                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
1510
1511                 if (breakpoint->length == 4) {
1512                         uint32_t verify = 0xffffffff;
1513
1514                         CHECK_RETVAL(target_read_buffer(target, breakpoint->address, breakpoint->length,
1515                                         breakpoint->orig_instr));
1516
1517                         CHECK_RETVAL(arc_write_instruction_u32(target, breakpoint->address,
1518                                         ARC_SDBBP_32));
1519
1520                         CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &verify));
1521
1522                         if (verify != ARC_SDBBP_32) {
1523                                 LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
1524                                                 " - check that memory is read/writable", breakpoint->address);
1525                                 return ERROR_FAIL;
1526                         }
1527                 } else if (breakpoint->length == 2) {
1528                         uint16_t verify = 0xffff;
1529
1530                         CHECK_RETVAL(target_read_buffer(target, breakpoint->address, breakpoint->length,
1531                                         breakpoint->orig_instr));
1532                         CHECK_RETVAL(target_write_u16(target, breakpoint->address, ARC_SDBBP_16));
1533
1534                         CHECK_RETVAL(target_read_u16(target, breakpoint->address, &verify));
1535                         if (verify != ARC_SDBBP_16) {
1536                                 LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
1537                                                 " - check that memory is read/writable", breakpoint->address);
1538                                 return ERROR_FAIL;
1539                         }
1540                 } else {
1541                         LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1542                         return ERROR_COMMAND_ARGUMENT_INVALID;
1543                 }
1544
1545                 breakpoint->is_set = true;
1546         } else if (breakpoint->type == BKPT_HARD) {
1547                 struct arc_common *arc = target_to_arc(target);
1548                 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1549                 unsigned int bp_num;
1550
1551                 for (bp_num = 0; bp_num < arc->actionpoints_num; bp_num++) {
1552                         if (!ap_list[bp_num].used)
1553                                 break;
1554                 }
1555
1556                 if (bp_num >= arc->actionpoints_num) {
1557                         LOG_ERROR("No free actionpoints, maximum amount is %u",
1558                                         arc->actionpoints_num);
1559                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1560                 }
1561
1562                 int retval = arc_configure_actionpoint(target, bp_num,
1563                                 breakpoint->address, AP_AC_TT_READWRITE, AP_AC_AT_INST_ADDR);
1564
1565                 if (retval == ERROR_OK) {
1566                         breakpoint_hw_set(breakpoint, bp_num);
1567                         ap_list[bp_num].used = 1;
1568                         ap_list[bp_num].bp_value = breakpoint->address;
1569                         ap_list[bp_num].type = ARC_AP_BREAKPOINT;
1570
1571                         LOG_DEBUG("bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
1572                                         breakpoint->unique_id, bp_num, ap_list[bp_num].bp_value);
1573                 }
1574
1575         } else {
1576                 LOG_DEBUG("ERROR: setting unknown breakpoint type");
1577                 return ERROR_FAIL;
1578         }
1579
1580         /* core instruction cache is now invalid. */
1581         CHECK_RETVAL(arc_cache_invalidate(target));
1582
1583         return ERROR_OK;
1584 }
1585
1586 static int arc_unset_breakpoint(struct target *target,
1587                 struct breakpoint *breakpoint)
1588 {
1589         int retval = ERROR_OK;
1590
1591         if (!breakpoint->is_set) {
1592                 LOG_WARNING("breakpoint not set");
1593                 return ERROR_OK;
1594         }
1595
1596         if (breakpoint->type == BKPT_SOFT) {
1597                 /* restore original instruction (kept in target endianness) */
1598                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
1599                 if (breakpoint->length == 4) {
1600                         uint32_t current_instr;
1601
1602                         /* check that user program has not modified breakpoint instruction */
1603                         CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &current_instr));
1604
1605                         if (current_instr == ARC_SDBBP_32) {
1606                                 retval = target_write_buffer(target, breakpoint->address,
1607                                         breakpoint->length, breakpoint->orig_instr);
1608                                 if (retval != ERROR_OK)
1609                                         return retval;
1610                         } else {
1611                                 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1612                                         " has been overwritten outside of debugger."
1613                                         "Expected: @0x%x, got: @0x%" PRIx32,
1614                                         breakpoint->address, ARC_SDBBP_32, current_instr);
1615                         }
1616                 } else if (breakpoint->length == 2) {
1617                         uint16_t current_instr;
1618
1619                         /* check that user program has not modified breakpoint instruction */
1620                         CHECK_RETVAL(target_read_u16(target, breakpoint->address, &current_instr));
1621                         if (current_instr == ARC_SDBBP_16) {
1622                                 retval = target_write_buffer(target, breakpoint->address,
1623                                         breakpoint->length, breakpoint->orig_instr);
1624                                 if (retval != ERROR_OK)
1625                                         return retval;
1626                         } else {
1627                                 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1628                                         " has been overwritten outside of debugger. "
1629                                         "Expected: 0x%04x, got: 0x%04" PRIx16,
1630                                         breakpoint->address, ARC_SDBBP_16, current_instr);
1631                         }
1632                 } else {
1633                         LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1634                         return ERROR_COMMAND_ARGUMENT_INVALID;
1635                 }
1636                 breakpoint->is_set = false;
1637
1638         }       else if (breakpoint->type == BKPT_HARD) {
1639                 struct arc_common *arc = target_to_arc(target);
1640                 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1641                 unsigned int bp_num = breakpoint->number;
1642
1643                 if (bp_num >= arc->actionpoints_num) {
1644                         LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
1645                                           bp_num, breakpoint->unique_id);
1646                         return ERROR_OK;
1647                 }
1648
1649                 retval = arc_configure_actionpoint(target, bp_num,
1650                                                 breakpoint->address, AP_AC_TT_DISABLE, AP_AC_AT_INST_ADDR);
1651
1652                 if (retval == ERROR_OK) {
1653                         breakpoint->is_set = false;
1654                         ap_list[bp_num].used = 0;
1655                         ap_list[bp_num].bp_value = 0;
1656
1657                         LOG_DEBUG("bpid: %" PRIu32 " - released actionpoint ID: %u",
1658                                         breakpoint->unique_id, bp_num);
1659                 }
1660         } else {
1661                         LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
1662                         return ERROR_FAIL;
1663         }
1664
1665         /* core instruction cache is now invalid. */
1666         CHECK_RETVAL(arc_cache_invalidate(target));
1667
1668         return retval;
1669 }
1670
1671
1672 static int arc_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1673 {
1674         if (target->state == TARGET_HALTED) {
1675                 return arc_set_breakpoint(target, breakpoint);
1676
1677         } else {
1678                 LOG_WARNING(" > core was not halted, please try again.");
1679                 return ERROR_TARGET_NOT_HALTED;
1680         }
1681 }
1682
1683 static int arc_remove_breakpoint(struct target *target,
1684         struct breakpoint *breakpoint)
1685 {
1686         if (target->state == TARGET_HALTED) {
1687                 if (breakpoint->is_set)
1688                         CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
1689         } else {
1690                 LOG_WARNING("target not halted");
1691                 return ERROR_TARGET_NOT_HALTED;
1692         }
1693
1694         return ERROR_OK;
1695 }
1696
1697 static void arc_reset_actionpoints(struct target *target)
1698 {
1699         struct arc_common *arc = target_to_arc(target);
1700         struct arc_actionpoint *ap_list = arc->actionpoints_list;
1701         struct breakpoint *next_b;
1702         struct watchpoint *next_w;
1703
1704         while (target->breakpoints) {
1705                 next_b = target->breakpoints->next;
1706                 arc_remove_breakpoint(target, target->breakpoints);
1707                 free(target->breakpoints->orig_instr);
1708                 free(target->breakpoints);
1709                 target->breakpoints = next_b;
1710         }
1711         while (target->watchpoints) {
1712                 next_w = target->watchpoints->next;
1713                 arc_remove_watchpoint(target, target->watchpoints);
1714                 free(target->watchpoints);
1715                 target->watchpoints = next_w;
1716         }
1717         for (unsigned int i = 0; i < arc->actionpoints_num; i++) {
1718                 if ((ap_list[i].used) && (ap_list[i].reg_address))
1719                         arc_remove_auxreg_actionpoint(target, ap_list[i].reg_address);
1720         }
1721 }
1722
1723 int arc_set_actionpoints_num(struct target *target, uint32_t ap_num)
1724 {
1725         LOG_DEBUG("target=%s actionpoints=%" PRIu32, target_name(target), ap_num);
1726         struct arc_common *arc = target_to_arc(target);
1727
1728         /* Make sure that there are no enabled actionpoints in target. */
1729         arc_reset_actionpoints(target);
1730
1731         /* Assume that all points have been removed from target.  */
1732         free(arc->actionpoints_list);
1733
1734         arc->actionpoints_num_avail = ap_num;
1735         arc->actionpoints_num = ap_num;
1736         /* calloc can be safely called when ncount == 0.  */
1737         arc->actionpoints_list = calloc(ap_num, sizeof(struct arc_actionpoint));
1738
1739         if (!arc->actionpoints_list) {
1740                 LOG_ERROR("Unable to allocate memory");
1741                 return ERROR_FAIL;
1742         }
1743         return ERROR_OK;
1744 }
1745
1746
1747 int arc_add_auxreg_actionpoint(struct target *target,
1748         uint32_t auxreg_addr, uint32_t transaction)
1749 {
1750         unsigned int ap_num = 0;
1751         int retval = ERROR_OK;
1752
1753         if (target->state != TARGET_HALTED)
1754                 return ERROR_TARGET_NOT_HALTED;
1755
1756         struct arc_common *arc = target_to_arc(target);
1757         struct arc_actionpoint *ap_list = arc->actionpoints_list;
1758
1759         while (ap_list[ap_num].used)
1760                 ap_num++;
1761
1762         if (ap_num >= arc->actionpoints_num) {
1763                 LOG_ERROR("No actionpoint free, maximum amount is %u",
1764                                 arc->actionpoints_num);
1765                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1766         }
1767
1768         retval =  arc_configure_actionpoint(target, ap_num,
1769                         auxreg_addr, transaction, AP_AC_AT_AUXREG_ADDR);
1770
1771         if (retval == ERROR_OK) {
1772                 ap_list[ap_num].used = 1;
1773                 ap_list[ap_num].reg_address = auxreg_addr;
1774         }
1775
1776         return retval;
1777 }
1778
1779 int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr)
1780 {
1781         int retval = ERROR_OK;
1782         bool ap_found = false;
1783         unsigned int ap_num = 0;
1784
1785         if (target->state != TARGET_HALTED)
1786                 return ERROR_TARGET_NOT_HALTED;
1787
1788         struct arc_common *arc = target_to_arc(target);
1789         struct arc_actionpoint *ap_list = arc->actionpoints_list;
1790
1791         while ((ap_list[ap_num].used) && (ap_num < arc->actionpoints_num)) {
1792                 if (ap_list[ap_num].reg_address == auxreg_addr) {
1793                         ap_found = true;
1794                         break;
1795                 }
1796                 ap_num++;
1797         }
1798
1799         if (ap_found) {
1800                 retval =  arc_configure_actionpoint(target, ap_num,
1801                                 auxreg_addr, AP_AC_TT_DISABLE, AP_AC_AT_AUXREG_ADDR);
1802
1803                 if (retval == ERROR_OK) {
1804                         ap_list[ap_num].used = 0;
1805                         ap_list[ap_num].bp_value = 0;
1806                 }
1807         } else {
1808                 LOG_ERROR("Register actionpoint not found");
1809         }
1810         return retval;
1811 }
1812
1813
1814 static int arc_set_watchpoint(struct target *target,
1815                 struct watchpoint *watchpoint)
1816 {
1817         unsigned int wp_num;
1818         struct arc_common *arc = target_to_arc(target);
1819         struct arc_actionpoint *ap_list = arc->actionpoints_list;
1820
1821         if (watchpoint->is_set) {
1822                 LOG_WARNING("watchpoint already set");
1823                 return ERROR_OK;
1824         }
1825
1826         for (wp_num = 0; wp_num < arc->actionpoints_num; wp_num++) {
1827                 if (!ap_list[wp_num].used)
1828                         break;
1829         }
1830
1831         if (wp_num >= arc->actionpoints_num) {
1832                 LOG_ERROR("No free actionpoints, maximum amount is %u",
1833                                 arc->actionpoints_num);
1834                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1835         }
1836
1837         if (watchpoint->length != 4) {
1838                 LOG_ERROR("Only watchpoints of length 4 are supported");
1839                 return ERROR_TARGET_UNALIGNED_ACCESS;
1840         }
1841
1842         int enable = AP_AC_TT_DISABLE;
1843         switch (watchpoint->rw) {
1844                 case WPT_READ:
1845                         enable = AP_AC_TT_READ;
1846                         break;
1847                 case WPT_WRITE:
1848                         enable = AP_AC_TT_WRITE;
1849                         break;
1850                 case WPT_ACCESS:
1851                         enable = AP_AC_TT_READWRITE;
1852                         break;
1853                 default:
1854                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
1855                         return ERROR_FAIL;
1856         }
1857
1858         int retval =  arc_configure_actionpoint(target, wp_num,
1859                                         watchpoint->address, enable, AP_AC_AT_MEMORY_ADDR);
1860
1861         if (retval == ERROR_OK) {
1862                 watchpoint_set(watchpoint, wp_num);
1863                 ap_list[wp_num].used = 1;
1864                 ap_list[wp_num].bp_value = watchpoint->address;
1865                 ap_list[wp_num].type = ARC_AP_WATCHPOINT;
1866
1867                 LOG_DEBUG("wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
1868                                 watchpoint->unique_id, wp_num, ap_list[wp_num].bp_value);
1869         }
1870
1871         return retval;
1872 }
1873
1874 static int arc_unset_watchpoint(struct target *target,
1875                 struct watchpoint *watchpoint)
1876 {
1877         /* get pointers to arch-specific information */
1878         struct arc_common *arc = target_to_arc(target);
1879         struct arc_actionpoint *ap_list = arc->actionpoints_list;
1880
1881         if (!watchpoint->is_set) {
1882                 LOG_WARNING("watchpoint not set");
1883                 return ERROR_OK;
1884         }
1885
1886         unsigned int wp_num = watchpoint->number;
1887         if (wp_num >= arc->actionpoints_num) {
1888                 LOG_DEBUG("Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
1889                                 wp_num, watchpoint->unique_id);
1890                 return ERROR_OK;
1891         }
1892
1893         int retval =  arc_configure_actionpoint(target, wp_num,
1894                                 watchpoint->address, AP_AC_TT_DISABLE, AP_AC_AT_MEMORY_ADDR);
1895
1896         if (retval == ERROR_OK) {
1897                 watchpoint->is_set = false;
1898                 ap_list[wp_num].used = 0;
1899                 ap_list[wp_num].bp_value = 0;
1900
1901                 LOG_DEBUG("wpid: %" PRIu32 " - releasing actionpoint ID: %u",
1902                                 watchpoint->unique_id, wp_num);
1903         }
1904
1905         return retval;
1906 }
1907
1908 static int arc_add_watchpoint(struct target *target,
1909         struct watchpoint *watchpoint)
1910 {
1911         if (target->state != TARGET_HALTED) {
1912                 LOG_WARNING("target not halted");
1913                 return ERROR_TARGET_NOT_HALTED;
1914         }
1915
1916         CHECK_RETVAL(arc_set_watchpoint(target, watchpoint));
1917
1918         return ERROR_OK;
1919 }
1920
1921 static int arc_remove_watchpoint(struct target *target,
1922         struct watchpoint *watchpoint)
1923 {
1924         if (target->state != TARGET_HALTED) {
1925                 LOG_WARNING("target not halted");
1926                 return ERROR_TARGET_NOT_HALTED;
1927         }
1928
1929         if (watchpoint->is_set)
1930                 CHECK_RETVAL(arc_unset_watchpoint(target, watchpoint));
1931
1932         return ERROR_OK;
1933 }
1934
1935 static int arc_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1936 {
1937         assert(target);
1938         assert(hit_watchpoint);
1939
1940         struct arc_actionpoint *actionpoint = NULL;
1941         CHECK_RETVAL(get_current_actionpoint(target, &actionpoint));
1942
1943         if (actionpoint) {
1944                 if (!actionpoint->used)
1945                         LOG_WARNING("Target halted by unused actionpoint.");
1946
1947                 /* If this check fails - that is some sort of an error in OpenOCD. */
1948                 if (actionpoint->type != ARC_AP_WATCHPOINT)
1949                         LOG_WARNING("Target halted by breakpoint, but is treated as a watchpoint.");
1950
1951                 for (struct watchpoint *watchpoint = target->watchpoints;
1952                                 watchpoint;
1953                                 watchpoint = watchpoint->next) {
1954                         if (actionpoint->bp_value == watchpoint->address) {
1955                                 *hit_watchpoint = watchpoint;
1956                                 LOG_DEBUG("Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u",
1957                                                         watchpoint->unique_id, watchpoint->number);
1958                                 return ERROR_OK;
1959                         }
1960                 }
1961         }
1962
1963         return ERROR_FAIL;
1964 }
1965
1966 /* Helper function which switches core to single_step mode by
1967  * doing aux r/w operations.  */
1968 static int arc_config_step(struct target *target, int enable_step)
1969 {
1970         uint32_t value;
1971
1972         struct arc_common *arc = target_to_arc(target);
1973
1974         /* enable core debug step mode */
1975         if (enable_step) {
1976                 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
1977                         &value));
1978                 value &= ~SET_CORE_AE_BIT; /* clear the AE bit */
1979                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
1980                         value));
1981                 LOG_DEBUG(" [status32:0x%08" PRIx32 "]", value);
1982
1983                 /* Doing read-modify-write, because DEBUG might contain manually set
1984                  * bits like UB or ED, which should be preserved.  */
1985                 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info,
1986                                         AUX_DEBUG_REG, &value));
1987                 value |= SET_CORE_SINGLE_INSTR_STEP; /* set the IS bit */
1988                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
1989                         value));
1990                 LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
1991
1992         } else {        /* disable core debug step mode */
1993                 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
1994                         &value));
1995                 value &= ~SET_CORE_SINGLE_INSTR_STEP; /* clear the IS bit */
1996                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
1997                         value));
1998                 LOG_DEBUG("core debug step mode disabled");
1999         }
2000
2001         return ERROR_OK;
2002 }
2003
2004 static int arc_step(struct target *target, int current, target_addr_t address,
2005         int handle_breakpoints)
2006 {
2007         /* get pointers to arch-specific information */
2008         struct arc_common *arc = target_to_arc(target);
2009         struct breakpoint *breakpoint = NULL;
2010         struct reg *pc = &(arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache]);
2011
2012         if (target->state != TARGET_HALTED) {
2013                 LOG_WARNING("target not halted");
2014                 return ERROR_TARGET_NOT_HALTED;
2015         }
2016
2017         /* current = 1: continue on current pc, otherwise continue at <address> */
2018         if (!current) {
2019                 buf_set_u32(pc->value, 0, 32, address);
2020                 pc->dirty = 1;
2021                 pc->valid = 1;
2022         }
2023
2024         LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32,
2025                 buf_get_u32(pc->value, 0, 32));
2026
2027         /* the front-end may request us not to handle breakpoints */
2028         if (handle_breakpoints) {
2029                 breakpoint = breakpoint_find(target, buf_get_u32(pc->value, 0, 32));
2030                 if (breakpoint)
2031                         CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
2032         }
2033
2034         /* restore context */
2035         CHECK_RETVAL(arc_restore_context(target));
2036
2037         target->debug_reason = DBG_REASON_SINGLESTEP;
2038
2039         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
2040
2041         /* disable interrupts while stepping */
2042         CHECK_RETVAL(arc_enable_interrupts(target, 0));
2043
2044         /* do a single step */
2045         CHECK_RETVAL(arc_config_step(target, 1));
2046
2047         /* make sure we done our step */
2048         alive_sleep(1);
2049
2050         /* registers are now invalid */
2051         register_cache_invalidate(arc->core_and_aux_cache);
2052
2053         if (breakpoint)
2054                 CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
2055
2056         LOG_DEBUG("target stepped ");
2057
2058         target->state = TARGET_HALTED;
2059
2060         /* Saving context */
2061         CHECK_RETVAL(arc_debug_entry(target));
2062         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
2063
2064         return ERROR_OK;
2065 }
2066
2067
2068 /* This function invalidates icache. */
2069 static int arc_icache_invalidate(struct target *target)
2070 {
2071         uint32_t value;
2072
2073         struct arc_common *arc = target_to_arc(target);
2074
2075         /* Don't waste time if already done. */
2076         if (!arc->has_icache || arc->icache_invalidated)
2077             return ERROR_OK;
2078
2079         LOG_DEBUG("Invalidating I$.");
2080
2081         value = IC_IVIC_INVALIDATE;     /* invalidate I$ */
2082         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value));
2083
2084         arc->icache_invalidated = true;
2085
2086         return ERROR_OK;
2087 }
2088
2089 /* This function invalidates dcache */
2090 static int arc_dcache_invalidate(struct target *target)
2091 {
2092         uint32_t value, dc_ctrl_value;
2093
2094         struct arc_common *arc = target_to_arc(target);
2095
2096         if (!arc->has_dcache || arc->dcache_invalidated)
2097             return ERROR_OK;
2098
2099         LOG_DEBUG("Invalidating D$.");
2100
2101         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value));
2102         dc_ctrl_value = value;
2103         value &= ~DC_CTRL_IM;
2104
2105         /* set DC_CTRL invalidate mode to invalidate-only (no flushing!!) */
2106         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
2107         value = DC_IVDC_INVALIDATE;     /* invalidate D$ */
2108         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
2109
2110         /* restore DC_CTRL invalidate mode */
2111         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
2112
2113         arc->dcache_invalidated = true;
2114
2115         return ERROR_OK;
2116 }
2117
2118 /* This function invalidates l2 cache. */
2119 static int arc_l2cache_invalidate(struct target *target)
2120 {
2121         uint32_t value, slc_ctrl_value;
2122
2123         struct arc_common *arc = target_to_arc(target);
2124
2125         if (!arc->has_l2cache || arc->l2cache_invalidated)
2126             return ERROR_OK;
2127
2128         LOG_DEBUG("Invalidating L2$.");
2129
2130         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
2131         slc_ctrl_value = value;
2132         value &= ~L2_CTRL_IM;
2133
2134         /* set L2_CTRL invalidate mode to invalidate-only (no flushing!!) */
2135         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, value));
2136         /* invalidate L2$ */
2137         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_INV, L2_INV_IV));
2138
2139         /* Wait until invalidate operation ends */
2140         do {
2141             LOG_DEBUG("Waiting for invalidation end.");
2142             CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
2143         } while (value & L2_CTRL_BS);
2144
2145         /* restore L2_CTRL invalidate mode */
2146         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, slc_ctrl_value));
2147
2148         arc->l2cache_invalidated = true;
2149
2150         return ERROR_OK;
2151 }
2152
2153
2154 int arc_cache_invalidate(struct target *target)
2155 {
2156         CHECK_RETVAL(arc_icache_invalidate(target));
2157         CHECK_RETVAL(arc_dcache_invalidate(target));
2158         CHECK_RETVAL(arc_l2cache_invalidate(target));
2159
2160         return ERROR_OK;
2161 }
2162
2163 /* Flush data cache. This function is cheap to call and return quickly if D$
2164  * already has been flushed since target had been halted. JTAG debugger reads
2165  * values directly from memory, bypassing cache, so if there are unflushed
2166  * lines debugger will read invalid values, which will cause a lot of troubles.
2167  * */
2168 static int arc_dcache_flush(struct target *target)
2169 {
2170         uint32_t value, dc_ctrl_value;
2171         bool has_to_set_dc_ctrl_im;
2172
2173         struct arc_common *arc = target_to_arc(target);
2174
2175         /* Don't waste time if already done. */
2176         if (!arc->has_dcache || arc->dcache_flushed)
2177             return ERROR_OK;
2178
2179         LOG_DEBUG("Flushing D$.");
2180
2181         /* Store current value of DC_CTRL */
2182         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value));
2183
2184         /* Set DC_CTRL invalidate mode to flush (if not already set) */
2185         has_to_set_dc_ctrl_im = (dc_ctrl_value & DC_CTRL_IM) == 0;
2186         if (has_to_set_dc_ctrl_im) {
2187                 value = dc_ctrl_value | DC_CTRL_IM;
2188                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
2189         }
2190
2191         /* Flush D$ */
2192         value = DC_IVDC_INVALIDATE;
2193         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
2194
2195         /* Restore DC_CTRL invalidate mode (even of flush failed) */
2196         if (has_to_set_dc_ctrl_im)
2197             CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
2198
2199         arc->dcache_flushed = true;
2200
2201         return ERROR_OK;
2202 }
2203
2204 /* This function flushes l2cache. */
2205 static int arc_l2cache_flush(struct target *target)
2206 {
2207         uint32_t value;
2208
2209         struct arc_common *arc = target_to_arc(target);
2210
2211         /* Don't waste time if already done. */
2212         if (!arc->has_l2cache || arc->l2cache_flushed)
2213             return ERROR_OK;
2214
2215         LOG_DEBUG("Flushing L2$.");
2216
2217         /* Flush L2 cache */
2218         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL));
2219
2220         /* Wait until flush operation ends */
2221         do {
2222             LOG_DEBUG("Waiting for flushing end.");
2223             CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
2224         } while (value & L2_CTRL_BS);
2225
2226         arc->l2cache_flushed = true;
2227
2228         return ERROR_OK;
2229 }
2230
2231 int arc_cache_flush(struct target *target)
2232 {
2233         CHECK_RETVAL(arc_dcache_flush(target));
2234         CHECK_RETVAL(arc_l2cache_flush(target));
2235
2236         return ERROR_OK;
2237 }
2238
2239 /* ARC v2 target */
2240 struct target_type arcv2_target = {
2241         .name = "arcv2",
2242
2243         .poll = arc_poll,
2244
2245         .arch_state = arc_arch_state,
2246
2247         /* TODO That seems like something similar to metaware hostlink, so perhaps
2248          * we can exploit this in the future. */
2249         .target_request_data = NULL,
2250
2251         .halt = arc_halt,
2252         .resume = arc_resume,
2253         .step = arc_step,
2254
2255         .assert_reset = arc_assert_reset,
2256         .deassert_reset = arc_deassert_reset,
2257
2258         /* TODO Implement soft_reset_halt */
2259         .soft_reset_halt = NULL,
2260
2261         .get_gdb_reg_list = arc_get_gdb_reg_list,
2262
2263         .read_memory = arc_mem_read,
2264         .write_memory = arc_mem_write,
2265         .checksum_memory = NULL,
2266         .blank_check_memory = NULL,
2267
2268         .add_breakpoint = arc_add_breakpoint,
2269         .add_context_breakpoint = NULL,
2270         .add_hybrid_breakpoint = NULL,
2271         .remove_breakpoint = arc_remove_breakpoint,
2272         .add_watchpoint = arc_add_watchpoint,
2273         .remove_watchpoint = arc_remove_watchpoint,
2274         .hit_watchpoint = arc_hit_watchpoint,
2275
2276         .run_algorithm = NULL,
2277         .start_algorithm = NULL,
2278         .wait_algorithm = NULL,
2279
2280         .commands = arc_monitor_command_handlers,
2281
2282         .target_create = arc_target_create,
2283         .init_target = arc_init_target,
2284         .deinit_target = arc_deinit_target,
2285         .examine = arc_examine,
2286
2287         .virt2phys = NULL,
2288         .read_phys_memory = NULL,
2289         .write_phys_memory = NULL,
2290         .mmu = NULL,
2291 };