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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2017 by Square, Inc.                                    *
   5  *   Steven Stallion <stallion@squareup.com>                               *
   6  ***************************************************************************/
   7
   8 #ifdef HAVE_CONFIG_H
   9 #include "config.h"
  10 #endif
  11
  12 #include <helper/types.h>
  13 #include <rtos/rtos.h>
  14 #include <rtos/rtos_standard_stackings.h>
  15 #include <target/armv7m.h>
  16 #include <target/esirisc.h>
  17
  18 static const struct stack_register_offset rtos_ucos_iii_cortex_m_stack_offsets[] = {
  19         { ARMV7M_R0,   0x20, 32 },      /* r0   */
  20         { ARMV7M_R1,   0x24, 32 },      /* r1   */
  21         { ARMV7M_R2,   0x28, 32 },      /* r2   */
  22         { ARMV7M_R3,   0x2c, 32 },      /* r3   */
  23         { ARMV7M_R4,   0x00, 32 },      /* r4   */
  24         { ARMV7M_R5,   0x04, 32 },      /* r5   */
  25         { ARMV7M_R6,   0x08, 32 },      /* r6   */
  26         { ARMV7M_R7,   0x0c, 32 },      /* r7   */
  27         { ARMV7M_R8,   0x10, 32 },      /* r8   */
  28         { ARMV7M_R9,   0x14, 32 },      /* r9   */
  29         { ARMV7M_R10,  0x18, 32 },      /* r10  */
  30         { ARMV7M_R11,  0x1c, 32 },      /* r11  */
  31         { ARMV7M_R12,  0x30, 32 },      /* r12  */
  32         { ARMV7M_R13,  -2,   32 },      /* sp   */
  33         { ARMV7M_R14,  0x34, 32 },      /* lr   */
  34         { ARMV7M_PC,   0x38, 32 },      /* pc   */
  35         { ARMV7M_xPSR, 0x3c, 32 },      /* xPSR */
  36 };
  37
  38 static const struct stack_register_offset rtos_ucos_iii_esi_risc_stack_offsets[] = {
  39         { ESIRISC_SP,  -2,   32 },      /* sp   */
  40         { ESIRISC_RA,  0x48, 32 },      /* ra   */
  41         { ESIRISC_R2,  0x44, 32 },      /* r2   */
  42         { ESIRISC_R3,  0x40, 32 },      /* r3   */
  43         { ESIRISC_R4,  0x3c, 32 },      /* r4   */
  44         { ESIRISC_R5,  0x38, 32 },      /* r5   */
  45         { ESIRISC_R6,  0x34, 32 },      /* r6   */
  46         { ESIRISC_R7,  0x30, 32 },      /* r7   */
  47         { ESIRISC_R8,  0x2c, 32 },      /* r8   */
  48         { ESIRISC_R9,  0x28, 32 },      /* r9   */
  49         { ESIRISC_R10, 0x24, 32 },      /* r10  */
  50         { ESIRISC_R11, 0x20, 32 },      /* r11  */
  51         { ESIRISC_R12, 0x1c, 32 },      /* r12  */
  52         { ESIRISC_R13, 0x18, 32 },      /* r13  */
  53         { ESIRISC_R14, 0x14, 32 },      /* r14  */
  54         { ESIRISC_R15, 0x10, 32 },      /* r15  */
  55         { ESIRISC_PC,  0x04, 32 },      /* PC   */
  56         { ESIRISC_CAS, 0x08, 32 },      /* CAS  */
  57 };
  58
  59 const struct rtos_register_stacking rtos_ucos_iii_cortex_m_stacking = {
  60         .stack_registers_size = 0x40,
  61         .stack_growth_direction = -1,
  62         .num_output_registers = ARRAY_SIZE(rtos_ucos_iii_cortex_m_stack_offsets),
  63         .calculate_process_stack = rtos_generic_stack_align8,
  64         .register_offsets = rtos_ucos_iii_cortex_m_stack_offsets
  65 };
  66
  67 const struct rtos_register_stacking rtos_ucos_iii_esi_risc_stacking = {
  68         .stack_registers_size = 0x4c,
  69         .stack_growth_direction = -1,
  70         .num_output_registers = ARRAY_SIZE(rtos_ucos_iii_esi_risc_stack_offsets),
  71         .register_offsets = rtos_ucos_iii_esi_risc_stack_offsets
  72 };