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   1 /***************************************************************************
   2  *   Copyright (C) 2017 by Square, Inc.                                    *
   3  *   Steven Stallion <stallion@squareup.com>                               *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifdef HAVE_CONFIG_H
  20 #include "config.h"
  21 #endif
  22
  23 #include <helper/types.h>
  24 #include <rtos/rtos.h>
  25 #include <rtos/rtos_standard_stackings.h>
  26 #include <target/armv7m.h>
  27 #include <target/esirisc.h>
  28
  29 static const struct stack_register_offset rtos_ucos_iii_cortex_m_stack_offsets[] = {
  30         { ARMV7M_R0,   0x20, 32 },      /* r0   */
  31         { ARMV7M_R1,   0x24, 32 },      /* r1   */
  32         { ARMV7M_R2,   0x28, 32 },      /* r2   */
  33         { ARMV7M_R3,   0x2c, 32 },      /* r3   */
  34         { ARMV7M_R4,   0x00, 32 },      /* r4   */
  35         { ARMV7M_R5,   0x04, 32 },      /* r5   */
  36         { ARMV7M_R6,   0x08, 32 },      /* r6   */
  37         { ARMV7M_R7,   0x0c, 32 },      /* r7   */
  38         { ARMV7M_R8,   0x10, 32 },      /* r8   */
  39         { ARMV7M_R9,   0x14, 32 },      /* r9   */
  40         { ARMV7M_R10,  0x18, 32 },      /* r10  */
  41         { ARMV7M_R11,  0x1c, 32 },      /* r11  */
  42         { ARMV7M_R12,  0x30, 32 },      /* r12  */
  43         { ARMV7M_R13,  -2,   32 },      /* sp   */
  44         { ARMV7M_R14,  0x34, 32 },      /* lr   */
  45         { ARMV7M_PC,   0x38, 32 },      /* pc   */
  46         { ARMV7M_xPSR, 0x3c, 32 },      /* xPSR */
  47 };
  48
  49 static const struct stack_register_offset rtos_ucos_iii_esi_risc_stack_offsets[] = {
  50         { ESIRISC_SP,  -2,   32 },      /* sp   */
  51         { ESIRISC_RA,  0x48, 32 },      /* ra   */
  52         { ESIRISC_R2,  0x44, 32 },      /* r2   */
  53         { ESIRISC_R3,  0x40, 32 },      /* r3   */
  54         { ESIRISC_R4,  0x3c, 32 },      /* r4   */
  55         { ESIRISC_R5,  0x38, 32 },      /* r5   */
  56         { ESIRISC_R6,  0x34, 32 },      /* r6   */
  57         { ESIRISC_R7,  0x30, 32 },      /* r7   */
  58         { ESIRISC_R8,  0x2c, 32 },      /* r8   */
  59         { ESIRISC_R9,  0x28, 32 },      /* r9   */
  60         { ESIRISC_R10, 0x24, 32 },      /* r10  */
  61         { ESIRISC_R11, 0x20, 32 },      /* r11  */
  62         { ESIRISC_R12, 0x1c, 32 },      /* r12  */
  63         { ESIRISC_R13, 0x18, 32 },      /* r13  */
  64         { ESIRISC_R14, 0x14, 32 },      /* r14  */
  65         { ESIRISC_R15, 0x10, 32 },      /* r15  */
  66         { ESIRISC_PC,  0x04, 32 },      /* PC   */
  67         { ESIRISC_CAS, 0x08, 32 },      /* CAS  */
  68 };
  69
  70 const struct rtos_register_stacking rtos_ucos_iii_cortex_m_stacking = {
  71         .stack_registers_size = 0x40,
  72         .stack_growth_direction = -1,
  73         .num_output_registers = ARRAY_SIZE(rtos_ucos_iii_cortex_m_stack_offsets),
  74         .calculate_process_stack = rtos_generic_stack_align8,
  75         .register_offsets = rtos_ucos_iii_cortex_m_stack_offsets
  76 };
  77
  78 const struct rtos_register_stacking rtos_ucos_iii_esi_risc_stacking = {
  79         .stack_registers_size = 0x4c,
  80         .stack_growth_direction = -1,
  81         .num_output_registers = ARRAY_SIZE(rtos_ucos_iii_esi_risc_stack_offsets),
  82         .register_offsets = rtos_ucos_iii_esi_risc_stack_offsets
  83 };