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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2012 by Matthias Blaicher                               *
   5  *   Matthias Blaicher - matthias@blaicher.com                             *
   6  *                                                                         *
   7  *   Copyright (C) 2011 by Broadcom Corporation                            *
   8  *   Evan Hunter - ehunter@broadcom.com                                    *
   9  ***************************************************************************/
  10
  11 #ifdef HAVE_CONFIG_H
  12 #include "config.h"
  13 #endif
  14
  15 #include "rtos.h"
  16 #include "target/armv7m.h"
  17
  18 static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
  19         { ARMV7M_R0,   -1,   32 },              /* r0   */
  20         { ARMV7M_R1,   -1,   32 },              /* r1   */
  21         { ARMV7M_R2,   -1,   32 },              /* r2   */
  22         { ARMV7M_R3,   -1,   32 },              /* r3   */
  23         { ARMV7M_R4,   0x00, 32 },              /* r4   */
  24         { ARMV7M_R5,   0x04, 32 },              /* r5   */
  25         { ARMV7M_R6,   0x08, 32 },              /* r6   */
  26         { ARMV7M_R7,   0x0c, 32 },              /* r7   */
  27         { ARMV7M_R8,   0x10, 32 },              /* r8   */
  28         { ARMV7M_R9,   0x14, 32 },              /* r9   */
  29         { ARMV7M_R10,  0x18, 32 },              /* r10  */
  30         { ARMV7M_R11,  0x1c, 32 },              /* r11  */
  31         { ARMV7M_R12,  -1,   32 },              /* r12  */
  32         { ARMV7M_R13,  -2,   32 },              /* sp   */
  33         { ARMV7M_R14,  -1,   32 },              /* lr   */
  34         { ARMV7M_PC,   0x20, 32 },              /* pc   */
  35         { ARMV7M_XPSR, -1,   32 },              /* xPSR */
  36 };
  37
  38 const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking = {
  39         .stack_registers_size = 0x24,
  40         .stack_growth_direction = -1,
  41         .num_output_registers = ARMV7M_NUM_CORE_REGS,
  42         .register_offsets = rtos_chibios_arm_v7m_stack_offsets
  43 };
  44
  45 static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets_w_fpu[ARMV7M_NUM_CORE_REGS] = {
  46         { ARMV7M_R0,   -1,   32 },              /* r0   */
  47         { ARMV7M_R1,   -1,   32 },              /* r1   */
  48         { ARMV7M_R2,   -1,   32 },              /* r2   */
  49         { ARMV7M_R3,   -1,   32 },              /* r3   */
  50         { ARMV7M_R4,   0x40, 32 },              /* r4   */
  51         { ARMV7M_R5,   0x44, 32 },              /* r5   */
  52         { ARMV7M_R6,   0x48, 32 },              /* r6   */
  53         { ARMV7M_R7,   0x4c, 32 },              /* r7   */
  54         { ARMV7M_R8,   0x50, 32 },              /* r8   */
  55         { ARMV7M_R9,   0x54, 32 },              /* r9   */
  56         { ARMV7M_R10,  0x58, 32 },              /* r10  */
  57         { ARMV7M_R11,  0x5c, 32 },              /* r11  */
  58         { ARMV7M_R12,  -1,   32 },              /* r12  */
  59         { ARMV7M_R13,  -2,   32 },              /* sp   */
  60         { ARMV7M_R14,  -1,   32 },              /* lr   */
  61         { ARMV7M_PC,   0x60, 32 },              /* pc   */
  62         { ARMV7M_XPSR, -1,   32 },              /* xPSR */
  63 };
  64
  65 const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking_w_fpu = {
  66         .stack_registers_size = 0x64,
  67         .stack_growth_direction = -1,
  68         .num_output_registers = ARMV7M_NUM_CORE_REGS,
  69         .register_offsets = rtos_chibios_arm_v7m_stack_offsets_w_fpu
  70 };