1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
23 #include <target/nds32_edm.h>
25 #define AICE_MAX_NUM_CORE (0x10)
27 #define ERROR_AICE_DISCONNECT (-200)
28 #define ERROR_AICE_TIMEOUT (-201)
30 enum aice_target_state_s {
37 AICE_TARGET_DEBUG_RUNNING,
40 enum aice_srst_type_s {
42 AICE_RESET_HOLD = 0x8,
45 enum aice_target_endian {
46 AICE_LITTLE_ENDIAN = 0,
77 AICE_SET_COMMAND_MODE,
79 AICE_SET_CUSTOM_SRST_SCRIPT,
80 AICE_SET_CUSTOM_TRST_SCRIPT,
81 AICE_SET_CUSTOM_RESTART_SCRIPT,
82 AICE_SET_COUNT_TO_CHECK_DBGER,
92 enum aice_cache_ctl_type {
93 AICE_CACHE_CTL_L1D_INVALALL = 0,
94 AICE_CACHE_CTL_L1D_VA_INVAL,
95 AICE_CACHE_CTL_L1D_WBALL,
96 AICE_CACHE_CTL_L1D_VA_WB,
97 AICE_CACHE_CTL_L1I_INVALALL,
98 AICE_CACHE_CTL_L1I_VA_INVAL,
101 enum aice_command_mode {
102 AICE_COMMAND_MODE_NORMAL,
103 AICE_COMMAND_MODE_PACK,
104 AICE_COMMAND_MODE_BATCH,
107 struct aice_port_param_s {
109 const char *device_desc;
124 const struct aice_port *port;
128 extern struct aice_port_api_s aice_usb_layout_api;
131 struct aice_port_api_s {
133 int (*open)(struct aice_port_param_s *param);
139 int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
141 int (*set_jtag_clock)(uint32_t a_clock);
143 int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
145 int (*run)(uint32_t coreid);
147 int (*halt)(uint32_t coreid);
149 int (*step)(uint32_t coreid);
151 int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
153 int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
155 int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
157 int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
159 int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
160 uint32_t count, uint8_t *buffer);
162 int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
163 uint32_t count, const uint8_t *buffer);
165 int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
168 int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
169 const uint8_t *buffer);
171 int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
173 int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
176 int (*state)(uint32_t coreid, enum aice_target_state_s *state);
179 int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
181 int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
184 int (*read_tlb)(uint32_t coreid, uint32_t virtual_address, uint32_t *physical_address);
187 int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
190 int (*set_retry_times)(uint32_t a_retry_times);
193 int (*program_edm)(uint32_t coreid, char *command_sequence);
196 int (*set_command_mode)(enum aice_command_mode command_mode);
199 int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
202 int (*set_custom_srst_script)(const char *script);
205 int (*set_custom_trst_script)(const char *script);
208 int (*set_custom_restart_script)(const char *script);
211 int (*set_count_to_check_dbger)(uint32_t count_to_check);
214 int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
217 int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
218 uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
221 #define AICE_PORT_UNKNOWN 0
222 #define AICE_PORT_AICE_USB 1
223 #define AICE_PORT_AICE_PIPE 2
232 struct aice_port_api_s *const api;
236 const struct aice_port *aice_port_get_list(void);