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   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 /* STM Serial Memory Interface (SMI) controller is a SPI bus controller
  21  * specifically designed for SPI memories.
  22  * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
  23  * Two working modes are available:
  24  * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
  25  *   on the bus.
  26  * - HW mode: the SPI but is under SMI control. Memory content is directly
  27  *   accessible in CPU memory space. CPU can read, write and execute memory
  28  *   content. */
  29
  30 /* ATTENTION:
  31  * To have flash memory mapped in CPU memory space, the SMI controller
  32  * have to be in "HW mode". This requires following constraints:
  33  * 1) The command "reset init" have to initialize SMI controller and put
  34  *    it in HW mode;
  35  * 2) every command in this file have to return to prompt in HW mode. */
  36
  37 #ifdef HAVE_CONFIG_H
  38 #include "config.h"
  39 #endif
  40
  41 #include "imp.h"
  42 #include "spi.h"
  43 #include <jtag/jtag.h>
  44 #include <helper/time_support.h>
  45
  46 #define SMI_READ_REG(a) (_SMI_READ_REG(a))
  47 #define _SMI_READ_REG(a)                        \
  48 {                                                                       \
  49         int __a;                                                \
  50         uint32_t __v;                                   \
  51                                                                         \
  52         __a = target_read_u32(target, io_base + (a), &__v); \
  53         if (__a != ERROR_OK)                    \
  54                 return __a;                                     \
  55         __v;                                                    \
  56 }
  57
  58 #define SMI_WRITE_REG(a, v)                     \
  59 {                                                                       \
  60         int __r;                                                \
  61                                                                         \
  62         __r = target_write_u32(target, io_base + (a), (v)); \
  63         if (__r != ERROR_OK)                    \
  64                 return __r;                                     \
  65 }
  66
  67 #define SMI_POLL_TFF(timeout)           \
  68 {                                                                       \
  69         int __r;                                                \
  70                                                                         \
  71         __r = poll_tff(target, io_base, timeout); \
  72         if (__r != ERROR_OK)                    \
  73                 return __r;                                     \
  74 }
  75
  76 #define SMI_SET_SW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  77         SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
  78 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
  79         (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
  80 #define SMI_SET_HW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  81         SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
  82 #define SMI_CLEAR_TFF()         SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
  83
  84 #define SMI_BANK_SIZE      (0x01000000)
  85
  86 #define SMI_CR1 (0x00) /* Control register 1 */
  87 #define SMI_CR2 (0x04) /* Control register 2 */
  88 #define SMI_SR  (0x08) /* Status register */
  89 #define SMI_TR  (0x0c) /* TX */
  90 #define SMI_RR  (0x10) /* RX */
  91
  92 /* fields in SMI_CR1 */
  93 #define SMI_SW_MODE       0x10000000 /* set to enable SW Mode */
  94 #define SMI_WB_MODE       0x20000000 /* Write Burst Mode */
  95
  96 /* fields in SMI_CR2 */
  97 #define SMI_TX_LEN_1      0x00000001 /* data length = 1 byte */
  98 #define SMI_TX_LEN_4      0x00000004 /* data length = 4 byte */
  99 #define SMI_RX_LEN_3      0x00000030 /* data length = 3 byte */
 100 #define SMI_SEND          0x00000080 /* Send data */
 101 #define SMI_RSR           0x00000400 /* reads status reg */
 102 #define SMI_WE            0x00000800 /* Write Enable */
 103 #define SMI_SEL_BANK0     0x00000000 /* Select Bank0 */
 104 #define SMI_SEL_BANK1     0x00001000 /* Select Bank1 */
 105 #define SMI_SEL_BANK2     0x00002000 /* Select Bank2 */
 106 #define SMI_SEL_BANK3     0x00003000 /* Select Bank3 */
 107
 108 /* fields in SMI_SR */
 109 #define SMI_TFF           0x00000100 /* Transfer Finished Flag */
 110
 111 /* Commands */
 112 #define SMI_READ_ID       0x0000009F /* Read Flash Identification */
 113
 114 /* Timeout in ms */
 115 #define SMI_CMD_TIMEOUT   (100)
 116 #define SMI_PROBE_TIMEOUT (100)
 117 #define SMI_MAX_TIMEOUT  (3000)
 118
 119 struct stmsmi_flash_bank {
 120         int probed;
 121         uint32_t io_base;
 122         uint32_t bank_num;
 123         struct flash_device *dev;
 124 };
 125
 126 struct stmsmi_target {
 127         char *name;
 128         uint32_t tap_idcode;
 129         uint32_t smi_base;
 130         uint32_t io_base;
 131 };
 132
 133 static struct stmsmi_target target_devices[] = {
 134         /* name,          tap_idcode, smi_base,   io_base */
 135         { "SPEAr3xx/6xx", 0x07926041, 0xf8000000, 0xfc000000 },
 136         { "STR75x",       0x4f1f0041, 0x80000000, 0x90000000 },
 137         { NULL,           0,          0,          0 }
 138 };
 139
 140 FLASH_BANK_COMMAND_HANDLER(stmsmi_flash_bank_command)
 141 {
 142         struct stmsmi_flash_bank *stmsmi_info;
 143
 144         LOG_DEBUG("%s", __func__);
 145
 146         if (CMD_ARGC < 6)
 147                 return ERROR_COMMAND_SYNTAX_ERROR;
 148
 149         stmsmi_info = malloc(sizeof(struct stmsmi_flash_bank));
 150         if (stmsmi_info == NULL) {
 151                 LOG_ERROR("not enough memory");
 152                 return ERROR_FAIL;
 153         }
 154
 155         bank->driver_priv = stmsmi_info;
 156         stmsmi_info->probed = 0;
 157
 158         return ERROR_OK;
 159 }
 160
 161 /* Poll transmit finished flag */
 162 /* timeout in ms */
 163 static int poll_tff(struct target *target, uint32_t io_base, int timeout)
 164 {
 165         long long endtime;
 166
 167         if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 168                 return ERROR_OK;
 169
 170         endtime = timeval_ms() + timeout;
 171         do {
 172                 alive_sleep(1);
 173                 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 174                         return ERROR_OK;
 175         } while (timeval_ms() < endtime);
 176
 177         LOG_ERROR("Timeout while polling TFF");
 178         return ERROR_FLASH_OPERATION_FAILED;
 179 }
 180
 181 /* Read the status register of the external SPI flash chip.
 182  * The operation is triggered by setting SMI_RSR bit.
 183  * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
 184 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
 185 {
 186         struct target *target = bank->target;
 187         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 188         uint32_t io_base = stmsmi_info->io_base;
 189
 190         /* clear transmit finished flag */
 191         SMI_CLEAR_TFF();
 192
 193         /* Read status */
 194         SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_RSR);
 195
 196         /* Poll transmit finished flag */
 197         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 198
 199         /* clear transmit finished flag */
 200         SMI_CLEAR_TFF();
 201
 202         *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
 203
 204         /* clean-up SMI_CR2 */
 205         SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
 206
 207         return ERROR_OK;
 208 }
 209
 210 /* check for WIP (write in progress) bit in status register */
 211 /* timeout in ms */
 212 static int wait_till_ready(struct flash_bank *bank, int timeout)
 213 {
 214         uint32_t status;
 215         int retval;
 216         long long endtime;
 217
 218         endtime = timeval_ms() + timeout;
 219         do {
 220                 /* read flash status register */
 221                 retval = read_status_reg(bank, &status);
 222                 if (retval != ERROR_OK)
 223                         return retval;
 224
 225                 if ((status & SPIFLASH_BSY_BIT) == 0)
 226                         return ERROR_OK;
 227                 alive_sleep(1);
 228         } while (timeval_ms() < endtime);
 229
 230         LOG_ERROR("timeout");
 231         return ERROR_FAIL;
 232 }
 233
 234 /* Send "write enable" command to SPI flash chip.
 235  * The operation is triggered by setting SMI_WE bit, and SMI sends
 236  * the proper SPI command (0x06) */
 237 static int smi_write_enable(struct flash_bank *bank)
 238 {
 239         struct target *target = bank->target;
 240         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 241         uint32_t io_base = stmsmi_info->io_base;
 242         uint32_t status;
 243         int retval;
 244
 245         /* Enter in HW mode */
 246         SMI_SET_HW_MODE(); /* AB: is this correct ?*/
 247
 248         /* clear transmit finished flag */
 249         SMI_CLEAR_TFF();
 250
 251         /* Send write enable command */
 252         SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_WE);
 253
 254         /* Poll transmit finished flag */
 255         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 256
 257         /* read flash status register */
 258         retval = read_status_reg(bank, &status);
 259         if (retval != ERROR_OK)
 260                 return retval;
 261
 262         /* Check write enabled */
 263         if ((status & SPIFLASH_WE_BIT) == 0) {
 264                 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
 265                 return ERROR_FAIL;
 266         }
 267
 268         return ERROR_OK;
 269 }
 270
 271 static uint32_t erase_command(struct stmsmi_flash_bank *stmsmi_info,
 272         uint32_t offset)
 273 {
 274         union {
 275                 uint32_t command;
 276                 uint8_t x[4];
 277         } cmd;
 278
 279         cmd.x[0] = stmsmi_info->dev->erase_cmd;
 280         cmd.x[1] = offset >> 16;
 281         cmd.x[2] = offset >> 8;
 282         cmd.x[3] = offset;
 283
 284         return cmd.command;
 285 }
 286
 287 static int smi_erase_sector(struct flash_bank *bank, int sector)
 288 {
 289         struct target *target = bank->target;
 290         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 291         uint32_t io_base = stmsmi_info->io_base;
 292         uint32_t cmd;
 293         int retval;
 294
 295         retval = smi_write_enable(bank);
 296         if (retval != ERROR_OK)
 297                 return retval;
 298
 299         /* Switch to SW mode to send sector erase command */
 300         SMI_SET_SW_MODE();
 301
 302         /* clear transmit finished flag */
 303         SMI_CLEAR_TFF();
 304
 305         /* send SPI command "block erase" */
 306         cmd = erase_command(stmsmi_info, bank->sectors[sector].offset);
 307         SMI_WRITE_REG(SMI_TR, cmd);
 308         SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
 309
 310         /* Poll transmit finished flag */
 311         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 312
 313         /* poll WIP for end of self timed Sector Erase cycle */
 314         retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
 315         if (retval != ERROR_OK)
 316                 return retval;
 317
 318         return ERROR_OK;
 319 }
 320
 321 static int stmsmi_erase(struct flash_bank *bank, int first, int last)
 322 {
 323         struct target *target = bank->target;
 324         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 325         uint32_t io_base = stmsmi_info->io_base;
 326         int retval = ERROR_OK;
 327         int sector;
 328
 329         LOG_DEBUG("%s: from sector %d to sector %d", __func__, first, last);
 330
 331         if (target->state != TARGET_HALTED) {
 332                 LOG_ERROR("Target not halted");
 333                 return ERROR_TARGET_NOT_HALTED;
 334         }
 335
 336         if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
 337                 LOG_ERROR("Flash sector invalid");
 338                 return ERROR_FLASH_SECTOR_INVALID;
 339         }
 340
 341         if (!(stmsmi_info->probed)) {
 342                 LOG_ERROR("Flash bank not probed");
 343                 return ERROR_FLASH_BANK_NOT_PROBED;
 344         }
 345
 346         for (sector = first; sector <= last; sector++) {
 347                 if (bank->sectors[sector].is_protected) {
 348                         LOG_ERROR("Flash sector %d protected", sector);
 349                         return ERROR_FAIL;
 350                 }
 351         }
 352
 353         for (sector = first; sector <= last; sector++) {
 354                 retval = smi_erase_sector(bank, sector);
 355                 if (retval != ERROR_OK)
 356                         break;
 357                 keep_alive();
 358         }
 359
 360         /* Switch to HW mode before return to prompt */
 361         SMI_SET_HW_MODE();
 362         return retval;
 363 }
 364
 365 static int stmsmi_protect(struct flash_bank *bank, int set,
 366         int first, int last)
 367 {
 368         int sector;
 369
 370         for (sector = first; sector <= last; sector++)
 371                 bank->sectors[sector].is_protected = set;
 372         return ERROR_OK;
 373 }
 374
 375 static int smi_write_buffer(struct flash_bank *bank, uint8_t *buffer,
 376         uint32_t address, uint32_t len)
 377 {
 378         struct target *target = bank->target;
 379         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 380         uint32_t io_base = stmsmi_info->io_base;
 381         int retval;
 382
 383         LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
 384                         __func__, address, len);
 385
 386         retval = smi_write_enable(bank);
 387         if (retval != ERROR_OK)
 388                 return retval;
 389
 390         /* HW mode, write burst mode */
 391         SMI_SET_HWWB_MODE();
 392
 393         retval = target_write_buffer(target, address, len, buffer);
 394         if (retval != ERROR_OK)
 395                 return retval;
 396
 397         return ERROR_OK;
 398 }
 399
 400 static int stmsmi_write(struct flash_bank *bank, uint8_t *buffer,
 401         uint32_t offset, uint32_t count)
 402 {
 403         struct target *target = bank->target;
 404         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 405         uint32_t io_base = stmsmi_info->io_base;
 406         uint32_t cur_count, page_size, page_offset;
 407         int sector;
 408         int retval = ERROR_OK;
 409
 410         LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
 411                 __func__, offset, count);
 412
 413         if (target->state != TARGET_HALTED) {
 414                 LOG_ERROR("Target not halted");
 415                 return ERROR_TARGET_NOT_HALTED;
 416         }
 417
 418         if (offset + count > stmsmi_info->dev->size_in_bytes) {
 419                 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
 420                 count = stmsmi_info->dev->size_in_bytes - offset;
 421         }
 422
 423         /* Check sector protection */
 424         for (sector = 0; sector < bank->num_sectors; sector++) {
 425                 /* Start offset in or before this sector? */
 426                 /* End offset in or behind this sector? */
 427                 if ((offset <
 428                                 (bank->sectors[sector].offset + bank->sectors[sector].size))
 429                         && ((offset + count - 1) >= bank->sectors[sector].offset)
 430                         && bank->sectors[sector].is_protected) {
 431                         LOG_ERROR("Flash sector %d protected", sector);
 432                         return ERROR_FAIL;
 433                 }
 434         }
 435
 436         page_size = stmsmi_info->dev->pagesize;
 437
 438         /* unaligned buffer head */
 439         if (count > 0 && (offset & 3) != 0) {
 440                 cur_count = 4 - (offset & 3);
 441                 if (cur_count > count)
 442                         cur_count = count;
 443                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 444                         cur_count);
 445                 if (retval != ERROR_OK)
 446                         goto err;
 447                 offset += cur_count;
 448                 buffer += cur_count;
 449                 count -= cur_count;
 450         }
 451
 452         page_offset = offset % page_size;
 453         /* central part, aligned words */
 454         while (count >= 4) {
 455                 /* clip block at page boundary */
 456                 if (page_offset + count > page_size)
 457                         cur_count = page_size - page_offset;
 458                 else
 459                         cur_count = count & ~3;
 460
 461                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 462                         cur_count);
 463                 if (retval != ERROR_OK)
 464                         goto err;
 465
 466                 page_offset = 0;
 467                 buffer += cur_count;
 468                 offset += cur_count;
 469                 count -= cur_count;
 470
 471                 keep_alive();
 472         }
 473
 474         /* buffer tail */
 475         if (count > 0)
 476                 retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
 477
 478 err:
 479         /* Switch to HW mode before return to prompt */
 480         SMI_SET_HW_MODE();
 481         return retval;
 482 }
 483
 484 /* Return ID of flash device */
 485 /* On exit, SW mode is kept */
 486 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
 487 {
 488         struct target *target = bank->target;
 489         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 490         uint32_t io_base = stmsmi_info->io_base;
 491         int retval;
 492
 493         if (target->state != TARGET_HALTED) {
 494                 LOG_ERROR("Target not halted");
 495                 return ERROR_TARGET_NOT_HALTED;
 496         }
 497
 498         /* poll WIP */
 499         retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
 500         if (retval != ERROR_OK)
 501                 return retval;
 502
 503         /* enter in SW mode */
 504         SMI_SET_SW_MODE();
 505
 506         /* clear transmit finished flag */
 507         SMI_CLEAR_TFF();
 508
 509         /* Send SPI command "read ID" */
 510         SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
 511         SMI_WRITE_REG(SMI_CR2,
 512                 stmsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
 513
 514         /* Poll transmit finished flag */
 515         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 516
 517         /* clear transmit finished flag */
 518         SMI_CLEAR_TFF();
 519
 520         /* read ID from Receive Register */
 521         *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
 522         return ERROR_OK;
 523 }
 524
 525 static int stmsmi_probe(struct flash_bank *bank)
 526 {
 527         struct target *target = bank->target;
 528         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 529         uint32_t io_base;
 530         struct flash_sector *sectors;
 531         uint32_t id = 0; /* silence uninitialized warning */
 532         struct stmsmi_target *target_device;
 533         int retval;
 534
 535         if (stmsmi_info->probed)
 536                 free(bank->sectors);
 537         stmsmi_info->probed = 0;
 538
 539         for (target_device = target_devices ; target_device->name ; ++target_device)
 540                 if (target_device->tap_idcode == target->tap->idcode)
 541                         break;
 542         if (!target_device->name) {
 543                 LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SMI capable",
 544                                 target->tap->idcode);
 545                 return ERROR_FAIL;
 546         }
 547
 548         switch (bank->base - target_device->smi_base) {
 549                 case 0:
 550                         stmsmi_info->bank_num = SMI_SEL_BANK0;
 551                         break;
 552                 case SMI_BANK_SIZE:
 553                         stmsmi_info->bank_num = SMI_SEL_BANK1;
 554                         break;
 555                 case 2*SMI_BANK_SIZE:
 556                         stmsmi_info->bank_num = SMI_SEL_BANK2;
 557                         break;
 558                 case 3*SMI_BANK_SIZE:
 559                         stmsmi_info->bank_num = SMI_SEL_BANK3;
 560                         break;
 561                 default:
 562                         LOG_ERROR("Invalid SMI base address 0x%" PRIx32, bank->base);
 563                         return ERROR_FAIL;
 564         }
 565         io_base = target_device->io_base;
 566         stmsmi_info->io_base = io_base;
 567
 568         LOG_DEBUG("Valid SMI on device %s at address 0x%" PRIx32,
 569                 target_device->name, bank->base);
 570
 571         /* read and decode flash ID; returns in SW mode */
 572         retval = read_flash_id(bank, &id);
 573         SMI_SET_HW_MODE();
 574         if (retval != ERROR_OK)
 575                 return retval;
 576
 577         stmsmi_info->dev = NULL;
 578         for (struct flash_device *p = flash_devices; p->name ; p++)
 579                 if (p->device_id == id) {
 580                         stmsmi_info->dev = p;
 581                         break;
 582                 }
 583
 584         if (!stmsmi_info->dev) {
 585                 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
 586                 return ERROR_FAIL;
 587         }
 588
 589         LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
 590                 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
 591
 592         /* Set correct size value */
 593         bank->size = stmsmi_info->dev->size_in_bytes;
 594
 595         /* create and fill sectors array */
 596         bank->num_sectors =
 597                 stmsmi_info->dev->size_in_bytes / stmsmi_info->dev->sectorsize;
 598         sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 599         if (sectors == NULL) {
 600                 LOG_ERROR("not enough memory");
 601                 return ERROR_FAIL;
 602         }
 603
 604         for (int sector = 0; sector < bank->num_sectors; sector++) {
 605                 sectors[sector].offset = sector * stmsmi_info->dev->sectorsize;
 606                 sectors[sector].size = stmsmi_info->dev->sectorsize;
 607                 sectors[sector].is_erased = -1;
 608                 sectors[sector].is_protected = 1;
 609         }
 610
 611         bank->sectors = sectors;
 612         stmsmi_info->probed = 1;
 613         return ERROR_OK;
 614 }
 615
 616 static int stmsmi_auto_probe(struct flash_bank *bank)
 617 {
 618         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 619         if (stmsmi_info->probed)
 620                 return ERROR_OK;
 621         return stmsmi_probe(bank);
 622 }
 623
 624 static int stmsmi_protect_check(struct flash_bank *bank)
 625 {
 626         /* Nothing to do. Protection is only handled in SW. */
 627         return ERROR_OK;
 628 }
 629
 630 static int get_stmsmi_info(struct flash_bank *bank, char *buf, int buf_size)
 631 {
 632         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 633
 634         if (!(stmsmi_info->probed)) {
 635                 snprintf(buf, buf_size,
 636                         "\nSMI flash bank not probed yet\n");
 637                 return ERROR_OK;
 638         }
 639
 640         snprintf(buf, buf_size, "\nSMI flash information:\n"
 641                 "  Device \'%s\' (ID 0x%08x)\n",
 642                 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
 643
 644         return ERROR_OK;
 645 }
 646
 647 struct flash_driver stmsmi_flash = {
 648         .name = "stmsmi",
 649         .flash_bank_command = stmsmi_flash_bank_command,
 650         .erase = stmsmi_erase,
 651         .protect = stmsmi_protect,
 652         .write = stmsmi_write,
 653         .read = default_flash_read,
 654         .probe = stmsmi_probe,
 655         .auto_probe = stmsmi_auto_probe,
 656         .erase_check = default_flash_blank_check,
 657         .protect_check = stmsmi_protect_check,
 658         .info = get_stmsmi_info,
 659 };