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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2008 by Spencer Oliver                                  *
   8  *   spen@spen-soft.co.uk                                                  *
   9  *                                                                         *
  10  *   Copyright (C) 2011 by Andreas Fritiofson                              *
  11  *   andreas.fritiofson@gmail.com                                          *
  12  ***************************************************************************/
  13
  14 #ifdef HAVE_CONFIG_H
  15 #include "config.h"
  16 #endif
  17
  18 #include <string.h>
  19
  20 #include "imp.h"
  21 #include <helper/binarybuffer.h>
  22 #include <target/algorithm.h>
  23 #include <target/cortex_m.h>
  24
  25 /* stm32x register locations */
  26
  27 #define FLASH_REG_BASE_B0 0x40022000
  28 #define FLASH_REG_BASE_B1 0x40022040
  29
  30 #define STM32_FLASH_ACR     0x00
  31 #define STM32_FLASH_KEYR    0x04
  32 #define STM32_FLASH_OPTKEYR 0x08
  33 #define STM32_FLASH_SR      0x0C
  34 #define STM32_FLASH_CR      0x10
  35 #define STM32_FLASH_AR      0x14
  36 #define STM32_FLASH_OBR     0x1C
  37 #define STM32_FLASH_WRPR    0x20
  38
  39 /* TODO: Check if code using these really should be hard coded to bank 0.
  40  * There are valid cases, on dual flash devices the protection of the
  41  * second bank is done on the bank0 reg's. */
  42 #define STM32_FLASH_ACR_B0     0x40022000
  43 #define STM32_FLASH_KEYR_B0    0x40022004
  44 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  45 #define STM32_FLASH_SR_B0      0x4002200C
  46 #define STM32_FLASH_CR_B0      0x40022010
  47 #define STM32_FLASH_AR_B0      0x40022014
  48 #define STM32_FLASH_OBR_B0     0x4002201C
  49 #define STM32_FLASH_WRPR_B0    0x40022020
  50
  51 /* option byte location */
  52
  53 #define STM32_OB_RDP            0x1FFFF800
  54 #define STM32_OB_USER           0x1FFFF802
  55 #define STM32_OB_DATA0          0x1FFFF804
  56 #define STM32_OB_DATA1          0x1FFFF806
  57 #define STM32_OB_WRP0           0x1FFFF808
  58 #define STM32_OB_WRP1           0x1FFFF80A
  59 #define STM32_OB_WRP2           0x1FFFF80C
  60 #define STM32_OB_WRP3           0x1FFFF80E
  61
  62 /* FLASH_CR register bits */
  63
  64 #define FLASH_PG                        (1 << 0)
  65 #define FLASH_PER                       (1 << 1)
  66 #define FLASH_MER                       (1 << 2)
  67 #define FLASH_OPTPG                     (1 << 4)
  68 #define FLASH_OPTER                     (1 << 5)
  69 #define FLASH_STRT                      (1 << 6)
  70 #define FLASH_LOCK                      (1 << 7)
  71 #define FLASH_OPTWRE            (1 << 9)
  72 #define FLASH_OBL_LAUNCH        (1 << 13)       /* except stm32f1x series */
  73
  74 /* FLASH_SR register bits */
  75
  76 #define FLASH_BSY               (1 << 0)
  77 #define FLASH_PGERR             (1 << 2)
  78 #define FLASH_WRPRTERR  (1 << 4)
  79 #define FLASH_EOP               (1 << 5)
  80
  81 /* STM32_FLASH_OBR bit definitions (reading) */
  82
  83 #define OPT_ERROR               0
  84 #define OPT_READOUT             1
  85 #define OPT_RDWDGSW             2
  86 #define OPT_RDRSTSTOP   3
  87 #define OPT_RDRSTSTDBY  4
  88 #define OPT_BFB2                5       /* dual flash bank only */
  89
  90 /* register unlock keys */
  91
  92 #define KEY1                    0x45670123
  93 #define KEY2                    0xCDEF89AB
  94
  95 /* timeout values */
  96
  97 #define FLASH_WRITE_TIMEOUT 10
  98 #define FLASH_ERASE_TIMEOUT 100
  99
 100 struct stm32x_options {
 101         uint8_t rdp;
 102         uint8_t user;
 103         uint16_t data;
 104         uint32_t protection;
 105 };
 106
 107 struct stm32x_flash_bank {
 108         struct stm32x_options option_bytes;
 109         int ppage_size;
 110         bool probed;
 111
 112         bool has_dual_banks;
 113         /* used to access dual flash bank stm32xl */
 114         bool can_load_options;
 115         uint32_t register_base;
 116         uint8_t default_rdp;
 117         int user_data_offset;
 118         int option_offset;
 119         uint32_t user_bank_size;
 120 };
 121
 122 static int stm32x_mass_erase(struct flash_bank *bank);
 123 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 124                 uint32_t address, uint32_t hwords_count);
 125
 126 /* flash bank stm32x <base> <size> 0 0 <target#>
 127  */
 128 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 129 {
 130         struct stm32x_flash_bank *stm32x_info;
 131
 132         if (CMD_ARGC < 6)
 133                 return ERROR_COMMAND_SYNTAX_ERROR;
 134
 135         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 136
 137         bank->driver_priv = stm32x_info;
 138         stm32x_info->probed = false;
 139         stm32x_info->has_dual_banks = false;
 140         stm32x_info->can_load_options = false;
 141         stm32x_info->register_base = FLASH_REG_BASE_B0;
 142         stm32x_info->user_bank_size = bank->size;
 143
 144         /* The flash write must be aligned to a halfword boundary */
 145         bank->write_start_alignment = bank->write_end_alignment = 2;
 146
 147         return ERROR_OK;
 148 }
 149
 150 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 151 {
 152         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 153         return reg + stm32x_info->register_base;
 154 }
 155
 156 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 157 {
 158         struct target *target = bank->target;
 159         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 160 }
 161
 162 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 163 {
 164         struct target *target = bank->target;
 165         uint32_t status;
 166         int retval = ERROR_OK;
 167
 168         /* wait for busy to clear */
 169         for (;;) {
 170                 retval = stm32x_get_flash_status(bank, &status);
 171                 if (retval != ERROR_OK)
 172                         return retval;
 173                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 174                 if ((status & FLASH_BSY) == 0)
 175                         break;
 176                 if (timeout-- <= 0) {
 177                         LOG_ERROR("timed out waiting for flash");
 178                         return ERROR_FLASH_BUSY;
 179                 }
 180                 alive_sleep(1);
 181         }
 182
 183         if (status & FLASH_WRPRTERR) {
 184                 LOG_ERROR("stm32x device protected");
 185                 retval = ERROR_FLASH_PROTECTED;
 186         }
 187
 188         if (status & FLASH_PGERR) {
 189                 LOG_ERROR("stm32x device programming failed / flash not erased");
 190                 retval = ERROR_FLASH_OPERATION_FAILED;
 191         }
 192
 193         /* Clear but report errors */
 194         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 195                 /* If this operation fails, we ignore it and report the original
 196                  * retval
 197                  */
 198                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 199                                 FLASH_WRPRTERR | FLASH_PGERR);
 200         }
 201         return retval;
 202 }
 203
 204 static int stm32x_check_operation_supported(struct flash_bank *bank)
 205 {
 206         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 207
 208         /* if we have a dual flash bank device then
 209          * we need to perform option byte stuff on bank0 only */
 210         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 211                 LOG_ERROR("Option byte operations must use bank 0");
 212                 return ERROR_FLASH_OPERATION_FAILED;
 213         }
 214
 215         return ERROR_OK;
 216 }
 217
 218 static int stm32x_read_options(struct flash_bank *bank)
 219 {
 220         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 221         struct target *target = bank->target;
 222         uint32_t option_bytes;
 223         int retval;
 224
 225         /* read user and read protection option bytes, user data option bytes */
 226         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
 227         if (retval != ERROR_OK)
 228                 return retval;
 229
 230         stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
 231         stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
 232         stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
 233
 234         /* read write protection option bytes */
 235         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
 236         if (retval != ERROR_OK)
 237                 return retval;
 238
 239         return ERROR_OK;
 240 }
 241
 242 static int stm32x_erase_options(struct flash_bank *bank)
 243 {
 244         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 245         struct target *target = bank->target;
 246
 247         /* read current options */
 248         stm32x_read_options(bank);
 249
 250         /* unlock flash registers */
 251         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 252         if (retval != ERROR_OK)
 253                 return retval;
 254         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 255         if (retval != ERROR_OK)
 256                 goto flash_lock;
 257
 258         /* unlock option flash registers */
 259         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 260         if (retval != ERROR_OK)
 261                 goto flash_lock;
 262         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 263         if (retval != ERROR_OK)
 264                 goto flash_lock;
 265
 266         /* erase option bytes */
 267         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 268         if (retval != ERROR_OK)
 269                 goto flash_lock;
 270         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 271         if (retval != ERROR_OK)
 272                 goto flash_lock;
 273
 274         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 275         if (retval != ERROR_OK)
 276                 goto flash_lock;
 277
 278         /* clear read protection option byte
 279          * this will also force a device unlock if set */
 280         stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
 281
 282         return ERROR_OK;
 283
 284 flash_lock:
 285         target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 286         return retval;
 287 }
 288
 289 static int stm32x_write_options(struct flash_bank *bank)
 290 {
 291         struct stm32x_flash_bank *stm32x_info = NULL;
 292         struct target *target = bank->target;
 293
 294         stm32x_info = bank->driver_priv;
 295
 296         /* unlock flash registers */
 297         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 298         if (retval != ERROR_OK)
 299                 return retval;
 300         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 301         if (retval != ERROR_OK)
 302                 goto flash_lock;
 303
 304         /* unlock option flash registers */
 305         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 306         if (retval != ERROR_OK)
 307                 goto flash_lock;
 308         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 309         if (retval != ERROR_OK)
 310                 goto flash_lock;
 311
 312         /* program option bytes */
 313         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 314         if (retval != ERROR_OK)
 315                 goto flash_lock;
 316
 317         uint8_t opt_bytes[16];
 318
 319         target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
 320         target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
 321         target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
 322         target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
 323         target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
 324         target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
 325         target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
 326         target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
 327
 328         /* Block write is preferred in favour of operation with ancient ST-Link
 329          * firmwares without 16-bit memory access. See
 330          * 480: flash: stm32f1x: write option bytes using the loader
 331          * https://review.openocd.org/c/openocd/+/480
 332          */
 333         retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
 334
 335 flash_lock:
 336         {
 337                 int retval2 = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 338                 if (retval == ERROR_OK)
 339                         retval = retval2;
 340         }
 341         return retval;
 342 }
 343
 344 static int stm32x_protect_check(struct flash_bank *bank)
 345 {
 346         struct target *target = bank->target;
 347         uint32_t protection;
 348
 349         int retval = stm32x_check_operation_supported(bank);
 350         if (retval != ERROR_OK)
 351                 return retval;
 352
 353         /* medium density - each bit refers to a 4 sector protection block
 354          * high density - each bit refers to a 2 sector protection block
 355          * bit 31 refers to all remaining sectors in a bank */
 356         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 357         if (retval != ERROR_OK)
 358                 return retval;
 359
 360         for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
 361                 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
 362
 363         return ERROR_OK;
 364 }
 365
 366 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 367                 unsigned int last)
 368 {
 369         struct target *target = bank->target;
 370
 371         if (bank->target->state != TARGET_HALTED) {
 372                 LOG_ERROR("Target not halted");
 373                 return ERROR_TARGET_NOT_HALTED;
 374         }
 375
 376         if ((first == 0) && (last == (bank->num_sectors - 1)))
 377                 return stm32x_mass_erase(bank);
 378
 379         /* unlock flash registers */
 380         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 381         if (retval != ERROR_OK)
 382                 return retval;
 383         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 384         if (retval != ERROR_OK)
 385                 goto flash_lock;
 386
 387         for (unsigned int i = first; i <= last; i++) {
 388                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 389                 if (retval != ERROR_OK)
 390                         goto flash_lock;
 391                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 392                                 bank->base + bank->sectors[i].offset);
 393                 if (retval != ERROR_OK)
 394                         goto flash_lock;
 395                 retval = target_write_u32(target,
 396                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 397                 if (retval != ERROR_OK)
 398                         goto flash_lock;
 399
 400                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 401                 if (retval != ERROR_OK)
 402                         goto flash_lock;
 403         }
 404
 405 flash_lock:
 406         {
 407                 int retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 408                 if (retval == ERROR_OK)
 409                         retval = retval2;
 410         }
 411         return retval;
 412 }
 413
 414 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 415                 unsigned int last)
 416 {
 417         struct target *target = bank->target;
 418         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 419
 420         if (target->state != TARGET_HALTED) {
 421                 LOG_ERROR("Target not halted");
 422                 return ERROR_TARGET_NOT_HALTED;
 423         }
 424
 425         int retval = stm32x_check_operation_supported(bank);
 426         if (retval != ERROR_OK)
 427                 return retval;
 428
 429         retval = stm32x_erase_options(bank);
 430         if (retval != ERROR_OK) {
 431                 LOG_ERROR("stm32x failed to erase options");
 432                 return retval;
 433         }
 434
 435         for (unsigned int i = first; i <= last; i++) {
 436                 if (set)
 437                         stm32x_info->option_bytes.protection &= ~(1 << i);
 438                 else
 439                         stm32x_info->option_bytes.protection |= (1 << i);
 440         }
 441
 442         return stm32x_write_options(bank);
 443 }
 444
 445 static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer,
 446                 uint32_t address, uint32_t hwords_count)
 447 {
 448         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 449         struct target *target = bank->target;
 450         uint32_t buffer_size;
 451         struct working_area *write_algorithm;
 452         struct working_area *source;
 453         struct armv7m_algorithm armv7m_info;
 454         int retval;
 455
 456         static const uint8_t stm32x_flash_write_code[] = {
 457 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
 458         };
 459
 460         /* flash write code */
 461         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 462                         &write_algorithm) != ERROR_OK) {
 463                 LOG_WARNING("no working area available, can't do block memory writes");
 464                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 465         }
 466
 467         retval = target_write_buffer(target, write_algorithm->address,
 468                         sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
 469         if (retval != ERROR_OK) {
 470                 target_free_working_area(target, write_algorithm);
 471                 return retval;
 472         }
 473
 474         /* memory buffer */
 475         buffer_size = target_get_working_area_avail(target);
 476         buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
 477         /* Normally we allocate all available working area.
 478          * MIN shrinks buffer_size if the size of the written block is smaller.
 479          * MAX prevents using async algo if the available working area is smaller
 480          * than 256, the following allocation fails with
 481          * ERROR_TARGET_RESOURCE_NOT_AVAILABLE and slow flashing takes place.
 482          */
 483
 484         retval = target_alloc_working_area(target, buffer_size, &source);
 485         /* Allocated size is always 32-bit word aligned */
 486         if (retval != ERROR_OK) {
 487                 target_free_working_area(target, write_algorithm);
 488                 LOG_WARNING("no large enough working area available, can't do block memory writes");
 489                 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
 490                  * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
 491                  */
 492                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 493         }
 494
 495         struct reg_param reg_params[5];
 496
 497         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 498         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 499         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 500         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 501         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 502
 503         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 504         buf_set_u32(reg_params[1].value, 0, 32, hwords_count);
 505         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 506         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 507         buf_set_u32(reg_params[4].value, 0, 32, address);
 508
 509         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 510         armv7m_info.core_mode = ARM_MODE_THREAD;
 511
 512         retval = target_run_flash_async_algorithm(target, buffer, hwords_count, 2,
 513                         0, NULL,
 514                         ARRAY_SIZE(reg_params), reg_params,
 515                         source->address, source->size,
 516                         write_algorithm->address, 0,
 517                         &armv7m_info);
 518
 519         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 520                 /* Actually we just need to check for programming errors
 521                  * stm32x_wait_status_busy also reports error and clears status bits.
 522                  *
 523                  * Target algo returns flash status in r0 only if properly finished.
 524                  * It is safer to re-read status register.
 525                  */
 526                 int retval2 = stm32x_wait_status_busy(bank, 5);
 527                 if (retval2 != ERROR_OK)
 528                         retval = retval2;
 529
 530                 LOG_ERROR("flash write failed just before address 0x%"PRIx32,
 531                                 buf_get_u32(reg_params[4].value, 0, 32));
 532         }
 533
 534         for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
 535                 destroy_reg_param(&reg_params[i]);
 536
 537         target_free_working_area(target, source);
 538         target_free_working_area(target, write_algorithm);
 539
 540         return retval;
 541 }
 542
 543 static int stm32x_write_block_riscv(struct flash_bank *bank, const uint8_t *buffer,
 544                 uint32_t address, uint32_t hwords_count)
 545 {
 546         struct target *target = bank->target;
 547         uint32_t buffer_size;
 548         struct working_area *write_algorithm;
 549         struct working_area *source;
 550         static const uint8_t gd32vf103_flash_write_code[] = {
 551 #include "../../../contrib/loaders/flash/gd32vf103/gd32vf103.inc"
 552         };
 553
 554         /* flash write code */
 555         if (target_alloc_working_area(target, sizeof(gd32vf103_flash_write_code),
 556                         &write_algorithm) != ERROR_OK) {
 557                 LOG_WARNING("no working area available, can't do block memory writes");
 558                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 559         }
 560
 561         int retval = target_write_buffer(target, write_algorithm->address,
 562                         sizeof(gd32vf103_flash_write_code), gd32vf103_flash_write_code);
 563         if (retval != ERROR_OK) {
 564                 target_free_working_area(target, write_algorithm);
 565                 return retval;
 566         }
 567
 568         /* memory buffer */
 569         buffer_size = target_get_working_area_avail(target);
 570         buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
 571
 572         retval = target_alloc_working_area(target, buffer_size, &source);
 573         /* Allocated size is always word aligned */
 574         if (retval != ERROR_OK) {
 575                 target_free_working_area(target, write_algorithm);
 576                 LOG_WARNING("no large enough working area available, can't do block memory writes");
 577                 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
 578                  * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
 579                  */
 580                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 581         }
 582
 583         struct reg_param reg_params[4];
 584
 585         init_reg_param(&reg_params[0], "a0", 32, PARAM_OUT);    /* poiner to FLASH_SR */
 586         init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 587         init_reg_param(&reg_params[2], "a2", 32, PARAM_OUT);    /* buffer start */
 588         init_reg_param(&reg_params[3], "a3", 32, PARAM_IN_OUT); /* target address */
 589
 590         while (hwords_count > 0) {
 591                 uint32_t thisrun_hwords = source->size / 2;
 592
 593                 /* Limit to the amount of data we actually want to write */
 594                 if (thisrun_hwords > hwords_count)
 595                         thisrun_hwords = hwords_count;
 596
 597                 /* Write data to buffer */
 598                 retval = target_write_buffer(target, source->address,
 599                                         thisrun_hwords * 2, buffer);
 600                 if (retval != ERROR_OK)
 601                         break;
 602
 603                 buf_set_u32(reg_params[0].value, 0, 32, stm32x_get_flash_reg(bank, STM32_FLASH_SR));
 604                 buf_set_u32(reg_params[1].value, 0, 32, thisrun_hwords);
 605                 buf_set_u32(reg_params[2].value, 0, 32, source->address);
 606                 buf_set_u32(reg_params[3].value, 0, 32, address);
 607
 608                 retval = target_run_algorithm(target,
 609                                 0, NULL,
 610                                 ARRAY_SIZE(reg_params), reg_params,
 611                                 write_algorithm->address,
 612                                 write_algorithm->address + sizeof(gd32vf103_flash_write_code) - 4,
 613                                 10000, NULL);
 614
 615                 if (retval != ERROR_OK) {
 616                         LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d",
 617                                         write_algorithm->address, retval);
 618                         break;
 619                 }
 620
 621                 /* Actually we just need to check for programming errors
 622                  * stm32x_wait_status_busy also reports error and clears status bits
 623                  */
 624                 retval = stm32x_wait_status_busy(bank, 5);
 625                 if (retval != ERROR_OK) {
 626                         LOG_ERROR("flash write failed at address 0x%"PRIx32,
 627                                         buf_get_u32(reg_params[3].value, 0, 32));
 628                         break;
 629                 }
 630
 631                 /* Update counters */
 632                 buffer += thisrun_hwords * 2;
 633                 address += thisrun_hwords * 2;
 634                 hwords_count -= thisrun_hwords;
 635         }
 636
 637         for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
 638                 destroy_reg_param(&reg_params[i]);
 639
 640         target_free_working_area(target, source);
 641         target_free_working_area(target, write_algorithm);
 642
 643         return retval;
 644 }
 645
 646 /** Writes a block to flash either using target algorithm
 647  *  or use fallback, host controlled halfword-by-halfword access.
 648  *  Flash controller must be unlocked before this call.
 649  */
 650 static int stm32x_write_block(struct flash_bank *bank,
 651                 const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
 652 {
 653         struct target *target = bank->target;
 654
 655         /* The flash write must be aligned to a halfword boundary.
 656          * The flash infrastructure ensures it, do just a security check
 657          */
 658         assert(address % 2 == 0);
 659
 660         int retval;
 661         struct arm *arm = target_to_arm(target);
 662         if (is_arm(arm)) {
 663                 /* try using a block write - on ARM architecture or... */
 664                 retval = stm32x_write_block_async(bank, buffer, address, hwords_count);
 665         } else {
 666                 /* ... RISC-V architecture */
 667                 retval = stm32x_write_block_riscv(bank, buffer, address, hwords_count);
 668         }
 669
 670         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 671                 /* if block write failed (no sufficient working area),
 672                  * we use normal (slow) single halfword accesses */
 673                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 674
 675                 while (hwords_count > 0) {
 676                         retval = target_write_memory(target, address, 2, 1, buffer);
 677                         if (retval != ERROR_OK)
 678                                 return retval;
 679
 680                         retval = stm32x_wait_status_busy(bank, 5);
 681                         if (retval != ERROR_OK)
 682                                 return retval;
 683
 684                         hwords_count--;
 685                         buffer += 2;
 686                         address += 2;
 687                 }
 688         }
 689         return retval;
 690 }
 691
 692 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 693                 uint32_t offset, uint32_t count)
 694 {
 695         struct target *target = bank->target;
 696
 697         if (bank->target->state != TARGET_HALTED) {
 698                 LOG_ERROR("Target not halted");
 699                 return ERROR_TARGET_NOT_HALTED;
 700         }
 701
 702         /* The flash write must be aligned to a halfword boundary.
 703          * The flash infrastructure ensures it, do just a security check
 704          */
 705         assert(offset % 2 == 0);
 706         assert(count % 2 == 0);
 707
 708         int retval, retval2;
 709
 710         /* unlock flash registers */
 711         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 712         if (retval != ERROR_OK)
 713                 return retval;
 714         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 715         if (retval != ERROR_OK)
 716                 goto reset_pg_and_lock;
 717
 718         /* enable flash programming */
 719         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 720         if (retval != ERROR_OK)
 721                 goto reset_pg_and_lock;
 722
 723         /* write to flash */
 724         retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2);
 725
 726 reset_pg_and_lock:
 727         retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 728         if (retval == ERROR_OK)
 729                 retval = retval2;
 730
 731         return retval;
 732 }
 733
 734 struct stm32x_property_addr {
 735         uint32_t device_id;
 736         uint32_t flash_size;
 737 };
 738
 739 static int stm32x_get_property_addr(struct target *target, struct stm32x_property_addr *addr)
 740 {
 741         if (!target_was_examined(target)) {
 742                 LOG_ERROR("Target not examined yet");
 743                 return ERROR_TARGET_NOT_EXAMINED;
 744         }
 745
 746         switch (cortex_m_get_partno_safe(target)) {
 747         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 748                 addr->device_id = 0x40015800;
 749                 addr->flash_size = 0x1FFFF7CC;
 750                 return ERROR_OK;
 751         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 752                 addr->device_id = 0xE0042000;
 753                 addr->flash_size = 0x1FFFF7E0;
 754                 return ERROR_OK;
 755         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 756                 addr->device_id = 0xE0042000;
 757                 addr->flash_size = 0x1FFFF7CC;
 758                 return ERROR_OK;
 759         case CORTEX_M23_PARTNO: /* GD32E23x devices */
 760                 addr->device_id = 0x40015800;
 761                 addr->flash_size = 0x1FFFF7E0;
 762                 return ERROR_OK;
 763         case CORTEX_M_PARTNO_INVALID:
 764                 /* Check for GD32VF103 with RISC-V CPU */
 765                 if (strcmp(target_type_name(target), "riscv") == 0
 766                                 && target_address_bits(target) == 32) {
 767                         /* There is nothing like arm common_magic in riscv_info_t
 768                          * check text name of target and if target is 32-bit
 769                          */
 770                         addr->device_id = 0xE0042000;
 771                         addr->flash_size = 0x1FFFF7E0;
 772                         return ERROR_OK;
 773                 }
 774                 /* fallthrough */
 775         default:
 776                 LOG_ERROR("Cannot identify target as a stm32x");
 777                 return ERROR_FAIL;
 778         }
 779 }
 780
 781 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 782 {
 783         struct target *target = bank->target;
 784         struct stm32x_property_addr addr;
 785
 786         int retval = stm32x_get_property_addr(target, &addr);
 787         if (retval != ERROR_OK)
 788                 return retval;
 789
 790         return target_read_u32(target, addr.device_id, device_id);
 791 }
 792
 793 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 794 {
 795         struct target *target = bank->target;
 796         struct stm32x_property_addr addr;
 797
 798         int retval = stm32x_get_property_addr(target, &addr);
 799         if (retval != ERROR_OK)
 800                 return retval;
 801
 802         return target_read_u16(target, addr.flash_size, flash_size_in_kb);
 803 }
 804
 805 static int stm32x_probe(struct flash_bank *bank)
 806 {
 807         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 808         uint16_t flash_size_in_kb;
 809         uint16_t max_flash_size_in_kb;
 810         uint32_t dbgmcu_idcode;
 811         int page_size;
 812         uint32_t base_address = 0x08000000;
 813
 814         stm32x_info->probed = false;
 815         stm32x_info->register_base = FLASH_REG_BASE_B0;
 816         stm32x_info->user_data_offset = 10;
 817         stm32x_info->option_offset = 0;
 818
 819         /* default factory read protection level 0 */
 820         stm32x_info->default_rdp = 0xA5;
 821
 822         /* read stm32 device id register */
 823         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 824         if (retval != ERROR_OK)
 825                 return retval;
 826
 827         LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
 828
 829         uint16_t device_id = dbgmcu_idcode & 0xfff;
 830         uint16_t rev_id = dbgmcu_idcode >> 16;
 831
 832         /* set page size, protection granularity and max flash size depending on family */
 833         switch (device_id) {
 834         case 0x440: /* stm32f05x */
 835                 page_size = 1024;
 836                 stm32x_info->ppage_size = 4;
 837                 max_flash_size_in_kb = 64;
 838                 stm32x_info->user_data_offset = 16;
 839                 stm32x_info->option_offset = 6;
 840                 stm32x_info->default_rdp = 0xAA;
 841                 stm32x_info->can_load_options = true;
 842                 break;
 843         case 0x444: /* stm32f03x */
 844         case 0x445: /* stm32f04x */
 845                 page_size = 1024;
 846                 stm32x_info->ppage_size = 4;
 847                 max_flash_size_in_kb = 32;
 848                 stm32x_info->user_data_offset = 16;
 849                 stm32x_info->option_offset = 6;
 850                 stm32x_info->default_rdp = 0xAA;
 851                 stm32x_info->can_load_options = true;
 852                 break;
 853         case 0x448: /* stm32f07x */
 854                 page_size = 2048;
 855                 stm32x_info->ppage_size = 4;
 856                 max_flash_size_in_kb = 128;
 857                 stm32x_info->user_data_offset = 16;
 858                 stm32x_info->option_offset = 6;
 859                 stm32x_info->default_rdp = 0xAA;
 860                 stm32x_info->can_load_options = true;
 861                 break;
 862         case 0x442: /* stm32f09x */
 863                 page_size = 2048;
 864                 stm32x_info->ppage_size = 4;
 865                 max_flash_size_in_kb = 256;
 866                 stm32x_info->user_data_offset = 16;
 867                 stm32x_info->option_offset = 6;
 868                 stm32x_info->default_rdp = 0xAA;
 869                 stm32x_info->can_load_options = true;
 870                 break;
 871         case 0x410: /* stm32f1x medium-density */
 872                 page_size = 1024;
 873                 stm32x_info->ppage_size = 4;
 874                 max_flash_size_in_kb = 128;
 875                 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
 876                    share DEV_ID with STM32F101/2/3 medium-density line,
 877                    however they use a REV_ID different from any STM32 device.
 878                    The main difference is another offset of user option bits
 879                    (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
 880                    (FLASH_OBR/FMC_OBSTAT 0x4002201C).
 881                    This caused problems e.g. during flash block programming
 882                    because of unexpected active hardware watchog. */
 883                 switch (rev_id) {
 884                 case 0x1303: /* gd32f1x0 */
 885                         stm32x_info->user_data_offset = 16;
 886                         stm32x_info->option_offset = 6;
 887                         max_flash_size_in_kb = 64;
 888                         stm32x_info->can_load_options = true;
 889                         break;
 890                 case 0x1704: /* gd32f3x0 */
 891                         stm32x_info->user_data_offset = 16;
 892                         stm32x_info->option_offset = 6;
 893                         stm32x_info->can_load_options = true;
 894                         break;
 895                 case 0x1906: /* gd32vf103 */
 896                         break;
 897                 case 0x1909: /* gd32e23x */
 898                         stm32x_info->user_data_offset = 16;
 899                         stm32x_info->option_offset = 6;
 900                         max_flash_size_in_kb = 64;
 901                         stm32x_info->can_load_options = true;
 902                         break;
 903                 }
 904                 break;
 905         case 0x412: /* stm32f1x low-density */
 906                 page_size = 1024;
 907                 stm32x_info->ppage_size = 4;
 908                 max_flash_size_in_kb = 32;
 909                 break;
 910         case 0x414: /* stm32f1x high-density */
 911                 page_size = 2048;
 912                 stm32x_info->ppage_size = 2;
 913                 max_flash_size_in_kb = 512;
 914                 break;
 915         case 0x418: /* stm32f1x connectivity */
 916                 page_size = 2048;
 917                 stm32x_info->ppage_size = 2;
 918                 max_flash_size_in_kb = 256;
 919                 break;
 920         case 0x430: /* stm32f1 XL-density (dual flash banks) */
 921                 page_size = 2048;
 922                 stm32x_info->ppage_size = 2;
 923                 max_flash_size_in_kb = 1024;
 924                 stm32x_info->has_dual_banks = true;
 925                 break;
 926         case 0x420: /* stm32f100xx low- and medium-density value line */
 927                 page_size = 1024;
 928                 stm32x_info->ppage_size = 4;
 929                 max_flash_size_in_kb = 128;
 930                 break;
 931         case 0x428: /* stm32f100xx high-density value line */
 932                 page_size = 2048;
 933                 stm32x_info->ppage_size = 4;
 934                 max_flash_size_in_kb = 512;
 935                 break;
 936         case 0x422: /* stm32f302/3xb/c */
 937                 page_size = 2048;
 938                 stm32x_info->ppage_size = 2;
 939                 max_flash_size_in_kb = 256;
 940                 stm32x_info->user_data_offset = 16;
 941                 stm32x_info->option_offset = 6;
 942                 stm32x_info->default_rdp = 0xAA;
 943                 stm32x_info->can_load_options = true;
 944                 break;
 945         case 0x446: /* stm32f303xD/E */
 946                 page_size = 2048;
 947                 stm32x_info->ppage_size = 2;
 948                 max_flash_size_in_kb = 512;
 949                 stm32x_info->user_data_offset = 16;
 950                 stm32x_info->option_offset = 6;
 951                 stm32x_info->default_rdp = 0xAA;
 952                 stm32x_info->can_load_options = true;
 953                 break;
 954         case 0x432: /* stm32f37x */
 955                 page_size = 2048;
 956                 stm32x_info->ppage_size = 2;
 957                 max_flash_size_in_kb = 256;
 958                 stm32x_info->user_data_offset = 16;
 959                 stm32x_info->option_offset = 6;
 960                 stm32x_info->default_rdp = 0xAA;
 961                 stm32x_info->can_load_options = true;
 962                 break;
 963         case 0x438: /* stm32f33x */
 964         case 0x439: /* stm32f302x6/8 */
 965                 page_size = 2048;
 966                 stm32x_info->ppage_size = 2;
 967                 max_flash_size_in_kb = 64;
 968                 stm32x_info->user_data_offset = 16;
 969                 stm32x_info->option_offset = 6;
 970                 stm32x_info->default_rdp = 0xAA;
 971                 stm32x_info->can_load_options = true;
 972                 break;
 973         default:
 974                 LOG_WARNING("Cannot identify target as a STM32 family.");
 975                 return ERROR_FAIL;
 976         }
 977
 978         /* get flash size from target. */
 979         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 980
 981         /* failed reading flash size or flash size invalid (early silicon),
 982          * default to max target family */
 983         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 984                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 985                         max_flash_size_in_kb);
 986                 flash_size_in_kb = max_flash_size_in_kb;
 987         }
 988
 989         if (stm32x_info->has_dual_banks) {
 990                 /* split reported size into matching bank */
 991                 if (bank->base != 0x08080000) {
 992                         /* bank 0 will be fixed 512k */
 993                         flash_size_in_kb = 512;
 994                 } else {
 995                         flash_size_in_kb -= 512;
 996                         /* bank1 also uses a register offset */
 997                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 998                         base_address = 0x08080000;
 999                 }
1000         }
1001
1002         /* if the user sets the size manually then ignore the probed value
1003          * this allows us to work around devices that have a invalid flash size register value */
1004         if (stm32x_info->user_bank_size) {
1005                 LOG_INFO("ignoring flash probed value, using configured bank size");
1006                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
1007         }
1008
1009         LOG_INFO("flash size = %d KiB", flash_size_in_kb);
1010
1011         /* did we assign flash size? */
1012         assert(flash_size_in_kb != 0xffff);
1013
1014         /* calculate numbers of pages */
1015         int num_pages = flash_size_in_kb * 1024 / page_size;
1016
1017         /* check that calculation result makes sense */
1018         assert(num_pages > 0);
1019
1020         free(bank->sectors);
1021         bank->sectors = NULL;
1022
1023         free(bank->prot_blocks);
1024         bank->prot_blocks = NULL;
1025
1026         bank->base = base_address;
1027         bank->size = (num_pages * page_size);
1028
1029         bank->num_sectors = num_pages;
1030         bank->sectors = alloc_block_array(0, page_size, num_pages);
1031         if (!bank->sectors)
1032                 return ERROR_FAIL;
1033
1034         /* calculate number of write protection blocks */
1035         int num_prot_blocks = num_pages / stm32x_info->ppage_size;
1036         if (num_prot_blocks > 32)
1037                 num_prot_blocks = 32;
1038
1039         bank->num_prot_blocks = num_prot_blocks;
1040         bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
1041         if (!bank->prot_blocks)
1042                 return ERROR_FAIL;
1043
1044         if (num_prot_blocks == 32)
1045                 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
1046
1047         stm32x_info->probed = true;
1048
1049         return ERROR_OK;
1050 }
1051
1052 static int stm32x_auto_probe(struct flash_bank *bank)
1053 {
1054         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1055         if (stm32x_info->probed)
1056                 return ERROR_OK;
1057         return stm32x_probe(bank);
1058 }
1059
1060 #if 0
1061 COMMAND_HANDLER(stm32x_handle_part_id_command)
1062 {
1063         return ERROR_OK;
1064 }
1065 #endif
1066
1067 static const char *get_stm32f0_revision(uint16_t rev_id)
1068 {
1069         const char *rev_str = NULL;
1070
1071         switch (rev_id) {
1072         case 0x1000:
1073                 rev_str = "1.0";
1074                 break;
1075         case 0x2000:
1076                 rev_str = "2.0";
1077                 break;
1078         }
1079         return rev_str;
1080 }
1081
1082 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
1083 {
1084         uint32_t dbgmcu_idcode;
1085
1086         /* read stm32 device id register */
1087         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1088         if (retval != ERROR_OK)
1089                 return retval;
1090
1091         uint16_t device_id = dbgmcu_idcode & 0xfff;
1092         uint16_t rev_id = dbgmcu_idcode >> 16;
1093         const char *device_str;
1094         const char *rev_str = NULL;
1095
1096         switch (device_id) {
1097         case 0x410:
1098                 device_str = "STM32F10x (Medium Density)";
1099
1100                 switch (rev_id) {
1101                 case 0x0000:
1102                         rev_str = "A";
1103                         break;
1104
1105                 case 0x1303: /* gd32f1x0 */
1106                         device_str = "GD32F1x0";
1107                         break;
1108
1109                 case 0x1704: /* gd32f3x0 */
1110                         device_str = "GD32F3x0";
1111                         break;
1112
1113                 case 0x1906:
1114                         device_str = "GD32VF103";
1115                         break;
1116
1117                 case 0x1909: /* gd32e23x */
1118                         device_str = "GD32E23x";
1119                         break;
1120
1121                 case 0x2000:
1122                         rev_str = "B";
1123                         break;
1124
1125                 case 0x2001:
1126                         rev_str = "Z";
1127                         break;
1128
1129                 case 0x2003:
1130                         rev_str = "Y";
1131                         break;
1132                 }
1133                 break;
1134
1135         case 0x412:
1136                 device_str = "STM32F10x (Low Density)";
1137
1138                 switch (rev_id) {
1139                 case 0x1000:
1140                         rev_str = "A";
1141                         break;
1142                 }
1143                 break;
1144
1145         case 0x414:
1146                 device_str = "STM32F10x (High Density)";
1147
1148                 switch (rev_id) {
1149                 case 0x1000:
1150                         rev_str = "A";
1151                         break;
1152
1153                 case 0x1001:
1154                         rev_str = "Z";
1155                         break;
1156
1157                 case 0x1003:
1158                         rev_str = "Y";
1159                         break;
1160                 }
1161                 break;
1162
1163         case 0x418:
1164                 device_str = "STM32F10x (Connectivity)";
1165
1166                 switch (rev_id) {
1167                 case 0x1000:
1168                         rev_str = "A";
1169                         break;
1170
1171                 case 0x1001:
1172                         rev_str = "Z";
1173                         break;
1174                 }
1175                 break;
1176
1177         case 0x420:
1178                 device_str = "STM32F100 (Low/Medium Density)";
1179
1180                 switch (rev_id) {
1181                 case 0x1000:
1182                         rev_str = "A";
1183                         break;
1184
1185                 case 0x1001:
1186                         rev_str = "Z";
1187                         break;
1188                 }
1189                 break;
1190
1191         case 0x422:
1192                 device_str = "STM32F302xB/C";
1193
1194                 switch (rev_id) {
1195                 case 0x1000:
1196                         rev_str = "A";
1197                         break;
1198
1199                 case 0x1001:
1200                         rev_str = "Z";
1201                         break;
1202
1203                 case 0x1003:
1204                         rev_str = "Y";
1205                         break;
1206
1207                 case 0x2000:
1208                         rev_str = "B";
1209                         break;
1210                 }
1211                 break;
1212
1213         case 0x428:
1214                 device_str = "STM32F100 (High Density)";
1215
1216                 switch (rev_id) {
1217                 case 0x1000:
1218                         rev_str = "A";
1219                         break;
1220
1221                 case 0x1001:
1222                         rev_str = "Z";
1223                         break;
1224                 }
1225                 break;
1226
1227         case 0x430:
1228                 device_str = "STM32F10x (XL Density)";
1229
1230                 switch (rev_id) {
1231                 case 0x1000:
1232                         rev_str = "A";
1233                         break;
1234                 }
1235                 break;
1236
1237         case 0x432:
1238                 device_str = "STM32F37x";
1239
1240                 switch (rev_id) {
1241                 case 0x1000:
1242                         rev_str = "A";
1243                         break;
1244
1245                 case 0x2000:
1246                         rev_str = "B";
1247                         break;
1248                 }
1249                 break;
1250
1251         case 0x438:
1252                 device_str = "STM32F33x";
1253
1254                 switch (rev_id) {
1255                 case 0x1000:
1256                         rev_str = "A";
1257                         break;
1258                 }
1259                 break;
1260
1261         case 0x439:
1262                 device_str = "STM32F302x6/8";
1263
1264                 switch (rev_id) {
1265                 case 0x1000:
1266                         rev_str = "A";
1267                         break;
1268
1269                 case 0x1001:
1270                         rev_str = "Z";
1271                         break;
1272                 }
1273                 break;
1274
1275         case 0x444:
1276                 device_str = "STM32F03x";
1277                 rev_str = get_stm32f0_revision(rev_id);
1278                 break;
1279
1280         case 0x440:
1281                 device_str = "STM32F05x";
1282                 rev_str = get_stm32f0_revision(rev_id);
1283                 break;
1284
1285         case 0x445:
1286                 device_str = "STM32F04x";
1287                 rev_str = get_stm32f0_revision(rev_id);
1288                 break;
1289
1290         case 0x446:
1291                 device_str = "STM32F303xD/E";
1292                 switch (rev_id) {
1293                 case 0x1000:
1294                         rev_str = "A";
1295                         break;
1296                 }
1297                 break;
1298
1299         case 0x448:
1300                 device_str = "STM32F07x";
1301                 rev_str = get_stm32f0_revision(rev_id);
1302                 break;
1303
1304         case 0x442:
1305                 device_str = "STM32F09x";
1306                 rev_str = get_stm32f0_revision(rev_id);
1307                 break;
1308
1309         default:
1310                 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1311                 return ERROR_FAIL;
1312         }
1313
1314         if (rev_str)
1315                 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1316         else
1317                 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1318
1319         return ERROR_OK;
1320 }
1321
1322 COMMAND_HANDLER(stm32x_handle_lock_command)
1323 {
1324         struct target *target = NULL;
1325         struct stm32x_flash_bank *stm32x_info = NULL;
1326
1327         if (CMD_ARGC < 1)
1328                 return ERROR_COMMAND_SYNTAX_ERROR;
1329
1330         struct flash_bank *bank;
1331         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1332         if (retval != ERROR_OK)
1333                 return retval;
1334
1335         stm32x_info = bank->driver_priv;
1336
1337         target = bank->target;
1338
1339         if (target->state != TARGET_HALTED) {
1340                 LOG_ERROR("Target not halted");
1341                 return ERROR_TARGET_NOT_HALTED;
1342         }
1343
1344         retval = stm32x_check_operation_supported(bank);
1345         if (retval != ERROR_OK)
1346                 return retval;
1347
1348         if (stm32x_erase_options(bank) != ERROR_OK) {
1349                 command_print(CMD, "stm32x failed to erase options");
1350                 return ERROR_OK;
1351         }
1352
1353         /* set readout protection */
1354         stm32x_info->option_bytes.rdp = 0;
1355
1356         if (stm32x_write_options(bank) != ERROR_OK) {
1357                 command_print(CMD, "stm32x failed to lock device");
1358                 return ERROR_OK;
1359         }
1360
1361         command_print(CMD, "stm32x locked");
1362
1363         return ERROR_OK;
1364 }
1365
1366 COMMAND_HANDLER(stm32x_handle_unlock_command)
1367 {
1368         struct target *target = NULL;
1369
1370         if (CMD_ARGC < 1)
1371                 return ERROR_COMMAND_SYNTAX_ERROR;
1372
1373         struct flash_bank *bank;
1374         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1375         if (retval != ERROR_OK)
1376                 return retval;
1377
1378         target = bank->target;
1379
1380         if (target->state != TARGET_HALTED) {
1381                 LOG_ERROR("Target not halted");
1382                 return ERROR_TARGET_NOT_HALTED;
1383         }
1384
1385         retval = stm32x_check_operation_supported(bank);
1386         if (retval != ERROR_OK)
1387                 return retval;
1388
1389         if (stm32x_erase_options(bank) != ERROR_OK) {
1390                 command_print(CMD, "stm32x failed to erase options");
1391                 return ERROR_OK;
1392         }
1393
1394         if (stm32x_write_options(bank) != ERROR_OK) {
1395                 command_print(CMD, "stm32x failed to unlock device");
1396                 return ERROR_OK;
1397         }
1398
1399         command_print(CMD, "stm32x unlocked.\n"
1400                         "INFO: a reset or power cycle is required "
1401                         "for the new settings to take effect.");
1402
1403         return ERROR_OK;
1404 }
1405
1406 COMMAND_HANDLER(stm32x_handle_options_read_command)
1407 {
1408         uint32_t optionbyte, protection;
1409         struct target *target = NULL;
1410         struct stm32x_flash_bank *stm32x_info = NULL;
1411
1412         if (CMD_ARGC < 1)
1413                 return ERROR_COMMAND_SYNTAX_ERROR;
1414
1415         struct flash_bank *bank;
1416         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1417         if (retval != ERROR_OK)
1418                 return retval;
1419
1420         stm32x_info = bank->driver_priv;
1421
1422         target = bank->target;
1423
1424         if (target->state != TARGET_HALTED) {
1425                 LOG_ERROR("Target not halted");
1426                 return ERROR_TARGET_NOT_HALTED;
1427         }
1428
1429         retval = stm32x_check_operation_supported(bank);
1430         if (retval != ERROR_OK)
1431                 return retval;
1432
1433         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1434         if (retval != ERROR_OK)
1435                 return retval;
1436
1437         uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1438
1439         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1440         if (retval != ERROR_OK)
1441                 return retval;
1442
1443         if (optionbyte & (1 << OPT_ERROR))
1444                 command_print(CMD, "option byte complement error");
1445
1446         command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1447         command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1448
1449         command_print(CMD, "read protection: %s",
1450                                 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1451
1452         /* user option bytes are offset depending on variant */
1453         optionbyte >>= stm32x_info->option_offset;
1454
1455         command_print(CMD, "watchdog: %sware",
1456                                 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1457
1458         command_print(CMD, "stop mode: %sreset generated upon entry",
1459                                 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1460
1461         command_print(CMD, "standby mode: %sreset generated upon entry",
1462                                 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1463
1464         if (stm32x_info->has_dual_banks)
1465                 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1466
1467         command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1468
1469         return ERROR_OK;
1470 }
1471
1472 COMMAND_HANDLER(stm32x_handle_options_write_command)
1473 {
1474         struct target *target = NULL;
1475         struct stm32x_flash_bank *stm32x_info = NULL;
1476         uint8_t optionbyte;
1477         uint16_t useropt;
1478
1479         if (CMD_ARGC < 2)
1480                 return ERROR_COMMAND_SYNTAX_ERROR;
1481
1482         struct flash_bank *bank;
1483         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1484         if (retval != ERROR_OK)
1485                 return retval;
1486
1487         stm32x_info = bank->driver_priv;
1488
1489         target = bank->target;
1490
1491         if (target->state != TARGET_HALTED) {
1492                 LOG_ERROR("Target not halted");
1493                 return ERROR_TARGET_NOT_HALTED;
1494         }
1495
1496         retval = stm32x_check_operation_supported(bank);
1497         if (retval != ERROR_OK)
1498                 return retval;
1499
1500         retval = stm32x_read_options(bank);
1501         if (retval != ERROR_OK)
1502                 return retval;
1503
1504         /* start with current options */
1505         optionbyte = stm32x_info->option_bytes.user;
1506         useropt = stm32x_info->option_bytes.data;
1507
1508         /* skip over flash bank */
1509         CMD_ARGC--;
1510         CMD_ARGV++;
1511
1512         while (CMD_ARGC) {
1513                 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1514                         optionbyte |= (1 << 0);
1515                 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1516                         optionbyte &= ~(1 << 0);
1517                 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1518                         optionbyte |= (1 << 1);
1519                 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1520                         optionbyte &= ~(1 << 1);
1521                 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1522                         optionbyte |= (1 << 2);
1523                 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1524                         optionbyte &= ~(1 << 2);
1525                 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1526                         if (CMD_ARGC < 2)
1527                                 return ERROR_COMMAND_SYNTAX_ERROR;
1528                         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1529                         CMD_ARGC--;
1530                         CMD_ARGV++;
1531                 } else if (stm32x_info->has_dual_banks) {
1532                         if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1533                                 optionbyte |= (1 << 3);
1534                         else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1535                                 optionbyte &= ~(1 << 3);
1536                         else
1537                                 return ERROR_COMMAND_SYNTAX_ERROR;
1538                 } else
1539                         return ERROR_COMMAND_SYNTAX_ERROR;
1540                 CMD_ARGC--;
1541                 CMD_ARGV++;
1542         }
1543
1544         if (stm32x_erase_options(bank) != ERROR_OK) {
1545                 command_print(CMD, "stm32x failed to erase options");
1546                 return ERROR_OK;
1547         }
1548
1549         stm32x_info->option_bytes.user = optionbyte;
1550         stm32x_info->option_bytes.data = useropt;
1551
1552         if (stm32x_write_options(bank) != ERROR_OK) {
1553                 command_print(CMD, "stm32x failed to write options");
1554                 return ERROR_OK;
1555         }
1556
1557         command_print(CMD, "stm32x write options complete.\n"
1558                                 "INFO: %spower cycle is required "
1559                                 "for the new settings to take effect.",
1560                                 stm32x_info->can_load_options
1561                                         ? "'stm32f1x options_load' command or " : "");
1562
1563         return ERROR_OK;
1564 }
1565
1566 COMMAND_HANDLER(stm32x_handle_options_load_command)
1567 {
1568         if (CMD_ARGC < 1)
1569                 return ERROR_COMMAND_SYNTAX_ERROR;
1570
1571         struct flash_bank *bank;
1572         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1573         if (retval != ERROR_OK)
1574                 return retval;
1575
1576         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1577
1578         if (!stm32x_info->can_load_options) {
1579                 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1580                         "required instead.");
1581                 return ERROR_FAIL;
1582         }
1583
1584         struct target *target = bank->target;
1585
1586         if (target->state != TARGET_HALTED) {
1587                 LOG_ERROR("Target not halted");
1588                 return ERROR_TARGET_NOT_HALTED;
1589         }
1590
1591         retval = stm32x_check_operation_supported(bank);
1592         if (retval != ERROR_OK)
1593                 return retval;
1594
1595         /* unlock option flash registers */
1596         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1597         if (retval != ERROR_OK)
1598                 return retval;
1599         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1600         if (retval != ERROR_OK) {
1601                 (void)target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1602                 return retval;
1603         }
1604
1605         /* force re-load of option bytes - generates software reset */
1606         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1607         if (retval != ERROR_OK)
1608                 return retval;
1609
1610         return ERROR_OK;
1611 }
1612
1613 static int stm32x_mass_erase(struct flash_bank *bank)
1614 {
1615         struct target *target = bank->target;
1616
1617         if (target->state != TARGET_HALTED) {
1618                 LOG_ERROR("Target not halted");
1619                 return ERROR_TARGET_NOT_HALTED;
1620         }
1621
1622         /* unlock option flash registers */
1623         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1624         if (retval != ERROR_OK)
1625                 return retval;
1626         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1627         if (retval != ERROR_OK)
1628                 goto flash_lock;
1629
1630         /* mass erase flash memory */
1631         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1632         if (retval != ERROR_OK)
1633                 goto flash_lock;
1634         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1635                         FLASH_MER | FLASH_STRT);
1636         if (retval != ERROR_OK)
1637                 goto flash_lock;
1638
1639         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1640
1641 flash_lock:
1642         {
1643                 int retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1644                 if (retval == ERROR_OK)
1645                         retval = retval2;
1646         }
1647         return retval;
1648 }
1649
1650 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1651 {
1652         if (CMD_ARGC < 1)
1653                 return ERROR_COMMAND_SYNTAX_ERROR;
1654
1655         struct flash_bank *bank;
1656         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1657         if (retval != ERROR_OK)
1658                 return retval;
1659
1660         retval = stm32x_mass_erase(bank);
1661         if (retval == ERROR_OK)
1662                 command_print(CMD, "stm32x mass erase complete");
1663         else
1664                 command_print(CMD, "stm32x mass erase failed");
1665
1666         return retval;
1667 }
1668
1669 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1670         {
1671                 .name = "lock",
1672                 .handler = stm32x_handle_lock_command,
1673                 .mode = COMMAND_EXEC,
1674                 .usage = "bank_id",
1675                 .help = "Lock entire flash device.",
1676         },
1677         {
1678                 .name = "unlock",
1679                 .handler = stm32x_handle_unlock_command,
1680                 .mode = COMMAND_EXEC,
1681                 .usage = "bank_id",
1682                 .help = "Unlock entire protected flash device.",
1683         },
1684         {
1685                 .name = "mass_erase",
1686                 .handler = stm32x_handle_mass_erase_command,
1687                 .mode = COMMAND_EXEC,
1688                 .usage = "bank_id",
1689                 .help = "Erase entire flash device.",
1690         },
1691         {
1692                 .name = "options_read",
1693                 .handler = stm32x_handle_options_read_command,
1694                 .mode = COMMAND_EXEC,
1695                 .usage = "bank_id",
1696                 .help = "Read and display device option bytes.",
1697         },
1698         {
1699                 .name = "options_write",
1700                 .handler = stm32x_handle_options_write_command,
1701                 .mode = COMMAND_EXEC,
1702                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1703                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1704                         "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1705                 .help = "Replace bits in device option bytes.",
1706         },
1707         {
1708                 .name = "options_load",
1709                 .handler = stm32x_handle_options_load_command,
1710                 .mode = COMMAND_EXEC,
1711                 .usage = "bank_id",
1712                 .help = "Force re-load of device option bytes.",
1713         },
1714         COMMAND_REGISTRATION_DONE
1715 };
1716
1717 static const struct command_registration stm32f1x_command_handlers[] = {
1718         {
1719                 .name = "stm32f1x",
1720                 .mode = COMMAND_ANY,
1721                 .help = "stm32f1x flash command group",
1722                 .usage = "",
1723                 .chain = stm32f1x_exec_command_handlers,
1724         },
1725         COMMAND_REGISTRATION_DONE
1726 };
1727
1728 const struct flash_driver stm32f1x_flash = {
1729         .name = "stm32f1x",
1730         .commands = stm32f1x_command_handlers,
1731         .flash_bank_command = stm32x_flash_bank_command,
1732         .erase = stm32x_erase,
1733         .protect = stm32x_protect,
1734         .write = stm32x_write,
1735         .read = default_flash_read,
1736         .probe = stm32x_probe,
1737         .auto_probe = stm32x_auto_probe,
1738         .erase_check = default_flash_blank_check,
1739         .protect_check = stm32x_protect_check,
1740         .info = get_stm32x_info,
1741         .free_driver_priv = default_flash_free_driver_priv,
1742 };