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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "imp.h"
  30 #include <helper/binarybuffer.h>
  31 #include <target/algorithm.h>
  32 #include <target/cortex_m.h>
  33
  34 /* stm32x register locations */
  35
  36 #define FLASH_REG_BASE_B0 0x40022000
  37 #define FLASH_REG_BASE_B1 0x40022040
  38
  39 #define STM32_FLASH_ACR     0x00
  40 #define STM32_FLASH_KEYR    0x04
  41 #define STM32_FLASH_OPTKEYR 0x08
  42 #define STM32_FLASH_SR      0x0C
  43 #define STM32_FLASH_CR      0x10
  44 #define STM32_FLASH_AR      0x14
  45 #define STM32_FLASH_OBR     0x1C
  46 #define STM32_FLASH_WRPR    0x20
  47
  48 /* TODO: Check if code using these really should be hard coded to bank 0.
  49  * There are valid cases, on dual flash devices the protection of the
  50  * second bank is done on the bank0 reg's. */
  51 #define STM32_FLASH_ACR_B0     0x40022000
  52 #define STM32_FLASH_KEYR_B0    0x40022004
  53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  54 #define STM32_FLASH_SR_B0      0x4002200C
  55 #define STM32_FLASH_CR_B0      0x40022010
  56 #define STM32_FLASH_AR_B0      0x40022014
  57 #define STM32_FLASH_OBR_B0     0x4002201C
  58 #define STM32_FLASH_WRPR_B0    0x40022020
  59
  60 /* option byte location */
  61
  62 #define STM32_OB_RDP            0x1FFFF800
  63 #define STM32_OB_USER           0x1FFFF802
  64 #define STM32_OB_DATA0          0x1FFFF804
  65 #define STM32_OB_DATA1          0x1FFFF806
  66 #define STM32_OB_WRP0           0x1FFFF808
  67 #define STM32_OB_WRP1           0x1FFFF80A
  68 #define STM32_OB_WRP2           0x1FFFF80C
  69 #define STM32_OB_WRP3           0x1FFFF80E
  70
  71 /* FLASH_CR register bits */
  72
  73 #define FLASH_PG                        (1 << 0)
  74 #define FLASH_PER                       (1 << 1)
  75 #define FLASH_MER                       (1 << 2)
  76 #define FLASH_OPTPG                     (1 << 4)
  77 #define FLASH_OPTER                     (1 << 5)
  78 #define FLASH_STRT                      (1 << 6)
  79 #define FLASH_LOCK                      (1 << 7)
  80 #define FLASH_OPTWRE            (1 << 9)
  81 #define FLASH_OBL_LAUNCH        (1 << 13)       /* except stm32f1x series */
  82
  83 /* FLASH_SR register bits */
  84
  85 #define FLASH_BSY               (1 << 0)
  86 #define FLASH_PGERR             (1 << 2)
  87 #define FLASH_WRPRTERR  (1 << 4)
  88 #define FLASH_EOP               (1 << 5)
  89
  90 /* STM32_FLASH_OBR bit definitions (reading) */
  91
  92 #define OPT_ERROR               0
  93 #define OPT_READOUT             1
  94 #define OPT_RDWDGSW             2
  95 #define OPT_RDRSTSTOP   3
  96 #define OPT_RDRSTSTDBY  4
  97 #define OPT_BFB2                5       /* dual flash bank only */
  98
  99 /* register unlock keys */
 100
 101 #define KEY1                    0x45670123
 102 #define KEY2                    0xCDEF89AB
 103
 104 /* timeout values */
 105
 106 #define FLASH_WRITE_TIMEOUT 10
 107 #define FLASH_ERASE_TIMEOUT 100
 108
 109 struct stm32x_options {
 110         uint8_t rdp;
 111         uint8_t user;
 112         uint16_t data;
 113         uint32_t protection;
 114 };
 115
 116 struct stm32x_flash_bank {
 117         struct stm32x_options option_bytes;
 118         int ppage_size;
 119         bool probed;
 120
 121         bool has_dual_banks;
 122         /* used to access dual flash bank stm32xl */
 123         bool can_load_options;
 124         uint32_t register_base;
 125         uint8_t default_rdp;
 126         int user_data_offset;
 127         int option_offset;
 128         uint32_t user_bank_size;
 129 };
 130
 131 static int stm32x_mass_erase(struct flash_bank *bank);
 132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
 133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 134                 uint32_t address, uint32_t count);
 135
 136 /* flash bank stm32x <base> <size> 0 0 <target#>
 137  */
 138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 139 {
 140         struct stm32x_flash_bank *stm32x_info;
 141
 142         if (CMD_ARGC < 6)
 143                 return ERROR_COMMAND_SYNTAX_ERROR;
 144
 145         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 146
 147         bank->driver_priv = stm32x_info;
 148         stm32x_info->probed = false;
 149         stm32x_info->has_dual_banks = false;
 150         stm32x_info->can_load_options = false;
 151         stm32x_info->register_base = FLASH_REG_BASE_B0;
 152         stm32x_info->user_bank_size = bank->size;
 153
 154         return ERROR_OK;
 155 }
 156
 157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 158 {
 159         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 160         return reg + stm32x_info->register_base;
 161 }
 162
 163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 164 {
 165         struct target *target = bank->target;
 166         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 167 }
 168
 169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 170 {
 171         struct target *target = bank->target;
 172         uint32_t status;
 173         int retval = ERROR_OK;
 174
 175         /* wait for busy to clear */
 176         for (;;) {
 177                 retval = stm32x_get_flash_status(bank, &status);
 178                 if (retval != ERROR_OK)
 179                         return retval;
 180                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 181                 if ((status & FLASH_BSY) == 0)
 182                         break;
 183                 if (timeout-- <= 0) {
 184                         LOG_ERROR("timed out waiting for flash");
 185                         return ERROR_FAIL;
 186                 }
 187                 alive_sleep(1);
 188         }
 189
 190         if (status & FLASH_WRPRTERR) {
 191                 LOG_ERROR("stm32x device protected");
 192                 retval = ERROR_FAIL;
 193         }
 194
 195         if (status & FLASH_PGERR) {
 196                 LOG_ERROR("stm32x device programming failed");
 197                 retval = ERROR_FAIL;
 198         }
 199
 200         /* Clear but report errors */
 201         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 202                 /* If this operation fails, we ignore it and report the original
 203                  * retval
 204                  */
 205                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 206                                 FLASH_WRPRTERR | FLASH_PGERR);
 207         }
 208         return retval;
 209 }
 210
 211 static int stm32x_check_operation_supported(struct flash_bank *bank)
 212 {
 213         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 214
 215         /* if we have a dual flash bank device then
 216          * we need to perform option byte stuff on bank0 only */
 217         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 218                 LOG_ERROR("Option byte operations must use bank 0");
 219                 return ERROR_FLASH_OPERATION_FAILED;
 220         }
 221
 222         return ERROR_OK;
 223 }
 224
 225 static int stm32x_read_options(struct flash_bank *bank)
 226 {
 227         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 228         struct target *target = bank->target;
 229         uint32_t option_bytes;
 230         int retval;
 231
 232         /* read user and read protection option bytes, user data option bytes */
 233         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
 234         if (retval != ERROR_OK)
 235                 return retval;
 236
 237         stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
 238         stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
 239         stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
 240
 241         /* read write protection option bytes */
 242         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
 243         if (retval != ERROR_OK)
 244                 return retval;
 245
 246         return ERROR_OK;
 247 }
 248
 249 static int stm32x_erase_options(struct flash_bank *bank)
 250 {
 251         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 252         struct target *target = bank->target;
 253
 254         /* read current options */
 255         stm32x_read_options(bank);
 256
 257         /* unlock flash registers */
 258         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 259         if (retval != ERROR_OK)
 260                 return retval;
 261
 262         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 263         if (retval != ERROR_OK)
 264                 return retval;
 265
 266         /* unlock option flash registers */
 267         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 268         if (retval != ERROR_OK)
 269                 return retval;
 270         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 271         if (retval != ERROR_OK)
 272                 return retval;
 273
 274         /* erase option bytes */
 275         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 276         if (retval != ERROR_OK)
 277                 return retval;
 278         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 279         if (retval != ERROR_OK)
 280                 return retval;
 281
 282         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 283         if (retval != ERROR_OK)
 284                 return retval;
 285
 286         /* clear read protection option byte
 287          * this will also force a device unlock if set */
 288         stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
 289
 290         return ERROR_OK;
 291 }
 292
 293 static int stm32x_write_options(struct flash_bank *bank)
 294 {
 295         struct stm32x_flash_bank *stm32x_info = NULL;
 296         struct target *target = bank->target;
 297
 298         stm32x_info = bank->driver_priv;
 299
 300         /* unlock flash registers */
 301         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 302         if (retval != ERROR_OK)
 303                 return retval;
 304         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 305         if (retval != ERROR_OK)
 306                 return retval;
 307
 308         /* unlock option flash registers */
 309         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 313         if (retval != ERROR_OK)
 314                 return retval;
 315
 316         /* program option bytes */
 317         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 318         if (retval != ERROR_OK)
 319                 return retval;
 320
 321         uint8_t opt_bytes[16];
 322
 323         target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
 324         target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
 325         target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
 326         target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
 327         target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
 328         target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
 329         target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
 330         target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
 331
 332         retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
 333         if (retval != ERROR_OK) {
 334                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 335                         LOG_ERROR("working area required to erase options bytes");
 336                 return retval;
 337         }
 338
 339         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 340         if (retval != ERROR_OK)
 341                 return retval;
 342
 343         return ERROR_OK;
 344 }
 345
 346 static int stm32x_protect_check(struct flash_bank *bank)
 347 {
 348         struct target *target = bank->target;
 349         uint32_t protection;
 350
 351         int retval = stm32x_check_operation_supported(bank);
 352         if (retval != ERROR_OK)
 353                 return retval;
 354
 355         /* medium density - each bit refers to a 4 sector protection block
 356          * high density - each bit refers to a 2 sector protection block
 357          * bit 31 refers to all remaining sectors in a bank */
 358         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 359         if (retval != ERROR_OK)
 360                 return retval;
 361
 362         for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
 363                 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
 364
 365         return ERROR_OK;
 366 }
 367
 368 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 369                 unsigned int last)
 370 {
 371         struct target *target = bank->target;
 372
 373         if (bank->target->state != TARGET_HALTED) {
 374                 LOG_ERROR("Target not halted");
 375                 return ERROR_TARGET_NOT_HALTED;
 376         }
 377
 378         if ((first == 0) && (last == (bank->num_sectors - 1)))
 379                 return stm32x_mass_erase(bank);
 380
 381         /* unlock flash registers */
 382         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 383         if (retval != ERROR_OK)
 384                 return retval;
 385         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 386         if (retval != ERROR_OK)
 387                 return retval;
 388
 389         for (unsigned int i = first; i <= last; i++) {
 390                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 391                 if (retval != ERROR_OK)
 392                         return retval;
 393                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 394                                 bank->base + bank->sectors[i].offset);
 395                 if (retval != ERROR_OK)
 396                         return retval;
 397                 retval = target_write_u32(target,
 398                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 399                 if (retval != ERROR_OK)
 400                         return retval;
 401
 402                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 403                 if (retval != ERROR_OK)
 404                         return retval;
 405         }
 406
 407         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 408         if (retval != ERROR_OK)
 409                 return retval;
 410
 411         return ERROR_OK;
 412 }
 413
 414 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 415                 unsigned int last)
 416 {
 417         struct target *target = bank->target;
 418         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 419
 420         if (target->state != TARGET_HALTED) {
 421                 LOG_ERROR("Target not halted");
 422                 return ERROR_TARGET_NOT_HALTED;
 423         }
 424
 425         int retval = stm32x_check_operation_supported(bank);
 426         if (retval != ERROR_OK)
 427                 return retval;
 428
 429         retval = stm32x_erase_options(bank);
 430         if (retval != ERROR_OK) {
 431                 LOG_ERROR("stm32x failed to erase options");
 432                 return retval;
 433         }
 434
 435         for (unsigned int i = first; i <= last; i++) {
 436                 if (set)
 437                         stm32x_info->option_bytes.protection &= ~(1 << i);
 438                 else
 439                         stm32x_info->option_bytes.protection |= (1 << i);
 440         }
 441
 442         return stm32x_write_options(bank);
 443 }
 444
 445 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 446                 uint32_t address, uint32_t count)
 447 {
 448         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 449         struct target *target = bank->target;
 450         uint32_t buffer_size = 16384;
 451         struct working_area *write_algorithm;
 452         struct working_area *source;
 453         struct reg_param reg_params[5];
 454         struct armv7m_algorithm armv7m_info;
 455         int retval = ERROR_OK;
 456
 457         static const uint8_t stm32x_flash_write_code[] = {
 458 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
 459         };
 460
 461         /* flash write code */
 462         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 463                         &write_algorithm) != ERROR_OK) {
 464                 LOG_WARNING("no working area available, can't do block memory writes");
 465                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 466         }
 467
 468         retval = target_write_buffer(target, write_algorithm->address,
 469                         sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
 470         if (retval != ERROR_OK) {
 471                 target_free_working_area(target, write_algorithm);
 472                 return retval;
 473         }
 474
 475         /* memory buffer */
 476         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 477                 buffer_size /= 2;
 478                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 479                 if (buffer_size <= 256) {
 480                         /* we already allocated the writing code, but failed to get a
 481                          * buffer, free the algorithm */
 482                         target_free_working_area(target, write_algorithm);
 483
 484                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 485                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 486                 }
 487         }
 488
 489         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 490         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 491         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 492         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 493         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 494
 495         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 496         buf_set_u32(reg_params[1].value, 0, 32, count);
 497         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 498         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 499         buf_set_u32(reg_params[4].value, 0, 32, address);
 500
 501         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 502         armv7m_info.core_mode = ARM_MODE_THREAD;
 503
 504         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 505                         0, NULL,
 506                         5, reg_params,
 507                         source->address, source->size,
 508                         write_algorithm->address, 0,
 509                         &armv7m_info);
 510
 511         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 512                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 513                                 buf_get_u32(reg_params[4].value, 0, 32));
 514
 515                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
 516                         LOG_ERROR("flash memory not erased before writing");
 517                         /* Clear but report errors */
 518                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
 519                 }
 520
 521                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
 522                         LOG_ERROR("flash memory write protected");
 523                         /* Clear but report errors */
 524                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
 525                 }
 526         }
 527
 528         target_free_working_area(target, source);
 529         target_free_working_area(target, write_algorithm);
 530
 531         destroy_reg_param(&reg_params[0]);
 532         destroy_reg_param(&reg_params[1]);
 533         destroy_reg_param(&reg_params[2]);
 534         destroy_reg_param(&reg_params[3]);
 535         destroy_reg_param(&reg_params[4]);
 536
 537         return retval;
 538 }
 539
 540 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 541                 uint32_t offset, uint32_t count)
 542 {
 543         struct target *target = bank->target;
 544         uint8_t *new_buffer = NULL;
 545
 546         if (bank->target->state != TARGET_HALTED) {
 547                 LOG_ERROR("Target not halted");
 548                 return ERROR_TARGET_NOT_HALTED;
 549         }
 550
 551         if (offset & 0x1) {
 552                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 553                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 554         }
 555
 556         /* If there's an odd number of bytes, the data has to be padded. Duplicate
 557          * the buffer and use the normal code path with a single block write since
 558          * it's probably cheaper than to special case the last odd write using
 559          * discrete accesses. */
 560         if (count & 1) {
 561                 new_buffer = malloc(count + 1);
 562                 if (!new_buffer) {
 563                         LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
 564                         return ERROR_FAIL;
 565                 }
 566                 LOG_INFO("odd number of bytes to write, padding with 0xff");
 567                 buffer = memcpy(new_buffer, buffer, count);
 568                 new_buffer[count++] = 0xff;
 569         }
 570
 571         uint32_t words_remaining = count / 2;
 572         int retval, retval2;
 573
 574         /* unlock flash registers */
 575         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 576         if (retval != ERROR_OK)
 577                 goto cleanup;
 578         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 579         if (retval != ERROR_OK)
 580                 goto cleanup;
 581
 582         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 583         if (retval != ERROR_OK)
 584                 goto cleanup;
 585
 586         /* try using a block write */
 587         retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
 588
 589         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 590                 /* if block write failed (no sufficient working area),
 591                  * we use normal (slow) single halfword accesses */
 592                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 593
 594                 while (words_remaining > 0) {
 595                         uint16_t value;
 596                         memcpy(&value, buffer, sizeof(uint16_t));
 597
 598                         retval = target_write_u16(target, bank->base + offset, value);
 599                         if (retval != ERROR_OK)
 600                                 goto reset_pg_and_lock;
 601
 602                         retval = stm32x_wait_status_busy(bank, 5);
 603                         if (retval != ERROR_OK)
 604                                 goto reset_pg_and_lock;
 605
 606                         words_remaining--;
 607                         buffer += 2;
 608                         offset += 2;
 609                 }
 610         }
 611
 612 reset_pg_and_lock:
 613         retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 614         if (retval == ERROR_OK)
 615                 retval = retval2;
 616
 617 cleanup:
 618         free(new_buffer);
 619         return retval;
 620 }
 621
 622 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 623 {
 624         struct target *target = bank->target;
 625         struct cortex_m_common *cortex_m = target_to_cm(target);
 626         uint32_t device_id_register = 0;
 627
 628         if (!target_was_examined(target)) {
 629                 LOG_ERROR("Target not examined yet");
 630                 return ERROR_FAIL;
 631         }
 632
 633         switch (cortex_m->core_info->partno) {
 634         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 635                 device_id_register = 0x40015800;
 636                 break;
 637         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 638                 device_id_register = 0xE0042000;
 639                 break;
 640         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 641                 device_id_register = 0xE0042000;
 642                 break;
 643         default:
 644                 LOG_ERROR("Cannot identify target as a stm32x");
 645                 return ERROR_FAIL;
 646         }
 647
 648         /* read stm32 device id register */
 649         int retval = target_read_u32(target, device_id_register, device_id);
 650         if (retval != ERROR_OK)
 651                 return retval;
 652
 653         return retval;
 654 }
 655
 656 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 657 {
 658         struct target *target = bank->target;
 659         struct cortex_m_common *cortex_m = target_to_cm(target);
 660         uint32_t flash_size_reg;
 661
 662         if (!target_was_examined(target)) {
 663                 LOG_ERROR("Target not examined yet");
 664                 return ERROR_FAIL;
 665         }
 666
 667         switch (cortex_m->core_info->partno) {
 668         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 669                 flash_size_reg = 0x1FFFF7CC;
 670                 break;
 671         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 672                 flash_size_reg = 0x1FFFF7E0;
 673                 break;
 674         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 675                 flash_size_reg = 0x1FFFF7CC;
 676                 break;
 677         default:
 678                 LOG_ERROR("Cannot identify target as a stm32x");
 679                 return ERROR_FAIL;
 680         }
 681
 682         int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
 683         if (retval != ERROR_OK)
 684                 return retval;
 685
 686         return retval;
 687 }
 688
 689 static int stm32x_probe(struct flash_bank *bank)
 690 {
 691         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 692         uint16_t flash_size_in_kb;
 693         uint16_t max_flash_size_in_kb;
 694         uint32_t dbgmcu_idcode;
 695         int page_size;
 696         uint32_t base_address = 0x08000000;
 697
 698         stm32x_info->probed = false;
 699         stm32x_info->register_base = FLASH_REG_BASE_B0;
 700         stm32x_info->user_data_offset = 10;
 701         stm32x_info->option_offset = 0;
 702
 703         /* default factory read protection level 0 */
 704         stm32x_info->default_rdp = 0xA5;
 705
 706         /* read stm32 device id register */
 707         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 708         if (retval != ERROR_OK)
 709                 return retval;
 710
 711         LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
 712
 713         uint16_t device_id = dbgmcu_idcode & 0xfff;
 714         uint16_t rev_id = dbgmcu_idcode >> 16;
 715
 716         /* set page size, protection granularity and max flash size depending on family */
 717         switch (device_id) {
 718         case 0x440: /* stm32f05x */
 719                 page_size = 1024;
 720                 stm32x_info->ppage_size = 4;
 721                 max_flash_size_in_kb = 64;
 722                 stm32x_info->user_data_offset = 16;
 723                 stm32x_info->option_offset = 6;
 724                 stm32x_info->default_rdp = 0xAA;
 725                 stm32x_info->can_load_options = true;
 726                 break;
 727         case 0x444: /* stm32f03x */
 728         case 0x445: /* stm32f04x */
 729                 page_size = 1024;
 730                 stm32x_info->ppage_size = 4;
 731                 max_flash_size_in_kb = 32;
 732                 stm32x_info->user_data_offset = 16;
 733                 stm32x_info->option_offset = 6;
 734                 stm32x_info->default_rdp = 0xAA;
 735                 stm32x_info->can_load_options = true;
 736                 break;
 737         case 0x448: /* stm32f07x */
 738                 page_size = 2048;
 739                 stm32x_info->ppage_size = 4;
 740                 max_flash_size_in_kb = 128;
 741                 stm32x_info->user_data_offset = 16;
 742                 stm32x_info->option_offset = 6;
 743                 stm32x_info->default_rdp = 0xAA;
 744                 stm32x_info->can_load_options = true;
 745                 break;
 746         case 0x442: /* stm32f09x */
 747                 page_size = 2048;
 748                 stm32x_info->ppage_size = 4;
 749                 max_flash_size_in_kb = 256;
 750                 stm32x_info->user_data_offset = 16;
 751                 stm32x_info->option_offset = 6;
 752                 stm32x_info->default_rdp = 0xAA;
 753                 stm32x_info->can_load_options = true;
 754                 break;
 755         case 0x410: /* stm32f1x medium-density */
 756                 page_size = 1024;
 757                 stm32x_info->ppage_size = 4;
 758                 max_flash_size_in_kb = 128;
 759                 /* GigaDevice GD32F1x0 & GD32F3x0 series devices share DEV_ID
 760                    with STM32F101/2/3 medium-density line,
 761                    however they use a REV_ID different from any STM32 device.
 762                    The main difference is another offset of user option bits
 763                    (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
 764                    (FLASH_OBR/FMC_OBSTAT 0x4002201C).
 765                    This caused problems e.g. during flash block programming
 766                    because of unexpected active hardware watchog. */
 767                 switch (rev_id) {
 768                 case 0x1303: /* gd32f1x0 */
 769                         stm32x_info->user_data_offset = 16;
 770                         stm32x_info->option_offset = 6;
 771                         max_flash_size_in_kb = 64;
 772                         break;
 773                 case 0x1704: /* gd32f3x0 */
 774                         stm32x_info->user_data_offset = 16;
 775                         stm32x_info->option_offset = 6;
 776                         break;
 777                 }
 778                 break;
 779         case 0x412: /* stm32f1x low-density */
 780                 page_size = 1024;
 781                 stm32x_info->ppage_size = 4;
 782                 max_flash_size_in_kb = 32;
 783                 break;
 784         case 0x414: /* stm32f1x high-density */
 785                 page_size = 2048;
 786                 stm32x_info->ppage_size = 2;
 787                 max_flash_size_in_kb = 512;
 788                 break;
 789         case 0x418: /* stm32f1x connectivity */
 790                 page_size = 2048;
 791                 stm32x_info->ppage_size = 2;
 792                 max_flash_size_in_kb = 256;
 793                 break;
 794         case 0x430: /* stm32f1 XL-density (dual flash banks) */
 795                 page_size = 2048;
 796                 stm32x_info->ppage_size = 2;
 797                 max_flash_size_in_kb = 1024;
 798                 stm32x_info->has_dual_banks = true;
 799                 break;
 800         case 0x420: /* stm32f100xx low- and medium-density value line */
 801                 page_size = 1024;
 802                 stm32x_info->ppage_size = 4;
 803                 max_flash_size_in_kb = 128;
 804                 break;
 805         case 0x428: /* stm32f100xx high-density value line */
 806                 page_size = 2048;
 807                 stm32x_info->ppage_size = 4;
 808                 max_flash_size_in_kb = 512;
 809                 break;
 810         case 0x422: /* stm32f302/3xb/c */
 811                 page_size = 2048;
 812                 stm32x_info->ppage_size = 2;
 813                 max_flash_size_in_kb = 256;
 814                 stm32x_info->user_data_offset = 16;
 815                 stm32x_info->option_offset = 6;
 816                 stm32x_info->default_rdp = 0xAA;
 817                 stm32x_info->can_load_options = true;
 818                 break;
 819         case 0x446: /* stm32f303xD/E */
 820                 page_size = 2048;
 821                 stm32x_info->ppage_size = 2;
 822                 max_flash_size_in_kb = 512;
 823                 stm32x_info->user_data_offset = 16;
 824                 stm32x_info->option_offset = 6;
 825                 stm32x_info->default_rdp = 0xAA;
 826                 stm32x_info->can_load_options = true;
 827                 break;
 828         case 0x432: /* stm32f37x */
 829                 page_size = 2048;
 830                 stm32x_info->ppage_size = 2;
 831                 max_flash_size_in_kb = 256;
 832                 stm32x_info->user_data_offset = 16;
 833                 stm32x_info->option_offset = 6;
 834                 stm32x_info->default_rdp = 0xAA;
 835                 stm32x_info->can_load_options = true;
 836                 break;
 837         case 0x438: /* stm32f33x */
 838         case 0x439: /* stm32f302x6/8 */
 839                 page_size = 2048;
 840                 stm32x_info->ppage_size = 2;
 841                 max_flash_size_in_kb = 64;
 842                 stm32x_info->user_data_offset = 16;
 843                 stm32x_info->option_offset = 6;
 844                 stm32x_info->default_rdp = 0xAA;
 845                 stm32x_info->can_load_options = true;
 846                 break;
 847         default:
 848                 LOG_WARNING("Cannot identify target as a STM32 family.");
 849                 return ERROR_FAIL;
 850         }
 851
 852         /* get flash size from target. */
 853         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 854
 855         /* failed reading flash size or flash size invalid (early silicon),
 856          * default to max target family */
 857         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 858                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 859                         max_flash_size_in_kb);
 860                 flash_size_in_kb = max_flash_size_in_kb;
 861         }
 862
 863         if (stm32x_info->has_dual_banks) {
 864                 /* split reported size into matching bank */
 865                 if (bank->base != 0x08080000) {
 866                         /* bank 0 will be fixed 512k */
 867                         flash_size_in_kb = 512;
 868                 } else {
 869                         flash_size_in_kb -= 512;
 870                         /* bank1 also uses a register offset */
 871                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 872                         base_address = 0x08080000;
 873                 }
 874         }
 875
 876         /* if the user sets the size manually then ignore the probed value
 877          * this allows us to work around devices that have a invalid flash size register value */
 878         if (stm32x_info->user_bank_size) {
 879                 LOG_INFO("ignoring flash probed value, using configured bank size");
 880                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
 881         }
 882
 883         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 884
 885         /* did we assign flash size? */
 886         assert(flash_size_in_kb != 0xffff);
 887
 888         /* calculate numbers of pages */
 889         int num_pages = flash_size_in_kb * 1024 / page_size;
 890
 891         /* check that calculation result makes sense */
 892         assert(num_pages > 0);
 893
 894         free(bank->sectors);
 895         bank->sectors = NULL;
 896
 897         free(bank->prot_blocks);
 898         bank->prot_blocks = NULL;
 899
 900         bank->base = base_address;
 901         bank->size = (num_pages * page_size);
 902
 903         bank->num_sectors = num_pages;
 904         bank->sectors = alloc_block_array(0, page_size, num_pages);
 905         if (!bank->sectors)
 906                 return ERROR_FAIL;
 907
 908         /* calculate number of write protection blocks */
 909         int num_prot_blocks = num_pages / stm32x_info->ppage_size;
 910         if (num_prot_blocks > 32)
 911                 num_prot_blocks = 32;
 912
 913         bank->num_prot_blocks = num_prot_blocks;
 914         bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
 915         if (!bank->prot_blocks)
 916                 return ERROR_FAIL;
 917
 918         if (num_prot_blocks == 32)
 919                 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
 920
 921         stm32x_info->probed = true;
 922
 923         return ERROR_OK;
 924 }
 925
 926 static int stm32x_auto_probe(struct flash_bank *bank)
 927 {
 928         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 929         if (stm32x_info->probed)
 930                 return ERROR_OK;
 931         return stm32x_probe(bank);
 932 }
 933
 934 #if 0
 935 COMMAND_HANDLER(stm32x_handle_part_id_command)
 936 {
 937         return ERROR_OK;
 938 }
 939 #endif
 940
 941 static const char *get_stm32f0_revision(uint16_t rev_id)
 942 {
 943         const char *rev_str = NULL;
 944
 945         switch (rev_id) {
 946         case 0x1000:
 947                 rev_str = "1.0";
 948                 break;
 949         case 0x2000:
 950                 rev_str = "2.0";
 951                 break;
 952         }
 953         return rev_str;
 954 }
 955
 956 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
 957 {
 958         uint32_t dbgmcu_idcode;
 959
 960         /* read stm32 device id register */
 961         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 962         if (retval != ERROR_OK)
 963                 return retval;
 964
 965         uint16_t device_id = dbgmcu_idcode & 0xfff;
 966         uint16_t rev_id = dbgmcu_idcode >> 16;
 967         const char *device_str;
 968         const char *rev_str = NULL;
 969
 970         switch (device_id) {
 971         case 0x410:
 972                 device_str = "STM32F10x (Medium Density)";
 973
 974                 switch (rev_id) {
 975                 case 0x0000:
 976                         rev_str = "A";
 977                         break;
 978
 979                 case 0x1303: /* gd32f1x0 */
 980                         device_str = "GD32F1x0";
 981                         break;
 982
 983                 case 0x1704: /* gd32f3x0 */
 984                         device_str = "GD32F3x0";
 985                         break;
 986
 987                 case 0x2000:
 988                         rev_str = "B";
 989                         break;
 990
 991                 case 0x2001:
 992                         rev_str = "Z";
 993                         break;
 994
 995                 case 0x2003:
 996                         rev_str = "Y";
 997                         break;
 998                 }
 999                 break;
1000
1001         case 0x412:
1002                 device_str = "STM32F10x (Low Density)";
1003
1004                 switch (rev_id) {
1005                 case 0x1000:
1006                         rev_str = "A";
1007                         break;
1008                 }
1009                 break;
1010
1011         case 0x414:
1012                 device_str = "STM32F10x (High Density)";
1013
1014                 switch (rev_id) {
1015                 case 0x1000:
1016                         rev_str = "A";
1017                         break;
1018
1019                 case 0x1001:
1020                         rev_str = "Z";
1021                         break;
1022
1023                 case 0x1003:
1024                         rev_str = "Y";
1025                         break;
1026                 }
1027                 break;
1028
1029         case 0x418:
1030                 device_str = "STM32F10x (Connectivity)";
1031
1032                 switch (rev_id) {
1033                 case 0x1000:
1034                         rev_str = "A";
1035                         break;
1036
1037                 case 0x1001:
1038                         rev_str = "Z";
1039                         break;
1040                 }
1041                 break;
1042
1043         case 0x420:
1044                 device_str = "STM32F100 (Low/Medium Density)";
1045
1046                 switch (rev_id) {
1047                 case 0x1000:
1048                         rev_str = "A";
1049                         break;
1050
1051                 case 0x1001:
1052                         rev_str = "Z";
1053                         break;
1054                 }
1055                 break;
1056
1057         case 0x422:
1058                 device_str = "STM32F302xB/C";
1059
1060                 switch (rev_id) {
1061                 case 0x1000:
1062                         rev_str = "A";
1063                         break;
1064
1065                 case 0x1001:
1066                         rev_str = "Z";
1067                         break;
1068
1069                 case 0x1003:
1070                         rev_str = "Y";
1071                         break;
1072
1073                 case 0x2000:
1074                         rev_str = "B";
1075                         break;
1076                 }
1077                 break;
1078
1079         case 0x428:
1080                 device_str = "STM32F100 (High Density)";
1081
1082                 switch (rev_id) {
1083                 case 0x1000:
1084                         rev_str = "A";
1085                         break;
1086
1087                 case 0x1001:
1088                         rev_str = "Z";
1089                         break;
1090                 }
1091                 break;
1092
1093         case 0x430:
1094                 device_str = "STM32F10x (XL Density)";
1095
1096                 switch (rev_id) {
1097                 case 0x1000:
1098                         rev_str = "A";
1099                         break;
1100                 }
1101                 break;
1102
1103         case 0x432:
1104                 device_str = "STM32F37x";
1105
1106                 switch (rev_id) {
1107                 case 0x1000:
1108                         rev_str = "A";
1109                         break;
1110
1111                 case 0x2000:
1112                         rev_str = "B";
1113                         break;
1114                 }
1115                 break;
1116
1117         case 0x438:
1118                 device_str = "STM32F33x";
1119
1120                 switch (rev_id) {
1121                 case 0x1000:
1122                         rev_str = "A";
1123                         break;
1124                 }
1125                 break;
1126
1127         case 0x439:
1128                 device_str = "STM32F302x6/8";
1129
1130                 switch (rev_id) {
1131                 case 0x1000:
1132                         rev_str = "A";
1133                         break;
1134
1135                 case 0x1001:
1136                         rev_str = "Z";
1137                         break;
1138                 }
1139                 break;
1140
1141         case 0x444:
1142                 device_str = "STM32F03x";
1143                 rev_str = get_stm32f0_revision(rev_id);
1144                 break;
1145
1146         case 0x440:
1147                 device_str = "STM32F05x";
1148                 rev_str = get_stm32f0_revision(rev_id);
1149                 break;
1150
1151         case 0x445:
1152                 device_str = "STM32F04x";
1153                 rev_str = get_stm32f0_revision(rev_id);
1154                 break;
1155
1156         case 0x446:
1157                 device_str = "STM32F303xD/E";
1158                 switch (rev_id) {
1159                 case 0x1000:
1160                         rev_str = "A";
1161                         break;
1162                 }
1163                 break;
1164
1165         case 0x448:
1166                 device_str = "STM32F07x";
1167                 rev_str = get_stm32f0_revision(rev_id);
1168                 break;
1169
1170         case 0x442:
1171                 device_str = "STM32F09x";
1172                 rev_str = get_stm32f0_revision(rev_id);
1173                 break;
1174
1175         default:
1176                 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1177                 return ERROR_FAIL;
1178         }
1179
1180         if (rev_str)
1181                 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1182         else
1183                 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1184
1185         return ERROR_OK;
1186 }
1187
1188 COMMAND_HANDLER(stm32x_handle_lock_command)
1189 {
1190         struct target *target = NULL;
1191         struct stm32x_flash_bank *stm32x_info = NULL;
1192
1193         if (CMD_ARGC < 1)
1194                 return ERROR_COMMAND_SYNTAX_ERROR;
1195
1196         struct flash_bank *bank;
1197         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1198         if (retval != ERROR_OK)
1199                 return retval;
1200
1201         stm32x_info = bank->driver_priv;
1202
1203         target = bank->target;
1204
1205         if (target->state != TARGET_HALTED) {
1206                 LOG_ERROR("Target not halted");
1207                 return ERROR_TARGET_NOT_HALTED;
1208         }
1209
1210         retval = stm32x_check_operation_supported(bank);
1211         if (retval != ERROR_OK)
1212                 return retval;
1213
1214         if (stm32x_erase_options(bank) != ERROR_OK) {
1215                 command_print(CMD, "stm32x failed to erase options");
1216                 return ERROR_OK;
1217         }
1218
1219         /* set readout protection */
1220         stm32x_info->option_bytes.rdp = 0;
1221
1222         if (stm32x_write_options(bank) != ERROR_OK) {
1223                 command_print(CMD, "stm32x failed to lock device");
1224                 return ERROR_OK;
1225         }
1226
1227         command_print(CMD, "stm32x locked");
1228
1229         return ERROR_OK;
1230 }
1231
1232 COMMAND_HANDLER(stm32x_handle_unlock_command)
1233 {
1234         struct target *target = NULL;
1235
1236         if (CMD_ARGC < 1)
1237                 return ERROR_COMMAND_SYNTAX_ERROR;
1238
1239         struct flash_bank *bank;
1240         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1241         if (retval != ERROR_OK)
1242                 return retval;
1243
1244         target = bank->target;
1245
1246         if (target->state != TARGET_HALTED) {
1247                 LOG_ERROR("Target not halted");
1248                 return ERROR_TARGET_NOT_HALTED;
1249         }
1250
1251         retval = stm32x_check_operation_supported(bank);
1252         if (retval != ERROR_OK)
1253                 return retval;
1254
1255         if (stm32x_erase_options(bank) != ERROR_OK) {
1256                 command_print(CMD, "stm32x failed to erase options");
1257                 return ERROR_OK;
1258         }
1259
1260         if (stm32x_write_options(bank) != ERROR_OK) {
1261                 command_print(CMD, "stm32x failed to unlock device");
1262                 return ERROR_OK;
1263         }
1264
1265         command_print(CMD, "stm32x unlocked.\n"
1266                         "INFO: a reset or power cycle is required "
1267                         "for the new settings to take effect.");
1268
1269         return ERROR_OK;
1270 }
1271
1272 COMMAND_HANDLER(stm32x_handle_options_read_command)
1273 {
1274         uint32_t optionbyte, protection;
1275         struct target *target = NULL;
1276         struct stm32x_flash_bank *stm32x_info = NULL;
1277
1278         if (CMD_ARGC < 1)
1279                 return ERROR_COMMAND_SYNTAX_ERROR;
1280
1281         struct flash_bank *bank;
1282         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1283         if (retval != ERROR_OK)
1284                 return retval;
1285
1286         stm32x_info = bank->driver_priv;
1287
1288         target = bank->target;
1289
1290         if (target->state != TARGET_HALTED) {
1291                 LOG_ERROR("Target not halted");
1292                 return ERROR_TARGET_NOT_HALTED;
1293         }
1294
1295         retval = stm32x_check_operation_supported(bank);
1296         if (retval != ERROR_OK)
1297                 return retval;
1298
1299         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1300         if (retval != ERROR_OK)
1301                 return retval;
1302
1303         uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1304
1305         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1306         if (retval != ERROR_OK)
1307                 return retval;
1308
1309         if (optionbyte & (1 << OPT_ERROR))
1310                 command_print(CMD, "option byte complement error");
1311
1312         command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1313         command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1314
1315         command_print(CMD, "read protection: %s",
1316                                 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1317
1318         /* user option bytes are offset depending on variant */
1319         optionbyte >>= stm32x_info->option_offset;
1320
1321         command_print(CMD, "watchdog: %sware",
1322                                 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1323
1324         command_print(CMD, "stop mode: %sreset generated upon entry",
1325                                 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1326
1327         command_print(CMD, "standby mode: %sreset generated upon entry",
1328                                 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1329
1330         if (stm32x_info->has_dual_banks)
1331                 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1332
1333         command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1334
1335         return ERROR_OK;
1336 }
1337
1338 COMMAND_HANDLER(stm32x_handle_options_write_command)
1339 {
1340         struct target *target = NULL;
1341         struct stm32x_flash_bank *stm32x_info = NULL;
1342         uint8_t optionbyte;
1343         uint16_t useropt;
1344
1345         if (CMD_ARGC < 2)
1346                 return ERROR_COMMAND_SYNTAX_ERROR;
1347
1348         struct flash_bank *bank;
1349         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1350         if (retval != ERROR_OK)
1351                 return retval;
1352
1353         stm32x_info = bank->driver_priv;
1354
1355         target = bank->target;
1356
1357         if (target->state != TARGET_HALTED) {
1358                 LOG_ERROR("Target not halted");
1359                 return ERROR_TARGET_NOT_HALTED;
1360         }
1361
1362         retval = stm32x_check_operation_supported(bank);
1363         if (retval != ERROR_OK)
1364                 return retval;
1365
1366         retval = stm32x_read_options(bank);
1367         if (retval != ERROR_OK)
1368                 return retval;
1369
1370         /* start with current options */
1371         optionbyte = stm32x_info->option_bytes.user;
1372         useropt = stm32x_info->option_bytes.data;
1373
1374         /* skip over flash bank */
1375         CMD_ARGC--;
1376         CMD_ARGV++;
1377
1378         while (CMD_ARGC) {
1379                 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1380                         optionbyte |= (1 << 0);
1381                 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1382                         optionbyte &= ~(1 << 0);
1383                 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1384                         optionbyte |= (1 << 1);
1385                 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1386                         optionbyte &= ~(1 << 1);
1387                 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1388                         optionbyte |= (1 << 2);
1389                 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1390                         optionbyte &= ~(1 << 2);
1391                 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1392                         if (CMD_ARGC < 2)
1393                                 return ERROR_COMMAND_SYNTAX_ERROR;
1394                         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1395                         CMD_ARGC--;
1396                         CMD_ARGV++;
1397                 } else if (stm32x_info->has_dual_banks) {
1398                         if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1399                                 optionbyte |= (1 << 3);
1400                         else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1401                                 optionbyte &= ~(1 << 3);
1402                         else
1403                                 return ERROR_COMMAND_SYNTAX_ERROR;
1404                 } else
1405                         return ERROR_COMMAND_SYNTAX_ERROR;
1406                 CMD_ARGC--;
1407                 CMD_ARGV++;
1408         }
1409
1410         if (stm32x_erase_options(bank) != ERROR_OK) {
1411                 command_print(CMD, "stm32x failed to erase options");
1412                 return ERROR_OK;
1413         }
1414
1415         stm32x_info->option_bytes.user = optionbyte;
1416         stm32x_info->option_bytes.data = useropt;
1417
1418         if (stm32x_write_options(bank) != ERROR_OK) {
1419                 command_print(CMD, "stm32x failed to write options");
1420                 return ERROR_OK;
1421         }
1422
1423         command_print(CMD, "stm32x write options complete.\n"
1424                                 "INFO: %spower cycle is required "
1425                                 "for the new settings to take effect.",
1426                                 stm32x_info->can_load_options
1427                                         ? "'stm32f1x options_load' command or " : "");
1428
1429         return ERROR_OK;
1430 }
1431
1432 COMMAND_HANDLER(stm32x_handle_options_load_command)
1433 {
1434         if (CMD_ARGC < 1)
1435                 return ERROR_COMMAND_SYNTAX_ERROR;
1436
1437         struct flash_bank *bank;
1438         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1439         if (retval != ERROR_OK)
1440                 return retval;
1441
1442         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1443
1444         if (!stm32x_info->can_load_options) {
1445                 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1446                         "required instead.");
1447                 return ERROR_FAIL;
1448         }
1449
1450         struct target *target = bank->target;
1451
1452         if (target->state != TARGET_HALTED) {
1453                 LOG_ERROR("Target not halted");
1454                 return ERROR_TARGET_NOT_HALTED;
1455         }
1456
1457         retval = stm32x_check_operation_supported(bank);
1458         if (retval != ERROR_OK)
1459                 return retval;
1460
1461         /* unlock option flash registers */
1462         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1463         if (retval != ERROR_OK)
1464                 return retval;
1465         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1466         if (retval != ERROR_OK)
1467                 return retval;
1468
1469         /* force re-load of option bytes - generates software reset */
1470         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1471         if (retval != ERROR_OK)
1472                 return retval;
1473
1474         return ERROR_OK;
1475 }
1476
1477 static int stm32x_mass_erase(struct flash_bank *bank)
1478 {
1479         struct target *target = bank->target;
1480
1481         if (target->state != TARGET_HALTED) {
1482                 LOG_ERROR("Target not halted");
1483                 return ERROR_TARGET_NOT_HALTED;
1484         }
1485
1486         /* unlock option flash registers */
1487         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1488         if (retval != ERROR_OK)
1489                 return retval;
1490         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1491         if (retval != ERROR_OK)
1492                 return retval;
1493
1494         /* mass erase flash memory */
1495         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1496         if (retval != ERROR_OK)
1497                 return retval;
1498         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1499                         FLASH_MER | FLASH_STRT);
1500         if (retval != ERROR_OK)
1501                 return retval;
1502
1503         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1504         if (retval != ERROR_OK)
1505                 return retval;
1506
1507         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1508         if (retval != ERROR_OK)
1509                 return retval;
1510
1511         return ERROR_OK;
1512 }
1513
1514 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1515 {
1516         if (CMD_ARGC < 1)
1517                 return ERROR_COMMAND_SYNTAX_ERROR;
1518
1519         struct flash_bank *bank;
1520         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1521         if (retval != ERROR_OK)
1522                 return retval;
1523
1524         retval = stm32x_mass_erase(bank);
1525         if (retval == ERROR_OK)
1526                 command_print(CMD, "stm32x mass erase complete");
1527         else
1528                 command_print(CMD, "stm32x mass erase failed");
1529
1530         return retval;
1531 }
1532
1533 static const struct command_registration stm32x_exec_command_handlers[] = {
1534         {
1535                 .name = "lock",
1536                 .handler = stm32x_handle_lock_command,
1537                 .mode = COMMAND_EXEC,
1538                 .usage = "bank_id",
1539                 .help = "Lock entire flash device.",
1540         },
1541         {
1542                 .name = "unlock",
1543                 .handler = stm32x_handle_unlock_command,
1544                 .mode = COMMAND_EXEC,
1545                 .usage = "bank_id",
1546                 .help = "Unlock entire protected flash device.",
1547         },
1548         {
1549                 .name = "mass_erase",
1550                 .handler = stm32x_handle_mass_erase_command,
1551                 .mode = COMMAND_EXEC,
1552                 .usage = "bank_id",
1553                 .help = "Erase entire flash device.",
1554         },
1555         {
1556                 .name = "options_read",
1557                 .handler = stm32x_handle_options_read_command,
1558                 .mode = COMMAND_EXEC,
1559                 .usage = "bank_id",
1560                 .help = "Read and display device option bytes.",
1561         },
1562         {
1563                 .name = "options_write",
1564                 .handler = stm32x_handle_options_write_command,
1565                 .mode = COMMAND_EXEC,
1566                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1567                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1568                         "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1569                 .help = "Replace bits in device option bytes.",
1570         },
1571         {
1572                 .name = "options_load",
1573                 .handler = stm32x_handle_options_load_command,
1574                 .mode = COMMAND_EXEC,
1575                 .usage = "bank_id",
1576                 .help = "Force re-load of device option bytes.",
1577         },
1578         COMMAND_REGISTRATION_DONE
1579 };
1580
1581 static const struct command_registration stm32x_command_handlers[] = {
1582         {
1583                 .name = "stm32f1x",
1584                 .mode = COMMAND_ANY,
1585                 .help = "stm32f1x flash command group",
1586                 .usage = "",
1587                 .chain = stm32x_exec_command_handlers,
1588         },
1589         COMMAND_REGISTRATION_DONE
1590 };
1591
1592 const struct flash_driver stm32f1x_flash = {
1593         .name = "stm32f1x",
1594         .commands = stm32x_command_handlers,
1595         .flash_bank_command = stm32x_flash_bank_command,
1596         .erase = stm32x_erase,
1597         .protect = stm32x_protect,
1598         .write = stm32x_write,
1599         .read = default_flash_read,
1600         .probe = stm32x_probe,
1601         .auto_probe = stm32x_auto_probe,
1602         .erase_check = default_flash_blank_check,
1603         .protect_check = stm32x_protect_check,
1604         .info = get_stm32x_info,
1605         .free_driver_priv = default_flash_free_driver_priv,
1606 };