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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *                                                                         *
  11  *   Copyright (C) 2013 by Roman Dmitrienko                                *
  12  *   me@iamroman.org                                                       *
  13  *                                                                         *
  14  *   Copyright (C) 2014 Nemui Trinomius                                    *
  15  *   nemuisan_kawausogasuki@live.jp                                        *
  16  *                                                                         *
  17  *   Copyright (C) 2021 Doug Brunner                                       *
  18  *   doug.a.brunner@gmail.com                                              *
  19  *                                                                         *
  20  *   This program is free software; you can redistribute it and/or modify  *
  21  *   it under the terms of the GNU General Public License as published by  *
  22  *   the Free Software Foundation; either version 2 of the License, or     *
  23  *   (at your option) any later version.                                   *
  24  *                                                                         *
  25  *   This program is distributed in the hope that it will be useful,       *
  26  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  27  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  28  *   GNU General Public License for more details.                          *
  29  *                                                                         *
  30  *   You should have received a copy of the GNU General Public License     *
  31  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  32  ***************************************************************************/
  33
  34 #ifdef HAVE_CONFIG_H
  35 #include "config.h"
  36 #endif
  37
  38 #include "imp.h"
  39 #include <helper/binarybuffer.h>
  40 #include <target/algorithm.h>
  41 #include <target/armv7m.h>
  42 #include <target/cortex_m.h>
  43
  44 #define EFM_FAMILY_ID_GIANT_GECKO       72
  45 #define EFM_FAMILY_ID_LEOPARD_GECKO     74
  46
  47 #define EFM32_FLASH_ERASE_TMO           100
  48 #define EFM32_FLASH_WDATAREADY_TMO      100
  49 #define EFM32_FLASH_WRITE_TMO           100
  50
  51 #define EFM32_FLASH_BASE                0
  52
  53 /* size in bytes, not words; must fit all Gecko devices */
  54 #define LOCKWORDS_SZ                512
  55
  56 #define EFM32_MSC_INFO_BASE             0x0fe00000
  57
  58 #define EFM32_MSC_USER_DATA             EFM32_MSC_INFO_BASE
  59 #define EFM32_MSC_LOCK_BITS             (EFM32_MSC_INFO_BASE+0x4000)
  60 #define EFM32_MSC_LOCK_BITS_EXTRA       (EFM32_MSC_LOCK_BITS+LOCKWORDS_SZ)
  61 #define EFM32_MSC_DEV_INFO              (EFM32_MSC_INFO_BASE+0x8000)
  62
  63 /* PAGE_SIZE is not present in Zero, Happy and the original Gecko MCU */
  64 #define EFM32_MSC_DI_PAGE_SIZE          (EFM32_MSC_DEV_INFO+0x1e7)
  65 #define EFM32_MSC_DI_FLASH_SZ           (EFM32_MSC_DEV_INFO+0x1f8)
  66 #define EFM32_MSC_DI_RAM_SZ             (EFM32_MSC_DEV_INFO+0x1fa)
  67 #define EFM32_MSC_DI_PART_NUM           (EFM32_MSC_DEV_INFO+0x1fc)
  68 #define EFM32_MSC_DI_PART_FAMILY        (EFM32_MSC_DEV_INFO+0x1fe)
  69 #define EFM32_MSC_DI_PROD_REV           (EFM32_MSC_DEV_INFO+0x1ff)
  70
  71 #define EFM32_MSC_REGBASE               0x400c0000
  72 #define EFM32_MSC_REGBASE_SERIES1       0x400e0000
  73 #define EFM32_MSC_REG_WRITECTRL         0x008
  74 #define EFM32_MSC_WRITECTRL_WREN_MASK   0x1
  75 #define EFM32_MSC_REG_WRITECMD          0x00c
  76 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
  77 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
  78 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
  79 #define EFM32_MSC_REG_ADDRB             0x010
  80 #define EFM32_MSC_REG_WDATA             0x018
  81 #define EFM32_MSC_REG_STATUS            0x01c
  82 #define EFM32_MSC_STATUS_BUSY_MASK      0x1
  83 #define EFM32_MSC_STATUS_LOCKED_MASK    0x2
  84 #define EFM32_MSC_STATUS_INVADDR_MASK   0x4
  85 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
  86 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
  87 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
  88 #define EFM32_MSC_REG_LOCK              0x03c
  89 #define EFM32_MSC_REG_LOCK_SERIES1      0x040
  90 #define EFM32_MSC_LOCK_LOCKKEY          0x1b71
  91
  92 enum efm32_bank_index {
  93         EFM32_BANK_INDEX_MAIN,
  94         EFM32_BANK_INDEX_USER_DATA,
  95         EFM32_BANK_INDEX_LOCK_BITS,
  96         EFM32_N_BANKS
  97 };
  98
  99 static int efm32x_get_bank_index(target_addr_t base)
 100 {
 101         switch (base) {
 102                 case EFM32_FLASH_BASE:
 103                         return EFM32_BANK_INDEX_MAIN;
 104                 case EFM32_MSC_USER_DATA:
 105                         return EFM32_BANK_INDEX_USER_DATA;
 106                 case EFM32_MSC_LOCK_BITS:
 107                         return EFM32_BANK_INDEX_LOCK_BITS;
 108                 default:
 109                         return ERROR_FAIL;
 110         }
 111 }
 112
 113 struct efm32_family_data {
 114         int family_id;
 115         const char *name;
 116
 117         /* EFM32 series (EFM32LG995F is the "old" series 0, while EFR32MG12P132
 118            is the "new" series 1). Determines location of MSC registers. */
 119         int series;
 120
 121         /* Page size in bytes, or 0 to read from EFM32_MSC_DI_PAGE_SIZE */
 122         int page_size;
 123
 124         /* MSC register base address, or 0 to use default */
 125         uint32_t msc_regbase;
 126 };
 127
 128 struct efm32_info {
 129         const struct efm32_family_data *family_data;
 130         uint16_t flash_sz_kib;
 131         uint16_t ram_sz_kib;
 132         uint16_t part_num;
 133         uint8_t part_family;
 134         uint8_t prod_rev;
 135         uint16_t page_size;
 136 };
 137
 138 struct efm32x_flash_chip {
 139         struct efm32_info info;
 140         bool probed[EFM32_N_BANKS];
 141         uint32_t lb_page[LOCKWORDS_SZ/4];
 142         uint32_t reg_base;
 143         uint32_t reg_lock;
 144         uint32_t refcount;
 145 };
 146
 147 static const struct efm32_family_data efm32_families[] = {
 148                 { 16, "EFR32MG1P Mighty", .series = 1 },
 149                 { 17, "EFR32MG1B Mighty", .series = 1 },
 150                 { 18, "EFR32MG1V Mighty", .series = 1 },
 151                 { 19, "EFR32BG1P Blue", .series = 1 },
 152                 { 20, "EFR32BG1B Blue", .series = 1 },
 153                 { 21, "EFR32BG1V Blue", .series = 1 },
 154                 { 25, "EFR32FG1P Flex", .series = 1 },
 155                 { 26, "EFR32FG1B Flex", .series = 1 },
 156                 { 27, "EFR32FG1V Flex", .series = 1 },
 157                 { 28, "EFR32MG2P Mighty", .series = 1 },
 158                 { 29, "EFR32MG2B Mighty", .series = 1 },
 159                 { 30, "EFR32MG2V Mighty", .series = 1 },
 160                 { 31, "EFR32BG12P Blue", .series = 1 },
 161                 { 32, "EFR32BG12B Blue", .series = 1 },
 162                 { 33, "EFR32BG12V Blue", .series = 1 },
 163                 { 37, "EFR32FG12P Flex", .series = 1 },
 164                 { 38, "EFR32FG12B Flex", .series = 1 },
 165                 { 39, "EFR32FG12V Flex", .series = 1 },
 166                 { 40, "EFR32MG13P Mighty", .series = 1 },
 167                 { 41, "EFR32MG13B Mighty", .series = 1 },
 168                 { 42, "EFR32MG13V Mighty", .series = 1 },
 169                 { 43, "EFR32BG13P Blue", .series = 1 },
 170                 { 44, "EFR32BG13B Blue", .series = 1 },
 171                 { 45, "EFR32BG13V Blue", .series = 1 },
 172                 { 46, "EFR32ZG13P Zen", .series = 1 },
 173                 { 49, "EFR32FG13P Flex", .series = 1 },
 174                 { 50, "EFR32FG13B Flex", .series = 1 },
 175                 { 51, "EFR32FG13V Flex", .series = 1 },
 176                 { 52, "EFR32MG14P Mighty", .series = 1 },
 177                 { 53, "EFR32MG14B Mighty", .series = 1 },
 178                 { 54, "EFR32MG14V Mighty", .series = 1 },
 179                 { 55, "EFR32BG14P Blue", .series = 1 },
 180                 { 56, "EFR32BG14B Blue", .series = 1 },
 181                 { 57, "EFR32BG14V Blue", .series = 1 },
 182                 { 58, "EFR32ZG14P Zen", .series = 1 },
 183                 { 61, "EFR32FG14P Flex", .series = 1 },
 184                 { 62, "EFR32FG14B Flex", .series = 1 },
 185                 { 63, "EFR32FG14V Flex", .series = 1 },
 186                 { 71, "EFM32G", .series = 0, .page_size = 512 },
 187                 { 72, "EFM32GG Giant", .series = 0 },
 188                 { 73, "EFM32TG Tiny", .series = 0, .page_size = 512 },
 189                 { 74, "EFM32LG Leopard", .series = 0 },
 190                 { 75, "EFM32WG Wonder", .series = 0 },
 191                 { 76, "EFM32ZG Zero", .series = 0, .page_size = 1024 },
 192                 { 77, "EFM32HG Happy", .series = 0, .page_size = 1024 },
 193                 { 81, "EFM32PG1B Pearl", .series = 1 },
 194                 { 83, "EFM32JG1B Jade", .series = 1 },
 195                 { 85, "EFM32PG12B Pearl", .series = 1 },
 196                 { 87, "EFM32JG12B Jade", .series = 1 },
 197                 { 89, "EFM32PG13B Pearl", .series = 1 },
 198                 { 91, "EFM32JG13B Jade", .series = 1 },
 199                 { 100, "EFM32GG11B Giant", .series = 1, .msc_regbase = 0x40000000 },
 200                 { 103, "EFM32TG11B Tiny", .series = 1, .msc_regbase = 0x40000000 },
 201                 { 106, "EFM32GG12B Giant", .series = 1, .msc_regbase = 0x40000000 },
 202                 { 120, "EZR32WG Wonder", .series = 0 },
 203                 { 121, "EZR32LG Leopard", .series = 0 },
 204                 { 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },
 205 };
 206
 207 const struct flash_driver efm32_flash;
 208
 209 static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 210         uint32_t addr, uint32_t count);
 211
 212 static int efm32x_write_only_lockbits(struct flash_bank *bank);
 213
 214 static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
 215 {
 216         return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
 217 }
 218
 219 static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
 220 {
 221         return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
 222 }
 223
 224 static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
 225 {
 226         return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
 227 }
 228
 229 static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
 230 {
 231         return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
 232 }
 233
 234 static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
 235 {
 236         return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
 237 }
 238
 239 static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
 240                                uint32_t *value)
 241 {
 242         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 243         uint32_t base = efm32x_info->reg_base;
 244
 245         return target_read_u32(bank->target, base + offset, value);
 246 }
 247
 248 static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
 249                                uint32_t value)
 250 {
 251         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 252         uint32_t base = efm32x_info->reg_base;
 253
 254         return target_write_u32(bank->target, base + offset, value);
 255 }
 256
 257 static int efm32x_read_info(struct flash_bank *bank)
 258 {
 259         int ret;
 260         uint32_t cpuid = 0;
 261         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 262         struct efm32_info *efm32_info = &(efm32x_info->info);
 263
 264         memset(efm32_info, 0, sizeof(struct efm32_info));
 265
 266         ret = target_read_u32(bank->target, CPUID, &cpuid);
 267         if (ret != ERROR_OK)
 268                 return ret;
 269
 270         if (((cpuid >> 4) & 0xfff) == 0xc23) {
 271                 /* Cortex-M3 device */
 272         } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
 273                 /* Cortex-M4 device (WONDER GECKO) */
 274         } else if (((cpuid >> 4) & 0xfff) == 0xc60) {
 275                 /* Cortex-M0+ device */
 276         } else {
 277                 LOG_ERROR("Target is not Cortex-Mx Device");
 278                 return ERROR_FAIL;
 279         }
 280
 281         ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
 282         if (ret != ERROR_OK)
 283                 return ret;
 284
 285         ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
 286         if (ret != ERROR_OK)
 287                 return ret;
 288
 289         ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
 290         if (ret != ERROR_OK)
 291                 return ret;
 292
 293         ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
 294         if (ret != ERROR_OK)
 295                 return ret;
 296
 297         ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
 298         if (ret != ERROR_OK)
 299                 return ret;
 300
 301         for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
 302                 if (efm32_families[i].family_id == efm32_info->part_family)
 303                         efm32_info->family_data = &efm32_families[i];
 304         }
 305
 306         if (!efm32_info->family_data) {
 307                 LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
 308                 return ERROR_FAIL;
 309         }
 310
 311         switch (efm32_info->family_data->series) {
 312                 case 0:
 313                         efm32x_info->reg_base = EFM32_MSC_REGBASE;
 314                         efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
 315                         break;
 316                 case 1:
 317                         efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1;
 318                         efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1;
 319                         break;
 320         }
 321
 322         if (efm32_info->family_data->msc_regbase != 0)
 323                 efm32x_info->reg_base = efm32_info->family_data->msc_regbase;
 324
 325         if (efm32_info->family_data->page_size != 0) {
 326                 efm32_info->page_size = efm32_info->family_data->page_size;
 327         } else {
 328                 uint8_t pg_size = 0;
 329                 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
 330                         &pg_size);
 331                 if (ret != ERROR_OK)
 332                         return ret;
 333
 334                 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
 335
 336                 if (efm32_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
 337                                 efm32_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
 338                         /* Giant or Leopard Gecko */
 339                         if (efm32_info->prod_rev < 18) {
 340                                 /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
 341                                    for MCUs with PROD_REV < 18 */
 342                                 if (efm32_info->flash_sz_kib < 512)
 343                                         efm32_info->page_size = 2048;
 344                                 else
 345                                         efm32_info->page_size = 4096;
 346                         }
 347                 }
 348
 349                 if ((efm32_info->page_size != 2048) &&
 350                                 (efm32_info->page_size != 4096)) {
 351                         LOG_ERROR("Invalid page size %u", efm32_info->page_size);
 352                         return ERROR_FAIL;
 353                 }
 354         }
 355
 356         return ERROR_OK;
 357 }
 358
 359 /* flash bank efm32 <base> <size> 0 0 <target#> */
 360 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
 361 {
 362         struct efm32x_flash_chip *efm32x_info = NULL;
 363
 364         if (CMD_ARGC < 6)
 365                 return ERROR_COMMAND_SYNTAX_ERROR;
 366
 367         int bank_index = efm32x_get_bank_index(bank->base);
 368         if (bank_index < 0) {
 369                 LOG_ERROR("Flash bank with base address %" PRIx32 " is not supported",
 370                         (uint32_t) bank->base);
 371                 return ERROR_FAIL;
 372         }
 373
 374         /* look for an existing flash structure matching target */
 375         for (struct flash_bank *bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
 376                 if (bank_iter->driver == &efm32_flash
 377                         && bank_iter->target == bank->target
 378                         && bank->driver_priv) {
 379                         efm32x_info = bank->driver_priv;
 380                         break;
 381                 }
 382         }
 383
 384         if (!efm32x_info) {
 385                 /* target not matched, make a new one */
 386                 efm32x_info = calloc(1, sizeof(struct efm32x_flash_chip));
 387
 388                 memset(efm32x_info->lb_page, 0xff, LOCKWORDS_SZ);
 389         }
 390
 391         ++efm32x_info->refcount;
 392         bank->driver_priv = efm32x_info;
 393
 394         return ERROR_OK;
 395 }
 396
 397 /**
 398  * Remove flash structure corresponding to this bank,
 399  * if and only if it's not used by any others
 400  */
 401 static void efm32x_free_driver_priv(struct flash_bank *bank)
 402 {
 403         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 404
 405         if (efm32x_info) {
 406                 /* Use ref count to determine if it can be freed; scanning bank list doesn't work,
 407                  * because this function can be called after some banks in the list have been
 408                  * already destroyed */
 409                 --efm32x_info->refcount;
 410                 if (efm32x_info->refcount == 0) {
 411                         free(efm32x_info);
 412                         bank->driver_priv = NULL;
 413                 }
 414         }
 415 }
 416
 417 /* set or reset given bits in a register */
 418 static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
 419         uint32_t bitmask, int set)
 420 {
 421         int ret = 0;
 422         uint32_t reg_val = 0;
 423
 424         ret = efm32x_read_reg_u32(bank, reg, &reg_val);
 425         if (ret != ERROR_OK)
 426                 return ret;
 427
 428         if (set)
 429                 reg_val |= bitmask;
 430         else
 431                 reg_val &= ~bitmask;
 432
 433         return efm32x_write_reg_u32(bank, reg, reg_val);
 434 }
 435
 436 static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
 437 {
 438         return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
 439                 EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
 440 }
 441
 442 static int efm32x_msc_lock(struct flash_bank *bank, int lock)
 443 {
 444         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 445         return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
 446                 (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
 447 }
 448
 449 static int efm32x_wait_status(struct flash_bank *bank, int timeout,
 450         uint32_t wait_mask, int wait_for_set)
 451 {
 452         int ret = 0;
 453         uint32_t status = 0;
 454
 455         while (1) {
 456                 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 457                 if (ret != ERROR_OK)
 458                         break;
 459
 460                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 461
 462                 if (((status & wait_mask) == 0) && (wait_for_set == 0))
 463                         break;
 464                 else if (((status & wait_mask) != 0) && wait_for_set)
 465                         break;
 466
 467                 if (timeout-- <= 0) {
 468                         LOG_ERROR("timed out waiting for MSC status");
 469                         return ERROR_FAIL;
 470                 }
 471
 472                 alive_sleep(1);
 473         }
 474
 475         if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
 476                 LOG_WARNING("page erase was aborted");
 477
 478         return ret;
 479 }
 480
 481 static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
 482 {
 483         /* this function DOES NOT set WREN; must be set already */
 484         /* 1. write address to ADDRB
 485            2. write LADDRIM
 486            3. check status (INVADDR, LOCKED)
 487            4. write ERASEPAGE
 488            5. wait until !STATUS_BUSY
 489          */
 490         int ret = 0;
 491         uint32_t status = 0;
 492         LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
 493
 494         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
 495         if (ret != ERROR_OK)
 496                 return ret;
 497
 498         ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 499                 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 500         if (ret != ERROR_OK)
 501                 return ret;
 502
 503         ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 504         if (ret != ERROR_OK)
 505                 return ret;
 506
 507         LOG_DEBUG("status 0x%" PRIx32, status);
 508
 509         if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
 510                 LOG_ERROR("Page is locked");
 511                 return ERROR_FAIL;
 512         } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
 513                 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
 514                 return ERROR_FAIL;
 515         }
 516
 517         ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 518                 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
 519         if (ret != ERROR_OK)
 520                 return ret;
 521
 522         return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
 523                 EFM32_MSC_STATUS_BUSY_MASK, 0);
 524 }
 525
 526 static int efm32x_erase(struct flash_bank *bank, unsigned int first,
 527                 unsigned int last)
 528 {
 529         struct target *target = bank->target;
 530         int ret = 0;
 531
 532         if (target->state != TARGET_HALTED) {
 533                 LOG_ERROR("Target not halted");
 534                 return ERROR_TARGET_NOT_HALTED;
 535         }
 536
 537         efm32x_msc_lock(bank, 0);
 538         ret = efm32x_set_wren(bank, 1);
 539         if (ret != ERROR_OK) {
 540                 LOG_ERROR("Failed to enable MSC write");
 541                 return ret;
 542         }
 543
 544         for (unsigned int i = first; i <= last; i++) {
 545                 ret = efm32x_erase_page(bank, bank->base + bank->sectors[i].offset);
 546                 if (ret != ERROR_OK)
 547                         LOG_ERROR("Failed to erase page %d", i);
 548         }
 549
 550         ret = efm32x_set_wren(bank, 0);
 551         efm32x_msc_lock(bank, 1);
 552         if (ret != ERROR_OK)
 553                 return ret;
 554
 555         if (bank->base == EFM32_MSC_LOCK_BITS) {
 556                 ret = efm32x_write_only_lockbits(bank);
 557                 if (ret != ERROR_OK)
 558                         LOG_ERROR("Failed to restore lockbits after erase");
 559         }
 560
 561         return ret;
 562 }
 563
 564 static int efm32x_read_lock_data(struct flash_bank *bank)
 565 {
 566         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 567         struct target *target = bank->target;
 568         int data_size = 0;
 569         uint32_t *ptr = NULL;
 570         int ret = 0;
 571
 572         assert(bank->num_sectors > 0);
 573
 574         /* calculate the number of 32-bit words to read (one lock bit per sector) */
 575         data_size = (bank->num_sectors + 31) / 32;
 576
 577         ptr = efm32x_info->lb_page;
 578
 579         for (int i = 0; i < data_size; i++, ptr++) {
 580                 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
 581                 if (ret != ERROR_OK) {
 582                         LOG_ERROR("Failed to read PLW %d", i);
 583                         return ret;
 584                 }
 585         }
 586
 587         /* also, read ULW, DLW, MLW, ALW and CLW words */
 588
 589         /* ULW, word 126 */
 590         ptr = efm32x_info->lb_page + 126;
 591         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
 592         if (ret != ERROR_OK) {
 593                 LOG_ERROR("Failed to read ULW");
 594                 return ret;
 595         }
 596
 597         /* DLW, word 127 */
 598         ptr = efm32x_info->lb_page + 127;
 599         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
 600         if (ret != ERROR_OK) {
 601                 LOG_ERROR("Failed to read DLW");
 602                 return ret;
 603         }
 604
 605         /* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
 606         ptr = efm32x_info->lb_page + 125;
 607         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
 608         if (ret != ERROR_OK) {
 609                 LOG_ERROR("Failed to read MLW");
 610                 return ret;
 611         }
 612
 613         /* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
 614         ptr = efm32x_info->lb_page + 124;
 615         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
 616         if (ret != ERROR_OK) {
 617                 LOG_ERROR("Failed to read ALW");
 618                 return ret;
 619         }
 620
 621         /* CLW1, word 123, present in EFR32 */
 622         ptr = efm32x_info->lb_page + 123;
 623         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
 624         if (ret != ERROR_OK) {
 625                 LOG_ERROR("Failed to read CLW1");
 626                 return ret;
 627         }
 628
 629         /* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
 630         ptr = efm32x_info->lb_page + 122;
 631         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
 632         if (ret != ERROR_OK) {
 633                 LOG_ERROR("Failed to read CLW0");
 634                 return ret;
 635         }
 636
 637         return ERROR_OK;
 638 }
 639
 640 static int efm32x_write_only_lockbits(struct flash_bank *bank)
 641 {
 642         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 643         return efm32x_priv_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS, LOCKWORDS_SZ);
 644 }
 645
 646 static int efm32x_write_lock_data(struct flash_bank *bank)
 647 {
 648         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 649         int ret = 0;
 650
 651         /* Preserve any data written to the high portion of the lockbits page */
 652         assert(efm32x_info->info.page_size >= LOCKWORDS_SZ);
 653         uint32_t extra_bytes = efm32x_info->info.page_size - LOCKWORDS_SZ;
 654         uint8_t *extra_data = NULL;
 655         if (extra_bytes) {
 656                 extra_data = malloc(extra_bytes);
 657                 ret = target_read_buffer(bank->target, EFM32_MSC_LOCK_BITS_EXTRA, extra_bytes, extra_data);
 658                 if (ret != ERROR_OK) {
 659                         LOG_ERROR("Failed to read extra contents of LB page");
 660                         free(extra_data);
 661                         return ret;
 662                 }
 663         }
 664
 665         ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
 666         if (ret != ERROR_OK) {
 667                 LOG_ERROR("Failed to erase LB page");
 668                 if (extra_data)
 669                         free(extra_data);
 670                 return ret;
 671         }
 672
 673         if (extra_data) {
 674                 ret = efm32x_priv_write(bank, extra_data, EFM32_MSC_LOCK_BITS_EXTRA, extra_bytes);
 675                 free(extra_data);
 676                 if (ret != ERROR_OK) {
 677                         LOG_ERROR("Failed to restore extra contents of LB page");
 678                         return ret;
 679                 }
 680         }
 681
 682         return efm32x_write_only_lockbits(bank);
 683 }
 684
 685 static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
 686 {
 687         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 688         uint32_t dw = 0;
 689         uint32_t mask = 0;
 690
 691         switch (bank->base) {
 692                 case EFM32_FLASH_BASE:
 693                         dw = efm32x_info->lb_page[page >> 5];
 694                         mask = 1 << (page & 0x1f);
 695                         break;
 696                 case EFM32_MSC_USER_DATA:
 697                         dw = efm32x_info->lb_page[126];
 698                         mask = 0x1;
 699                         break;
 700                 case EFM32_MSC_LOCK_BITS:
 701                         dw = efm32x_info->lb_page[126];
 702                         mask = 0x2;
 703                         break;
 704         }
 705
 706         return (dw & mask) ? 0 : 1;
 707 }
 708
 709 static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
 710 {
 711         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 712
 713         if (bank->base != EFM32_FLASH_BASE) {
 714                 LOG_ERROR("Locking user and lockbits pages is not supported yet");
 715                 return ERROR_FAIL;
 716         }
 717
 718         uint32_t *dw = &efm32x_info->lb_page[page >> 5];
 719         uint32_t mask = 0;
 720
 721         mask = 1 << (page & 0x1f);
 722
 723         if (!set)
 724                 *dw |= mask;
 725         else
 726                 *dw &= ~mask;
 727
 728         return ERROR_OK;
 729 }
 730
 731 static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 732                 unsigned int last)
 733 {
 734         struct target *target = bank->target;
 735         int ret = 0;
 736
 737         if (target->state != TARGET_HALTED) {
 738                 LOG_ERROR("Target not halted");
 739                 return ERROR_TARGET_NOT_HALTED;
 740         }
 741
 742         for (unsigned int i = first; i <= last; i++) {
 743                 ret = efm32x_set_page_lock(bank, i, set);
 744                 if (ret != ERROR_OK) {
 745                         LOG_ERROR("Failed to set lock on page %d", i);
 746                         return ret;
 747                 }
 748         }
 749
 750         ret = efm32x_write_lock_data(bank);
 751         if (ret != ERROR_OK) {
 752                 LOG_ERROR("Failed to write LB page");
 753                 return ret;
 754         }
 755
 756         return ERROR_OK;
 757 }
 758
 759 static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
 760         uint32_t address, uint32_t count)
 761 {
 762         struct target *target = bank->target;
 763         uint32_t buffer_size = 16384;
 764         struct working_area *write_algorithm;
 765         struct working_area *source;
 766         struct reg_param reg_params[5];
 767         struct armv7m_algorithm armv7m_info;
 768         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 769         int ret = ERROR_OK;
 770
 771         /* see contrib/loaders/flash/efm32.S for src */
 772         static const uint8_t efm32x_flash_write_code[] = {
 773                 /* #define EFM32_MSC_WRITECTRL_OFFSET      0x008 */
 774                 /* #define EFM32_MSC_WRITECMD_OFFSET       0x00c */
 775                 /* #define EFM32_MSC_ADDRB_OFFSET          0x010 */
 776                 /* #define EFM32_MSC_WDATA_OFFSET          0x018 */
 777                 /* #define EFM32_MSC_STATUS_OFFSET         0x01c */
 778
 779                         0x01, 0x26,    /* movs    r6, #1 */
 780                         0x86, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
 781
 782                 /* wait_fifo: */
 783                         0x16, 0x68,    /* ldr     r6, [r2, #0] */
 784                         0x00, 0x2e,    /* cmp     r6, #0 */
 785                         0x22, 0xd0,    /* beq     exit */
 786                         0x55, 0x68,    /* ldr     r5, [r2, #4] */
 787                         0xb5, 0x42,    /* cmp     r5, r6 */
 788                         0xf9, 0xd0,    /* beq     wait_fifo */
 789
 790                         0x04, 0x61,    /* str     r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
 791                         0x01, 0x26,    /* movs    r6, #1 */
 792                         0xc6, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
 793                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 794                         0x06, 0x27,    /* movs    r7, #6 */
 795                         0x3e, 0x42,    /* tst     r6, r7 */
 796                         0x16, 0xd1,    /* bne     error */
 797
 798                 /* wait_wdataready: */
 799                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 800                         0x08, 0x27,    /* movs    r7, #8 */
 801                         0x3e, 0x42,    /* tst     r6, r7 */
 802                         0xfb, 0xd0,    /* beq     wait_wdataready */
 803
 804                         0x2e, 0x68,    /* ldr     r6, [r5] */
 805                         0x86, 0x61,    /* str     r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
 806                         0x08, 0x26,    /* movs    r6, #8 */
 807                         0xc6, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
 808
 809                         0x04, 0x35,    /* adds    r5, #4 */
 810                         0x04, 0x34,    /* adds    r4, #4 */
 811
 812                 /* busy: */
 813                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 814                         0x01, 0x27,    /* movs    r7, #1 */
 815                         0x3e, 0x42,    /* tst     r6, r7 */
 816                         0xfb, 0xd1,    /* bne     busy */
 817
 818                         0x9d, 0x42,    /* cmp     r5, r3 */
 819                         0x01, 0xd3,    /* bcc     no_wrap */
 820                         0x15, 0x46,    /* mov     r5, r2 */
 821                         0x08, 0x35,    /* adds    r5, #8 */
 822
 823                 /* no_wrap: */
 824                         0x55, 0x60,    /* str     r5, [r2, #4] */
 825                         0x01, 0x39,    /* subs    r1, r1, #1 */
 826                         0x00, 0x29,    /* cmp     r1, #0 */
 827                         0x02, 0xd0,    /* beq     exit */
 828                         0xdb, 0xe7,    /* b       wait_fifo */
 829
 830                 /* error: */
 831                         0x00, 0x20,    /* movs    r0, #0 */
 832                         0x50, 0x60,    /* str     r0, [r2, #4] */
 833
 834                 /* exit: */
 835                         0x30, 0x46,    /* mov     r0, r6 */
 836                         0x00, 0xbe,    /* bkpt    #0 */
 837         };
 838
 839
 840         /* flash write code */
 841         if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
 842                         &write_algorithm) != ERROR_OK) {
 843                 LOG_WARNING("no working area available, can't do block memory writes");
 844                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 845         }
 846
 847         ret = target_write_buffer(target, write_algorithm->address,
 848                         sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
 849         if (ret != ERROR_OK)
 850                 return ret;
 851
 852         /* memory buffer */
 853         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 854                 buffer_size /= 2;
 855                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 856                 if (buffer_size <= 256) {
 857                         /* we already allocated the writing code, but failed to get a
 858                          * buffer, free the algorithm */
 859                         target_free_working_area(target, write_algorithm);
 860
 861                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 862                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 863                 }
 864         }
 865
 866         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 867         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (word-32bit) */
 868         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 869         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 870         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 871
 872         buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
 873         buf_set_u32(reg_params[1].value, 0, 32, count);
 874         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 875         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 876         buf_set_u32(reg_params[4].value, 0, 32, address);
 877
 878         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 879         armv7m_info.core_mode = ARM_MODE_THREAD;
 880
 881         ret = target_run_flash_async_algorithm(target, buf, count, 4,
 882                         0, NULL,
 883                         5, reg_params,
 884                         source->address, source->size,
 885                         write_algorithm->address, 0,
 886                         &armv7m_info);
 887
 888         if (ret == ERROR_FLASH_OPERATION_FAILED) {
 889                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 890                                 buf_get_u32(reg_params[4].value, 0, 32));
 891
 892                 if (buf_get_u32(reg_params[0].value, 0, 32) &
 893                                 EFM32_MSC_STATUS_LOCKED_MASK) {
 894                         LOG_ERROR("flash memory write protected");
 895                 }
 896
 897                 if (buf_get_u32(reg_params[0].value, 0, 32) &
 898                                 EFM32_MSC_STATUS_INVADDR_MASK) {
 899                         LOG_ERROR("invalid flash memory write address");
 900                 }
 901         }
 902
 903         target_free_working_area(target, source);
 904         target_free_working_area(target, write_algorithm);
 905
 906         destroy_reg_param(&reg_params[0]);
 907         destroy_reg_param(&reg_params[1]);
 908         destroy_reg_param(&reg_params[2]);
 909         destroy_reg_param(&reg_params[3]);
 910         destroy_reg_param(&reg_params[4]);
 911
 912         return ret;
 913 }
 914
 915 static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 916         uint32_t val)
 917 {
 918         /* this function DOES NOT set WREN; must be set already */
 919         /* 1. write address to ADDRB
 920            2. write LADDRIM
 921            3. check status (INVADDR, LOCKED)
 922            4. wait for WDATAREADY
 923            5. write data to WDATA
 924            6. write WRITECMD_WRITEONCE to WRITECMD
 925            7. wait until !STATUS_BUSY
 926          */
 927
 928         /* FIXME: EFM32G ref states (7.3.2) that writes should be
 929          * performed twice per dword */
 930
 931         int ret = 0;
 932         uint32_t status = 0;
 933
 934         /* if not called, GDB errors will be reported during large writes */
 935         keep_alive();
 936
 937         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
 938         if (ret != ERROR_OK)
 939                 return ret;
 940
 941         ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 942                 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 943         if (ret != ERROR_OK)
 944                 return ret;
 945
 946         ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 947         if (ret != ERROR_OK)
 948                 return ret;
 949
 950         LOG_DEBUG("status 0x%" PRIx32, status);
 951
 952         if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
 953                 LOG_ERROR("Page is locked");
 954                 return ERROR_FAIL;
 955         } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
 956                 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
 957                 return ERROR_FAIL;
 958         }
 959
 960         ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
 961                 EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
 962         if (ret != ERROR_OK) {
 963                 LOG_ERROR("Wait for WDATAREADY failed");
 964                 return ret;
 965         }
 966
 967         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
 968         if (ret != ERROR_OK) {
 969                 LOG_ERROR("WDATA write failed");
 970                 return ret;
 971         }
 972
 973         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
 974                 EFM32_MSC_WRITECMD_WRITEONCE_MASK);
 975         if (ret != ERROR_OK) {
 976                 LOG_ERROR("WRITECMD write failed");
 977                 return ret;
 978         }
 979
 980         ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
 981                 EFM32_MSC_STATUS_BUSY_MASK, 0);
 982         if (ret != ERROR_OK) {
 983                 LOG_ERROR("Wait for BUSY failed");
 984                 return ret;
 985         }
 986
 987         return ERROR_OK;
 988 }
 989
 990 static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 991                 uint32_t addr, uint32_t count)
 992 {
 993         struct target *target = bank->target;
 994         uint8_t *new_buffer = NULL;
 995
 996         if (target->state != TARGET_HALTED) {
 997                 LOG_ERROR("Target not halted");
 998                 return ERROR_TARGET_NOT_HALTED;
 999         }
1000
1001         if (addr & 0x3) {
1002                 LOG_ERROR("addr 0x%" PRIx32 " breaks required 4-byte "
1003                         "alignment", addr);
1004                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1005         }
1006
1007         if (count & 0x3) {
1008                 uint32_t old_count = count;
1009                 count = (old_count | 3) + 1;
1010                 new_buffer = malloc(count);
1011                 if (!new_buffer) {
1012                         LOG_ERROR("odd number of bytes to write and no memory "
1013                                 "for padding buffer");
1014                         return ERROR_FAIL;
1015                 }
1016                 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
1017                         "and padding with 0xff", old_count, count);
1018                 memset(new_buffer, 0xff, count);
1019                 buffer = memcpy(new_buffer, buffer, old_count);
1020         }
1021
1022         uint32_t words_remaining = count / 4;
1023         int retval, retval2;
1024
1025         /* unlock flash registers */
1026         efm32x_msc_lock(bank, 0);
1027         retval = efm32x_set_wren(bank, 1);
1028         if (retval != ERROR_OK)
1029                 goto cleanup;
1030
1031         /* try using a block write */
1032         retval = efm32x_write_block(bank, buffer, addr, words_remaining);
1033
1034         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1035                 /* if block write failed (no sufficient working area),
1036                  * we use normal (slow) single word accesses */
1037                 LOG_WARNING("couldn't use block writes, falling back to single "
1038                         "memory accesses");
1039
1040                 while (words_remaining > 0) {
1041                         uint32_t value;
1042                         memcpy(&value, buffer, sizeof(uint32_t));
1043
1044                         retval = efm32x_write_word(bank, addr, value);
1045                         if (retval != ERROR_OK)
1046                                 goto reset_pg_and_lock;
1047
1048                         words_remaining--;
1049                         buffer += 4;
1050                         addr += 4;
1051                 }
1052         }
1053
1054 reset_pg_and_lock:
1055         retval2 = efm32x_set_wren(bank, 0);
1056         efm32x_msc_lock(bank, 1);
1057         if (retval == ERROR_OK)
1058                 retval = retval2;
1059
1060 cleanup:
1061         free(new_buffer);
1062         return retval;
1063 }
1064
1065 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
1066                 uint32_t offset, uint32_t count)
1067 {
1068         if (bank->base == EFM32_MSC_LOCK_BITS && offset < LOCKWORDS_SZ) {
1069                 LOG_ERROR("Cannot write to lock words");
1070                 return ERROR_FAIL;
1071         }
1072         return efm32x_priv_write(bank, buffer, bank->base + offset, count);
1073 }
1074
1075 static int efm32x_probe(struct flash_bank *bank)
1076 {
1077         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
1078         struct efm32_info *efm32_mcu_info = &(efm32x_info->info);
1079         int ret;
1080
1081         int bank_index = efm32x_get_bank_index(bank->base);
1082         assert(bank_index >= 0);
1083
1084         efm32x_info->probed[bank_index] = false;
1085         memset(efm32x_info->lb_page, 0xff, LOCKWORDS_SZ);
1086
1087         ret = efm32x_read_info(bank);
1088         if (ret != ERROR_OK)
1089                 return ret;
1090
1091         LOG_INFO("detected part: %s Gecko, rev %d",
1092                         efm32_mcu_info->family_data->name, efm32_mcu_info->prod_rev);
1093         LOG_INFO("flash size = %dkbytes", efm32_mcu_info->flash_sz_kib);
1094         LOG_INFO("flash page size = %dbytes", efm32_mcu_info->page_size);
1095
1096         assert(efm32_mcu_info->page_size != 0);
1097
1098         free(bank->sectors);
1099         bank->sectors = NULL;
1100
1101         if (bank->base == EFM32_FLASH_BASE) {
1102                 bank->num_sectors = efm32_mcu_info->flash_sz_kib * 1024 /
1103                         efm32_mcu_info->page_size;
1104                 assert(bank->num_sectors > 0);
1105
1106                 ret = efm32x_read_lock_data(bank);
1107                 if (ret != ERROR_OK) {
1108                         LOG_ERROR("Failed to read LB data");
1109                         return ret;
1110                 }
1111         } else
1112                 bank->num_sectors = 1;
1113         bank->size = bank->num_sectors * efm32_mcu_info->page_size;
1114         bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
1115
1116         for (uint32_t i = 0; i < bank->num_sectors; i++) {
1117                 bank->sectors[i].offset = i * efm32_mcu_info->page_size;
1118                 bank->sectors[i].size = efm32_mcu_info->page_size;
1119                 bank->sectors[i].is_erased = -1;
1120                 bank->sectors[i].is_protected = 1;
1121         }
1122
1123         efm32x_info->probed[bank_index] = true;
1124
1125         return ERROR_OK;
1126 }
1127
1128 static int efm32x_auto_probe(struct flash_bank *bank)
1129 {
1130         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
1131
1132         int bank_index = efm32x_get_bank_index(bank->base);
1133         assert(bank_index >= 0);
1134
1135         if (efm32x_info->probed[bank_index])
1136                 return ERROR_OK;
1137         return efm32x_probe(bank);
1138 }
1139
1140 static int efm32x_protect_check(struct flash_bank *bank)
1141 {
1142         struct target *target = bank->target;
1143         int ret = 0;
1144
1145         if (target->state != TARGET_HALTED) {
1146                 LOG_ERROR("Target not halted");
1147                 return ERROR_TARGET_NOT_HALTED;
1148         }
1149
1150         ret = efm32x_read_lock_data(bank);
1151         if (ret != ERROR_OK) {
1152                 LOG_ERROR("Failed to read LB data");
1153                 return ret;
1154         }
1155
1156         assert(bank->sectors);
1157
1158         for (unsigned int i = 0; i < bank->num_sectors; i++)
1159                 bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
1160
1161         return ERROR_OK;
1162 }
1163
1164 static int get_efm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
1165 {
1166         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
1167         int ret;
1168
1169         ret = efm32x_read_info(bank);
1170         if (ret != ERROR_OK) {
1171                 LOG_ERROR("Failed to read EFM32 info");
1172                 return ret;
1173         }
1174
1175         command_print_sameline(cmd, "%s Gecko, rev %d", efm32x_info->info.family_data->name,
1176                 efm32x_info->info.prod_rev);
1177         return ERROR_OK;
1178 }
1179
1180 COMMAND_HANDLER(efm32x_handle_debuglock_command)
1181 {
1182         struct target *target = NULL;
1183
1184         if (CMD_ARGC < 1)
1185                 return ERROR_COMMAND_SYNTAX_ERROR;
1186
1187         struct flash_bank *bank;
1188         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1189         if (retval != ERROR_OK)
1190                 return retval;
1191
1192         struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
1193
1194         target = bank->target;
1195
1196         if (target->state != TARGET_HALTED) {
1197                 LOG_ERROR("Target not halted");
1198                 return ERROR_TARGET_NOT_HALTED;
1199         }
1200
1201         uint32_t *ptr;
1202         ptr = efm32x_info->lb_page + 127;
1203         *ptr = 0;
1204
1205         retval = efm32x_write_lock_data(bank);
1206         if (retval != ERROR_OK) {
1207                 LOG_ERROR("Failed to write LB page");
1208                 return retval;
1209         }
1210
1211         command_print(CMD, "efm32x debug interface locked, reset the device to apply");
1212
1213         return ERROR_OK;
1214 }
1215
1216 static const struct command_registration efm32x_exec_command_handlers[] = {
1217         {
1218                 .name = "debuglock",
1219                 .handler = efm32x_handle_debuglock_command,
1220                 .mode = COMMAND_EXEC,
1221                 .usage = "bank_id",
1222                 .help = "Lock the debug interface of the device.",
1223         },
1224         COMMAND_REGISTRATION_DONE
1225 };
1226
1227 static const struct command_registration efm32x_command_handlers[] = {
1228         {
1229                 .name = "efm32",
1230                 .mode = COMMAND_ANY,
1231                 .help = "efm32 flash command group",
1232                 .usage = "",
1233                 .chain = efm32x_exec_command_handlers,
1234         },
1235         COMMAND_REGISTRATION_DONE
1236 };
1237
1238 const struct flash_driver efm32_flash = {
1239         .name = "efm32",
1240         .commands = efm32x_command_handlers,
1241         .flash_bank_command = efm32x_flash_bank_command,
1242         .erase = efm32x_erase,
1243         .protect = efm32x_protect,
1244         .write = efm32x_write,
1245         .read = default_flash_read,
1246         .probe = efm32x_probe,
1247         .auto_probe = efm32x_auto_probe,
1248         .erase_check = default_flash_blank_check,
1249         .protect_check = efm32x_protect_check,
1250         .info = get_efm32x_info,
1251         .free_driver_priv = efm32x_free_driver_priv,
1252 };