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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *   Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com>            *
   7  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "imp.h"
  29 #include "cfi.h"
  30 #include "non_cfi.h"
  31 #include <target/arm.h>
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34
  35
  36 #define CFI_MAX_BUS_WIDTH       4
  37 #define CFI_MAX_CHIP_WIDTH      4
  38
  39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  40 #define CFI_MAX_INTEL_CODESIZE 256
  41
  42 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
  43 {
  44         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  45         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  46 };
  47
  48 /* CFI fixups foward declarations */
  49 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
  50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
  51 static void cfi_fixup_reversed_erase_regions(struct flash_bank *flash, void *param);
  52
  53 /* fixup after reading cmdset 0002 primary query table */
  54 static const struct cfi_fixup cfi_0002_fixups[] = {
  55         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  56         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  57         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  58         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  59         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  60         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
  61         {CFI_MFR_ST,  0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
  62    {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  63         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  64         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  65         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  66         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  67         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  68         {0, 0, NULL, NULL}
  69 };
  70
  71 /* fixup after reading cmdset 0001 primary query table */
  72 static const struct cfi_fixup cfi_0001_fixups[] = {
  73         {0, 0, NULL, NULL}
  74 };
  75
  76 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
  77 {
  78         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  79         const struct cfi_fixup *f;
  80
  81         for (f = fixups; f->fixup; f++)
  82         {
  83                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
  84                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
  85                 {
  86                         f->fixup(bank, f->param);
  87                 }
  88         }
  89 }
  90
  91 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
  92 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
  93 {
  94         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  95
  96         if (cfi_info->x16_as_x8) offset *= 2;
  97
  98         /* while the sector list isn't built, only accesses to sector 0 work */
  99         if (sector == 0)
 100                 return bank->base + offset * bank->bus_width;
 101         else
 102         {
 103                 if (!bank->sectors)
 104                 {
 105                         LOG_ERROR("BUG: sector list not yet built");
 106                         exit(-1);
 107                 }
 108                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 109         }
 110 }
 111
 112 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
 113 {
 114         int i;
 115
 116         /* clear whole buffer, to ensure bits that exceed the bus_width
 117          * are set to zero
 118          */
 119         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 120                 cmd_buf[i] = 0;
 121
 122         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 123         {
 124                 for (i = bank->bus_width; i > 0; i--)
 125                 {
 126                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 127                 }
 128         }
 129         else
 130         {
 131                 for (i = 1; i <= bank->bus_width; i++)
 132                 {
 133                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 134                 }
 135         }
 136 }
 137
 138 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
 139 {
 140     uint8_t command[CFI_MAX_BUS_WIDTH];
 141
 142     cfi_command(bank, cmd, command);
 143     return target_write_memory(bank->target, address, bank->bus_width, 1, command);
 144 }
 145
 146 /* read unsigned 8-bit value from the bank
 147  * flash banks are expected to be made of similar chips
 148  * the query result should be the same for all
 149  */
 150 static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
 151 {
 152         struct target *target = bank->target;
 153         uint8_t data[CFI_MAX_BUS_WIDTH];
 154
 155         int retval;
 156         retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 157         if (retval != ERROR_OK)
 158                 return retval;
 159
 160         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 161                 *val = data[0];
 162         else
 163                 *val = data[bank->bus_width - 1];
 164
 165         return ERROR_OK;
 166 }
 167
 168 /* read unsigned 8-bit value from the bank
 169  * in case of a bank made of multiple chips,
 170  * the individual values are ORed
 171  */
 172 static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
 173 {
 174         struct target *target = bank->target;
 175         uint8_t data[CFI_MAX_BUS_WIDTH];
 176         int i;
 177
 178         int retval;
 179         retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 180         if (retval != ERROR_OK)
 181                 return retval;
 182
 183         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 184         {
 185                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 186                         data[0] |= data[i];
 187
 188                 *val = data[0];
 189         }
 190         else
 191         {
 192                 uint8_t value = 0;
 193                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 194                         value |= data[bank->bus_width - 1 - i];
 195
 196                 *val = value;
 197         }
 198         return ERROR_OK;
 199 }
 200
 201 static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
 202 {
 203         struct target *target = bank->target;
 204         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 205         uint8_t data[CFI_MAX_BUS_WIDTH * 2];
 206         int retval;
 207
 208         if (cfi_info->x16_as_x8)
 209         {
 210                 uint8_t i;
 211                 for (i = 0;i < 2;i++)
 212                 {
 213                         retval = target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 214                                 &data[i*bank->bus_width]);
 215                         if (retval != ERROR_OK)
 216                                 return retval;
 217                 }
 218         } else
 219         {
 220                 retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 221                 if (retval != ERROR_OK)
 222                         return retval;
 223         }
 224
 225         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 226                 *val = data[0] | data[bank->bus_width] << 8;
 227         else
 228                 *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 229
 230         return ERROR_OK;
 231 }
 232
 233 static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
 234 {
 235         struct target *target = bank->target;
 236         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 237         uint8_t data[CFI_MAX_BUS_WIDTH * 4];
 238         int retval;
 239
 240         if (cfi_info->x16_as_x8)
 241         {
 242                 uint8_t i;
 243                 for (i = 0;i < 4;i++)
 244                 {
 245                         retval = target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 246                                 &data[i*bank->bus_width]);
 247                         if (retval != ERROR_OK)
 248                                 return retval;
 249                 }
 250         }
 251         else
 252         {
 253                 retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 254                 if (retval != ERROR_OK)
 255                         return retval;
 256         }
 257
 258         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 259                 *val = data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 260         else
 261                 *val = data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 262                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 263
 264         return ERROR_OK;
 265 }
 266
 267 static int cfi_reset(struct flash_bank *bank)
 268 {
 269         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 270         int retval = ERROR_OK;
 271
 272         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 273         {
 274                 return retval;
 275         }
 276
 277         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 278         {
 279                 return retval;
 280         }
 281
 282         if (cfi_info->manufacturer == 0x20 &&
 283                         (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
 284         {
 285                 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
 286                  * so we send an extra 0xF0 reset to fix the bug */
 287                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
 288                 {
 289                         return retval;
 290                 }
 291         }
 292
 293         return retval;
 294 }
 295
 296 static void cfi_intel_clear_status_register(struct flash_bank *bank)
 297 {
 298         struct target *target = bank->target;
 299
 300         if (target->state != TARGET_HALTED)
 301         {
 302                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 303                 exit(-1);
 304         }
 305
 306         cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
 307 }
 308
 309 static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
 310 {
 311         uint8_t status;
 312
 313         int retval = ERROR_OK;
 314
 315         for (;;)
 316         {
 317                 if (timeout-- < 0)
 318                 {
 319                   LOG_ERROR("timeout while waiting for WSM to become ready");
 320                   return ERROR_FAIL;
 321                 }
 322
 323                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 324                 if (retval != ERROR_OK)
 325                         return retval;
 326
 327                 if (status & 0x80)
 328                         break;
 329
 330                 alive_sleep(1);
 331         }
 332
 333         /* mask out bit 0 (reserved) */
 334         status = status & 0xfe;
 335
 336         LOG_DEBUG("status: 0x%x", status);
 337
 338         if (status != 0x80)
 339         {
 340                 LOG_ERROR("status register: 0x%x", status);
 341                 if (status & 0x2)
 342                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 343                 if (status & 0x4)
 344                         LOG_ERROR("Program suspended");
 345                 if (status & 0x8)
 346                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 347                 if (status & 0x10)
 348                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 349                 if (status & 0x20)
 350                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 351                 if (status & 0x40)
 352                         LOG_ERROR("Block Erase Suspended");
 353
 354                 cfi_intel_clear_status_register(bank);
 355
 356                 retval = ERROR_FAIL;
 357         }
 358
 359         *val = status;
 360         return retval;
 361 }
 362
 363 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
 364 {
 365         uint8_t status, oldstatus;
 366         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 367         int retval;
 368
 369         retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
 370         if (retval != ERROR_OK)
 371                 return retval;
 372
 373         do {
 374                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 375
 376                 if (retval != ERROR_OK)
 377                         return retval;
 378
 379                 if ((status ^ oldstatus) & 0x40) {
 380                         if (status & cfi_info->status_poll_mask & 0x20) {
 381                                 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
 382                                 if (retval != ERROR_OK)
 383                                         return retval;
 384                                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 385                                 if (retval != ERROR_OK)
 386                                         return retval;
 387                                 if ((status ^ oldstatus) & 0x40) {
 388                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 389                                         return(ERROR_FLASH_OPERATION_FAILED);
 390                                 } else {
 391                                         LOG_DEBUG("status: 0x%x", status);
 392                                         return(ERROR_OK);
 393                                 }
 394                         }
 395                 } else { /* no toggle: finished, OK */
 396                         LOG_DEBUG("status: 0x%x", status);
 397                         return(ERROR_OK);
 398                 }
 399
 400                 oldstatus = status;
 401                 alive_sleep(1);
 402         } while (timeout-- > 0);
 403
 404         LOG_ERROR("timeout, status: 0x%x", status);
 405
 406         return(ERROR_FLASH_BUSY);
 407 }
 408
 409 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
 410 {
 411         int retval;
 412         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 413         struct cfi_intel_pri_ext *pri_ext;
 414
 415         if (cfi_info->pri_ext)
 416                 free(cfi_info->pri_ext);
 417
 418         pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
 419         if (pri_ext == NULL)
 420         {
 421                 LOG_ERROR("Out of memory");
 422                 return ERROR_FAIL;
 423         }
 424         cfi_info->pri_ext = pri_ext;
 425
 426         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
 427         if (retval != ERROR_OK)
 428                 return retval;
 429         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
 430         if (retval != ERROR_OK)
 431                 return retval;
 432         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
 433         if (retval != ERROR_OK)
 434                 return retval;
 435
 436         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 437         {
 438                 if ((retval = cfi_reset(bank)) != ERROR_OK)
 439                 {
 440                         return retval;
 441                 }
 442                 LOG_ERROR("Could not read bank flash bank information");
 443                 return ERROR_FLASH_BANK_INVALID;
 444         }
 445
 446         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
 447         if (retval != ERROR_OK)
 448                 return retval;
 449         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
 450         if (retval != ERROR_OK)
 451                 return retval;
 452
 453         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 454
 455         retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
 456         if (retval != ERROR_OK)
 457                 return retval;
 458         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
 459         if (retval != ERROR_OK)
 460                 return retval;
 461         retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
 462         if (retval != ERROR_OK)
 463                 return retval;
 464
 465         LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
 466                   pri_ext->feature_support,
 467                   pri_ext->suspend_cmd_support,
 468                   pri_ext->blk_status_reg_mask);
 469
 470         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
 471         if (retval != ERROR_OK)
 472                 return retval;
 473         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
 474         if (retval != ERROR_OK)
 475                 return retval;
 476
 477         LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
 478                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 479                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 480
 481         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
 482         if (retval != ERROR_OK)
 483                 return retval;
 484         if (pri_ext->num_protection_fields != 1)
 485         {
 486                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 487         }
 488
 489         retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
 490         if (retval != ERROR_OK)
 491                 return retval;
 492         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
 493         if (retval != ERROR_OK)
 494                 return retval;
 495         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
 496         if (retval != ERROR_OK)
 497                 return retval;
 498
 499         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 500
 501         return ERROR_OK;
 502 }
 503
 504 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
 505 {
 506         int retval;
 507         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 508         struct cfi_spansion_pri_ext *pri_ext;
 509
 510         if (cfi_info->pri_ext)
 511                 free(cfi_info->pri_ext);
 512
 513         pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 514         if (pri_ext == NULL)
 515         {
 516                 LOG_ERROR("Out of memory");
 517                 return ERROR_FAIL;
 518         }
 519         cfi_info->pri_ext = pri_ext;
 520
 521         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
 522         if (retval != ERROR_OK)
 523                 return retval;
 524         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
 525         if (retval != ERROR_OK)
 526                 return retval;
 527         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
 528         if (retval != ERROR_OK)
 529                 return retval;
 530
 531         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 532         {
 533                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 534                 {
 535                         return retval;
 536                 }
 537                 LOG_ERROR("Could not read spansion bank information");
 538                 return ERROR_FLASH_BANK_INVALID;
 539         }
 540
 541         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
 542         if (retval != ERROR_OK)
 543                 return retval;
 544         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
 545         if (retval != ERROR_OK)
 546                 return retval;
 547
 548         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 549
 550         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
 551         if (retval != ERROR_OK)
 552                 return retval;
 553         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
 554         if (retval != ERROR_OK)
 555                 return retval;
 556         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
 557         if (retval != ERROR_OK)
 558                 return retval;
 559         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
 560         if (retval != ERROR_OK)
 561                 return retval;
 562         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
 563         if (retval != ERROR_OK)
 564                 return retval;
 565         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
 566         if (retval != ERROR_OK)
 567                 return retval;
 568         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
 569         if (retval != ERROR_OK)
 570                 return retval;
 571         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
 572         if (retval != ERROR_OK)
 573                 return retval;
 574         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
 575         if (retval != ERROR_OK)
 576                 return retval;
 577         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
 578         if (retval != ERROR_OK)
 579                 return retval;
 580         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
 581         if (retval != ERROR_OK)
 582                 return retval;
 583
 584         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 585               pri_ext->EraseSuspend, pri_ext->BlkProt);
 586
 587         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 588               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 589
 590         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 591
 592
 593         LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
 594                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 595                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 596
 597         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 598
 599         /* default values for implementation specific workarounds */
 600         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 601         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 602         pri_ext->_reversed_geometry = 0;
 603
 604         return ERROR_OK;
 605 }
 606
 607 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
 608 {
 609         int retval;
 610         struct cfi_atmel_pri_ext atmel_pri_ext;
 611         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 612         struct cfi_spansion_pri_ext *pri_ext;
 613
 614         if (cfi_info->pri_ext)
 615                 free(cfi_info->pri_ext);
 616
 617         pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 618         if (pri_ext == NULL)
 619         {
 620                 LOG_ERROR("Out of memory");
 621                 return ERROR_FAIL;
 622         }
 623
 624         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 625          * but a different primary extended query table.
 626          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 627          */
 628
 629         memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
 630
 631         cfi_info->pri_ext = pri_ext;
 632
 633         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
 634         if (retval != ERROR_OK)
 635                 return retval;
 636         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
 637         if (retval != ERROR_OK)
 638                 return retval;
 639         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
 640         if (retval != ERROR_OK)
 641                 return retval;
 642
 643         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 644         {
 645                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 646                 {
 647                         return retval;
 648                 }
 649                 LOG_ERROR("Could not read atmel bank information");
 650                 return ERROR_FLASH_BANK_INVALID;
 651         }
 652
 653         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 654         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 655         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 656
 657         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
 658         if (retval != ERROR_OK)
 659                 return retval;
 660         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
 661         if (retval != ERROR_OK)
 662                 return retval;
 663
 664         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 665
 666         pri_ext->major_version = atmel_pri_ext.major_version;
 667         pri_ext->minor_version = atmel_pri_ext.minor_version;
 668
 669         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
 670         if (retval != ERROR_OK)
 671                 return retval;
 672         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
 673         if (retval != ERROR_OK)
 674                 return retval;
 675         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
 676         if (retval != ERROR_OK)
 677                 return retval;
 678         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
 679         if (retval != ERROR_OK)
 680                 return retval;
 681
 682         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 683                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 684
 685         if (atmel_pri_ext.features & 0x02)
 686                 pri_ext->EraseSuspend = 2;
 687
 688         if (atmel_pri_ext.bottom_boot)
 689                 pri_ext->TopBottom = 2;
 690         else
 691                 pri_ext->TopBottom = 3;
 692
 693         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 694         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 695
 696         return ERROR_OK;
 697 }
 698
 699 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
 700 {
 701         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 702
 703         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 704         {
 705                 return cfi_read_atmel_pri_ext(bank);
 706         }
 707         else
 708         {
 709                 return cfi_read_spansion_pri_ext(bank);
 710         }
 711 }
 712
 713 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
 714 {
 715         int printed;
 716         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 717         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 718
 719         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 720         buf += printed;
 721         buf_size -= printed;
 722
 723         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 724                            pri_ext->pri[1], pri_ext->pri[2],
 725                            pri_ext->major_version, pri_ext->minor_version);
 726         buf += printed;
 727         buf_size -= printed;
 728
 729         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 730                            (pri_ext->SiliconRevision) >> 2,
 731                            (pri_ext->SiliconRevision) & 0x03);
 732         buf += printed;
 733         buf_size -= printed;
 734
 735         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 736                            pri_ext->EraseSuspend,
 737                            pri_ext->BlkProt);
 738         buf += printed;
 739         buf_size -= printed;
 740
 741         printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
 742                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 743                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 744
 745         return ERROR_OK;
 746 }
 747
 748 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
 749 {
 750         int printed;
 751         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 752         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 753
 754         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 755         buf += printed;
 756         buf_size -= printed;
 757
 758         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 759         buf += printed;
 760         buf_size -= printed;
 761
 762         printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 763         buf += printed;
 764         buf_size -= printed;
 765
 766         printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
 767                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 768                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 769         buf += printed;
 770         buf_size -= printed;
 771
 772         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 773
 774         return ERROR_OK;
 775 }
 776
 777 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 778  */
 779 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
 780 {
 781         struct cfi_flash_bank *cfi_info;
 782
 783         if (CMD_ARGC < 6)
 784         {
 785                 LOG_WARNING("incomplete flash_bank cfi configuration");
 786                 return ERROR_FLASH_BANK_INVALID;
 787         }
 788
 789         /* both widths must:
 790          * - not exceed max value;
 791          * - not be null;
 792          * - be equal to a power of 2.
 793          * bus must be wide enought to hold one chip */
 794         if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
 795                         || (bank->bus_width > CFI_MAX_BUS_WIDTH)
 796                         || (bank->chip_width == 0)
 797                         || (bank->bus_width == 0)
 798                         || (bank->chip_width & (bank->chip_width - 1))
 799                         || (bank->bus_width & (bank->bus_width - 1))
 800                         || (bank->chip_width > bank->bus_width))
 801         {
 802                 LOG_ERROR("chip and bus width have to specified in bytes");
 803                 return ERROR_FLASH_BANK_INVALID;
 804         }
 805
 806         cfi_info = malloc(sizeof(struct cfi_flash_bank));
 807         cfi_info->probed = 0;
 808         cfi_info->erase_region_info = NULL;
 809         cfi_info->pri_ext = NULL;
 810         bank->driver_priv = cfi_info;
 811
 812         cfi_info->write_algorithm = NULL;
 813
 814         cfi_info->x16_as_x8 = 0;
 815         cfi_info->jedec_probe = 0;
 816         cfi_info->not_cfi = 0;
 817
 818         for (unsigned i = 6; i < CMD_ARGC; i++)
 819         {
 820                 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
 821                 {
 822                         cfi_info->x16_as_x8 = 1;
 823                 }
 824                 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
 825                 {
 826                         cfi_info->jedec_probe = 1;
 827                 }
 828         }
 829
 830         cfi_info->write_algorithm = NULL;
 831
 832         /* bank wasn't probed yet */
 833         cfi_info->qry[0] = 0xff;
 834
 835         return ERROR_OK;
 836 }
 837
 838 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
 839 {
 840         int retval;
 841         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 842         int i;
 843
 844         cfi_intel_clear_status_register(bank);
 845
 846         for (i = first; i <= last; i++)
 847         {
 848                 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
 849                 {
 850                         return retval;
 851                 }
 852
 853                 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
 854                 {
 855                         return retval;
 856                 }
 857
 858                 uint8_t status;
 859                 retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ), &status);
 860                 if (retval != ERROR_OK)
 861                         return retval;
 862
 863                 if (status == 0x80)
 864                         bank->sectors[i].is_erased = 1;
 865                 else
 866                 {
 867                         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 868                         {
 869                                 return retval;
 870                         }
 871
 872                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
 873                         return ERROR_FLASH_OPERATION_FAILED;
 874                 }
 875         }
 876
 877         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
 878 }
 879
 880 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
 881 {
 882         int retval;
 883         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 884         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 885         int i;
 886
 887         for (i = first; i <= last; i++)
 888         {
 889                 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 890                 {
 891                         return retval;
 892                 }
 893
 894                 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 895                 {
 896                         return retval;
 897                 }
 898
 899                 if ((retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 900                 {
 901                         return retval;
 902                 }
 903
 904                 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 905                 {
 906                         return retval;
 907                 }
 908
 909                 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 910                 {
 911                         return retval;
 912                 }
 913
 914                 if ((retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0))) != ERROR_OK)
 915                 {
 916                         return retval;
 917                 }
 918
 919                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 920                         bank->sectors[i].is_erased = 1;
 921                 else
 922                 {
 923                         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 924                         {
 925                                 return retval;
 926                         }
 927
 928                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
 929                         return ERROR_FLASH_OPERATION_FAILED;
 930                 }
 931         }
 932
 933         return  cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
 934 }
 935
 936 static int cfi_erase(struct flash_bank *bank, int first, int last)
 937 {
 938         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 939
 940         if (bank->target->state != TARGET_HALTED)
 941         {
 942                 LOG_ERROR("Target not halted");
 943                 return ERROR_TARGET_NOT_HALTED;
 944         }
 945
 946         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 947         {
 948                 return ERROR_FLASH_SECTOR_INVALID;
 949         }
 950
 951         if (cfi_info->qry[0] != 'Q')
 952                 return ERROR_FLASH_BANK_NOT_PROBED;
 953
 954         switch (cfi_info->pri_id)
 955         {
 956                 case 1:
 957                 case 3:
 958                         return cfi_intel_erase(bank, first, last);
 959                         break;
 960                 case 2:
 961                         return cfi_spansion_erase(bank, first, last);
 962                         break;
 963                 default:
 964                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 965                         break;
 966         }
 967
 968         return ERROR_OK;
 969 }
 970
 971 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
 972 {
 973         int retval;
 974         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 975         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 976         int retry = 0;
 977         int i;
 978
 979         /* if the device supports neither legacy lock/unlock (bit 3) nor
 980          * instant individual block locking (bit 5).
 981          */
 982         if (!(pri_ext->feature_support & 0x28))
 983         {
 984                 LOG_ERROR("lock/unlock not supported on flash");
 985                 return ERROR_FLASH_OPERATION_FAILED;
 986         }
 987
 988         cfi_intel_clear_status_register(bank);
 989
 990         for (i = first; i <= last; i++)
 991         {
 992                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
 993                 {
 994                         return retval;
 995                 }
 996                 if (set)
 997                 {
 998                         if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
 999                         {
1000                                 return retval;
1001                         }
1002                         bank->sectors[i].is_protected = 1;
1003                 }
1004                 else
1005                 {
1006                         if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
1007                         {
1008                                 return retval;
1009                         }
1010                         bank->sectors[i].is_protected = 0;
1011                 }
1012
1013                 /* instant individual block locking doesn't require reading of the status register */
1014                 if (!(pri_ext->feature_support & 0x20))
1015                 {
1016                         /* Clear lock bits operation may take up to 1.4s */
1017                         uint8_t status;
1018                         retval = cfi_intel_wait_status_busy(bank, 1400, &status);
1019                         if (retval != ERROR_OK)
1020                                 return retval;
1021                 }
1022                 else
1023                 {
1024                         uint8_t block_status;
1025                         /* read block lock bit, to verify status */
1026                         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
1027                         {
1028                                 return retval;
1029                         }
1030                         retval = cfi_get_u8(bank, i, 0x2, &block_status);
1031                         if (retval != ERROR_OK)
1032                                 return retval;
1033
1034                         if ((block_status & 0x1) != set)
1035                         {
1036                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
1037                                 if ((retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55))) != ERROR_OK)
1038                                 {
1039                                         return retval;
1040                                 }
1041                                 uint8_t status;
1042                                 retval = cfi_intel_wait_status_busy(bank, 10, &status);
1043                                 if (retval != ERROR_OK)
1044                                         return retval;
1045
1046                                 if (retry > 10)
1047                                         return ERROR_FLASH_OPERATION_FAILED;
1048                                 else
1049                                 {
1050                                         i--;
1051                                         retry++;
1052                                 }
1053                         }
1054                 }
1055         }
1056
1057         /* if the device doesn't support individual block lock bits set/clear,
1058          * all blocks have been unlocked in parallel, so we set those that should be protected
1059          */
1060         if ((!set) && (!(pri_ext->feature_support & 0x20)))
1061         {
1062                 /* FIX!!! this code path is broken!!!
1063                  *
1064                  * The correct approach is:
1065                  *
1066                  * 1. read out current protection status
1067                  *
1068                  * 2. override read out protection status w/unprotected.
1069                  *
1070                  * 3. re-protect what should be protected.
1071                  *
1072                  */
1073                 for (i = 0; i < bank->num_sectors; i++)
1074                 {
1075                         if (bank->sectors[i].is_protected == 1)
1076                         {
1077                                 cfi_intel_clear_status_register(bank);
1078
1079                                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
1080                                 {
1081                                         return retval;
1082                                 }
1083
1084                                 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
1085                                 {
1086                                         return retval;
1087                                 }
1088
1089                                 uint8_t status;
1090                                 retval = cfi_intel_wait_status_busy(bank, 100, &status);
1091                                 if (retval != ERROR_OK)
1092                                         return retval;
1093                         }
1094                 }
1095         }
1096
1097         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
1098 }
1099
1100 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
1101 {
1102         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1103
1104         if (bank->target->state != TARGET_HALTED)
1105         {
1106                 LOG_ERROR("Target not halted");
1107                 return ERROR_TARGET_NOT_HALTED;
1108         }
1109
1110         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
1111         {
1112                 LOG_ERROR("Invalid sector range");
1113                 return ERROR_FLASH_SECTOR_INVALID;
1114         }
1115
1116         if (cfi_info->qry[0] != 'Q')
1117                 return ERROR_FLASH_BANK_NOT_PROBED;
1118
1119         switch (cfi_info->pri_id)
1120         {
1121                 case 1:
1122                 case 3:
1123                         return cfi_intel_protect(bank, set, first, last);
1124                         break;
1125                 default:
1126                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
1127                         return ERROR_FAIL;
1128         }
1129 }
1130
1131 /* Convert code image to target endian */
1132 /* FIXME create general block conversion fcts in target.c?) */
1133 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
1134 {
1135         uint32_t i;
1136         for (i = 0; i< count; i++)
1137         {
1138                 target_buffer_set_u32(target, dest, *src);
1139                 dest += 4;
1140                 src++;
1141         }
1142 }
1143
1144 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
1145 {
1146         struct target *target = bank->target;
1147
1148         uint8_t buf[CFI_MAX_BUS_WIDTH];
1149         cfi_command(bank, cmd, buf);
1150         switch (bank->bus_width)
1151         {
1152         case 1 :
1153                 return buf[0];
1154                 break;
1155         case 2 :
1156                 return target_buffer_get_u16(target, buf);
1157                 break;
1158         case 4 :
1159                 return target_buffer_get_u32(target, buf);
1160                 break;
1161         default :
1162                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1163                 return 0;
1164         }
1165 }
1166
1167 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1168 {
1169         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1170         struct target *target = bank->target;
1171         struct reg_param reg_params[7];
1172         struct arm_algorithm armv4_5_info;
1173         struct working_area *source;
1174         uint32_t buffer_size = 32768;
1175         uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1176
1177         /* algorithm register usage:
1178          * r0: source address (in RAM)
1179          * r1: target address (in Flash)
1180          * r2: count
1181          * r3: flash write command
1182          * r4: status byte (returned to host)
1183          * r5: busy test pattern
1184          * r6: error test pattern
1185          */
1186
1187         static const uint32_t word_32_code[] = {
1188                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1189                 0xe5813000,   /*                str r3, [r1] */
1190                 0xe5814000,   /*                str r4, [r1] */
1191                 0xe5914000,   /* busy:  ldr r4, [r1] */
1192                 0xe0047005,   /*                and r7, r4, r5 */
1193                 0xe1570005,   /*                cmp r7, r5 */
1194                 0x1afffffb,   /*                bne busy */
1195                 0xe1140006,   /*                tst r4, r6 */
1196                 0x1a000003,   /*                bne done */
1197                 0xe2522001,   /*                subs r2, r2, #1 */
1198                 0x0a000001,   /*                beq done */
1199                 0xe2811004,   /*                add r1, r1 #4 */
1200                 0xeafffff2,   /*                b loop */
1201                 0xeafffffe    /* done:  b -2 */
1202         };
1203
1204         static const uint32_t word_16_code[] = {
1205                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1206                 0xe1c130b0,   /*                strh r3, [r1] */
1207                 0xe1c140b0,   /*                strh r4, [r1] */
1208                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1209                 0xe0047005,   /*                and r7, r4, r5 */
1210                 0xe1570005,   /*                cmp r7, r5 */
1211                 0x1afffffb,   /*                bne busy */
1212                 0xe1140006,   /*                tst r4, r6 */
1213                 0x1a000003,   /*                bne done */
1214                 0xe2522001,   /*                subs r2, r2, #1 */
1215                 0x0a000001,   /*                beq done */
1216                 0xe2811002,   /*                add r1, r1 #2 */
1217                 0xeafffff2,   /*                b loop */
1218                 0xeafffffe    /* done:  b -2 */
1219         };
1220
1221         static const uint32_t word_8_code[] = {
1222                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1223                 0xe5c13000,   /*                strb r3, [r1] */
1224                 0xe5c14000,   /*                strb r4, [r1] */
1225                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1226                 0xe0047005,   /*                and r7, r4, r5 */
1227                 0xe1570005,   /*                cmp r7, r5 */
1228                 0x1afffffb,   /*                bne busy */
1229                 0xe1140006,   /*                tst r4, r6 */
1230                 0x1a000003,   /*                bne done */
1231                 0xe2522001,   /*                subs r2, r2, #1 */
1232                 0x0a000001,   /*                beq done */
1233                 0xe2811001,   /*                add r1, r1 #1 */
1234                 0xeafffff2,   /*                b loop */
1235                 0xeafffffe    /* done:  b -2 */
1236         };
1237         uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1238         const uint32_t *target_code_src;
1239         uint32_t target_code_size;
1240         int retval = ERROR_OK;
1241
1242
1243         cfi_intel_clear_status_register(bank);
1244
1245         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1246         armv4_5_info.core_mode = ARM_MODE_SVC;
1247         armv4_5_info.core_state = ARM_STATE_ARM;
1248
1249         /* If we are setting up the write_algorith, we need target_code_src */
1250         /* if not we only need target_code_size. */
1251
1252         /* However, we don't want to create multiple code paths, so we */
1253         /* do the unecessary evaluation of target_code_src, which the */
1254         /* compiler will probably nicely optimize away if not needed */
1255
1256         /* prepare algorithm code for target endian */
1257         switch (bank->bus_width)
1258         {
1259         case 1 :
1260                 target_code_src = word_8_code;
1261                 target_code_size = sizeof(word_8_code);
1262                 break;
1263         case 2 :
1264                 target_code_src = word_16_code;
1265                 target_code_size = sizeof(word_16_code);
1266                 break;
1267         case 4 :
1268                 target_code_src = word_32_code;
1269                 target_code_size = sizeof(word_32_code);
1270                 break;
1271         default:
1272                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1273                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1274         }
1275
1276         /* flash write code */
1277         if (!cfi_info->write_algorithm)
1278         {
1279                 if (target_code_size > sizeof(target_code))
1280                 {
1281                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1282                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1283                 }
1284                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1285
1286                 /* Get memory for block write handler */
1287                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1288                 if (retval != ERROR_OK)
1289                 {
1290                         LOG_WARNING("No working area available, can't do block memory writes");
1291                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1292                 };
1293
1294                 /* write algorithm code to working area */
1295                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1296                 if (retval != ERROR_OK)
1297                 {
1298                         LOG_ERROR("Unable to write block write code to target");
1299                         goto cleanup;
1300                 }
1301         }
1302
1303         /* Get a workspace buffer for the data to flash starting with 32k size.
1304            Half size until buffer would be smaller 256 Bytem then fail back */
1305         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1306         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1307         {
1308                 buffer_size /= 2;
1309                 if (buffer_size <= 256)
1310                 {
1311                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1312                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1313                         goto cleanup;
1314                 }
1315         };
1316
1317         /* setup algo registers */
1318         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1319         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1320         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1321         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1322         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1323         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1324         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1325
1326         /* prepare command and status register patterns */
1327         write_command_val = cfi_command_val(bank, 0x40);
1328         busy_pattern_val  = cfi_command_val(bank, 0x80);
1329         error_pattern_val = cfi_command_val(bank, 0x7e);
1330
1331         LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1332
1333         /* Programming main loop */
1334         while (count > 0)
1335         {
1336                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1337                 uint32_t wsm_error;
1338
1339                 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1340                 {
1341                         goto cleanup;
1342                 }
1343
1344                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1345                 buf_set_u32(reg_params[1].value, 0, 32, address);
1346                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1347
1348                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1349                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1350                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1351
1352                 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1353
1354                 /* Execute algorithm, assume breakpoint for last instruction */
1355                 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1356                         cfi_info->write_algorithm->address,
1357                         cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1358                         10000, /* 10s should be enough for max. 32k of data */
1359                         &armv4_5_info);
1360
1361                 /* On failure try a fall back to direct word writes */
1362                 if (retval != ERROR_OK)
1363                 {
1364                         cfi_intel_clear_status_register(bank);
1365                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1366                         retval = ERROR_FLASH_OPERATION_FAILED;
1367                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1368                         /* FIXME To allow fall back or recovery, we must save the actual status
1369                            somewhere, so that a higher level code can start recovery. */
1370                         goto cleanup;
1371                 }
1372
1373                 /* Check return value from algo code */
1374                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1375                 if (wsm_error)
1376                 {
1377                         /* read status register (outputs debug inforation) */
1378                         uint8_t status;
1379                         cfi_intel_wait_status_busy(bank, 100, &status);
1380                         cfi_intel_clear_status_register(bank);
1381                         retval = ERROR_FLASH_OPERATION_FAILED;
1382                         goto cleanup;
1383                 }
1384
1385                 buffer += thisrun_count;
1386                 address += thisrun_count;
1387                 count -= thisrun_count;
1388
1389                 keep_alive();
1390         }
1391
1392         /* free up resources */
1393 cleanup:
1394         if (source)
1395                 target_free_working_area(target, source);
1396
1397         if (cfi_info->write_algorithm)
1398         {
1399                 target_free_working_area(target, cfi_info->write_algorithm);
1400                 cfi_info->write_algorithm = NULL;
1401         }
1402
1403         destroy_reg_param(&reg_params[0]);
1404         destroy_reg_param(&reg_params[1]);
1405         destroy_reg_param(&reg_params[2]);
1406         destroy_reg_param(&reg_params[3]);
1407         destroy_reg_param(&reg_params[4]);
1408         destroy_reg_param(&reg_params[5]);
1409         destroy_reg_param(&reg_params[6]);
1410
1411         return retval;
1412 }
1413
1414 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1415 {
1416         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1417         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1418         struct target *target = bank->target;
1419         struct reg_param reg_params[10];
1420         struct arm_algorithm armv4_5_info;
1421         struct working_area *source;
1422         uint32_t buffer_size = 32768;
1423         uint32_t status;
1424         int retval = ERROR_OK;
1425
1426         /* input parameters - */
1427         /*      R0 = source address */
1428         /*      R1 = destination address */
1429         /*      R2 = number of writes */
1430         /*      R3 = flash write command */
1431         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1432         /* output parameters - */
1433         /*      R5 = 0x80 ok 0x00 bad */
1434         /* temp registers - */
1435         /*      R6 = value read from flash to test status */
1436         /*      R7 = holding register */
1437         /* unlock registers - */
1438         /*  R8 = unlock1_addr */
1439         /*  R9 = unlock1_cmd */
1440         /*  R10 = unlock2_addr */
1441         /*  R11 = unlock2_cmd */
1442
1443         static const uint32_t word_32_code[] = {
1444                                                 /* 00008100 <sp_32_code>:               */
1445                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1446                 0xe5889000,     /* str  r9, [r8]                                */
1447                 0xe58ab000,     /* str  r11, [r10]                              */
1448                 0xe5883000,     /* str  r3, [r8]                                */
1449                 0xe5815000,     /* str  r5, [r1]                                */
1450                 0xe1a00000,     /* nop                                                  */
1451                                                 /*                                                              */
1452                                                 /* 00008110 <sp_32_busy>:               */
1453                 0xe5916000,     /* ldr  r6, [r1]                                */
1454                 0xe0257006,     /* eor  r7, r5, r6                              */
1455                 0xe0147007,     /* ands r7, r4, r7                              */
1456                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1457                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1458                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1459                 0xe5916000,     /* ldr  r6, [r1]                                */
1460                 0xe0257006,     /* eor  r7, r5, r6                              */
1461                 0xe0147007,     /* ands r7, r4, r7                              */
1462                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1463                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1464                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1465                                                 /*                                                              */
1466                                 /* 00008140 <sp_32_cont>:                               */
1467                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1468                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1469                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1470                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1471                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1472                                                 /*                                                              */
1473                                                 /* 00008154 <sp_32_done>:               */
1474                 0xeafffffe              /* b    8154 <sp_32_done>               */
1475                 };
1476
1477                 static const uint32_t word_16_code[] = {
1478                                 /* 00008158 <sp_16_code>:              */
1479                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1480                 0xe1c890b0,     /* strh r9, [r8]                                */
1481                 0xe1cab0b0,     /* strh r11, [r10]                              */
1482                 0xe1c830b0,     /* strh r3, [r8]                                */
1483                 0xe1c150b0,     /* strh r5, [r1]                       */
1484                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1485                                 /*                                     */
1486                                 /* 00008168 <sp_16_busy>:              */
1487                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1488                 0xe0257006,     /* eor  r7, r5, r6                     */
1489                 0xe0147007,     /* ands r7, r4, r7                     */
1490                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1491                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1492                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1493                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1494                 0xe0257006,     /* eor  r7, r5, r6                     */
1495                 0xe0147007,     /* ands r7, r4, r7                     */
1496                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1497                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1498                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1499                                 /*                                     */
1500                                 /* 00008198 <sp_16_cont>:              */
1501                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1502                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1503                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1504                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1505                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1506                                 /*                                     */
1507                                 /* 000081ac <sp_16_done>:              */
1508                 0xeafffffe      /* b    81ac <sp_16_done>              */
1509                 };
1510
1511                 static const uint32_t word_16_code_dq7only[] = {
1512                                 /* <sp_16_code>:                       */
1513                 0xe0d050b2,     /* ldrh r5, [r0], #2                   */
1514                 0xe1c890b0,     /* strh r9, [r8]                       */
1515                 0xe1cab0b0,     /* strh r11, [r10]                              */
1516                 0xe1c830b0,     /* strh r3, [r8]                                */
1517                 0xe1c150b0,     /* strh r5, [r1]                       */
1518                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1519                                 /*                                     */
1520                                 /* <sp_16_busy>:                       */
1521                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1522                 0xe0257006,     /* eor  r7, r5, r6                     */
1523                 0xe2177080,     /* ands r7, #0x80                      */
1524                 0x1afffffb,     /* bne  8168 <sp_16_busy>              */
1525                                 /*                                     */
1526                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1527                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1528                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1529                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1530                 0xeafffff0,     /* b    8158 <sp_16_code>              */
1531                                 /*                                     */
1532                                 /* 000081ac <sp_16_done>:              */
1533                 0xeafffffe      /* b    81ac <sp_16_done>              */
1534                 };
1535
1536                 static const uint32_t word_8_code[] = {
1537                                 /* 000081b0 <sp_16_code_end>:          */
1538                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1539                 0xe5c89000,     /* strb r9, [r8]                                */
1540                 0xe5cab000,     /* strb r11, [r10]                              */
1541                 0xe5c83000,     /* strb r3, [r8]                                */
1542                 0xe5c15000,     /* strb r5, [r1]                       */
1543                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1544                                 /*                                     */
1545                                 /* 000081c0 <sp_8_busy>:               */
1546                 0xe5d16000,     /* ldrb r6, [r1]                       */
1547                 0xe0257006,     /* eor  r7, r5, r6                     */
1548                 0xe0147007,     /* ands r7, r4, r7                     */
1549                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1550                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1551                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1552                 0xe5d16000,     /* ldrb r6, [r1]                       */
1553                 0xe0257006,     /* eor  r7, r5, r6                     */
1554                 0xe0147007,     /* ands r7, r4, r7                     */
1555                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1556                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1557                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1558                                 /*                                     */
1559                                 /* 000081f0 <sp_8_cont>:               */
1560                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1561                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1562                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1563                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1564                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1565                                 /*                                     */
1566                                 /* 00008204 <sp_8_done>:               */
1567                 0xeafffffe      /* b    8204 <sp_8_done>               */
1568         };
1569
1570         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1571         armv4_5_info.core_mode = ARM_MODE_SVC;
1572         armv4_5_info.core_state = ARM_STATE_ARM;
1573
1574         int target_code_size;
1575         const uint32_t *target_code_src;
1576
1577         switch (bank->bus_width)
1578         {
1579         case 1 :
1580                 target_code_src = word_8_code;
1581                 target_code_size = sizeof(word_8_code);
1582                 break;
1583         case 2 :
1584                 /* Check for DQ5 support */
1585                 if( cfi_info->status_poll_mask & (1 << 5) )
1586                 {
1587                         target_code_src = word_16_code;
1588                         target_code_size = sizeof(word_16_code);
1589                 }
1590                 else
1591                 {
1592                         /* No DQ5 support. Use DQ7 DATA# polling only. */
1593                         target_code_src = word_16_code_dq7only;
1594                         target_code_size = sizeof(word_16_code_dq7only);
1595                 }
1596                 break;
1597         case 4 :
1598                 target_code_src = word_32_code;
1599                 target_code_size = sizeof(word_32_code);
1600                 break;
1601         default:
1602                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1603                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1604         }
1605
1606         /* flash write code */
1607         if (!cfi_info->write_algorithm)
1608         {
1609                 uint8_t *target_code;
1610
1611                 /* convert bus-width dependent algorithm code to correct endiannes */
1612                 target_code = malloc(target_code_size);
1613                 if (target_code == NULL)
1614                 {
1615                         LOG_ERROR("Out of memory");
1616                         return ERROR_FAIL;
1617                 }
1618                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1619
1620                 /* allocate working area */
1621                 retval = target_alloc_working_area(target, target_code_size,
1622                                 &cfi_info->write_algorithm);
1623                 if (retval != ERROR_OK)
1624                 {
1625                         free(target_code);
1626                         return retval;
1627                 }
1628
1629                 /* write algorithm code to working area */
1630                 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1631                                     target_code_size, target_code)) != ERROR_OK)
1632                 {
1633                         free(target_code);
1634                         return retval;
1635                 }
1636
1637                 free(target_code);
1638         }
1639         /* the following code still assumes target code is fixed 24*4 bytes */
1640
1641         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1642         {
1643                 buffer_size /= 2;
1644                 if (buffer_size <= 256)
1645                 {
1646                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1647                         if (cfi_info->write_algorithm)
1648                                 target_free_working_area(target, cfi_info->write_algorithm);
1649
1650                         LOG_WARNING("not enough working area available, can't do block memory writes");
1651                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1652                 }
1653         };
1654
1655         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1656         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1657         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1658         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1659         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1660         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1661         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1662         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1663         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1664         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1665
1666         while (count > 0)
1667         {
1668                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1669
1670                 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1671                 if (retval != ERROR_OK)
1672                 {
1673                         break;
1674                 }
1675
1676                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1677                 buf_set_u32(reg_params[1].value, 0, 32, address);
1678                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1679                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1680                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1681                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1682                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1683                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1684                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1685
1686                 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1687                                                      cfi_info->write_algorithm->address,
1688                                                      cfi_info->write_algorithm->address + ((target_code_size) - 4),
1689                                                      10000, &armv4_5_info);
1690                 if (retval != ERROR_OK)
1691                 {
1692                         break;
1693                 }
1694
1695                 status = buf_get_u32(reg_params[5].value, 0, 32);
1696                 if (status != 0x80)
1697                 {
1698                         LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
1699                         retval = ERROR_FLASH_OPERATION_FAILED;
1700                         break;
1701                 }
1702
1703                 buffer += thisrun_count;
1704                 address += thisrun_count;
1705                 count -= thisrun_count;
1706         }
1707
1708         target_free_all_working_areas(target);
1709
1710         destroy_reg_param(&reg_params[0]);
1711         destroy_reg_param(&reg_params[1]);
1712         destroy_reg_param(&reg_params[2]);
1713         destroy_reg_param(&reg_params[3]);
1714         destroy_reg_param(&reg_params[4]);
1715         destroy_reg_param(&reg_params[5]);
1716         destroy_reg_param(&reg_params[6]);
1717         destroy_reg_param(&reg_params[7]);
1718         destroy_reg_param(&reg_params[8]);
1719         destroy_reg_param(&reg_params[9]);
1720
1721         return retval;
1722 }
1723
1724 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1725 {
1726         int retval;
1727         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1728         struct target *target = bank->target;
1729
1730         cfi_intel_clear_status_register(bank);
1731         if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1732         {
1733                 return retval;
1734         }
1735
1736         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1737         {
1738                 return retval;
1739         }
1740
1741         uint8_t status;
1742         retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max), &status);
1743         if (retval != 0x80)
1744         {
1745                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1746                 {
1747                         return retval;
1748                 }
1749
1750                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1751                 return ERROR_FLASH_OPERATION_FAILED;
1752         }
1753
1754         return ERROR_OK;
1755 }
1756
1757 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1758 {
1759         int retval;
1760         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1761         struct target *target = bank->target;
1762
1763         /* Calculate buffer size and boundary mask */
1764         /* buffersize is (buffer size per chip) * (number of chips) */
1765         /* bufferwsize is buffersize in words */
1766         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1767         uint32_t buffermask = buffersize-1;
1768         uint32_t bufferwsize = buffersize / bank->bus_width;
1769
1770         /* Check for valid range */
1771         if (address & buffermask)
1772         {
1773                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1774                           bank->base, address, cfi_info->max_buf_write_size);
1775                 return ERROR_FLASH_OPERATION_FAILED;
1776         }
1777
1778         /* Check for valid size */
1779         if (wordcount > bufferwsize)
1780         {
1781                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1782                 return ERROR_FLASH_OPERATION_FAILED;
1783         }
1784
1785         /* Write to flash buffer */
1786         cfi_intel_clear_status_register(bank);
1787
1788         /* Initiate buffer operation _*/
1789         if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1790         {
1791                 return retval;
1792         }
1793         uint8_t status;
1794         retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max), &status);
1795         if (retval != ERROR_OK)
1796                 return retval;
1797         if (status != 0x80)
1798         {
1799                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1800                 {
1801                         return retval;
1802                 }
1803
1804                 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1805                 return ERROR_FLASH_OPERATION_FAILED;
1806         }
1807
1808         /* Write buffer wordcount-1 and data words */
1809         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1810         {
1811                 return retval;
1812         }
1813
1814         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1815         {
1816                 return retval;
1817         }
1818
1819         /* Commit write operation */
1820         if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1821         {
1822                 return retval;
1823         }
1824
1825         retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max), &status);
1826         if (retval != ERROR_OK)
1827                 return retval;
1828
1829         if (status != 0x80)
1830         {
1831                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1832                 {
1833                         return retval;
1834                 }
1835
1836                 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1837                 return ERROR_FLASH_OPERATION_FAILED;
1838         }
1839
1840         return ERROR_OK;
1841 }
1842
1843 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1844 {
1845         int retval;
1846         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1847         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1848         struct target *target = bank->target;
1849
1850         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1851         {
1852                 return retval;
1853         }
1854
1855         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1856         {
1857                 return retval;
1858         }
1859
1860         if ((retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1861         {
1862                 return retval;
1863         }
1864
1865         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1866         {
1867                 return retval;
1868         }
1869
1870         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1871         {
1872                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1873                 {
1874                         return retval;
1875                 }
1876
1877                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1878                 return ERROR_FLASH_OPERATION_FAILED;
1879         }
1880
1881         return ERROR_OK;
1882 }
1883
1884 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1885 {
1886         int retval;
1887         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1888         struct target *target = bank->target;
1889         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1890
1891         /* Calculate buffer size and boundary mask */
1892         /* buffersize is (buffer size per chip) * (number of chips) */
1893         /* bufferwsize is buffersize in words */
1894         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1895         uint32_t buffermask = buffersize-1;
1896         uint32_t bufferwsize = buffersize / bank->bus_width;
1897
1898         /* Check for valid range */
1899         if (address & buffermask)
1900         {
1901                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1902                 return ERROR_FLASH_OPERATION_FAILED;
1903         }
1904
1905         /* Check for valid size */
1906         if (wordcount > bufferwsize)
1907         {
1908                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1909                 return ERROR_FLASH_OPERATION_FAILED;
1910         }
1911
1912         // Unlock
1913         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1914         {
1915                 return retval;
1916         }
1917
1918         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1919         {
1920                 return retval;
1921         }
1922
1923         // Buffer load command
1924         if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1925         {
1926                 return retval;
1927         }
1928
1929         /* Write buffer wordcount-1 and data words */
1930         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1931         {
1932                 return retval;
1933         }
1934
1935         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1936         {
1937                 return retval;
1938         }
1939
1940         /* Commit write operation */
1941         if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
1942         {
1943                 return retval;
1944         }
1945
1946         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1947         {
1948                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1949                 {
1950                         return retval;
1951                 }
1952
1953                 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1954                 return ERROR_FLASH_OPERATION_FAILED;
1955         }
1956
1957         return ERROR_OK;
1958 }
1959
1960 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1961 {
1962         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1963
1964         switch (cfi_info->pri_id)
1965         {
1966                 case 1:
1967                 case 3:
1968                         return cfi_intel_write_word(bank, word, address);
1969                         break;
1970                 case 2:
1971                         return cfi_spansion_write_word(bank, word, address);
1972                         break;
1973                 default:
1974                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1975                         break;
1976         }
1977
1978         return ERROR_FLASH_OPERATION_FAILED;
1979 }
1980
1981 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1982 {
1983         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1984
1985         switch (cfi_info->pri_id)
1986         {
1987                 case 1:
1988                 case 3:
1989                         return cfi_intel_write_words(bank, word, wordcount, address);
1990                         break;
1991                 case 2:
1992                         return cfi_spansion_write_words(bank, word, wordcount, address);
1993                         break;
1994                 default:
1995                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1996                         break;
1997         }
1998
1999         return ERROR_FLASH_OPERATION_FAILED;
2000 }
2001
2002 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2003 {
2004         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2005         struct target *target = bank->target;
2006         uint32_t address = bank->base + offset;
2007         uint32_t read_p;
2008         int align;      /* number of unaligned bytes */
2009         uint8_t current_word[CFI_MAX_BUS_WIDTH];
2010         int i;
2011         int retval;
2012
2013         LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2014                 (int)count, (unsigned)offset);
2015
2016         if (bank->target->state != TARGET_HALTED)
2017         {
2018                 LOG_ERROR("Target not halted");
2019                 return ERROR_TARGET_NOT_HALTED;
2020         }
2021
2022         if (offset + count > bank->size)
2023                 return ERROR_FLASH_DST_OUT_OF_BANK;
2024
2025         if (cfi_info->qry[0] != 'Q')
2026                 return ERROR_FLASH_BANK_NOT_PROBED;
2027
2028         /* start at the first byte of the first word (bus_width size) */
2029         read_p = address & ~(bank->bus_width - 1);
2030         if ((align = address - read_p) != 0)
2031         {
2032                 LOG_INFO("Fixup %d unaligned read head bytes", align);
2033
2034                 /* read a complete word from flash */
2035                 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2036                         return retval;
2037
2038                 /* take only bytes we need */
2039                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2040                         *buffer++ = current_word[i];
2041
2042                 read_p += bank->bus_width;
2043         }
2044
2045         align = count / bank->bus_width;
2046         if (align)
2047         {
2048                 if ((retval = target_read_memory(target, read_p, bank->bus_width, align, buffer)) != ERROR_OK)
2049                         return retval;
2050
2051                 read_p += align * bank->bus_width;
2052                 buffer += align * bank->bus_width;
2053                 count -= align * bank->bus_width;
2054         }
2055
2056         if (count)
2057         {
2058                 LOG_INFO("Fixup %d unaligned read tail bytes", count);
2059
2060                 /* read a complete word from flash */
2061                 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2062                         return retval;
2063
2064                 /* take only bytes we need */
2065                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2066                         *buffer++ = current_word[i];
2067         }
2068
2069         return ERROR_OK;
2070 }
2071
2072 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2073 {
2074         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2075         struct target *target = bank->target;
2076         uint32_t address = bank->base + offset; /* address of first byte to be programmed */
2077         uint32_t write_p;
2078         int align;      /* number of unaligned bytes */
2079         int blk_count; /* number of bus_width bytes for block copy */
2080         uint8_t current_word[CFI_MAX_BUS_WIDTH * 4];    /* word (bus_width size) currently being programmed */
2081         int i;
2082         int retval;
2083
2084         if (bank->target->state != TARGET_HALTED)
2085         {
2086                 LOG_ERROR("Target not halted");
2087                 return ERROR_TARGET_NOT_HALTED;
2088         }
2089
2090         if (offset + count > bank->size)
2091                 return ERROR_FLASH_DST_OUT_OF_BANK;
2092
2093         if (cfi_info->qry[0] != 'Q')
2094                 return ERROR_FLASH_BANK_NOT_PROBED;
2095
2096         /* start at the first byte of the first word (bus_width size) */
2097         write_p = address & ~(bank->bus_width - 1);
2098         if ((align = address - write_p) != 0)
2099         {
2100                 LOG_INFO("Fixup %d unaligned head bytes", align);
2101
2102                 /* read a complete word from flash */
2103                 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2104                         return retval;
2105
2106                 /* replace only bytes that must be written */
2107                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2108                         current_word[i] = *buffer++;
2109
2110                 retval = cfi_write_word(bank, current_word, write_p);
2111                 if (retval != ERROR_OK)
2112                         return retval;
2113                 write_p += bank->bus_width;
2114         }
2115
2116         /* handle blocks of bus_size aligned bytes */
2117         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
2118         switch (cfi_info->pri_id)
2119         {
2120                 /* try block writes (fails without working area) */
2121                 case 1:
2122                 case 3:
2123                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
2124                         break;
2125                 case 2:
2126                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
2127                         break;
2128                 default:
2129                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2130                         retval = ERROR_FLASH_OPERATION_FAILED;
2131                         break;
2132         }
2133         if (retval == ERROR_OK)
2134         {
2135                 /* Increment pointers and decrease count on succesful block write */
2136                 buffer += blk_count;
2137                 write_p += blk_count;
2138                 count -= blk_count;
2139         }
2140         else
2141         {
2142                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
2143                 {
2144                         /* Calculate buffer size and boundary mask */
2145                         /* buffersize is (buffer size per chip) * (number of chips) */
2146                         /* bufferwsize is buffersize in words */
2147                         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2148                         uint32_t buffermask = buffersize-1;
2149                         uint32_t bufferwsize = buffersize / bank->bus_width;
2150
2151                         /* fall back to memory writes */
2152                         while (count >= (uint32_t)bank->bus_width)
2153                         {
2154                                 int fallback;
2155                                 if ((write_p & 0xff) == 0)
2156                                 {
2157                                         LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
2158                                 }
2159                                 fallback = 1;
2160                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
2161                                 {
2162                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2163                                         if (retval == ERROR_OK)
2164                                         {
2165                                                 buffer += buffersize;
2166                                                 write_p += buffersize;
2167                                                 count -= buffersize;
2168                                                 fallback = 0;
2169                                         }
2170                                 }
2171                                 /* try the slow way? */
2172                                 if (fallback)
2173                                 {
2174                                         for (i = 0; i < bank->bus_width; i++)
2175                                                 current_word[i] = *buffer++;
2176
2177                                         retval = cfi_write_word(bank, current_word, write_p);
2178                                         if (retval != ERROR_OK)
2179                                                 return retval;
2180
2181                                         write_p += bank->bus_width;
2182                                         count -= bank->bus_width;
2183                                 }
2184                         }
2185                 }
2186                 else
2187                         return retval;
2188         }
2189
2190         /* return to read array mode, so we can read from flash again for padding */
2191         if ((retval = cfi_reset(bank)) != ERROR_OK)
2192         {
2193                 return retval;
2194         }
2195
2196         /* handle unaligned tail bytes */
2197         if (count > 0)
2198         {
2199                 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2200
2201                 /* read a complete word from flash */
2202                 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2203                         return retval;
2204
2205                 /* replace only bytes that must be written */
2206                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2207                         current_word[i] = *buffer++;
2208
2209                 retval = cfi_write_word(bank, current_word, write_p);
2210                 if (retval != ERROR_OK)
2211                         return retval;
2212         }
2213
2214         /* return to read array mode */
2215         return cfi_reset(bank);
2216 }
2217
2218 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param)
2219 {
2220         (void) param;
2221         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2222         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2223
2224         pri_ext->_reversed_geometry = 1;
2225 }
2226
2227 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2228 {
2229         int i;
2230         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2231         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2232         (void) param;
2233
2234         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2235         {
2236                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2237
2238                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2239                 {
2240                         int j = (cfi_info->num_erase_regions - 1) - i;
2241                         uint32_t swap;
2242
2243                         swap = cfi_info->erase_region_info[i];
2244                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2245                         cfi_info->erase_region_info[j] = swap;
2246                 }
2247         }
2248 }
2249
2250 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2251 {
2252         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2253         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2254         struct cfi_unlock_addresses *unlock_addresses = param;
2255
2256         pri_ext->_unlock1 = unlock_addresses->unlock1;
2257         pri_ext->_unlock2 = unlock_addresses->unlock2;
2258 }
2259
2260
2261 static int cfi_query_string(struct flash_bank *bank, int address)
2262 {
2263         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2264         int retval;
2265
2266         if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2267         {
2268                 return retval;
2269         }
2270
2271         retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
2272         if (retval != ERROR_OK)
2273                 return retval;
2274         retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
2275         if (retval != ERROR_OK)
2276                 return retval;
2277         retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
2278         if (retval != ERROR_OK)
2279                 return retval;
2280
2281         LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2282
2283         if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2284         {
2285                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2286                 {
2287                         return retval;
2288                 }
2289                 LOG_ERROR("Could not probe bank: no QRY");
2290                 return ERROR_FLASH_BANK_INVALID;
2291         }
2292
2293         return ERROR_OK;
2294 }
2295
2296 static int cfi_probe(struct flash_bank *bank)
2297 {
2298         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2299         struct target *target = bank->target;
2300         int num_sectors = 0;
2301         int i;
2302         int sector = 0;
2303         uint32_t unlock1 = 0x555;
2304         uint32_t unlock2 = 0x2aa;
2305         int retval;
2306         uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2307
2308         if (bank->target->state != TARGET_HALTED)
2309         {
2310                 LOG_ERROR("Target not halted");
2311                 return ERROR_TARGET_NOT_HALTED;
2312         }
2313
2314         cfi_info->probed = 0;
2315         if (bank->sectors)
2316         {
2317                 free(bank->sectors);
2318                 bank->sectors = NULL;
2319         }
2320         if(cfi_info->erase_region_info)
2321         {
2322                 free(cfi_info->erase_region_info);
2323                 cfi_info->erase_region_info = NULL;
2324         }
2325
2326         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2327          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2328          */
2329         if (cfi_info->jedec_probe)
2330         {
2331                 unlock1 = 0x5555;
2332                 unlock2 = 0x2aaa;
2333         }
2334
2335         /* switch to read identifier codes mode ("AUTOSELECT") */
2336         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2337         {
2338                 return retval;
2339         }
2340         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2341         {
2342                 return retval;
2343         }
2344         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2345         {
2346                 return retval;
2347         }
2348
2349         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, value_buf0)) != ERROR_OK)
2350         {
2351                 return retval;
2352         }
2353         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01), bank->bus_width, 1, value_buf1)) != ERROR_OK)
2354         {
2355                 return retval;
2356         }
2357         switch (bank->chip_width) {
2358                 case 1:
2359                         cfi_info->manufacturer = *value_buf0;
2360                         cfi_info->device_id = *value_buf1;
2361                         break;
2362                 case 2:
2363                         cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2364                         cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2365                         break;
2366                 case 4:
2367                         cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2368                         cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2369                         break;
2370                 default:
2371                         LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
2372                         return ERROR_FLASH_OPERATION_FAILED;
2373         }
2374
2375         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2376         /* switch back to read array mode */
2377         if ((retval = cfi_reset(bank)) != ERROR_OK)
2378         {
2379                 return retval;
2380         }
2381
2382         /* check device/manufacturer ID for known non-CFI flashes. */
2383         cfi_fixup_non_cfi(bank);
2384
2385         /* query only if this is a CFI compatible flash,
2386          * otherwise the relevant info has already been filled in
2387          */
2388         if (cfi_info->not_cfi == 0)
2389         {
2390                 /* enter CFI query mode
2391                  * according to JEDEC Standard No. 68.01,
2392                  * a single bus sequence with address = 0x55, data = 0x98 should put
2393                  * the device into CFI query mode.
2394                  *
2395                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2396                  */
2397
2398                 retval = cfi_query_string(bank, 0x55);
2399                 if (retval != ERROR_OK)
2400                 {
2401                         /*
2402                          * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2403                          * be harmless enough:
2404                          *
2405                          * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2406                          */
2407                         LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2408                         retval = cfi_query_string(bank, 0x555);
2409                 }
2410                 if (retval != ERROR_OK)
2411                         return retval;
2412
2413                 retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
2414                 if (retval != ERROR_OK)
2415                         return retval;
2416                 retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
2417                 if (retval != ERROR_OK)
2418                         return retval;
2419                 retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
2420                 if (retval != ERROR_OK)
2421                         return retval;
2422                 retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
2423                 if (retval != ERROR_OK)
2424                         return retval;
2425
2426                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2427
2428                 retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
2429                 if (retval != ERROR_OK)
2430                         return retval;
2431                 retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
2432                 if (retval != ERROR_OK)
2433                         return retval;
2434                 retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
2435                 if (retval != ERROR_OK)
2436                         return retval;
2437                 retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
2438                 if (retval != ERROR_OK)
2439                         return retval;
2440                 retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
2441                 if (retval != ERROR_OK)
2442                         return retval;
2443                 retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
2444                 if (retval != ERROR_OK)
2445                         return retval;
2446                 retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
2447                 if (retval != ERROR_OK)
2448                         return retval;
2449                 retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
2450                 if (retval != ERROR_OK)
2451                         return retval;
2452                 retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
2453                 if (retval != ERROR_OK)
2454                         return retval;
2455                 retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
2456                 if (retval != ERROR_OK)
2457                         return retval;
2458                 retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
2459                 if (retval != ERROR_OK)
2460                         return retval;
2461                 retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
2462                 if (retval != ERROR_OK)
2463                         return retval;
2464
2465                 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2466                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2467                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2468                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2469                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2470                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2471                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2472                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2473                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2474                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2475                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2476
2477                 uint8_t data;
2478                 retval = cfi_query_u8(bank, 0, 0x27, &data);
2479                 if (retval != ERROR_OK)
2480                         return retval;
2481                 cfi_info->dev_size = 1 << data;
2482
2483                 retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
2484                 if (retval != ERROR_OK)
2485                         return retval;
2486                 retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
2487                 if (retval != ERROR_OK)
2488                         return retval;
2489                 retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
2490                 if (retval != ERROR_OK)
2491                         return retval;
2492
2493                 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2494
2495                 if (cfi_info->num_erase_regions)
2496                 {
2497                         cfi_info->erase_region_info = malloc(sizeof(*cfi_info->erase_region_info)
2498                                         * cfi_info->num_erase_regions);
2499                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2500                         {
2501                                 retval = cfi_query_u32(bank, 0, 0x2d + (4 * i), &cfi_info->erase_region_info[i]);
2502                                 if (retval != ERROR_OK)
2503                                         return retval;
2504                                 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2505                                           i,
2506                                           (cfi_info->erase_region_info[i] & 0xffff) + 1,
2507                                           (cfi_info->erase_region_info[i] >> 16) * 256);
2508                         }
2509                 }
2510                 else
2511                 {
2512                         cfi_info->erase_region_info = NULL;
2513                 }
2514
2515                 /* We need to read the primary algorithm extended query table before calculating
2516                  * the sector layout to be able to apply fixups
2517                  */
2518                 switch (cfi_info->pri_id)
2519                 {
2520                         /* Intel command set (standard and extended) */
2521                         case 0x0001:
2522                         case 0x0003:
2523                                 cfi_read_intel_pri_ext(bank);
2524                                 break;
2525                         /* AMD/Spansion, Atmel, ... command set */
2526                         case 0x0002:
2527                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2528                                 cfi_read_0002_pri_ext(bank);
2529                                 break;
2530                         default:
2531                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2532                                 break;
2533                 }
2534
2535                 /* return to read array mode
2536                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2537                  */
2538                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2539                 {
2540                         return retval;
2541                 }
2542         } /* end CFI case */
2543
2544         /* apply fixups depending on the primary command set */
2545         switch (cfi_info->pri_id)
2546         {
2547                 /* Intel command set (standard and extended) */
2548                 case 0x0001:
2549                 case 0x0003:
2550                         cfi_fixup(bank, cfi_0001_fixups);
2551                         break;
2552                 /* AMD/Spansion, Atmel, ... command set */
2553                 case 0x0002:
2554                         cfi_fixup(bank, cfi_0002_fixups);
2555                         break;
2556                 default:
2557                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2558                         break;
2559         }
2560
2561         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2562         {
2563                 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2564         }
2565
2566         if (cfi_info->num_erase_regions == 0)
2567         {
2568                 /* a device might have only one erase block, spanning the whole device */
2569                 bank->num_sectors = 1;
2570                 bank->sectors = malloc(sizeof(struct flash_sector));
2571
2572                 bank->sectors[sector].offset = 0x0;
2573                 bank->sectors[sector].size = bank->size;
2574                 bank->sectors[sector].is_erased = -1;
2575                 bank->sectors[sector].is_protected = -1;
2576         }
2577         else
2578         {
2579                 uint32_t offset = 0;
2580
2581                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2582                 {
2583                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2584                 }
2585
2586                 bank->num_sectors = num_sectors;
2587                 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2588
2589                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2590                 {
2591                         uint32_t j;
2592                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2593                         {
2594                                 bank->sectors[sector].offset = offset;
2595                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2596                                 offset += bank->sectors[sector].size;
2597                                 bank->sectors[sector].is_erased = -1;
2598                                 bank->sectors[sector].is_protected = -1;
2599                                 sector++;
2600                         }
2601                 }
2602                 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2603                 {
2604                         LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2605                                 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2606                 }
2607         }
2608
2609         cfi_info->probed = 1;
2610
2611         return ERROR_OK;
2612 }
2613
2614 static int cfi_auto_probe(struct flash_bank *bank)
2615 {
2616         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2617         if (cfi_info->probed)
2618                 return ERROR_OK;
2619         return cfi_probe(bank);
2620 }
2621
2622 static int cfi_intel_protect_check(struct flash_bank *bank)
2623 {
2624         int retval;
2625         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2626         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2627         int i;
2628
2629         /* check if block lock bits are supported on this device */
2630         if (!(pri_ext->blk_status_reg_mask & 0x1))
2631                 return ERROR_FLASH_OPERATION_FAILED;
2632
2633         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2634         {
2635                 return retval;
2636         }
2637
2638         for (i = 0; i < bank->num_sectors; i++)
2639         {
2640                 uint8_t block_status;
2641                 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2642                 if (retval != ERROR_OK)
2643                         return retval;
2644
2645                 if (block_status & 1)
2646                         bank->sectors[i].is_protected = 1;
2647                 else
2648                         bank->sectors[i].is_protected = 0;
2649         }
2650
2651         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2652 }
2653
2654 static int cfi_spansion_protect_check(struct flash_bank *bank)
2655 {
2656         int retval;
2657         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2658         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2659         int i;
2660
2661         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2662         {
2663                 return retval;
2664         }
2665
2666         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2667         {
2668                 return retval;
2669         }
2670
2671         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2672         {
2673                 return retval;
2674         }
2675
2676         for (i = 0; i < bank->num_sectors; i++)
2677         {
2678                 uint8_t block_status;
2679                 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2680                 if (retval != ERROR_OK)
2681                         return retval;
2682
2683                 if (block_status & 1)
2684                         bank->sectors[i].is_protected = 1;
2685                 else
2686                         bank->sectors[i].is_protected = 0;
2687         }
2688
2689         return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2690 }
2691
2692 static int cfi_protect_check(struct flash_bank *bank)
2693 {
2694         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2695
2696         if (bank->target->state != TARGET_HALTED)
2697         {
2698                 LOG_ERROR("Target not halted");
2699                 return ERROR_TARGET_NOT_HALTED;
2700         }
2701
2702         if (cfi_info->qry[0] != 'Q')
2703                 return ERROR_FLASH_BANK_NOT_PROBED;
2704
2705         switch (cfi_info->pri_id)
2706         {
2707                 case 1:
2708                 case 3:
2709                         return cfi_intel_protect_check(bank);
2710                         break;
2711                 case 2:
2712                         return cfi_spansion_protect_check(bank);
2713                         break;
2714                 default:
2715                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2716                         break;
2717         }
2718
2719         return ERROR_OK;
2720 }
2721
2722 static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2723 {
2724         int printed;
2725         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2726
2727         if (cfi_info->qry[0] == 0xff)
2728         {
2729                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2730                 return ERROR_OK;
2731         }
2732
2733         if (cfi_info->not_cfi == 0)
2734                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2735         else
2736                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2737         buf += printed;
2738         buf_size -= printed;
2739
2740         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2741                 cfi_info->manufacturer, cfi_info->device_id);
2742         buf += printed;
2743         buf_size -= printed;
2744
2745         if (cfi_info->not_cfi == 0)
2746         {
2747         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2748         buf += printed;
2749         buf_size -= printed;
2750
2751                 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2752                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2753         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2754         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2755         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2756         buf += printed;
2757         buf_size -= printed;
2758
2759                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2760                                    1 << cfi_info->word_write_timeout_typ,
2761                                    1 << cfi_info->buf_write_timeout_typ,
2762                                    1 << cfi_info->block_erase_timeout_typ,
2763                                    1 << cfi_info->chip_erase_timeout_typ);
2764         buf += printed;
2765         buf_size -= printed;
2766
2767                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2768                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2769                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2770                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2771                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2772         buf += printed;
2773         buf_size -= printed;
2774
2775                 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2776                                    cfi_info->dev_size,
2777                                    cfi_info->interface_desc,
2778                                    1 << cfi_info->max_buf_write_size);
2779         buf += printed;
2780         buf_size -= printed;
2781
2782         switch (cfi_info->pri_id)
2783         {
2784                 case 1:
2785                 case 3:
2786                         cfi_intel_info(bank, buf, buf_size);
2787                         break;
2788                 case 2:
2789                         cfi_spansion_info(bank, buf, buf_size);
2790                         break;
2791                 default:
2792                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2793                         break;
2794         }
2795         }
2796
2797         return ERROR_OK;
2798 }
2799
2800 struct flash_driver cfi_flash = {
2801         .name = "cfi",
2802         .flash_bank_command = cfi_flash_bank_command,
2803         .erase = cfi_erase,
2804         .protect = cfi_protect,
2805         .write = cfi_write,
2806         .read = cfi_read,
2807         .probe = cfi_probe,
2808         .auto_probe = cfi_auto_probe,
2809         /* FIXME: access flash at bus_width size */
2810         .erase_check = default_flash_blank_check,
2811         .protect_check = cfi_protect_check,
2812         .info = get_cfi_info,
2813 };