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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *   Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com>            *
   7  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "imp.h"
  29 #include "cfi.h"
  30 #include "non_cfi.h"
  31 #include <target/arm.h>
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34
  35
  36 #define CFI_MAX_BUS_WIDTH       4
  37 #define CFI_MAX_CHIP_WIDTH      4
  38
  39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  40 #define CFI_MAX_INTEL_CODESIZE 256
  41
  42 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
  43 {
  44         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  45         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  46 };
  47
  48 /* CFI fixups foward declarations */
  49 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
  50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
  51 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
  52
  53 /* fixup after reading cmdset 0002 primary query table */
  54 static const struct cfi_fixup cfi_0002_fixups[] = {
  55         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  56         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  57         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  58         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  59         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  60         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  61    {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  62         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  63         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  64         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  65         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  66         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  67         {0, 0, NULL, NULL}
  68 };
  69
  70 /* fixup after reading cmdset 0001 primary query table */
  71 static const struct cfi_fixup cfi_0001_fixups[] = {
  72         {0, 0, NULL, NULL}
  73 };
  74
  75 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
  76 {
  77         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  78         const struct cfi_fixup *f;
  79
  80         for (f = fixups; f->fixup; f++)
  81         {
  82                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
  83                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
  84                 {
  85                         f->fixup(bank, f->param);
  86                 }
  87         }
  88 }
  89
  90 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
  91 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
  92 {
  93         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  94
  95         if (cfi_info->x16_as_x8) offset *= 2;
  96
  97         /* while the sector list isn't built, only accesses to sector 0 work */
  98         if (sector == 0)
  99                 return bank->base + offset * bank->bus_width;
 100         else
 101         {
 102                 if (!bank->sectors)
 103                 {
 104                         LOG_ERROR("BUG: sector list not yet built");
 105                         exit(-1);
 106                 }
 107                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 108         }
 109 }
 110
 111 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
 112 {
 113         int i;
 114
 115         /* clear whole buffer, to ensure bits that exceed the bus_width
 116          * are set to zero
 117          */
 118         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 119                 cmd_buf[i] = 0;
 120
 121         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 122         {
 123                 for (i = bank->bus_width; i > 0; i--)
 124                 {
 125                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 126                 }
 127         }
 128         else
 129         {
 130                 for (i = 1; i <= bank->bus_width; i++)
 131                 {
 132                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 133                 }
 134         }
 135 }
 136
 137 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
 138 {
 139     uint8_t command[CFI_MAX_BUS_WIDTH];
 140
 141     cfi_command(bank, cmd, command);
 142     return target_write_memory(bank->target, address, bank->bus_width, 1, command);
 143 }
 144
 145 /* read unsigned 8-bit value from the bank
 146  * flash banks are expected to be made of similar chips
 147  * the query result should be the same for all
 148  */
 149 static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
 150 {
 151         struct target *target = bank->target;
 152         uint8_t data[CFI_MAX_BUS_WIDTH];
 153
 154         int retval;
 155         retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 156         if (retval != ERROR_OK)
 157                 return retval;
 158
 159         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 160                 *val = data[0];
 161         else
 162                 *val = data[bank->bus_width - 1];
 163
 164         return ERROR_OK;
 165 }
 166
 167 /* read unsigned 8-bit value from the bank
 168  * in case of a bank made of multiple chips,
 169  * the individual values are ORed
 170  */
 171 static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
 172 {
 173         struct target *target = bank->target;
 174         uint8_t data[CFI_MAX_BUS_WIDTH];
 175         int i;
 176
 177         int retval;
 178         retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 179         if (retval != ERROR_OK)
 180                 return retval;
 181
 182         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 183         {
 184                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 185                         data[0] |= data[i];
 186
 187                 *val = data[0];
 188         }
 189         else
 190         {
 191                 uint8_t value = 0;
 192                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 193                         value |= data[bank->bus_width - 1 - i];
 194
 195                 *val = value;
 196         }
 197         return ERROR_OK;
 198 }
 199
 200 static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
 201 {
 202         struct target *target = bank->target;
 203         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 204         uint8_t data[CFI_MAX_BUS_WIDTH * 2];
 205         int retval;
 206
 207         if (cfi_info->x16_as_x8)
 208         {
 209                 uint8_t i;
 210                 for (i = 0;i < 2;i++)
 211                 {
 212                         retval = target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 213                                 &data[i*bank->bus_width]);
 214                         if (retval != ERROR_OK)
 215                                 return retval;
 216                 }
 217         } else
 218         {
 219                 retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 220                 if (retval != ERROR_OK)
 221                         return retval;
 222         }
 223
 224         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 225                 *val = data[0] | data[bank->bus_width] << 8;
 226         else
 227                 *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 228
 229         return ERROR_OK;
 230 }
 231
 232 static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
 233 {
 234         struct target *target = bank->target;
 235         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 236         uint8_t data[CFI_MAX_BUS_WIDTH * 4];
 237         int retval;
 238
 239         if (cfi_info->x16_as_x8)
 240         {
 241                 uint8_t i;
 242                 for (i = 0;i < 4;i++)
 243                 {
 244                         retval = target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 245                                 &data[i*bank->bus_width]);
 246                         if (retval != ERROR_OK)
 247                                 return retval;
 248                 }
 249         }
 250         else
 251         {
 252                 retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 253                 if (retval != ERROR_OK)
 254                         return retval;
 255         }
 256
 257         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 258                 *val = data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 259         else
 260                 *val = data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 261                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 262
 263         return ERROR_OK;
 264 }
 265
 266 static int cfi_reset(struct flash_bank *bank)
 267 {
 268         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 269         int retval = ERROR_OK;
 270
 271         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 272         {
 273                 return retval;
 274         }
 275
 276         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 277         {
 278                 return retval;
 279         }
 280
 281         if (cfi_info->manufacturer == 0x20 &&
 282                         (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
 283         {
 284                 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
 285                  * so we send an extra 0xF0 reset to fix the bug */
 286                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
 287                 {
 288                         return retval;
 289                 }
 290         }
 291
 292         return retval;
 293 }
 294
 295 static void cfi_intel_clear_status_register(struct flash_bank *bank)
 296 {
 297         struct target *target = bank->target;
 298
 299         if (target->state != TARGET_HALTED)
 300         {
 301                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 302                 exit(-1);
 303         }
 304
 305         cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
 306 }
 307
 308 static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
 309 {
 310         uint8_t status;
 311
 312         int retval = ERROR_OK;
 313
 314         for (;;)
 315         {
 316                 if (timeout-- < 0)
 317                 {
 318                   LOG_ERROR("timeout while waiting for WSM to become ready");
 319                   return ERROR_FAIL;
 320                 }
 321
 322                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 323                 if (retval != ERROR_OK)
 324                         return retval;
 325
 326                 if (status & 0x80)
 327                         break;
 328
 329                 alive_sleep(1);
 330         }
 331
 332         /* mask out bit 0 (reserved) */
 333         status = status & 0xfe;
 334
 335         LOG_DEBUG("status: 0x%x", status);
 336
 337         if (status != 0x80)
 338         {
 339                 LOG_ERROR("status register: 0x%x", status);
 340                 if (status & 0x2)
 341                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 342                 if (status & 0x4)
 343                         LOG_ERROR("Program suspended");
 344                 if (status & 0x8)
 345                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 346                 if (status & 0x10)
 347                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 348                 if (status & 0x20)
 349                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 350                 if (status & 0x40)
 351                         LOG_ERROR("Block Erase Suspended");
 352
 353                 cfi_intel_clear_status_register(bank);
 354
 355                 retval = ERROR_FAIL;
 356         }
 357
 358         *val = status;
 359         return retval;
 360 }
 361
 362 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
 363 {
 364         uint8_t status, oldstatus;
 365         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 366         int retval;
 367
 368         retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
 369         if (retval != ERROR_OK)
 370                 return retval;
 371
 372         do {
 373                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 374
 375                 if (retval != ERROR_OK)
 376                         return retval;
 377
 378                 if ((status ^ oldstatus) & 0x40) {
 379                         if (status & cfi_info->status_poll_mask & 0x20) {
 380                                 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
 381                                 if (retval != ERROR_OK)
 382                                         return retval;
 383                                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 384                                 if (retval != ERROR_OK)
 385                                         return retval;
 386                                 if ((status ^ oldstatus) & 0x40) {
 387                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 388                                         return(ERROR_FLASH_OPERATION_FAILED);
 389                                 } else {
 390                                         LOG_DEBUG("status: 0x%x", status);
 391                                         return(ERROR_OK);
 392                                 }
 393                         }
 394                 } else { /* no toggle: finished, OK */
 395                         LOG_DEBUG("status: 0x%x", status);
 396                         return(ERROR_OK);
 397                 }
 398
 399                 oldstatus = status;
 400                 alive_sleep(1);
 401         } while (timeout-- > 0);
 402
 403         LOG_ERROR("timeout, status: 0x%x", status);
 404
 405         return(ERROR_FLASH_BUSY);
 406 }
 407
 408 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
 409 {
 410         int retval;
 411         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 412         struct cfi_intel_pri_ext *pri_ext;
 413
 414         if (cfi_info->pri_ext)
 415                 free(cfi_info->pri_ext);
 416
 417         pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
 418         if (pri_ext == NULL)
 419         {
 420                 LOG_ERROR("Out of memory");
 421                 return ERROR_FAIL;
 422         }
 423         cfi_info->pri_ext = pri_ext;
 424
 425         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
 426         if (retval != ERROR_OK)
 427                 return retval;
 428         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
 429         if (retval != ERROR_OK)
 430                 return retval;
 431         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
 432         if (retval != ERROR_OK)
 433                 return retval;
 434
 435         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 436         {
 437                 if ((retval = cfi_reset(bank)) != ERROR_OK)
 438                 {
 439                         return retval;
 440                 }
 441                 LOG_ERROR("Could not read bank flash bank information");
 442                 return ERROR_FLASH_BANK_INVALID;
 443         }
 444
 445         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
 446         if (retval != ERROR_OK)
 447                 return retval;
 448         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
 449         if (retval != ERROR_OK)
 450                 return retval;
 451
 452         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 453
 454         retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
 455         if (retval != ERROR_OK)
 456                 return retval;
 457         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
 458         if (retval != ERROR_OK)
 459                 return retval;
 460         retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
 461         if (retval != ERROR_OK)
 462                 return retval;
 463
 464         LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
 465                   pri_ext->feature_support,
 466                   pri_ext->suspend_cmd_support,
 467                   pri_ext->blk_status_reg_mask);
 468
 469         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
 470         if (retval != ERROR_OK)
 471                 return retval;
 472         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
 473         if (retval != ERROR_OK)
 474                 return retval;
 475
 476         LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
 477                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 478                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 479
 480         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
 481         if (retval != ERROR_OK)
 482                 return retval;
 483         if (pri_ext->num_protection_fields != 1)
 484         {
 485                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 486         }
 487
 488         retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
 489         if (retval != ERROR_OK)
 490                 return retval;
 491         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
 492         if (retval != ERROR_OK)
 493                 return retval;
 494         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
 495         if (retval != ERROR_OK)
 496                 return retval;
 497
 498         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 499
 500         return ERROR_OK;
 501 }
 502
 503 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
 504 {
 505         int retval;
 506         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 507         struct cfi_spansion_pri_ext *pri_ext;
 508
 509         if (cfi_info->pri_ext)
 510                 free(cfi_info->pri_ext);
 511
 512         pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 513         if (pri_ext == NULL)
 514         {
 515                 LOG_ERROR("Out of memory");
 516                 return ERROR_FAIL;
 517         }
 518         cfi_info->pri_ext = pri_ext;
 519
 520         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
 521         if (retval != ERROR_OK)
 522                 return retval;
 523         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
 524         if (retval != ERROR_OK)
 525                 return retval;
 526         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
 527         if (retval != ERROR_OK)
 528                 return retval;
 529
 530         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 531         {
 532                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 533                 {
 534                         return retval;
 535                 }
 536                 LOG_ERROR("Could not read spansion bank information");
 537                 return ERROR_FLASH_BANK_INVALID;
 538         }
 539
 540         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
 541         if (retval != ERROR_OK)
 542                 return retval;
 543         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
 544         if (retval != ERROR_OK)
 545                 return retval;
 546
 547         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 548
 549         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
 550         if (retval != ERROR_OK)
 551                 return retval;
 552         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
 553         if (retval != ERROR_OK)
 554                 return retval;
 555         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
 556         if (retval != ERROR_OK)
 557                 return retval;
 558         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
 559         if (retval != ERROR_OK)
 560                 return retval;
 561         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
 562         if (retval != ERROR_OK)
 563                 return retval;
 564         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
 565         if (retval != ERROR_OK)
 566                 return retval;
 567         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
 568         if (retval != ERROR_OK)
 569                 return retval;
 570         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
 571         if (retval != ERROR_OK)
 572                 return retval;
 573         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
 574         if (retval != ERROR_OK)
 575                 return retval;
 576         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
 577         if (retval != ERROR_OK)
 578                 return retval;
 579         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
 580         if (retval != ERROR_OK)
 581                 return retval;
 582
 583         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 584               pri_ext->EraseSuspend, pri_ext->BlkProt);
 585
 586         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 587               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 588
 589         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 590
 591
 592         LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
 593                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 594                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 595
 596         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 597
 598         /* default values for implementation specific workarounds */
 599         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 600         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 601         pri_ext->_reversed_geometry = 0;
 602
 603         return ERROR_OK;
 604 }
 605
 606 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
 607 {
 608         int retval;
 609         struct cfi_atmel_pri_ext atmel_pri_ext;
 610         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 611         struct cfi_spansion_pri_ext *pri_ext;
 612
 613         if (cfi_info->pri_ext)
 614                 free(cfi_info->pri_ext);
 615
 616         pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 617         if (pri_ext == NULL)
 618         {
 619                 LOG_ERROR("Out of memory");
 620                 return ERROR_FAIL;
 621         }
 622
 623         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 624          * but a different primary extended query table.
 625          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 626          */
 627
 628         memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
 629
 630         cfi_info->pri_ext = pri_ext;
 631
 632         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
 633         if (retval != ERROR_OK)
 634                 return retval;
 635         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
 636         if (retval != ERROR_OK)
 637                 return retval;
 638         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
 639         if (retval != ERROR_OK)
 640                 return retval;
 641
 642         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 643         {
 644                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 645                 {
 646                         return retval;
 647                 }
 648                 LOG_ERROR("Could not read atmel bank information");
 649                 return ERROR_FLASH_BANK_INVALID;
 650         }
 651
 652         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 653         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 654         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 655
 656         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
 657         if (retval != ERROR_OK)
 658                 return retval;
 659         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
 660         if (retval != ERROR_OK)
 661                 return retval;
 662
 663         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 664
 665         pri_ext->major_version = atmel_pri_ext.major_version;
 666         pri_ext->minor_version = atmel_pri_ext.minor_version;
 667
 668         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
 669         if (retval != ERROR_OK)
 670                 return retval;
 671         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
 672         if (retval != ERROR_OK)
 673                 return retval;
 674         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
 675         if (retval != ERROR_OK)
 676                 return retval;
 677         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
 678         if (retval != ERROR_OK)
 679                 return retval;
 680
 681         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 682                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 683
 684         if (atmel_pri_ext.features & 0x02)
 685                 pri_ext->EraseSuspend = 2;
 686
 687         if (atmel_pri_ext.bottom_boot)
 688                 pri_ext->TopBottom = 2;
 689         else
 690                 pri_ext->TopBottom = 3;
 691
 692         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 693         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 694
 695         return ERROR_OK;
 696 }
 697
 698 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
 699 {
 700         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 701
 702         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 703         {
 704                 return cfi_read_atmel_pri_ext(bank);
 705         }
 706         else
 707         {
 708                 return cfi_read_spansion_pri_ext(bank);
 709         }
 710 }
 711
 712 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
 713 {
 714         int printed;
 715         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 716         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 717
 718         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 719         buf += printed;
 720         buf_size -= printed;
 721
 722         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 723                            pri_ext->pri[1], pri_ext->pri[2],
 724                            pri_ext->major_version, pri_ext->minor_version);
 725         buf += printed;
 726         buf_size -= printed;
 727
 728         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 729                            (pri_ext->SiliconRevision) >> 2,
 730                            (pri_ext->SiliconRevision) & 0x03);
 731         buf += printed;
 732         buf_size -= printed;
 733
 734         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 735                            pri_ext->EraseSuspend,
 736                            pri_ext->BlkProt);
 737         buf += printed;
 738         buf_size -= printed;
 739
 740         printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
 741                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 742                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 743
 744         return ERROR_OK;
 745 }
 746
 747 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
 748 {
 749         int printed;
 750         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 751         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 752
 753         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 754         buf += printed;
 755         buf_size -= printed;
 756
 757         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 758         buf += printed;
 759         buf_size -= printed;
 760
 761         printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 762         buf += printed;
 763         buf_size -= printed;
 764
 765         printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
 766                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 767                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 768         buf += printed;
 769         buf_size -= printed;
 770
 771         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 772
 773         return ERROR_OK;
 774 }
 775
 776 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 777  */
 778 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
 779 {
 780         struct cfi_flash_bank *cfi_info;
 781
 782         if (CMD_ARGC < 6)
 783         {
 784                 LOG_WARNING("incomplete flash_bank cfi configuration");
 785                 return ERROR_FLASH_BANK_INVALID;
 786         }
 787
 788         /* both widths must:
 789          * - not exceed max value;
 790          * - not be null;
 791          * - be equal to a power of 2.
 792          * bus must be wide enought to hold one chip */
 793         if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
 794                         || (bank->bus_width > CFI_MAX_BUS_WIDTH)
 795                         || (bank->chip_width == 0)
 796                         || (bank->bus_width == 0)
 797                         || (bank->chip_width & (bank->chip_width - 1))
 798                         || (bank->bus_width & (bank->bus_width - 1))
 799                         || (bank->chip_width > bank->bus_width))
 800         {
 801                 LOG_ERROR("chip and bus width have to specified in bytes");
 802                 return ERROR_FLASH_BANK_INVALID;
 803         }
 804
 805         cfi_info = malloc(sizeof(struct cfi_flash_bank));
 806         cfi_info->probed = 0;
 807         cfi_info->erase_region_info = 0;
 808         cfi_info->pri_ext = NULL;
 809         bank->driver_priv = cfi_info;
 810
 811         cfi_info->write_algorithm = NULL;
 812
 813         cfi_info->x16_as_x8 = 0;
 814         cfi_info->jedec_probe = 0;
 815         cfi_info->not_cfi = 0;
 816
 817         for (unsigned i = 6; i < CMD_ARGC; i++)
 818         {
 819                 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
 820                 {
 821                         cfi_info->x16_as_x8 = 1;
 822                 }
 823                 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
 824                 {
 825                         cfi_info->jedec_probe = 1;
 826                 }
 827         }
 828
 829         cfi_info->write_algorithm = NULL;
 830
 831         /* bank wasn't probed yet */
 832         cfi_info->qry[0] = 0xff;
 833
 834         return ERROR_OK;
 835 }
 836
 837 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
 838 {
 839         int retval;
 840         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 841         int i;
 842
 843         cfi_intel_clear_status_register(bank);
 844
 845         for (i = first; i <= last; i++)
 846         {
 847                 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
 848                 {
 849                         return retval;
 850                 }
 851
 852                 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
 853                 {
 854                         return retval;
 855                 }
 856
 857                 uint8_t status;
 858                 retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ), &status);
 859                 if (retval != ERROR_OK)
 860                         return retval;
 861
 862                 if (status == 0x80)
 863                         bank->sectors[i].is_erased = 1;
 864                 else
 865                 {
 866                         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 867                         {
 868                                 return retval;
 869                         }
 870
 871                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
 872                         return ERROR_FLASH_OPERATION_FAILED;
 873                 }
 874         }
 875
 876         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
 877 }
 878
 879 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
 880 {
 881         int retval;
 882         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 883         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 884         int i;
 885
 886         for (i = first; i <= last; i++)
 887         {
 888                 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 889                 {
 890                         return retval;
 891                 }
 892
 893                 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 894                 {
 895                         return retval;
 896                 }
 897
 898                 if ((retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 899                 {
 900                         return retval;
 901                 }
 902
 903                 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 904                 {
 905                         return retval;
 906                 }
 907
 908                 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 909                 {
 910                         return retval;
 911                 }
 912
 913                 if ((retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0))) != ERROR_OK)
 914                 {
 915                         return retval;
 916                 }
 917
 918                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 919                         bank->sectors[i].is_erased = 1;
 920                 else
 921                 {
 922                         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 923                         {
 924                                 return retval;
 925                         }
 926
 927                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
 928                         return ERROR_FLASH_OPERATION_FAILED;
 929                 }
 930         }
 931
 932         return  cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
 933 }
 934
 935 static int cfi_erase(struct flash_bank *bank, int first, int last)
 936 {
 937         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 938
 939         if (bank->target->state != TARGET_HALTED)
 940         {
 941                 LOG_ERROR("Target not halted");
 942                 return ERROR_TARGET_NOT_HALTED;
 943         }
 944
 945         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 946         {
 947                 return ERROR_FLASH_SECTOR_INVALID;
 948         }
 949
 950         if (cfi_info->qry[0] != 'Q')
 951                 return ERROR_FLASH_BANK_NOT_PROBED;
 952
 953         switch (cfi_info->pri_id)
 954         {
 955                 case 1:
 956                 case 3:
 957                         return cfi_intel_erase(bank, first, last);
 958                         break;
 959                 case 2:
 960                         return cfi_spansion_erase(bank, first, last);
 961                         break;
 962                 default:
 963                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 964                         break;
 965         }
 966
 967         return ERROR_OK;
 968 }
 969
 970 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
 971 {
 972         int retval;
 973         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 974         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 975         int retry = 0;
 976         int i;
 977
 978         /* if the device supports neither legacy lock/unlock (bit 3) nor
 979          * instant individual block locking (bit 5).
 980          */
 981         if (!(pri_ext->feature_support & 0x28))
 982                 return ERROR_FLASH_OPERATION_FAILED;
 983
 984         cfi_intel_clear_status_register(bank);
 985
 986         for (i = first; i <= last; i++)
 987         {
 988                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
 989                 {
 990                         return retval;
 991                 }
 992                 if (set)
 993                 {
 994                         if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
 995                         {
 996                                 return retval;
 997                         }
 998                         bank->sectors[i].is_protected = 1;
 999                 }
1000                 else
1001                 {
1002                         if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
1003                         {
1004                                 return retval;
1005                         }
1006                         bank->sectors[i].is_protected = 0;
1007                 }
1008
1009                 /* instant individual block locking doesn't require reading of the status register */
1010                 if (!(pri_ext->feature_support & 0x20))
1011                 {
1012                         /* Clear lock bits operation may take up to 1.4s */
1013                         uint8_t status;
1014                         retval = cfi_intel_wait_status_busy(bank, 1400, &status);
1015                         if (retval != ERROR_OK)
1016                                 return retval;
1017                 }
1018                 else
1019                 {
1020                         uint8_t block_status;
1021                         /* read block lock bit, to verify status */
1022                         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
1023                         {
1024                                 return retval;
1025                         }
1026                         retval = cfi_get_u8(bank, i, 0x2, &block_status);
1027                         if (retval != ERROR_OK)
1028                                 return retval;
1029
1030                         if ((block_status & 0x1) != set)
1031                         {
1032                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
1033                                 if ((retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55))) != ERROR_OK)
1034                                 {
1035                                         return retval;
1036                                 }
1037                                 uint8_t status;
1038                                 retval = cfi_intel_wait_status_busy(bank, 10, &status);
1039                                 if (retval != ERROR_OK)
1040                                         return retval;
1041
1042                                 if (retry > 10)
1043                                         return ERROR_FLASH_OPERATION_FAILED;
1044                                 else
1045                                 {
1046                                         i--;
1047                                         retry++;
1048                                 }
1049                         }
1050                 }
1051         }
1052
1053         /* if the device doesn't support individual block lock bits set/clear,
1054          * all blocks have been unlocked in parallel, so we set those that should be protected
1055          */
1056         if ((!set) && (!(pri_ext->feature_support & 0x20)))
1057         {
1058                 /* FIX!!! this code path is broken!!!
1059                  *
1060                  * The correct approach is:
1061                  *
1062                  * 1. read out current protection status
1063                  *
1064                  * 2. override read out protection status w/unprotected.
1065                  *
1066                  * 3. re-protect what should be protected.
1067                  *
1068                  */
1069                 for (i = 0; i < bank->num_sectors; i++)
1070                 {
1071                         if (bank->sectors[i].is_protected == 1)
1072                         {
1073                                 cfi_intel_clear_status_register(bank);
1074
1075                                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
1076                                 {
1077                                         return retval;
1078                                 }
1079
1080                                 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
1081                                 {
1082                                         return retval;
1083                                 }
1084
1085                                 uint8_t status;
1086                                 retval = cfi_intel_wait_status_busy(bank, 100, &status);
1087                                 if (retval != ERROR_OK)
1088                                         return retval;
1089                         }
1090                 }
1091         }
1092
1093         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
1094 }
1095
1096 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
1097 {
1098         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1099
1100         if (bank->target->state != TARGET_HALTED)
1101         {
1102                 LOG_ERROR("Target not halted");
1103                 return ERROR_TARGET_NOT_HALTED;
1104         }
1105
1106         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
1107         {
1108                 LOG_ERROR("Invalid sector range");
1109                 return ERROR_FLASH_SECTOR_INVALID;
1110         }
1111
1112         if (cfi_info->qry[0] != 'Q')
1113                 return ERROR_FLASH_BANK_NOT_PROBED;
1114
1115         switch (cfi_info->pri_id)
1116         {
1117                 case 1:
1118                 case 3:
1119                         return cfi_intel_protect(bank, set, first, last);
1120                         break;
1121                 default:
1122                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
1123                         return ERROR_FAIL;
1124         }
1125 }
1126
1127 /* Convert code image to target endian */
1128 /* FIXME create general block conversion fcts in target.c?) */
1129 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
1130 {
1131         uint32_t i;
1132         for (i = 0; i< count; i++)
1133         {
1134                 target_buffer_set_u32(target, dest, *src);
1135                 dest += 4;
1136                 src++;
1137         }
1138 }
1139
1140 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
1141 {
1142         struct target *target = bank->target;
1143
1144         uint8_t buf[CFI_MAX_BUS_WIDTH];
1145         cfi_command(bank, cmd, buf);
1146         switch (bank->bus_width)
1147         {
1148         case 1 :
1149                 return buf[0];
1150                 break;
1151         case 2 :
1152                 return target_buffer_get_u16(target, buf);
1153                 break;
1154         case 4 :
1155                 return target_buffer_get_u32(target, buf);
1156                 break;
1157         default :
1158                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1159                 return 0;
1160         }
1161 }
1162
1163 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1164 {
1165         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1166         struct target *target = bank->target;
1167         struct reg_param reg_params[7];
1168         struct arm_algorithm armv4_5_info;
1169         struct working_area *source;
1170         uint32_t buffer_size = 32768;
1171         uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1172
1173         /* algorithm register usage:
1174          * r0: source address (in RAM)
1175          * r1: target address (in Flash)
1176          * r2: count
1177          * r3: flash write command
1178          * r4: status byte (returned to host)
1179          * r5: busy test pattern
1180          * r6: error test pattern
1181          */
1182
1183         static const uint32_t word_32_code[] = {
1184                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1185                 0xe5813000,   /*                str r3, [r1] */
1186                 0xe5814000,   /*                str r4, [r1] */
1187                 0xe5914000,   /* busy:  ldr r4, [r1] */
1188                 0xe0047005,   /*                and r7, r4, r5 */
1189                 0xe1570005,   /*                cmp r7, r5 */
1190                 0x1afffffb,   /*                bne busy */
1191                 0xe1140006,   /*                tst r4, r6 */
1192                 0x1a000003,   /*                bne done */
1193                 0xe2522001,   /*                subs r2, r2, #1 */
1194                 0x0a000001,   /*                beq done */
1195                 0xe2811004,   /*                add r1, r1 #4 */
1196                 0xeafffff2,   /*                b loop */
1197                 0xeafffffe    /* done:  b -2 */
1198         };
1199
1200         static const uint32_t word_16_code[] = {
1201                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1202                 0xe1c130b0,   /*                strh r3, [r1] */
1203                 0xe1c140b0,   /*                strh r4, [r1] */
1204                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1205                 0xe0047005,   /*                and r7, r4, r5 */
1206                 0xe1570005,   /*                cmp r7, r5 */
1207                 0x1afffffb,   /*                bne busy */
1208                 0xe1140006,   /*                tst r4, r6 */
1209                 0x1a000003,   /*                bne done */
1210                 0xe2522001,   /*                subs r2, r2, #1 */
1211                 0x0a000001,   /*                beq done */
1212                 0xe2811002,   /*                add r1, r1 #2 */
1213                 0xeafffff2,   /*                b loop */
1214                 0xeafffffe    /* done:  b -2 */
1215         };
1216
1217         static const uint32_t word_8_code[] = {
1218                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1219                 0xe5c13000,   /*                strb r3, [r1] */
1220                 0xe5c14000,   /*                strb r4, [r1] */
1221                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1222                 0xe0047005,   /*                and r7, r4, r5 */
1223                 0xe1570005,   /*                cmp r7, r5 */
1224                 0x1afffffb,   /*                bne busy */
1225                 0xe1140006,   /*                tst r4, r6 */
1226                 0x1a000003,   /*                bne done */
1227                 0xe2522001,   /*                subs r2, r2, #1 */
1228                 0x0a000001,   /*                beq done */
1229                 0xe2811001,   /*                add r1, r1 #1 */
1230                 0xeafffff2,   /*                b loop */
1231                 0xeafffffe    /* done:  b -2 */
1232         };
1233         uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1234         const uint32_t *target_code_src;
1235         uint32_t target_code_size;
1236         int retval = ERROR_OK;
1237
1238
1239         cfi_intel_clear_status_register(bank);
1240
1241         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1242         armv4_5_info.core_mode = ARM_MODE_SVC;
1243         armv4_5_info.core_state = ARM_STATE_ARM;
1244
1245         /* If we are setting up the write_algorith, we need target_code_src */
1246         /* if not we only need target_code_size. */
1247
1248         /* However, we don't want to create multiple code paths, so we */
1249         /* do the unecessary evaluation of target_code_src, which the */
1250         /* compiler will probably nicely optimize away if not needed */
1251
1252         /* prepare algorithm code for target endian */
1253         switch (bank->bus_width)
1254         {
1255         case 1 :
1256                 target_code_src = word_8_code;
1257                 target_code_size = sizeof(word_8_code);
1258                 break;
1259         case 2 :
1260                 target_code_src = word_16_code;
1261                 target_code_size = sizeof(word_16_code);
1262                 break;
1263         case 4 :
1264                 target_code_src = word_32_code;
1265                 target_code_size = sizeof(word_32_code);
1266                 break;
1267         default:
1268                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1269                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1270         }
1271
1272         /* flash write code */
1273         if (!cfi_info->write_algorithm)
1274         {
1275                 if (target_code_size > sizeof(target_code))
1276                 {
1277                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1278                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1279                 }
1280                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1281
1282                 /* Get memory for block write handler */
1283                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1284                 if (retval != ERROR_OK)
1285                 {
1286                         LOG_WARNING("No working area available, can't do block memory writes");
1287                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1288                 };
1289
1290                 /* write algorithm code to working area */
1291                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1292                 if (retval != ERROR_OK)
1293                 {
1294                         LOG_ERROR("Unable to write block write code to target");
1295                         goto cleanup;
1296                 }
1297         }
1298
1299         /* Get a workspace buffer for the data to flash starting with 32k size.
1300            Half size until buffer would be smaller 256 Bytem then fail back */
1301         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1302         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1303         {
1304                 buffer_size /= 2;
1305                 if (buffer_size <= 256)
1306                 {
1307                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1308                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1309                         goto cleanup;
1310                 }
1311         };
1312
1313         /* setup algo registers */
1314         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1315         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1316         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1317         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1318         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1319         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1320         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1321
1322         /* prepare command and status register patterns */
1323         write_command_val = cfi_command_val(bank, 0x40);
1324         busy_pattern_val  = cfi_command_val(bank, 0x80);
1325         error_pattern_val = cfi_command_val(bank, 0x7e);
1326
1327         LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1328
1329         /* Programming main loop */
1330         while (count > 0)
1331         {
1332                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1333                 uint32_t wsm_error;
1334
1335                 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1336                 {
1337                         goto cleanup;
1338                 }
1339
1340                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1341                 buf_set_u32(reg_params[1].value, 0, 32, address);
1342                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1343
1344                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1345                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1346                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1347
1348                 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1349
1350                 /* Execute algorithm, assume breakpoint for last instruction */
1351                 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1352                         cfi_info->write_algorithm->address,
1353                         cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1354                         10000, /* 10s should be enough for max. 32k of data */
1355                         &armv4_5_info);
1356
1357                 /* On failure try a fall back to direct word writes */
1358                 if (retval != ERROR_OK)
1359                 {
1360                         cfi_intel_clear_status_register(bank);
1361                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1362                         retval = ERROR_FLASH_OPERATION_FAILED;
1363                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1364                         /* FIXME To allow fall back or recovery, we must save the actual status
1365                            somewhere, so that a higher level code can start recovery. */
1366                         goto cleanup;
1367                 }
1368
1369                 /* Check return value from algo code */
1370                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1371                 if (wsm_error)
1372                 {
1373                         /* read status register (outputs debug inforation) */
1374                         uint8_t status;
1375                         cfi_intel_wait_status_busy(bank, 100, &status);
1376                         cfi_intel_clear_status_register(bank);
1377                         retval = ERROR_FLASH_OPERATION_FAILED;
1378                         goto cleanup;
1379                 }
1380
1381                 buffer += thisrun_count;
1382                 address += thisrun_count;
1383                 count -= thisrun_count;
1384
1385                 keep_alive();
1386         }
1387
1388         /* free up resources */
1389 cleanup:
1390         if (source)
1391                 target_free_working_area(target, source);
1392
1393         if (cfi_info->write_algorithm)
1394         {
1395                 target_free_working_area(target, cfi_info->write_algorithm);
1396                 cfi_info->write_algorithm = NULL;
1397         }
1398
1399         destroy_reg_param(&reg_params[0]);
1400         destroy_reg_param(&reg_params[1]);
1401         destroy_reg_param(&reg_params[2]);
1402         destroy_reg_param(&reg_params[3]);
1403         destroy_reg_param(&reg_params[4]);
1404         destroy_reg_param(&reg_params[5]);
1405         destroy_reg_param(&reg_params[6]);
1406
1407         return retval;
1408 }
1409
1410 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1411 {
1412         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1413         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1414         struct target *target = bank->target;
1415         struct reg_param reg_params[10];
1416         struct arm_algorithm armv4_5_info;
1417         struct working_area *source;
1418         uint32_t buffer_size = 32768;
1419         uint32_t status;
1420         int retval = ERROR_OK;
1421
1422         /* input parameters - */
1423         /*      R0 = source address */
1424         /*      R1 = destination address */
1425         /*      R2 = number of writes */
1426         /*      R3 = flash write command */
1427         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1428         /* output parameters - */
1429         /*      R5 = 0x80 ok 0x00 bad */
1430         /* temp registers - */
1431         /*      R6 = value read from flash to test status */
1432         /*      R7 = holding register */
1433         /* unlock registers - */
1434         /*  R8 = unlock1_addr */
1435         /*  R9 = unlock1_cmd */
1436         /*  R10 = unlock2_addr */
1437         /*  R11 = unlock2_cmd */
1438
1439         static const uint32_t word_32_code[] = {
1440                                                 /* 00008100 <sp_32_code>:               */
1441                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1442                 0xe5889000,     /* str  r9, [r8]                                */
1443                 0xe58ab000,     /* str  r11, [r10]                              */
1444                 0xe5883000,     /* str  r3, [r8]                                */
1445                 0xe5815000,     /* str  r5, [r1]                                */
1446                 0xe1a00000,     /* nop                                                  */
1447                                                 /*                                                              */
1448                                                 /* 00008110 <sp_32_busy>:               */
1449                 0xe5916000,     /* ldr  r6, [r1]                                */
1450                 0xe0257006,     /* eor  r7, r5, r6                              */
1451                 0xe0147007,     /* ands r7, r4, r7                              */
1452                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1453                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1454                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1455                 0xe5916000,     /* ldr  r6, [r1]                                */
1456                 0xe0257006,     /* eor  r7, r5, r6                              */
1457                 0xe0147007,     /* ands r7, r4, r7                              */
1458                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1459                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1460                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1461                                                 /*                                                              */
1462                                 /* 00008140 <sp_32_cont>:                               */
1463                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1464                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1465                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1466                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1467                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1468                                                 /*                                                              */
1469                                                 /* 00008154 <sp_32_done>:               */
1470                 0xeafffffe              /* b    8154 <sp_32_done>               */
1471                 };
1472
1473                 static const uint32_t word_16_code[] = {
1474                                 /* 00008158 <sp_16_code>:              */
1475                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1476                 0xe1c890b0,     /* strh r9, [r8]                                */
1477                 0xe1cab0b0,     /* strh r11, [r10]                              */
1478                 0xe1c830b0,     /* strh r3, [r8]                                */
1479                 0xe1c150b0,     /* strh r5, [r1]                       */
1480                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1481                                 /*                                     */
1482                                 /* 00008168 <sp_16_busy>:              */
1483                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1484                 0xe0257006,     /* eor  r7, r5, r6                     */
1485                 0xe0147007,     /* ands r7, r4, r7                     */
1486                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1487                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1488                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1489                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1490                 0xe0257006,     /* eor  r7, r5, r6                     */
1491                 0xe0147007,     /* ands r7, r4, r7                     */
1492                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1493                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1494                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1495                                 /*                                     */
1496                                 /* 00008198 <sp_16_cont>:              */
1497                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1498                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1499                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1500                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1501                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1502                                 /*                                     */
1503                                 /* 000081ac <sp_16_done>:              */
1504                 0xeafffffe      /* b    81ac <sp_16_done>              */
1505                 };
1506
1507                 static const uint32_t word_16_code_dq7only[] = {
1508                                 /* <sp_16_code>:                       */
1509                 0xe0d050b2,     /* ldrh r5, [r0], #2                   */
1510                 0xe1c890b0,     /* strh r9, [r8]                       */
1511                 0xe1cab0b0,     /* strh r11, [r10]                              */
1512                 0xe1c830b0,     /* strh r3, [r8]                                */
1513                 0xe1c150b0,     /* strh r5, [r1]                       */
1514                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1515                                 /*                                     */
1516                                 /* <sp_16_busy>:                       */
1517                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1518                 0xe0257006,     /* eor  r7, r5, r6                     */
1519                 0xe2177080,     /* ands r7, #0x80                      */
1520                 0x1afffffb,     /* bne  8168 <sp_16_busy>              */
1521                                 /*                                     */
1522                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1523                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1524                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1525                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1526                 0xeafffff0,     /* b    8158 <sp_16_code>              */
1527                                 /*                                     */
1528                                 /* 000081ac <sp_16_done>:              */
1529                 0xeafffffe      /* b    81ac <sp_16_done>              */
1530                 };
1531
1532                 static const uint32_t word_8_code[] = {
1533                                 /* 000081b0 <sp_16_code_end>:          */
1534                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1535                 0xe5c89000,     /* strb r9, [r8]                                */
1536                 0xe5cab000,     /* strb r11, [r10]                              */
1537                 0xe5c83000,     /* strb r3, [r8]                                */
1538                 0xe5c15000,     /* strb r5, [r1]                       */
1539                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1540                                 /*                                     */
1541                                 /* 000081c0 <sp_8_busy>:               */
1542                 0xe5d16000,     /* ldrb r6, [r1]                       */
1543                 0xe0257006,     /* eor  r7, r5, r6                     */
1544                 0xe0147007,     /* ands r7, r4, r7                     */
1545                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1546                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1547                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1548                 0xe5d16000,     /* ldrb r6, [r1]                       */
1549                 0xe0257006,     /* eor  r7, r5, r6                     */
1550                 0xe0147007,     /* ands r7, r4, r7                     */
1551                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1552                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1553                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1554                                 /*                                     */
1555                                 /* 000081f0 <sp_8_cont>:               */
1556                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1557                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1558                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1559                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1560                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1561                                 /*                                     */
1562                                 /* 00008204 <sp_8_done>:               */
1563                 0xeafffffe      /* b    8204 <sp_8_done>               */
1564         };
1565
1566         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1567         armv4_5_info.core_mode = ARM_MODE_SVC;
1568         armv4_5_info.core_state = ARM_STATE_ARM;
1569
1570         int target_code_size;
1571         const uint32_t *target_code_src;
1572
1573         switch (bank->bus_width)
1574         {
1575         case 1 :
1576                 target_code_src = word_8_code;
1577                 target_code_size = sizeof(word_8_code);
1578                 break;
1579         case 2 :
1580                 /* Check for DQ5 support */
1581                 if( cfi_info->status_poll_mask & (1 << 5) )
1582                 {
1583                         target_code_src = word_16_code;
1584                         target_code_size = sizeof(word_16_code);
1585                 }
1586                 else
1587                 {
1588                         /* No DQ5 support. Use DQ7 DATA# polling only. */
1589                         target_code_src = word_16_code_dq7only;
1590                         target_code_size = sizeof(word_16_code_dq7only);
1591                 }
1592                 break;
1593         case 4 :
1594                 target_code_src = word_32_code;
1595                 target_code_size = sizeof(word_32_code);
1596                 break;
1597         default:
1598                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1599                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1600         }
1601
1602         /* flash write code */
1603         if (!cfi_info->write_algorithm)
1604         {
1605                 uint8_t *target_code;
1606
1607                 /* convert bus-width dependent algorithm code to correct endiannes */
1608                 target_code = malloc(target_code_size);
1609                 if (target_code == NULL)
1610                 {
1611                         LOG_ERROR("Out of memory");
1612                         return ERROR_FAIL;
1613                 }
1614                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1615
1616                 /* allocate working area */
1617                 retval = target_alloc_working_area(target, target_code_size,
1618                                 &cfi_info->write_algorithm);
1619                 if (retval != ERROR_OK)
1620                 {
1621                         free(target_code);
1622                         return retval;
1623                 }
1624
1625                 /* write algorithm code to working area */
1626                 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1627                                     target_code_size, target_code)) != ERROR_OK)
1628                 {
1629                         free(target_code);
1630                         return retval;
1631                 }
1632
1633                 free(target_code);
1634         }
1635         /* the following code still assumes target code is fixed 24*4 bytes */
1636
1637         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1638         {
1639                 buffer_size /= 2;
1640                 if (buffer_size <= 256)
1641                 {
1642                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1643                         if (cfi_info->write_algorithm)
1644                                 target_free_working_area(target, cfi_info->write_algorithm);
1645
1646                         LOG_WARNING("not enough working area available, can't do block memory writes");
1647                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1648                 }
1649         };
1650
1651         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1652         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1653         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1654         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1655         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1656         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1657         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1658         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1659         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1660         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1661
1662         while (count > 0)
1663         {
1664                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1665
1666                 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1667                 if (retval != ERROR_OK)
1668                 {
1669                         break;
1670                 }
1671
1672                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1673                 buf_set_u32(reg_params[1].value, 0, 32, address);
1674                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1675                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1676                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1677                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1678                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1679                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1680                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1681
1682                 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1683                                                      cfi_info->write_algorithm->address,
1684                                                      cfi_info->write_algorithm->address + ((target_code_size) - 4),
1685                                                      10000, &armv4_5_info);
1686                 if (retval != ERROR_OK)
1687                 {
1688                         break;
1689                 }
1690
1691                 status = buf_get_u32(reg_params[5].value, 0, 32);
1692                 if (status != 0x80)
1693                 {
1694                         LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
1695                         retval = ERROR_FLASH_OPERATION_FAILED;
1696                         break;
1697                 }
1698
1699                 buffer += thisrun_count;
1700                 address += thisrun_count;
1701                 count -= thisrun_count;
1702         }
1703
1704         target_free_all_working_areas(target);
1705
1706         destroy_reg_param(&reg_params[0]);
1707         destroy_reg_param(&reg_params[1]);
1708         destroy_reg_param(&reg_params[2]);
1709         destroy_reg_param(&reg_params[3]);
1710         destroy_reg_param(&reg_params[4]);
1711         destroy_reg_param(&reg_params[5]);
1712         destroy_reg_param(&reg_params[6]);
1713         destroy_reg_param(&reg_params[7]);
1714         destroy_reg_param(&reg_params[8]);
1715         destroy_reg_param(&reg_params[9]);
1716
1717         return retval;
1718 }
1719
1720 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1721 {
1722         int retval;
1723         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1724         struct target *target = bank->target;
1725
1726         cfi_intel_clear_status_register(bank);
1727         if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1728         {
1729                 return retval;
1730         }
1731
1732         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1733         {
1734                 return retval;
1735         }
1736
1737         uint8_t status;
1738         retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max), &status);
1739         if (retval != 0x80)
1740         {
1741                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1742                 {
1743                         return retval;
1744                 }
1745
1746                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1747                 return ERROR_FLASH_OPERATION_FAILED;
1748         }
1749
1750         return ERROR_OK;
1751 }
1752
1753 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1754 {
1755         int retval;
1756         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1757         struct target *target = bank->target;
1758
1759         /* Calculate buffer size and boundary mask */
1760         /* buffersize is (buffer size per chip) * (number of chips) */
1761         /* bufferwsize is buffersize in words */
1762         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1763         uint32_t buffermask = buffersize-1;
1764         uint32_t bufferwsize = buffersize / bank->bus_width;
1765
1766         /* Check for valid range */
1767         if (address & buffermask)
1768         {
1769                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1770                           bank->base, address, cfi_info->max_buf_write_size);
1771                 return ERROR_FLASH_OPERATION_FAILED;
1772         }
1773
1774         /* Check for valid size */
1775         if (wordcount > bufferwsize)
1776         {
1777                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1778                 return ERROR_FLASH_OPERATION_FAILED;
1779         }
1780
1781         /* Write to flash buffer */
1782         cfi_intel_clear_status_register(bank);
1783
1784         /* Initiate buffer operation _*/
1785         if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1786         {
1787                 return retval;
1788         }
1789         uint8_t status;
1790         retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max), &status);
1791         if (retval != ERROR_OK)
1792                 return retval;
1793         if (status != 0x80)
1794         {
1795                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1796                 {
1797                         return retval;
1798                 }
1799
1800                 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1801                 return ERROR_FLASH_OPERATION_FAILED;
1802         }
1803
1804         /* Write buffer wordcount-1 and data words */
1805         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1806         {
1807                 return retval;
1808         }
1809
1810         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1811         {
1812                 return retval;
1813         }
1814
1815         /* Commit write operation */
1816         if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1817         {
1818                 return retval;
1819         }
1820
1821         retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max), &status);
1822         if (retval != ERROR_OK)
1823                 return retval;
1824
1825         if (status != 0x80)
1826         {
1827                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1828                 {
1829                         return retval;
1830                 }
1831
1832                 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1833                 return ERROR_FLASH_OPERATION_FAILED;
1834         }
1835
1836         return ERROR_OK;
1837 }
1838
1839 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1840 {
1841         int retval;
1842         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1843         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1844         struct target *target = bank->target;
1845
1846         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1847         {
1848                 return retval;
1849         }
1850
1851         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1852         {
1853                 return retval;
1854         }
1855
1856         if ((retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1857         {
1858                 return retval;
1859         }
1860
1861         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1862         {
1863                 return retval;
1864         }
1865
1866         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1867         {
1868                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1869                 {
1870                         return retval;
1871                 }
1872
1873                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1874                 return ERROR_FLASH_OPERATION_FAILED;
1875         }
1876
1877         return ERROR_OK;
1878 }
1879
1880 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1881 {
1882         int retval;
1883         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1884         struct target *target = bank->target;
1885         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1886
1887         /* Calculate buffer size and boundary mask */
1888         /* buffersize is (buffer size per chip) * (number of chips) */
1889         /* bufferwsize is buffersize in words */
1890         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1891         uint32_t buffermask = buffersize-1;
1892         uint32_t bufferwsize = buffersize / bank->bus_width;
1893
1894         /* Check for valid range */
1895         if (address & buffermask)
1896         {
1897                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1898                 return ERROR_FLASH_OPERATION_FAILED;
1899         }
1900
1901         /* Check for valid size */
1902         if (wordcount > bufferwsize)
1903         {
1904                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1905                 return ERROR_FLASH_OPERATION_FAILED;
1906         }
1907
1908         // Unlock
1909         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1910         {
1911                 return retval;
1912         }
1913
1914         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1915         {
1916                 return retval;
1917         }
1918
1919         // Buffer load command
1920         if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1921         {
1922                 return retval;
1923         }
1924
1925         /* Write buffer wordcount-1 and data words */
1926         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1927         {
1928                 return retval;
1929         }
1930
1931         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1932         {
1933                 return retval;
1934         }
1935
1936         /* Commit write operation */
1937         if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
1938         {
1939                 return retval;
1940         }
1941
1942         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1943         {
1944                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1945                 {
1946                         return retval;
1947                 }
1948
1949                 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1950                 return ERROR_FLASH_OPERATION_FAILED;
1951         }
1952
1953         return ERROR_OK;
1954 }
1955
1956 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1957 {
1958         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1959
1960         switch (cfi_info->pri_id)
1961         {
1962                 case 1:
1963                 case 3:
1964                         return cfi_intel_write_word(bank, word, address);
1965                         break;
1966                 case 2:
1967                         return cfi_spansion_write_word(bank, word, address);
1968                         break;
1969                 default:
1970                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1971                         break;
1972         }
1973
1974         return ERROR_FLASH_OPERATION_FAILED;
1975 }
1976
1977 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1978 {
1979         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1980
1981         switch (cfi_info->pri_id)
1982         {
1983                 case 1:
1984                 case 3:
1985                         return cfi_intel_write_words(bank, word, wordcount, address);
1986                         break;
1987                 case 2:
1988                         return cfi_spansion_write_words(bank, word, wordcount, address);
1989                         break;
1990                 default:
1991                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1992                         break;
1993         }
1994
1995         return ERROR_FLASH_OPERATION_FAILED;
1996 }
1997
1998 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1999 {
2000         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2001         struct target *target = bank->target;
2002         uint32_t address = bank->base + offset;
2003         uint32_t read_p;
2004         int align;      /* number of unaligned bytes */
2005         uint8_t current_word[CFI_MAX_BUS_WIDTH];
2006         int i;
2007         int retval;
2008
2009         LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2010                 (int)count, (unsigned)offset);
2011
2012         if (bank->target->state != TARGET_HALTED)
2013         {
2014                 LOG_ERROR("Target not halted");
2015                 return ERROR_TARGET_NOT_HALTED;
2016         }
2017
2018         if (offset + count > bank->size)
2019                 return ERROR_FLASH_DST_OUT_OF_BANK;
2020
2021         if (cfi_info->qry[0] != 'Q')
2022                 return ERROR_FLASH_BANK_NOT_PROBED;
2023
2024         /* start at the first byte of the first word (bus_width size) */
2025         read_p = address & ~(bank->bus_width - 1);
2026         if ((align = address - read_p) != 0)
2027         {
2028                 LOG_INFO("Fixup %d unaligned read head bytes", align);
2029
2030                 /* read a complete word from flash */
2031                 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2032                         return retval;
2033
2034                 /* take only bytes we need */
2035                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2036                         *buffer++ = current_word[i];
2037
2038                 read_p += bank->bus_width;
2039         }
2040
2041         align = count / bank->bus_width;
2042         if (align)
2043         {
2044                 if ((retval = target_read_memory(target, read_p, bank->bus_width, align, buffer)) != ERROR_OK)
2045                         return retval;
2046
2047                 read_p += align * bank->bus_width;
2048                 buffer += align * bank->bus_width;
2049                 count -= align * bank->bus_width;
2050         }
2051
2052         if (count)
2053         {
2054                 LOG_INFO("Fixup %d unaligned read tail bytes", count);
2055
2056                 /* read a complete word from flash */
2057                 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2058                         return retval;
2059
2060                 /* take only bytes we need */
2061                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2062                         *buffer++ = current_word[i];
2063         }
2064
2065         return ERROR_OK;
2066 }
2067
2068 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2069 {
2070         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2071         struct target *target = bank->target;
2072         uint32_t address = bank->base + offset; /* address of first byte to be programmed */
2073         uint32_t write_p;
2074         int align;      /* number of unaligned bytes */
2075         int blk_count; /* number of bus_width bytes for block copy */
2076         uint8_t current_word[CFI_MAX_BUS_WIDTH * 4];    /* word (bus_width size) currently being programmed */
2077         int i;
2078         int retval;
2079
2080         if (bank->target->state != TARGET_HALTED)
2081         {
2082                 LOG_ERROR("Target not halted");
2083                 return ERROR_TARGET_NOT_HALTED;
2084         }
2085
2086         if (offset + count > bank->size)
2087                 return ERROR_FLASH_DST_OUT_OF_BANK;
2088
2089         if (cfi_info->qry[0] != 'Q')
2090                 return ERROR_FLASH_BANK_NOT_PROBED;
2091
2092         /* start at the first byte of the first word (bus_width size) */
2093         write_p = address & ~(bank->bus_width - 1);
2094         if ((align = address - write_p) != 0)
2095         {
2096                 LOG_INFO("Fixup %d unaligned head bytes", align);
2097
2098                 /* read a complete word from flash */
2099                 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2100                         return retval;
2101
2102                 /* replace only bytes that must be written */
2103                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2104                         current_word[i] = *buffer++;
2105
2106                 retval = cfi_write_word(bank, current_word, write_p);
2107                 if (retval != ERROR_OK)
2108                         return retval;
2109                 write_p += bank->bus_width;
2110         }
2111
2112         /* handle blocks of bus_size aligned bytes */
2113         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
2114         switch (cfi_info->pri_id)
2115         {
2116                 /* try block writes (fails without working area) */
2117                 case 1:
2118                 case 3:
2119                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
2120                         break;
2121                 case 2:
2122                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
2123                         break;
2124                 default:
2125                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2126                         retval = ERROR_FLASH_OPERATION_FAILED;
2127                         break;
2128         }
2129         if (retval == ERROR_OK)
2130         {
2131                 /* Increment pointers and decrease count on succesful block write */
2132                 buffer += blk_count;
2133                 write_p += blk_count;
2134                 count -= blk_count;
2135         }
2136         else
2137         {
2138                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
2139                 {
2140                         /* Calculate buffer size and boundary mask */
2141                         /* buffersize is (buffer size per chip) * (number of chips) */
2142                         /* bufferwsize is buffersize in words */
2143                         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2144                         uint32_t buffermask = buffersize-1;
2145                         uint32_t bufferwsize = buffersize / bank->bus_width;
2146
2147                         /* fall back to memory writes */
2148                         while (count >= (uint32_t)bank->bus_width)
2149                         {
2150                                 int fallback;
2151                                 if ((write_p & 0xff) == 0)
2152                                 {
2153                                         LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
2154                                 }
2155                                 fallback = 1;
2156                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
2157                                 {
2158                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2159                                         if (retval == ERROR_OK)
2160                                         {
2161                                                 buffer += buffersize;
2162                                                 write_p += buffersize;
2163                                                 count -= buffersize;
2164                                                 fallback = 0;
2165                                         }
2166                                 }
2167                                 /* try the slow way? */
2168                                 if (fallback)
2169                                 {
2170                                         for (i = 0; i < bank->bus_width; i++)
2171                                                 current_word[i] = *buffer++;
2172
2173                                         retval = cfi_write_word(bank, current_word, write_p);
2174                                         if (retval != ERROR_OK)
2175                                                 return retval;
2176
2177                                         write_p += bank->bus_width;
2178                                         count -= bank->bus_width;
2179                                 }
2180                         }
2181                 }
2182                 else
2183                         return retval;
2184         }
2185
2186         /* return to read array mode, so we can read from flash again for padding */
2187         if ((retval = cfi_reset(bank)) != ERROR_OK)
2188         {
2189                 return retval;
2190         }
2191
2192         /* handle unaligned tail bytes */
2193         if (count > 0)
2194         {
2195                 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2196
2197                 /* read a complete word from flash */
2198                 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2199                         return retval;
2200
2201                 /* replace only bytes that must be written */
2202                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2203                         current_word[i] = *buffer++;
2204
2205                 retval = cfi_write_word(bank, current_word, write_p);
2206                 if (retval != ERROR_OK)
2207                         return retval;
2208         }
2209
2210         /* return to read array mode */
2211         return cfi_reset(bank);
2212 }
2213
2214 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
2215 {
2216         (void) param;
2217         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2218         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2219
2220         pri_ext->_reversed_geometry = 1;
2221 }
2222
2223 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2224 {
2225         int i;
2226         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2227         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2228         (void) param;
2229
2230         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2231         {
2232                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2233
2234                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2235                 {
2236                         int j = (cfi_info->num_erase_regions - 1) - i;
2237                         uint32_t swap;
2238
2239                         swap = cfi_info->erase_region_info[i];
2240                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2241                         cfi_info->erase_region_info[j] = swap;
2242                 }
2243         }
2244 }
2245
2246 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2247 {
2248         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2249         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2250         struct cfi_unlock_addresses *unlock_addresses = param;
2251
2252         pri_ext->_unlock1 = unlock_addresses->unlock1;
2253         pri_ext->_unlock2 = unlock_addresses->unlock2;
2254 }
2255
2256
2257 static int cfi_query_string(struct flash_bank *bank, int address)
2258 {
2259         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2260         int retval;
2261
2262         if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2263         {
2264                 return retval;
2265         }
2266
2267         retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
2268         if (retval != ERROR_OK)
2269                 return retval;
2270         retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
2271         if (retval != ERROR_OK)
2272                 return retval;
2273         retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
2274         if (retval != ERROR_OK)
2275                 return retval;
2276
2277         LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2278
2279         if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2280         {
2281                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2282                 {
2283                         return retval;
2284                 }
2285                 LOG_ERROR("Could not probe bank: no QRY");
2286                 return ERROR_FLASH_BANK_INVALID;
2287         }
2288
2289         return ERROR_OK;
2290 }
2291
2292 static int cfi_probe(struct flash_bank *bank)
2293 {
2294         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2295         struct target *target = bank->target;
2296         int num_sectors = 0;
2297         int i;
2298         int sector = 0;
2299         uint32_t unlock1 = 0x555;
2300         uint32_t unlock2 = 0x2aa;
2301         int retval;
2302         uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2303
2304         if (bank->target->state != TARGET_HALTED)
2305         {
2306                 LOG_ERROR("Target not halted");
2307                 return ERROR_TARGET_NOT_HALTED;
2308         }
2309
2310         cfi_info->probed = 0;
2311         if (bank->sectors)
2312         {
2313                 free(bank->sectors);
2314                 bank->sectors = NULL;
2315         }
2316         if(cfi_info->erase_region_info)
2317         {
2318                 free(cfi_info->erase_region_info);
2319                 cfi_info->erase_region_info = NULL;
2320         }
2321
2322         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2323          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2324          */
2325         if (cfi_info->jedec_probe)
2326         {
2327                 unlock1 = 0x5555;
2328                 unlock2 = 0x2aaa;
2329         }
2330
2331         /* switch to read identifier codes mode ("AUTOSELECT") */
2332         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2333         {
2334                 return retval;
2335         }
2336         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2337         {
2338                 return retval;
2339         }
2340         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2341         {
2342                 return retval;
2343         }
2344
2345         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, value_buf0)) != ERROR_OK)
2346         {
2347                 return retval;
2348         }
2349         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01), bank->bus_width, 1, value_buf1)) != ERROR_OK)
2350         {
2351                 return retval;
2352         }
2353         switch (bank->chip_width) {
2354                 case 1:
2355                         cfi_info->manufacturer = *value_buf0;
2356                         cfi_info->device_id = *value_buf1;
2357                         break;
2358                 case 2:
2359                         cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2360                         cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2361                         break;
2362                 case 4:
2363                         cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2364                         cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2365                         break;
2366                 default:
2367                         LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
2368                         return ERROR_FLASH_OPERATION_FAILED;
2369         }
2370
2371         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2372         /* switch back to read array mode */
2373         if ((retval = cfi_reset(bank)) != ERROR_OK)
2374         {
2375                 return retval;
2376         }
2377
2378         /* check device/manufacturer ID for known non-CFI flashes. */
2379         cfi_fixup_non_cfi(bank);
2380
2381         /* query only if this is a CFI compatible flash,
2382          * otherwise the relevant info has already been filled in
2383          */
2384         if (cfi_info->not_cfi == 0)
2385         {
2386                 int retval;
2387
2388                 /* enter CFI query mode
2389                  * according to JEDEC Standard No. 68.01,
2390                  * a single bus sequence with address = 0x55, data = 0x98 should put
2391                  * the device into CFI query mode.
2392                  *
2393                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2394                  */
2395
2396                 retval = cfi_query_string(bank, 0x55);
2397                 if (retval != ERROR_OK)
2398                 {
2399                         /*
2400                          * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2401                          * be harmless enough:
2402                          *
2403                          * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2404                          */
2405                         LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2406                         retval = cfi_query_string(bank, 0x555);
2407                 }
2408                 if (retval != ERROR_OK)
2409                         return retval;
2410
2411                 retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
2412                 if (retval != ERROR_OK)
2413                         return retval;
2414                 retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
2415                 if (retval != ERROR_OK)
2416                         return retval;
2417                 retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
2418                 if (retval != ERROR_OK)
2419                         return retval;
2420                 retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
2421                 if (retval != ERROR_OK)
2422                         return retval;
2423
2424                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2425
2426                 retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
2427                 if (retval != ERROR_OK)
2428                         return retval;
2429                 retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
2430                 if (retval != ERROR_OK)
2431                         return retval;
2432                 retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
2433                 if (retval != ERROR_OK)
2434                         return retval;
2435                 retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
2436                 if (retval != ERROR_OK)
2437                         return retval;
2438                 retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
2439                 if (retval != ERROR_OK)
2440                         return retval;
2441                 retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
2442                 if (retval != ERROR_OK)
2443                         return retval;
2444                 retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
2445                 if (retval != ERROR_OK)
2446                         return retval;
2447                 retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
2448                 if (retval != ERROR_OK)
2449                         return retval;
2450                 retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
2451                 if (retval != ERROR_OK)
2452                         return retval;
2453                 retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
2454                 if (retval != ERROR_OK)
2455                         return retval;
2456                 retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
2457                 if (retval != ERROR_OK)
2458                         return retval;
2459                 retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
2460                 if (retval != ERROR_OK)
2461                         return retval;
2462
2463                 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2464                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2465                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2466                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2467                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2468                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2469                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2470                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2471                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2472                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2473                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2474
2475                 uint8_t data;
2476                 retval = 1 << cfi_query_u8(bank, 0, 0x27, &data);
2477                 if (retval != ERROR_OK)
2478                         return retval;
2479                 cfi_info->dev_size = data;
2480
2481                 retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
2482                 if (retval != ERROR_OK)
2483                         return retval;
2484                 retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
2485                 if (retval != ERROR_OK)
2486                         return retval;
2487                 retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
2488                 if (retval != ERROR_OK)
2489                         return retval;
2490
2491                 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2492
2493                 if (cfi_info->num_erase_regions)
2494                 {
2495                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2496                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2497                         {
2498                                 retval = cfi_query_u32(bank, 0, 0x2d + (4 * i), &cfi_info->erase_region_info[i]);
2499                                 if (retval != ERROR_OK)
2500                                         return retval;
2501                                 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2502                                           i,
2503                                           (cfi_info->erase_region_info[i] & 0xffff) + 1,
2504                                           (cfi_info->erase_region_info[i] >> 16) * 256);
2505                         }
2506                 }
2507                 else
2508                 {
2509                         cfi_info->erase_region_info = NULL;
2510                 }
2511
2512                 /* We need to read the primary algorithm extended query table before calculating
2513                  * the sector layout to be able to apply fixups
2514                  */
2515                 switch (cfi_info->pri_id)
2516                 {
2517                         /* Intel command set (standard and extended) */
2518                         case 0x0001:
2519                         case 0x0003:
2520                                 cfi_read_intel_pri_ext(bank);
2521                                 break;
2522                         /* AMD/Spansion, Atmel, ... command set */
2523                         case 0x0002:
2524                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2525                                 cfi_read_0002_pri_ext(bank);
2526                                 break;
2527                         default:
2528                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2529                                 break;
2530                 }
2531
2532                 /* return to read array mode
2533                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2534                  */
2535                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2536                 {
2537                         return retval;
2538                 }
2539         } /* end CFI case */
2540
2541         /* apply fixups depending on the primary command set */
2542         switch (cfi_info->pri_id)
2543         {
2544                 /* Intel command set (standard and extended) */
2545                 case 0x0001:
2546                 case 0x0003:
2547                         cfi_fixup(bank, cfi_0001_fixups);
2548                         break;
2549                 /* AMD/Spansion, Atmel, ... command set */
2550                 case 0x0002:
2551                         cfi_fixup(bank, cfi_0002_fixups);
2552                         break;
2553                 default:
2554                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2555                         break;
2556         }
2557
2558         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2559         {
2560                 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2561         }
2562
2563         if (cfi_info->num_erase_regions == 0)
2564         {
2565                 /* a device might have only one erase block, spanning the whole device */
2566                 bank->num_sectors = 1;
2567                 bank->sectors = malloc(sizeof(struct flash_sector));
2568
2569                 bank->sectors[sector].offset = 0x0;
2570                 bank->sectors[sector].size = bank->size;
2571                 bank->sectors[sector].is_erased = -1;
2572                 bank->sectors[sector].is_protected = -1;
2573         }
2574         else
2575         {
2576                 uint32_t offset = 0;
2577
2578                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2579                 {
2580                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2581                 }
2582
2583                 bank->num_sectors = num_sectors;
2584                 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2585
2586                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2587                 {
2588                         uint32_t j;
2589                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2590                         {
2591                                 bank->sectors[sector].offset = offset;
2592                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2593                                 offset += bank->sectors[sector].size;
2594                                 bank->sectors[sector].is_erased = -1;
2595                                 bank->sectors[sector].is_protected = -1;
2596                                 sector++;
2597                         }
2598                 }
2599                 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2600                 {
2601                         LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2602                                 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2603                 }
2604         }
2605
2606         cfi_info->probed = 1;
2607
2608         return ERROR_OK;
2609 }
2610
2611 static int cfi_auto_probe(struct flash_bank *bank)
2612 {
2613         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2614         if (cfi_info->probed)
2615                 return ERROR_OK;
2616         return cfi_probe(bank);
2617 }
2618
2619 static int cfi_intel_protect_check(struct flash_bank *bank)
2620 {
2621         int retval;
2622         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2623         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2624         int i;
2625
2626         /* check if block lock bits are supported on this device */
2627         if (!(pri_ext->blk_status_reg_mask & 0x1))
2628                 return ERROR_FLASH_OPERATION_FAILED;
2629
2630         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2631         {
2632                 return retval;
2633         }
2634
2635         for (i = 0; i < bank->num_sectors; i++)
2636         {
2637                 uint8_t block_status;
2638                 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2639                 if (retval != ERROR_OK)
2640                         return retval;
2641
2642                 if (block_status & 1)
2643                         bank->sectors[i].is_protected = 1;
2644                 else
2645                         bank->sectors[i].is_protected = 0;
2646         }
2647
2648         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2649 }
2650
2651 static int cfi_spansion_protect_check(struct flash_bank *bank)
2652 {
2653         int retval;
2654         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2655         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2656         int i;
2657
2658         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2659         {
2660                 return retval;
2661         }
2662
2663         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2664         {
2665                 return retval;
2666         }
2667
2668         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2669         {
2670                 return retval;
2671         }
2672
2673         for (i = 0; i < bank->num_sectors; i++)
2674         {
2675                 uint8_t block_status;
2676                 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2677                 if (retval != ERROR_OK)
2678                         return retval;
2679
2680                 if (block_status & 1)
2681                         bank->sectors[i].is_protected = 1;
2682                 else
2683                         bank->sectors[i].is_protected = 0;
2684         }
2685
2686         return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2687 }
2688
2689 static int cfi_protect_check(struct flash_bank *bank)
2690 {
2691         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2692
2693         if (bank->target->state != TARGET_HALTED)
2694         {
2695                 LOG_ERROR("Target not halted");
2696                 return ERROR_TARGET_NOT_HALTED;
2697         }
2698
2699         if (cfi_info->qry[0] != 'Q')
2700                 return ERROR_FLASH_BANK_NOT_PROBED;
2701
2702         switch (cfi_info->pri_id)
2703         {
2704                 case 1:
2705                 case 3:
2706                         return cfi_intel_protect_check(bank);
2707                         break;
2708                 case 2:
2709                         return cfi_spansion_protect_check(bank);
2710                         break;
2711                 default:
2712                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2713                         break;
2714         }
2715
2716         return ERROR_OK;
2717 }
2718
2719 static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2720 {
2721         int printed;
2722         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2723
2724         if (cfi_info->qry[0] == 0xff)
2725         {
2726                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2727                 return ERROR_OK;
2728         }
2729
2730         if (cfi_info->not_cfi == 0)
2731                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2732         else
2733                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2734         buf += printed;
2735         buf_size -= printed;
2736
2737         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2738                 cfi_info->manufacturer, cfi_info->device_id);
2739         buf += printed;
2740         buf_size -= printed;
2741
2742         if (cfi_info->not_cfi == 0)
2743         {
2744         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2745         buf += printed;
2746         buf_size -= printed;
2747
2748                 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2749                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2750         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2751         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2752         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2753         buf += printed;
2754         buf_size -= printed;
2755
2756                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2757                                    1 << cfi_info->word_write_timeout_typ,
2758                                    1 << cfi_info->buf_write_timeout_typ,
2759                                    1 << cfi_info->block_erase_timeout_typ,
2760                                    1 << cfi_info->chip_erase_timeout_typ);
2761         buf += printed;
2762         buf_size -= printed;
2763
2764                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2765                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2766                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2767                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2768                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2769         buf += printed;
2770         buf_size -= printed;
2771
2772                 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2773                                    cfi_info->dev_size,
2774                                    cfi_info->interface_desc,
2775                                    1 << cfi_info->max_buf_write_size);
2776         buf += printed;
2777         buf_size -= printed;
2778
2779         switch (cfi_info->pri_id)
2780         {
2781                 case 1:
2782                 case 3:
2783                         cfi_intel_info(bank, buf, buf_size);
2784                         break;
2785                 case 2:
2786                         cfi_spansion_info(bank, buf, buf_size);
2787                         break;
2788                 default:
2789                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2790                         break;
2791         }
2792         }
2793
2794         return ERROR_OK;
2795 }
2796
2797 struct flash_driver cfi_flash = {
2798         .name = "cfi",
2799         .flash_bank_command = cfi_flash_bank_command,
2800         .erase = cfi_erase,
2801         .protect = cfi_protect,
2802         .write = cfi_write,
2803         .read = cfi_read,
2804         .probe = cfi_probe,
2805         .auto_probe = cfi_auto_probe,
2806         /* FIXME: access flash at bus_width size */
2807         .erase_check = default_flash_blank_check,
2808         .protect_check = cfi_protect_check,
2809         .info = cfi_info,
2810 };