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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *   Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com>            *
   7  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "imp.h"
  29 #include "cfi.h"
  30 #include "non_cfi.h"
  31 #include <target/arm.h>
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34
  35
  36 #define CFI_MAX_BUS_WIDTH       4
  37 #define CFI_MAX_CHIP_WIDTH      4
  38
  39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  40 #define CFI_MAX_INTEL_CODESIZE 256
  41
  42 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
  43 {
  44         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  45         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  46 };
  47
  48 /* CFI fixups foward declarations */
  49 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param);
  50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param);
  51 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param);
  52 static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, void *param);
  53
  54 /* fixup after reading cmdset 0002 primary query table */
  55 static const struct cfi_fixup cfi_0002_fixups[] = {
  56         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  57         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  58         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  59         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  60         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  61         {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  62         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
  63         {CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
  64         {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  65         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  66         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  67         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  68         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  69         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  70         {CFI_MFR_ST, 0x227E, cfi_fixup_0002_write_buffer, NULL}, /* M29W128G */
  71         {0, 0, NULL, NULL}
  72 };
  73
  74 /* fixup after reading cmdset 0001 primary query table */
  75 static const struct cfi_fixup cfi_0001_fixups[] = {
  76         {0, 0, NULL, NULL}
  77 };
  78
  79 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
  80 {
  81         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  82         const struct cfi_fixup *f;
  83
  84         for (f = fixups; f->fixup; f++)
  85         {
  86                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
  87                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
  88                 {
  89                         f->fixup(bank, f->param);
  90                 }
  91         }
  92 }
  93
  94 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
  95 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
  96 {
  97         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  98
  99         if (cfi_info->x16_as_x8) offset *= 2;
 100
 101         /* while the sector list isn't built, only accesses to sector 0 work */
 102         if (sector == 0)
 103                 return bank->base + offset * bank->bus_width;
 104         else
 105         {
 106                 if (!bank->sectors)
 107                 {
 108                         LOG_ERROR("BUG: sector list not yet built");
 109                         exit(-1);
 110                 }
 111                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 112         }
 113 }
 114
 115 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
 116 {
 117         int i;
 118
 119         /* clear whole buffer, to ensure bits that exceed the bus_width
 120          * are set to zero
 121          */
 122         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 123                 cmd_buf[i] = 0;
 124
 125         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 126         {
 127                 for (i = bank->bus_width; i > 0; i--)
 128                 {
 129                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 130                 }
 131         }
 132         else
 133         {
 134                 for (i = 1; i <= bank->bus_width; i++)
 135                 {
 136                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 137                 }
 138         }
 139 }
 140
 141 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
 142 {
 143         uint8_t command[CFI_MAX_BUS_WIDTH];
 144
 145         cfi_command(bank, cmd, command);
 146         return target_write_memory(bank->target, address, bank->bus_width, 1, command);
 147 }
 148
 149 /* read unsigned 8-bit value from the bank
 150  * flash banks are expected to be made of similar chips
 151  * the query result should be the same for all
 152  */
 153 static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
 154 {
 155         struct target *target = bank->target;
 156         uint8_t data[CFI_MAX_BUS_WIDTH];
 157
 158         int retval;
 159         retval = target_read_memory(target, flash_address(bank, sector, offset),
 160                         bank->bus_width, 1, data);
 161         if (retval != ERROR_OK)
 162                 return retval;
 163
 164         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 165                 *val = data[0];
 166         else
 167                 *val = data[bank->bus_width - 1];
 168
 169         return ERROR_OK;
 170 }
 171
 172 /* read unsigned 8-bit value from the bank
 173  * in case of a bank made of multiple chips,
 174  * the individual values are ORed
 175  */
 176 static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
 177 {
 178         struct target *target = bank->target;
 179         uint8_t data[CFI_MAX_BUS_WIDTH];
 180         int i;
 181
 182         int retval;
 183         retval = target_read_memory(target, flash_address(bank, sector, offset),
 184                         bank->bus_width, 1, data);
 185         if (retval != ERROR_OK)
 186                 return retval;
 187
 188         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 189         {
 190                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 191                         data[0] |= data[i];
 192
 193                 *val = data[0];
 194         }
 195         else
 196         {
 197                 uint8_t value = 0;
 198                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 199                         value |= data[bank->bus_width - 1 - i];
 200
 201                 *val = value;
 202         }
 203         return ERROR_OK;
 204 }
 205
 206 static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
 207 {
 208         struct target *target = bank->target;
 209         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 210         uint8_t data[CFI_MAX_BUS_WIDTH * 2];
 211         int retval;
 212
 213         if (cfi_info->x16_as_x8)
 214         {
 215                 uint8_t i;
 216                 for (i = 0;i < 2;i++)
 217                 {
 218                         retval = target_read_memory(target, flash_address(bank, sector, offset + i),
 219                                         bank->bus_width, 1, &data[i * bank->bus_width]);
 220                         if (retval != ERROR_OK)
 221                                 return retval;
 222                 }
 223         } else
 224         {
 225                 retval = target_read_memory(target, flash_address(bank, sector, offset),
 226                                 bank->bus_width, 2, data);
 227                 if (retval != ERROR_OK)
 228                         return retval;
 229         }
 230
 231         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 232                 *val = data[0] | data[bank->bus_width] << 8;
 233         else
 234                 *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 235
 236         return ERROR_OK;
 237 }
 238
 239 static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
 240 {
 241         struct target *target = bank->target;
 242         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 243         uint8_t data[CFI_MAX_BUS_WIDTH * 4];
 244         int retval;
 245
 246         if (cfi_info->x16_as_x8)
 247         {
 248                 uint8_t i;
 249                 for (i = 0;i < 4;i++)
 250                 {
 251                         retval = target_read_memory(target, flash_address(bank, sector, offset + i),
 252                                         bank->bus_width, 1, &data[i * bank->bus_width]);
 253                         if (retval != ERROR_OK)
 254                                 return retval;
 255                 }
 256         }
 257         else
 258         {
 259                 retval = target_read_memory(target, flash_address(bank, sector, offset),
 260                                 bank->bus_width, 4, data);
 261                 if (retval != ERROR_OK)
 262                         return retval;
 263         }
 264
 265         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 266                 *val = data[0] | data[bank->bus_width] << 8 |
 267                                 data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 268         else
 269                 *val = data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 270                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 271
 272         return ERROR_OK;
 273 }
 274
 275 static int cfi_reset(struct flash_bank *bank)
 276 {
 277         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 278         int retval = ERROR_OK;
 279
 280         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 281         {
 282                 return retval;
 283         }
 284
 285         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 286         {
 287                 return retval;
 288         }
 289
 290         if (cfi_info->manufacturer == 0x20 &&
 291                         (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
 292         {
 293                 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
 294                  * so we send an extra 0xF0 reset to fix the bug */
 295                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
 296                 {
 297                         return retval;
 298                 }
 299         }
 300
 301         return retval;
 302 }
 303
 304 static void cfi_intel_clear_status_register(struct flash_bank *bank)
 305 {
 306         struct target *target = bank->target;
 307
 308         if (target->state != TARGET_HALTED)
 309         {
 310                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 311                 exit(-1);
 312         }
 313
 314         cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
 315 }
 316
 317 static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
 318 {
 319         uint8_t status;
 320
 321         int retval = ERROR_OK;
 322
 323         for (;;)
 324         {
 325                 if (timeout-- < 0)
 326                 {
 327                         LOG_ERROR("timeout while waiting for WSM to become ready");
 328                         return ERROR_FAIL;
 329                 }
 330
 331                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 332                 if (retval != ERROR_OK)
 333                         return retval;
 334
 335                 if (status & 0x80)
 336                         break;
 337
 338                 alive_sleep(1);
 339         }
 340
 341         /* mask out bit 0 (reserved) */
 342         status = status & 0xfe;
 343
 344         LOG_DEBUG("status: 0x%x", status);
 345
 346         if (status != 0x80)
 347         {
 348                 LOG_ERROR("status register: 0x%x", status);
 349                 if (status & 0x2)
 350                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 351                 if (status & 0x4)
 352                         LOG_ERROR("Program suspended");
 353                 if (status & 0x8)
 354                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 355                 if (status & 0x10)
 356                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 357                 if (status & 0x20)
 358                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 359                 if (status & 0x40)
 360                         LOG_ERROR("Block Erase Suspended");
 361
 362                 cfi_intel_clear_status_register(bank);
 363
 364                 retval = ERROR_FAIL;
 365         }
 366
 367         *val = status;
 368         return retval;
 369 }
 370
 371 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
 372 {
 373         uint8_t status, oldstatus;
 374         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 375         int retval;
 376
 377         retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
 378         if (retval != ERROR_OK)
 379                 return retval;
 380
 381         do {
 382                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 383
 384                 if (retval != ERROR_OK)
 385                         return retval;
 386
 387                 if ((status ^ oldstatus) & 0x40) {
 388                         if (status & cfi_info->status_poll_mask & 0x20) {
 389                                 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
 390                                 if (retval != ERROR_OK)
 391                                         return retval;
 392                                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 393                                 if (retval != ERROR_OK)
 394                                         return retval;
 395                                 if ((status ^ oldstatus) & 0x40) {
 396                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 397                                         return(ERROR_FLASH_OPERATION_FAILED);
 398                                 } else {
 399                                         LOG_DEBUG("status: 0x%x", status);
 400                                         return(ERROR_OK);
 401                                 }
 402                         }
 403                 } else { /* no toggle: finished, OK */
 404                         LOG_DEBUG("status: 0x%x", status);
 405                         return(ERROR_OK);
 406                 }
 407
 408                 oldstatus = status;
 409                 alive_sleep(1);
 410         } while (timeout-- > 0);
 411
 412         LOG_ERROR("timeout, status: 0x%x", status);
 413
 414         return(ERROR_FLASH_BUSY);
 415 }
 416
 417 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
 418 {
 419         int retval;
 420         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 421         struct cfi_intel_pri_ext *pri_ext;
 422
 423         if (cfi_info->pri_ext)
 424                 free(cfi_info->pri_ext);
 425
 426         pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
 427         if (pri_ext == NULL)
 428         {
 429                 LOG_ERROR("Out of memory");
 430                 return ERROR_FAIL;
 431         }
 432         cfi_info->pri_ext = pri_ext;
 433
 434         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
 435         if (retval != ERROR_OK)
 436                 return retval;
 437         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
 438         if (retval != ERROR_OK)
 439                 return retval;
 440         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
 441         if (retval != ERROR_OK)
 442                 return retval;
 443
 444         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 445         {
 446                 if ((retval = cfi_reset(bank)) != ERROR_OK)
 447                 {
 448                         return retval;
 449                 }
 450                 LOG_ERROR("Could not read bank flash bank information");
 451                 return ERROR_FLASH_BANK_INVALID;
 452         }
 453
 454         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
 455         if (retval != ERROR_OK)
 456                 return retval;
 457         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
 458         if (retval != ERROR_OK)
 459                 return retval;
 460
 461         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
 462                         pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 463
 464         retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
 465         if (retval != ERROR_OK)
 466                 return retval;
 467         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
 468         if (retval != ERROR_OK)
 469                 return retval;
 470         retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
 471         if (retval != ERROR_OK)
 472                 return retval;
 473
 474         LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: "
 475                         "0x%x, blk_status_reg_mask: 0x%x",
 476                         pri_ext->feature_support,
 477                         pri_ext->suspend_cmd_support,
 478                         pri_ext->blk_status_reg_mask);
 479
 480         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
 481         if (retval != ERROR_OK)
 482                 return retval;
 483         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
 484         if (retval != ERROR_OK)
 485                 return retval;
 486
 487         LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
 488                         (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 489                         (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 490
 491         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
 492         if (retval != ERROR_OK)
 493                 return retval;
 494         if (pri_ext->num_protection_fields != 1)
 495         {
 496                 LOG_WARNING("expected one protection register field, but found %i",
 497                                 pri_ext->num_protection_fields);
 498         }
 499
 500         retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
 501         if (retval != ERROR_OK)
 502                 return retval;
 503         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
 504         if (retval != ERROR_OK)
 505                 return retval;
 506         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
 507         if (retval != ERROR_OK)
 508                 return retval;
 509
 510         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
 511                         "factory pre-programmed: %i, user programmable: %i",
 512                         pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
 513                         1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 514
 515         return ERROR_OK;
 516 }
 517
 518 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
 519 {
 520         int retval;
 521         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 522         struct cfi_spansion_pri_ext *pri_ext;
 523
 524         if (cfi_info->pri_ext)
 525                 free(cfi_info->pri_ext);
 526
 527         pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 528         if (pri_ext == NULL)
 529         {
 530                 LOG_ERROR("Out of memory");
 531                 return ERROR_FAIL;
 532         }
 533         cfi_info->pri_ext = pri_ext;
 534
 535         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
 536         if (retval != ERROR_OK)
 537                 return retval;
 538         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
 539         if (retval != ERROR_OK)
 540                 return retval;
 541         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
 542         if (retval != ERROR_OK)
 543                 return retval;
 544
 545         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 546         {
 547                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 548                 {
 549                         return retval;
 550                 }
 551                 LOG_ERROR("Could not read spansion bank information");
 552                 return ERROR_FLASH_BANK_INVALID;
 553         }
 554
 555         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
 556         if (retval != ERROR_OK)
 557                 return retval;
 558         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
 559         if (retval != ERROR_OK)
 560                 return retval;
 561
 562         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
 563                         pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 564
 565         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
 566         if (retval != ERROR_OK)
 567                 return retval;
 568         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
 569         if (retval != ERROR_OK)
 570                 return retval;
 571         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
 572         if (retval != ERROR_OK)
 573                 return retval;
 574         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
 575         if (retval != ERROR_OK)
 576                 return retval;
 577         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
 578         if (retval != ERROR_OK)
 579                 return retval;
 580         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
 581         if (retval != ERROR_OK)
 582                 return retval;
 583         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
 584         if (retval != ERROR_OK)
 585                 return retval;
 586         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
 587         if (retval != ERROR_OK)
 588                 return retval;
 589         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
 590         if (retval != ERROR_OK)
 591                 return retval;
 592         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
 593         if (retval != ERROR_OK)
 594                 return retval;
 595         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
 596         if (retval != ERROR_OK)
 597                 return retval;
 598
 599         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
 600                         pri_ext->SiliconRevision, pri_ext->EraseSuspend, pri_ext->BlkProt);
 601
 602         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
 603                         "Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 604                         pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 605
 606         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 607
 608
 609         LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
 610                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 611                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 612
 613         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 614
 615         /* default values for implementation specific workarounds */
 616         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 617         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 618         pri_ext->_reversed_geometry = 0;
 619
 620         return ERROR_OK;
 621 }
 622
 623 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
 624 {
 625         int retval;
 626         struct cfi_atmel_pri_ext atmel_pri_ext;
 627         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 628         struct cfi_spansion_pri_ext *pri_ext;
 629
 630         if (cfi_info->pri_ext)
 631                 free(cfi_info->pri_ext);
 632
 633         pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 634         if (pri_ext == NULL)
 635         {
 636                 LOG_ERROR("Out of memory");
 637                 return ERROR_FAIL;
 638         }
 639
 640         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 641          * but a different primary extended query table.
 642          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 643          */
 644
 645         memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
 646
 647         cfi_info->pri_ext = pri_ext;
 648
 649         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
 650         if (retval != ERROR_OK)
 651                 return retval;
 652         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
 653         if (retval != ERROR_OK)
 654                 return retval;
 655         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
 656         if (retval != ERROR_OK)
 657                 return retval;
 658
 659         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R')
 660                         || (atmel_pri_ext.pri[2] != 'I'))
 661         {
 662                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 663                 {
 664                         return retval;
 665                 }
 666                 LOG_ERROR("Could not read atmel bank information");
 667                 return ERROR_FLASH_BANK_INVALID;
 668         }
 669
 670         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 671         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 672         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 673
 674         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
 675         if (retval != ERROR_OK)
 676                 return retval;
 677         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
 678         if (retval != ERROR_OK)
 679                 return retval;
 680
 681         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0],
 682                         atmel_pri_ext.pri[1], atmel_pri_ext.pri[2],
 683                         atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 684
 685         pri_ext->major_version = atmel_pri_ext.major_version;
 686         pri_ext->minor_version = atmel_pri_ext.minor_version;
 687
 688         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
 689         if (retval != ERROR_OK)
 690                 return retval;
 691         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
 692         if (retval != ERROR_OK)
 693                 return retval;
 694         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
 695         if (retval != ERROR_OK)
 696                 return retval;
 697         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
 698         if (retval != ERROR_OK)
 699                 return retval;
 700
 701         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 702                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot,
 703                 atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 704
 705         if (atmel_pri_ext.features & 0x02)
 706                 pri_ext->EraseSuspend = 2;
 707
 708         if (atmel_pri_ext.bottom_boot)
 709                 pri_ext->TopBottom = 2;
 710         else
 711                 pri_ext->TopBottom = 3;
 712
 713         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 714         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 715
 716         return ERROR_OK;
 717 }
 718
 719 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
 720 {
 721         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 722
 723         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 724         {
 725                 return cfi_read_atmel_pri_ext(bank);
 726         }
 727         else
 728         {
 729                 return cfi_read_spansion_pri_ext(bank);
 730         }
 731 }
 732
 733 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
 734 {
 735         int printed;
 736         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 737         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 738
 739         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 740         buf += printed;
 741         buf_size -= printed;
 742
 743         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 744                         pri_ext->pri[1], pri_ext->pri[2],
 745                         pri_ext->major_version, pri_ext->minor_version);
 746         buf += printed;
 747         buf_size -= printed;
 748
 749         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 750                         (pri_ext->SiliconRevision) >> 2,
 751                         (pri_ext->SiliconRevision) & 0x03);
 752         buf += printed;
 753         buf_size -= printed;
 754
 755         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 756                         pri_ext->EraseSuspend,
 757                         pri_ext->BlkProt);
 758         buf += printed;
 759         buf_size -= printed;
 760
 761         printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
 762                         (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 763                         (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 764
 765         return ERROR_OK;
 766 }
 767
 768 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
 769 {
 770         int printed;
 771         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 772         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 773
 774         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 775         buf += printed;
 776         buf_size -= printed;
 777
 778         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 779                         pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 780         buf += printed;
 781         buf_size -= printed;
 782
 783         printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", "
 784                         "suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
 785                         pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 786         buf += printed;
 787         buf_size -= printed;
 788
 789         printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
 790                         (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 791                         (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 792         buf += printed;
 793         buf_size -= printed;
 794
 795         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, "
 796                         "factory pre-programmed: %i, user programmable: %i\n",
 797                         pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
 798                         1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 799
 800         return ERROR_OK;
 801 }
 802
 803 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 804  */
 805 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
 806 {
 807         struct cfi_flash_bank *cfi_info;
 808
 809         if (CMD_ARGC < 6)
 810         {
 811                 LOG_WARNING("incomplete flash_bank cfi configuration");
 812                 return ERROR_FLASH_BANK_INVALID;
 813         }
 814
 815         /* both widths must:
 816          * - not exceed max value;
 817          * - not be null;
 818          * - be equal to a power of 2.
 819          * bus must be wide enought to hold one chip */
 820         if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
 821                         || (bank->bus_width > CFI_MAX_BUS_WIDTH)
 822                         || (bank->chip_width == 0)
 823                         || (bank->bus_width == 0)
 824                         || (bank->chip_width & (bank->chip_width - 1))
 825                         || (bank->bus_width & (bank->bus_width - 1))
 826                         || (bank->chip_width > bank->bus_width))
 827         {
 828                 LOG_ERROR("chip and bus width have to specified in bytes");
 829                 return ERROR_FLASH_BANK_INVALID;
 830         }
 831
 832         cfi_info = malloc(sizeof(struct cfi_flash_bank));
 833         cfi_info->probed = 0;
 834         cfi_info->erase_region_info = NULL;
 835         cfi_info->pri_ext = NULL;
 836         bank->driver_priv = cfi_info;
 837
 838         cfi_info->write_algorithm = NULL;
 839
 840         cfi_info->x16_as_x8 = 0;
 841         cfi_info->jedec_probe = 0;
 842         cfi_info->not_cfi = 0;
 843
 844         for (unsigned i = 6; i < CMD_ARGC; i++)
 845         {
 846                 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
 847                 {
 848                         cfi_info->x16_as_x8 = 1;
 849                 }
 850                 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
 851                 {
 852                         cfi_info->jedec_probe = 1;
 853                 }
 854         }
 855
 856         cfi_info->write_algorithm = NULL;
 857
 858         /* bank wasn't probed yet */
 859         cfi_info->qry[0] = 0xff;
 860
 861         return ERROR_OK;
 862 }
 863
 864 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
 865 {
 866         int retval;
 867         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 868         int i;
 869
 870         cfi_intel_clear_status_register(bank);
 871
 872         for (i = first; i <= last; i++)
 873         {
 874                 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
 875                 {
 876                         return retval;
 877                 }
 878
 879                 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
 880                 {
 881                         return retval;
 882                 }
 883
 884                 uint8_t status;
 885                 retval = cfi_intel_wait_status_busy(bank, cfi_info->block_erase_timeout, &status);
 886                 if (retval != ERROR_OK)
 887                         return retval;
 888
 889                 if (status == 0x80)
 890                         bank->sectors[i].is_erased = 1;
 891                 else
 892                 {
 893                         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 894                         {
 895                                 return retval;
 896                         }
 897
 898                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
 899                         return ERROR_FLASH_OPERATION_FAILED;
 900                 }
 901         }
 902
 903         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
 904 }
 905
 906 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
 907 {
 908         int retval;
 909         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 910         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 911         int i;
 912
 913         for (i = first; i <= last; i++)
 914         {
 915                 if ((retval = cfi_send_command(bank, 0xaa,
 916                                 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 917                 {
 918                         return retval;
 919                 }
 920
 921                 if ((retval = cfi_send_command(bank, 0x55,
 922                                 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 923                 {
 924                         return retval;
 925                 }
 926
 927                 if ((retval = cfi_send_command(bank, 0x80,
 928                                 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 929                 {
 930                         return retval;
 931                 }
 932
 933                 if ((retval = cfi_send_command(bank, 0xaa,
 934                                 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 935                 {
 936                         return retval;
 937                 }
 938
 939                 if ((retval = cfi_send_command(bank, 0x55,
 940                                 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 941                 {
 942                         return retval;
 943                 }
 944
 945                 if ((retval = cfi_send_command(bank, 0x30,
 946                                 flash_address(bank, i, 0x0))) != ERROR_OK)
 947                 {
 948                         return retval;
 949                 }
 950
 951                 if (cfi_spansion_wait_status_busy(bank, cfi_info->block_erase_timeout) == ERROR_OK)
 952                 {
 953                         bank->sectors[i].is_erased = 1;
 954                 }
 955                 else
 956                 {
 957                         if ((retval = cfi_send_command(bank, 0xf0,
 958                                         flash_address(bank, 0, 0x0))) != ERROR_OK)
 959                         {
 960                                 return retval;
 961                         }
 962
 963                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
 964                                         PRIx32, i, bank->base);
 965                         return ERROR_FLASH_OPERATION_FAILED;
 966                 }
 967         }
 968
 969         return  cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
 970 }
 971
 972 static int cfi_erase(struct flash_bank *bank, int first, int last)
 973 {
 974         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 975
 976         if (bank->target->state != TARGET_HALTED)
 977         {
 978                 LOG_ERROR("Target not halted");
 979                 return ERROR_TARGET_NOT_HALTED;
 980         }
 981
 982         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 983         {
 984                 return ERROR_FLASH_SECTOR_INVALID;
 985         }
 986
 987         if (cfi_info->qry[0] != 'Q')
 988                 return ERROR_FLASH_BANK_NOT_PROBED;
 989
 990         switch (cfi_info->pri_id)
 991         {
 992                 case 1:
 993                 case 3:
 994                         return cfi_intel_erase(bank, first, last);
 995                         break;
 996                 case 2:
 997                         return cfi_spansion_erase(bank, first, last);
 998                         break;
 999                 default:
1000                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1001                         break;
1002         }
1003
1004         return ERROR_OK;
1005 }
1006
1007 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
1008 {
1009         int retval;
1010         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1011         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
1012         int retry = 0;
1013         int i;
1014
1015         /* if the device supports neither legacy lock/unlock (bit 3) nor
1016          * instant individual block locking (bit 5).
1017          */
1018         if (!(pri_ext->feature_support & 0x28))
1019         {
1020                 LOG_ERROR("lock/unlock not supported on flash");
1021                 return ERROR_FLASH_OPERATION_FAILED;
1022         }
1023
1024         cfi_intel_clear_status_register(bank);
1025
1026         for (i = first; i <= last; i++)
1027         {
1028                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
1029                 {
1030                         return retval;
1031                 }
1032                 if (set)
1033                 {
1034                         if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
1035                         {
1036                                 return retval;
1037                         }
1038                         bank->sectors[i].is_protected = 1;
1039                 }
1040                 else
1041                 {
1042                         if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
1043                         {
1044                                 return retval;
1045                         }
1046                         bank->sectors[i].is_protected = 0;
1047                 }
1048
1049                 /* instant individual block locking doesn't require reading of the status register */
1050                 if (!(pri_ext->feature_support & 0x20))
1051                 {
1052                         /* Clear lock bits operation may take up to 1.4s */
1053                         uint8_t status;
1054                         retval = cfi_intel_wait_status_busy(bank, 1400, &status);
1055                         if (retval != ERROR_OK)
1056                                 return retval;
1057                 }
1058                 else
1059                 {
1060                         uint8_t block_status;
1061                         /* read block lock bit, to verify status */
1062                         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
1063                         {
1064                                 return retval;
1065                         }
1066                         retval = cfi_get_u8(bank, i, 0x2, &block_status);
1067                         if (retval != ERROR_OK)
1068                                 return retval;
1069
1070                         if ((block_status & 0x1) != set)
1071                         {
1072                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)",
1073                                                 set, block_status);
1074                                 if ((retval = cfi_send_command(bank, 0x70,
1075                                                 flash_address(bank, 0, 0x55))) != ERROR_OK)
1076                                 {
1077                                         return retval;
1078                                 }
1079                                 uint8_t status;
1080                                 retval = cfi_intel_wait_status_busy(bank, 10, &status);
1081                                 if (retval != ERROR_OK)
1082                                         return retval;
1083
1084                                 if (retry > 10)
1085                                         return ERROR_FLASH_OPERATION_FAILED;
1086                                 else
1087                                 {
1088                                         i--;
1089                                         retry++;
1090                                 }
1091                         }
1092                 }
1093         }
1094
1095         /* if the device doesn't support individual block lock bits set/clear,
1096          * all blocks have been unlocked in parallel, so we set those that should be protected
1097          */
1098         if ((!set) && (!(pri_ext->feature_support & 0x20)))
1099         {
1100                 /* FIX!!! this code path is broken!!!
1101                  *
1102                  * The correct approach is:
1103                  *
1104                  * 1. read out current protection status
1105                  *
1106                  * 2. override read out protection status w/unprotected.
1107                  *
1108                  * 3. re-protect what should be protected.
1109                  *
1110                  */
1111                 for (i = 0; i < bank->num_sectors; i++)
1112                 {
1113                         if (bank->sectors[i].is_protected == 1)
1114                         {
1115                                 cfi_intel_clear_status_register(bank);
1116
1117                                 if ((retval = cfi_send_command(bank, 0x60,
1118                                                 flash_address(bank, i, 0x0))) != ERROR_OK)
1119                                 {
1120                                         return retval;
1121                                 }
1122
1123                                 if ((retval = cfi_send_command(bank, 0x01,
1124                                                 flash_address(bank, i, 0x0))) != ERROR_OK)
1125                                 {
1126                                         return retval;
1127                                 }
1128
1129                                 uint8_t status;
1130                                 retval = cfi_intel_wait_status_busy(bank, 100, &status);
1131                                 if (retval != ERROR_OK)
1132                                         return retval;
1133                         }
1134                 }
1135         }
1136
1137         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
1138 }
1139
1140 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
1141 {
1142         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1143
1144         if (bank->target->state != TARGET_HALTED)
1145         {
1146                 LOG_ERROR("Target not halted");
1147                 return ERROR_TARGET_NOT_HALTED;
1148         }
1149
1150         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
1151         {
1152                 LOG_ERROR("Invalid sector range");
1153                 return ERROR_FLASH_SECTOR_INVALID;
1154         }
1155
1156         if (cfi_info->qry[0] != 'Q')
1157                 return ERROR_FLASH_BANK_NOT_PROBED;
1158
1159         switch (cfi_info->pri_id)
1160         {
1161                 case 1:
1162                 case 3:
1163                         return cfi_intel_protect(bank, set, first, last);
1164                         break;
1165                 default:
1166                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
1167                         return ERROR_FAIL;
1168         }
1169 }
1170
1171 /* Convert code image to target endian */
1172 /* FIXME create general block conversion fcts in target.c?) */
1173 static void cfi_fix_code_endian(struct target *target, uint8_t *dest,
1174                 const uint32_t *src, uint32_t count)
1175 {
1176         uint32_t i;
1177         for (i = 0; i< count; i++)
1178         {
1179                 target_buffer_set_u32(target, dest, *src);
1180                 dest += 4;
1181                 src++;
1182         }
1183 }
1184
1185 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
1186 {
1187         struct target *target = bank->target;
1188
1189         uint8_t buf[CFI_MAX_BUS_WIDTH];
1190         cfi_command(bank, cmd, buf);
1191         switch (bank->bus_width)
1192         {
1193         case 1 :
1194                 return buf[0];
1195                 break;
1196         case 2 :
1197                 return target_buffer_get_u16(target, buf);
1198                 break;
1199         case 4 :
1200                 return target_buffer_get_u32(target, buf);
1201                 break;
1202         default :
1203                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1204                 return 0;
1205         }
1206 }
1207
1208 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
1209                 uint32_t address, uint32_t count)
1210 {
1211         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1212         struct target *target = bank->target;
1213         struct reg_param reg_params[7];
1214         struct arm_algorithm armv4_5_info;
1215         struct working_area *source;
1216         uint32_t buffer_size = 32768;
1217         uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1218
1219         /* algorithm register usage:
1220          * r0: source address (in RAM)
1221          * r1: target address (in Flash)
1222          * r2: count
1223          * r3: flash write command
1224          * r4: status byte (returned to host)
1225          * r5: busy test pattern
1226          * r6: error test pattern
1227          */
1228
1229         static const uint32_t word_32_code[] = {
1230                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1231                 0xe5813000,   /*                str r3, [r1] */
1232                 0xe5814000,   /*                str r4, [r1] */
1233                 0xe5914000,   /* busy:  ldr r4, [r1] */
1234                 0xe0047005,   /*                and r7, r4, r5 */
1235                 0xe1570005,   /*                cmp r7, r5 */
1236                 0x1afffffb,   /*                bne busy */
1237                 0xe1140006,   /*                tst r4, r6 */
1238                 0x1a000003,   /*                bne done */
1239                 0xe2522001,   /*                subs r2, r2, #1 */
1240                 0x0a000001,   /*                beq done */
1241                 0xe2811004,   /*                add r1, r1 #4 */
1242                 0xeafffff2,   /*                b loop */
1243                 0xeafffffe    /* done:  b -2 */
1244         };
1245
1246         static const uint32_t word_16_code[] = {
1247                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1248                 0xe1c130b0,   /*                strh r3, [r1] */
1249                 0xe1c140b0,   /*                strh r4, [r1] */
1250                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1251                 0xe0047005,   /*                and r7, r4, r5 */
1252                 0xe1570005,   /*                cmp r7, r5 */
1253                 0x1afffffb,   /*                bne busy */
1254                 0xe1140006,   /*                tst r4, r6 */
1255                 0x1a000003,   /*                bne done */
1256                 0xe2522001,   /*                subs r2, r2, #1 */
1257                 0x0a000001,   /*                beq done */
1258                 0xe2811002,   /*                add r1, r1 #2 */
1259                 0xeafffff2,   /*                b loop */
1260                 0xeafffffe    /* done:  b -2 */
1261         };
1262
1263         static const uint32_t word_8_code[] = {
1264                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1265                 0xe5c13000,   /*                strb r3, [r1] */
1266                 0xe5c14000,   /*                strb r4, [r1] */
1267                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1268                 0xe0047005,   /*                and r7, r4, r5 */
1269                 0xe1570005,   /*                cmp r7, r5 */
1270                 0x1afffffb,   /*                bne busy */
1271                 0xe1140006,   /*                tst r4, r6 */
1272                 0x1a000003,   /*                bne done */
1273                 0xe2522001,   /*                subs r2, r2, #1 */
1274                 0x0a000001,   /*                beq done */
1275                 0xe2811001,   /*                add r1, r1 #1 */
1276                 0xeafffff2,   /*                b loop */
1277                 0xeafffffe    /* done:  b -2 */
1278         };
1279         uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1280         const uint32_t *target_code_src;
1281         uint32_t target_code_size;
1282         int retval = ERROR_OK;
1283
1284
1285         cfi_intel_clear_status_register(bank);
1286
1287         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1288         armv4_5_info.core_mode = ARM_MODE_SVC;
1289         armv4_5_info.core_state = ARM_STATE_ARM;
1290
1291         /* If we are setting up the write_algorith, we need target_code_src */
1292         /* if not we only need target_code_size. */
1293
1294         /* However, we don't want to create multiple code paths, so we */
1295         /* do the unecessary evaluation of target_code_src, which the */
1296         /* compiler will probably nicely optimize away if not needed */
1297
1298         /* prepare algorithm code for target endian */
1299         switch (bank->bus_width)
1300         {
1301         case 1 :
1302                 target_code_src = word_8_code;
1303                 target_code_size = sizeof(word_8_code);
1304                 break;
1305         case 2 :
1306                 target_code_src = word_16_code;
1307                 target_code_size = sizeof(word_16_code);
1308                 break;
1309         case 4 :
1310                 target_code_src = word_32_code;
1311                 target_code_size = sizeof(word_32_code);
1312                 break;
1313         default:
1314                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1315                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1316         }
1317
1318         /* flash write code */
1319         if (!cfi_info->write_algorithm)
1320         {
1321                 if (target_code_size > sizeof(target_code))
1322                 {
1323                         LOG_WARNING("Internal error - target code buffer to small. "
1324                                         "Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1325                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1326                 }
1327                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1328
1329                 /* Get memory for block write handler */
1330                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1331                 if (retval != ERROR_OK)
1332                 {
1333                         LOG_WARNING("No working area available, can't do block memory writes");
1334                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1335                 };
1336
1337                 /* write algorithm code to working area */
1338                 retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1339                                 target_code_size, target_code);
1340                 if (retval != ERROR_OK)
1341                 {
1342                         LOG_ERROR("Unable to write block write code to target");
1343                         goto cleanup;
1344                 }
1345         }
1346
1347         /* Get a workspace buffer for the data to flash starting with 32k size.
1348            Half size until buffer would be smaller 256 Bytem then fail back */
1349         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1350         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1351         {
1352                 buffer_size /= 2;
1353                 if (buffer_size <= 256)
1354                 {
1355                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1356                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1357                         goto cleanup;
1358                 }
1359         };
1360
1361         /* setup algo registers */
1362         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1363         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1364         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1365         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1366         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1367         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1368         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1369
1370         /* prepare command and status register patterns */
1371         write_command_val = cfi_command_val(bank, 0x40);
1372         busy_pattern_val  = cfi_command_val(bank, 0x80);
1373         error_pattern_val = cfi_command_val(bank, 0x7e);
1374
1375         LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32,
1376                         source->address, buffer_size);
1377
1378         /* Programming main loop */
1379         while (count > 0)
1380         {
1381                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1382                 uint32_t wsm_error;
1383
1384                 if ((retval = target_write_buffer(target, source->address,
1385                                 thisrun_count, buffer)) != ERROR_OK)
1386                 {
1387                         goto cleanup;
1388                 }
1389
1390                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1391                 buf_set_u32(reg_params[1].value, 0, 32, address);
1392                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1393
1394                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1395                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1396                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1397
1398                 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1399
1400                 /* Execute algorithm, assume breakpoint for last instruction */
1401                 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1402                         cfi_info->write_algorithm->address,
1403                         cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1404                         10000, /* 10s should be enough for max. 32k of data */
1405                         &armv4_5_info);
1406
1407                 /* On failure try a fall back to direct word writes */
1408                 if (retval != ERROR_OK)
1409                 {
1410                         cfi_intel_clear_status_register(bank);
1411                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1412                         retval = ERROR_FLASH_OPERATION_FAILED;
1413                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1414                         /* FIXME To allow fall back or recovery, we must save the actual status
1415                          * somewhere, so that a higher level code can start recovery. */
1416                         goto cleanup;
1417                 }
1418
1419                 /* Check return value from algo code */
1420                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1421                 if (wsm_error)
1422                 {
1423                         /* read status register (outputs debug inforation) */
1424                         uint8_t status;
1425                         cfi_intel_wait_status_busy(bank, 100, &status);
1426                         cfi_intel_clear_status_register(bank);
1427                         retval = ERROR_FLASH_OPERATION_FAILED;
1428                         goto cleanup;
1429                 }
1430
1431                 buffer += thisrun_count;
1432                 address += thisrun_count;
1433                 count -= thisrun_count;
1434
1435                 keep_alive();
1436         }
1437
1438         /* free up resources */
1439 cleanup:
1440         if (source)
1441                 target_free_working_area(target, source);
1442
1443         if (cfi_info->write_algorithm)
1444         {
1445                 target_free_working_area(target, cfi_info->write_algorithm);
1446                 cfi_info->write_algorithm = NULL;
1447         }
1448
1449         destroy_reg_param(&reg_params[0]);
1450         destroy_reg_param(&reg_params[1]);
1451         destroy_reg_param(&reg_params[2]);
1452         destroy_reg_param(&reg_params[3]);
1453         destroy_reg_param(&reg_params[4]);
1454         destroy_reg_param(&reg_params[5]);
1455         destroy_reg_param(&reg_params[6]);
1456
1457         return retval;
1458 }
1459
1460 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
1461                 uint32_t address, uint32_t count)
1462 {
1463         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1464         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1465         struct target *target = bank->target;
1466         struct reg_param reg_params[10];
1467         struct arm_algorithm armv4_5_info;
1468         struct working_area *source;
1469         uint32_t buffer_size = 32768;
1470         uint32_t status;
1471         int retval = ERROR_OK;
1472
1473         /* input parameters - */
1474         /*      R0 = source address */
1475         /*      R1 = destination address */
1476         /*      R2 = number of writes */
1477         /*      R3 = flash write command */
1478         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1479         /* output parameters - */
1480         /*      R5 = 0x80 ok 0x00 bad */
1481         /* temp registers - */
1482         /*      R6 = value read from flash to test status */
1483         /*      R7 = holding register */
1484         /* unlock registers - */
1485         /*  R8 = unlock1_addr */
1486         /*  R9 = unlock1_cmd */
1487         /*  R10 = unlock2_addr */
1488         /*  R11 = unlock2_cmd */
1489
1490         static const uint32_t word_32_code[] = {
1491                                                 /* 00008100 <sp_32_code>:               */
1492                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1493                 0xe5889000,             /* str  r9, [r8]                                */
1494                 0xe58ab000,             /* str  r11, [r10]                              */
1495                 0xe5883000,             /* str  r3, [r8]                                */
1496                 0xe5815000,             /* str  r5, [r1]                                */
1497                 0xe1a00000,             /* nop                                                  */
1498                                                 /*                                                              */
1499                                                 /* 00008110 <sp_32_busy>:               */
1500                 0xe5916000,             /* ldr  r6, [r1]                                */
1501                 0xe0257006,             /* eor  r7, r5, r6                              */
1502                 0xe0147007,             /* ands r7, r4, r7                              */
1503                 0x0a000007,             /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1504                 0xe0166124,             /* ands r6, r6, r4, lsr #2              */
1505                 0x0afffff9,             /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1506                 0xe5916000,             /* ldr  r6, [r1]                                */
1507                 0xe0257006,             /* eor  r7, r5, r6                              */
1508                 0xe0147007,             /* ands r7, r4, r7                              */
1509                 0x0a000001,             /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1510                 0xe3a05000,             /* mov  r5, #0  ; 0x0 - return 0x00, error */
1511                 0x1a000004,             /* bne  8154 <sp_32_done>               */
1512                                                 /*                                                              */
1513                                                 /* 00008140 <sp_32_cont>:               */
1514                 0xe2522001,             /* subs r2, r2, #1      ; 0x1           */
1515                 0x03a05080,             /* moveq        r5, #128        ; 0x80  */
1516                 0x0a000001,             /* beq  8154 <sp_32_done>               */
1517                 0xe2811004,             /* add  r1, r1, #4      ; 0x4           */
1518                 0xeaffffe8,             /* b    8100 <sp_32_code>               */
1519                                                 /*                                                              */
1520                                                 /* 00008154 <sp_32_done>:               */
1521                 0xeafffffe              /* b    8154 <sp_32_done>               */
1522                 };
1523
1524                 static const uint32_t word_16_code[] = {
1525                                                 /* 00008158 <sp_16_code>:               */
1526                 0xe0d050b2,             /* ldrh r5, [r0], #2                    */
1527                 0xe1c890b0,             /* strh r9, [r8]                                */
1528                 0xe1cab0b0,             /* strh r11, [r10]                              */
1529                 0xe1c830b0,             /* strh r3, [r8]                                */
1530                 0xe1c150b0,             /* strh r5, [r1]                                */
1531                 0xe1a00000,             /* nop                  (mov r0,r0)             */
1532                                                 /*                                                              */
1533                                                 /* 00008168 <sp_16_busy>:               */
1534                 0xe1d160b0,             /* ldrh r6, [r1]                                */
1535                 0xe0257006,             /* eor  r7, r5, r6                              */
1536                 0xe0147007,             /* ands r7, r4, r7                              */
1537                 0x0a000007,             /* beq  8198 <sp_16_cont>               */
1538                 0xe0166124,             /* ands r6, r6, r4, lsr #2              */
1539                 0x0afffff9,             /* beq  8168 <sp_16_busy>               */
1540                 0xe1d160b0,             /* ldrh r6, [r1]                                */
1541                 0xe0257006,             /* eor  r7, r5, r6                              */
1542                 0xe0147007,             /* ands r7, r4, r7                              */
1543                 0x0a000001,             /* beq  8198 <sp_16_cont>               */
1544                 0xe3a05000,             /* mov  r5, #0  ; 0x0                   */
1545                 0x1a000004,             /* bne  81ac <sp_16_done>               */
1546                                                 /*                                                              */
1547                                                 /* 00008198 <sp_16_cont>:               */
1548                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1549                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1550                 0x0a000001,     /* beq  81ac <sp_16_done>               */
1551                 0xe2811002,     /* add  r1, r1, #2      ; 0x2           */
1552                 0xeaffffe8,     /* b    8158 <sp_16_code>               */
1553                                                 /*                                                              */
1554                                                 /* 000081ac <sp_16_done>:               */
1555                 0xeafffffe              /* b    81ac <sp_16_done>               */
1556                 };
1557
1558                 static const uint32_t word_16_code_dq7only[] = {
1559                                                 /* <sp_16_code>:                                */
1560                 0xe0d050b2,             /* ldrh r5, [r0], #2                    */
1561                 0xe1c890b0,             /* strh r9, [r8]                                */
1562                 0xe1cab0b0,             /* strh r11, [r10]                              */
1563                 0xe1c830b0,             /* strh r3, [r8]                                */
1564                 0xe1c150b0,             /* strh r5, [r1]                                */
1565                 0xe1a00000,             /* nop                  (mov r0,r0)             */
1566                                                 /*                                                              */
1567                                                 /* <sp_16_busy>:                                */
1568                 0xe1d160b0,             /* ldrh r6, [r1]                                */
1569                 0xe0257006,             /* eor  r7, r5, r6                              */
1570                 0xe2177080,             /* ands r7, #0x80                               */
1571                 0x1afffffb,             /* bne  8168 <sp_16_busy>               */
1572                                                 /*                                                              */
1573                 0xe2522001,             /* subs r2, r2, #1      ; 0x1           */
1574                 0x03a05080,             /* moveq        r5, #128        ; 0x80  */
1575                 0x0a000001,             /* beq  81ac <sp_16_done>               */
1576                 0xe2811002,             /* add  r1, r1, #2      ; 0x2           */
1577                 0xeafffff0,             /* b    8158 <sp_16_code>               */
1578                                                 /*                                                              */
1579                                                 /* 000081ac <sp_16_done>:               */
1580                 0xeafffffe              /* b    81ac <sp_16_done>               */
1581                 };
1582
1583                 static const uint32_t word_8_code[] = {
1584                                                 /* 000081b0 <sp_16_code_end>:   */
1585                 0xe4d05001,             /* ldrb r5, [r0], #1                    */
1586                 0xe5c89000,             /* strb r9, [r8]                                */
1587                 0xe5cab000,             /* strb r11, [r10]                              */
1588                 0xe5c83000,             /* strb r3, [r8]                                */
1589                 0xe5c15000,             /* strb r5, [r1]                                */
1590                 0xe1a00000,             /* nop                  (mov r0,r0)             */
1591                                                 /*                                                              */
1592                                                 /* 000081c0 <sp_8_busy>:                */
1593                 0xe5d16000,             /* ldrb r6, [r1]                                */
1594                 0xe0257006,             /* eor  r7, r5, r6                              */
1595                 0xe0147007,             /* ands r7, r4, r7                              */
1596                 0x0a000007,             /* beq  81f0 <sp_8_cont>                */
1597                 0xe0166124,             /* ands r6, r6, r4, lsr #2              */
1598                 0x0afffff9,             /* beq  81c0 <sp_8_busy>                */
1599                 0xe5d16000,             /* ldrb r6, [r1]                                */
1600                 0xe0257006,             /* eor  r7, r5, r6                              */
1601                 0xe0147007,             /* ands r7, r4, r7                              */
1602                 0x0a000001,             /* beq  81f0 <sp_8_cont>                */
1603                 0xe3a05000,             /* mov  r5, #0  ; 0x0                   */
1604                 0x1a000004,             /* bne  8204 <sp_8_done>                */
1605                                                 /*                                                              */
1606                                                 /* 000081f0 <sp_8_cont>:                */
1607                 0xe2522001,             /* subs r2, r2, #1      ; 0x1           */
1608                 0x03a05080,             /* moveq        r5, #128        ; 0x80  */
1609                 0x0a000001,             /* beq  8204 <sp_8_done>                */
1610                 0xe2811001,             /* add  r1, r1, #1      ; 0x1           */
1611                 0xeaffffe8,             /* b    81b0 <sp_16_code_end>   */
1612                                                 /*                                                              */
1613                                                 /* 00008204 <sp_8_done>:                */
1614                 0xeafffffe              /* b    8204 <sp_8_done>                */
1615         };
1616
1617         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1618         armv4_5_info.core_mode = ARM_MODE_SVC;
1619         armv4_5_info.core_state = ARM_STATE_ARM;
1620
1621         int target_code_size;
1622         const uint32_t *target_code_src;
1623
1624         switch (bank->bus_width)
1625         {
1626         case 1 :
1627                 target_code_src = word_8_code;
1628                 target_code_size = sizeof(word_8_code);
1629                 break;
1630         case 2 :
1631                 /* Check for DQ5 support */
1632                 if( cfi_info->status_poll_mask & (1 << 5) )
1633                 {
1634                         target_code_src = word_16_code;
1635                         target_code_size = sizeof(word_16_code);
1636                 }
1637                 else
1638                 {
1639                         /* No DQ5 support. Use DQ7 DATA# polling only. */
1640                         target_code_src = word_16_code_dq7only;
1641                         target_code_size = sizeof(word_16_code_dq7only);
1642                 }
1643                 break;
1644         case 4 :
1645                 target_code_src = word_32_code;
1646                 target_code_size = sizeof(word_32_code);
1647                 break;
1648         default:
1649                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1650                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1651         }
1652
1653         /* flash write code */
1654         if (!cfi_info->write_algorithm)
1655         {
1656                 uint8_t *target_code;
1657
1658                 /* convert bus-width dependent algorithm code to correct endiannes */
1659                 target_code = malloc(target_code_size);
1660                 if (target_code == NULL)
1661                 {
1662                         LOG_ERROR("Out of memory");
1663                         return ERROR_FAIL;
1664                 }
1665                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1666
1667                 /* allocate working area */
1668                 retval = target_alloc_working_area(target, target_code_size,
1669                                 &cfi_info->write_algorithm);
1670                 if (retval != ERROR_OK)
1671                 {
1672                         free(target_code);
1673                         return retval;
1674                 }
1675
1676                 /* write algorithm code to working area */
1677                 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1678                                 target_code_size, target_code)) != ERROR_OK)
1679                 {
1680                         free(target_code);
1681                         return retval;
1682                 }
1683
1684                 free(target_code);
1685         }
1686         /* the following code still assumes target code is fixed 24*4 bytes */
1687
1688         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1689         {
1690                 buffer_size /= 2;
1691                 if (buffer_size <= 256)
1692                 {
1693                         /* if we already allocated the writing code, but failed to get a
1694                          * buffer, free the algorithm */
1695                         if (cfi_info->write_algorithm)
1696                                 target_free_working_area(target, cfi_info->write_algorithm);
1697
1698                         LOG_WARNING("not enough working area available, can't do block memory writes");
1699                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1700                 }
1701         };
1702
1703         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1704         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1705         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1706         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1707         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1708         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1709         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1710         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1711         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1712         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1713
1714         while (count > 0)
1715         {
1716                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1717
1718                 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1719                 if (retval != ERROR_OK)
1720                 {
1721                         break;
1722                 }
1723
1724                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1725                 buf_set_u32(reg_params[1].value, 0, 32, address);
1726                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1727                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1728                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1729                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1730                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1731                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1732                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1733
1734                 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1735                                 cfi_info->write_algorithm->address,
1736                                 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1737                                 10000, &armv4_5_info);
1738                 if (retval != ERROR_OK)
1739                 {
1740                         break;
1741                 }
1742
1743                 status = buf_get_u32(reg_params[5].value, 0, 32);
1744                 if (status != 0x80)
1745                 {
1746                         LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
1747                         retval = ERROR_FLASH_OPERATION_FAILED;
1748                         break;
1749                 }
1750
1751                 buffer += thisrun_count;
1752                 address += thisrun_count;
1753                 count -= thisrun_count;
1754         }
1755
1756         target_free_all_working_areas(target);
1757
1758         destroy_reg_param(&reg_params[0]);
1759         destroy_reg_param(&reg_params[1]);
1760         destroy_reg_param(&reg_params[2]);
1761         destroy_reg_param(&reg_params[3]);
1762         destroy_reg_param(&reg_params[4]);
1763         destroy_reg_param(&reg_params[5]);
1764         destroy_reg_param(&reg_params[6]);
1765         destroy_reg_param(&reg_params[7]);
1766         destroy_reg_param(&reg_params[8]);
1767         destroy_reg_param(&reg_params[9]);
1768
1769         return retval;
1770 }
1771
1772 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1773 {
1774         int retval;
1775         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1776         struct target *target = bank->target;
1777
1778         cfi_intel_clear_status_register(bank);
1779         if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1780         {
1781                 return retval;
1782         }
1783
1784         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1785         {
1786                 return retval;
1787         }
1788
1789         uint8_t status;
1790         retval = cfi_intel_wait_status_busy(bank, cfi_info->word_write_timeout, &status);
1791         if (retval != 0x80)
1792         {
1793                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1794                 {
1795                         return retval;
1796                 }
1797
1798                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address 0x%" PRIx32,
1799                                 bank->base, address);
1800                 return ERROR_FLASH_OPERATION_FAILED;
1801         }
1802
1803         return ERROR_OK;
1804 }
1805
1806 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word,
1807                 uint32_t wordcount, uint32_t address)
1808 {
1809         int retval;
1810         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1811         struct target *target = bank->target;
1812
1813         /* Calculate buffer size and boundary mask */
1814         /* buffersize is (buffer size per chip) * (number of chips) */
1815         /* bufferwsize is buffersize in words */
1816         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1817         uint32_t buffermask = buffersize-1;
1818         uint32_t bufferwsize = buffersize / bank->bus_width;
1819
1820         /* Check for valid range */
1821         if (address & buffermask)
1822         {
1823                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address 0x%" PRIx32
1824                                 " not aligned to 2^%d boundary",
1825                                 bank->base, address, cfi_info->max_buf_write_size);
1826                 return ERROR_FLASH_OPERATION_FAILED;
1827         }
1828
1829         /* Check for valid size */
1830         if (wordcount > bufferwsize)
1831         {
1832                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32,
1833                                 wordcount, buffersize);
1834                 return ERROR_FLASH_OPERATION_FAILED;
1835         }
1836
1837         /* Write to flash buffer */
1838         cfi_intel_clear_status_register(bank);
1839
1840         /* Initiate buffer operation _*/
1841         if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1842         {
1843                 return retval;
1844         }
1845         uint8_t status;
1846         retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
1847         if (retval != ERROR_OK)
1848                 return retval;
1849         if (status != 0x80)
1850         {
1851                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1852                 {
1853                         return retval;
1854                 }
1855
1856                 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address 0x%" PRIx32,
1857                                 bank->base, address);
1858                 return ERROR_FLASH_OPERATION_FAILED;
1859         }
1860
1861         /* Write buffer wordcount-1 and data words */
1862         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1863         {
1864                 return retval;
1865         }
1866
1867         if ((retval = target_write_memory(target,
1868                         address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1869         {
1870                 return retval;
1871         }
1872
1873         /* Commit write operation */
1874         if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1875         {
1876                 return retval;
1877         }
1878
1879         retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
1880         if (retval != ERROR_OK)
1881                 return retval;
1882
1883         if (status != 0x80)
1884         {
1885                 if ((retval = cfi_send_command(bank, 0xff,
1886                                 flash_address(bank, 0, 0x0))) != ERROR_OK)
1887                 {
1888                         return retval;
1889                 }
1890
1891                 LOG_ERROR("Buffer write at base 0x%" PRIx32
1892                                 ", address 0x%" PRIx32 " failed.", bank->base, address);
1893                 return ERROR_FLASH_OPERATION_FAILED;
1894         }
1895
1896         return ERROR_OK;
1897 }
1898
1899 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1900 {
1901         int retval;
1902         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1903         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1904         struct target *target = bank->target;
1905
1906         if ((retval = cfi_send_command(bank, 0xaa,
1907                         flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1908         {
1909                 return retval;
1910         }
1911
1912         if ((retval = cfi_send_command(bank, 0x55,
1913                         flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1914         {
1915                 return retval;
1916         }
1917
1918         if ((retval = cfi_send_command(bank, 0xa0,
1919                         flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1920         {
1921                 return retval;
1922         }
1923
1924         if ((retval = target_write_memory(target,
1925                         address, bank->bus_width, 1, word)) != ERROR_OK)
1926         {
1927                 return retval;
1928         }
1929
1930         if (cfi_spansion_wait_status_busy(bank, cfi_info->word_write_timeout) != ERROR_OK)
1931         {
1932                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1933                 {
1934                         return retval;
1935                 }
1936
1937                 LOG_ERROR("couldn't write word at base 0x%" PRIx32
1938                                 ", address 0x%" PRIx32 , bank->base, address);
1939                 return ERROR_FLASH_OPERATION_FAILED;
1940         }
1941
1942         return ERROR_OK;
1943 }
1944
1945 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word,
1946                 uint32_t wordcount, uint32_t address)
1947 {
1948         int retval;
1949         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1950         struct target *target = bank->target;
1951         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1952
1953         /* Calculate buffer size and boundary mask */
1954         /* buffersize is (buffer size per chip) * (number of chips) */
1955         /* bufferwsize is buffersize in words */
1956         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1957         uint32_t buffermask = buffersize-1;
1958         uint32_t bufferwsize = buffersize / bank->bus_width;
1959
1960         /* Check for valid range */
1961         if (address & buffermask)
1962         {
1963                 LOG_ERROR("Write address at base 0x%" PRIx32
1964                                 ", address 0x%" PRIx32 " not aligned to 2^%d boundary",
1965                                 bank->base, address, cfi_info->max_buf_write_size);
1966                 return ERROR_FLASH_OPERATION_FAILED;
1967         }
1968
1969         /* Check for valid size */
1970         if (wordcount > bufferwsize)
1971         {
1972                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %"
1973                                 PRId32, wordcount, buffersize);
1974                 return ERROR_FLASH_OPERATION_FAILED;
1975         }
1976
1977         /* Unlock */
1978         if ((retval = cfi_send_command(bank, 0xaa,
1979                         flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1980         {
1981                 return retval;
1982         }
1983
1984         if ((retval = cfi_send_command(bank, 0x55,
1985                         flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1986         {
1987                 return retval;
1988         }
1989
1990         /* Buffer load command */
1991         if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1992         {
1993                 return retval;
1994         }
1995
1996         /* Write buffer wordcount-1 and data words */
1997         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1998         {
1999                 return retval;
2000         }
2001
2002         if ((retval = target_write_memory(target,
2003                         address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
2004         {
2005                 return retval;
2006         }
2007
2008         /* Commit write operation */
2009         if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
2010         {
2011                 return retval;
2012         }
2013
2014         if (cfi_spansion_wait_status_busy(bank, cfi_info->buf_write_timeout) != ERROR_OK)
2015         {
2016                 if ((retval = cfi_send_command(bank, 0xf0,
2017                                 flash_address(bank, 0, 0x0))) != ERROR_OK)
2018                 {
2019                         return retval;
2020                 }
2021
2022                 LOG_ERROR("couldn't write block at base 0x%" PRIx32
2023                                 ", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address, bufferwsize);
2024                 return ERROR_FLASH_OPERATION_FAILED;
2025         }
2026
2027         return ERROR_OK;
2028 }
2029
2030 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
2031 {
2032         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2033
2034         switch (cfi_info->pri_id)
2035         {
2036                 case 1:
2037                 case 3:
2038                         return cfi_intel_write_word(bank, word, address);
2039                         break;
2040                 case 2:
2041                         return cfi_spansion_write_word(bank, word, address);
2042                         break;
2043                 default:
2044                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2045                         break;
2046         }
2047
2048         return ERROR_FLASH_OPERATION_FAILED;
2049 }
2050
2051 static int cfi_write_words(struct flash_bank *bank, uint8_t *word,
2052                 uint32_t wordcount, uint32_t address)
2053 {
2054         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2055
2056         if (cfi_info->buf_write_timeout_typ == 0)
2057         {
2058                 /* buffer writes are not supported */
2059                 LOG_DEBUG("Buffer Writes Not Supported");
2060                 return ERROR_FLASH_OPER_UNSUPPORTED;
2061         }
2062
2063         switch (cfi_info->pri_id)
2064         {
2065                 case 1:
2066                 case 3:
2067                         return cfi_intel_write_words(bank, word, wordcount, address);
2068                         break;
2069                 case 2:
2070                         return cfi_spansion_write_words(bank, word, wordcount, address);
2071                         break;
2072                 default:
2073                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2074                         break;
2075         }
2076
2077         return ERROR_FLASH_OPERATION_FAILED;
2078 }
2079
2080 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2081 {
2082         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2083         struct target *target = bank->target;
2084         uint32_t address = bank->base + offset;
2085         uint32_t read_p;
2086         int align;      /* number of unaligned bytes */
2087         uint8_t current_word[CFI_MAX_BUS_WIDTH];
2088         int i;
2089         int retval;
2090
2091         LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2092                 (int)count, (unsigned)offset);
2093
2094         if (bank->target->state != TARGET_HALTED)
2095         {
2096                 LOG_ERROR("Target not halted");
2097                 return ERROR_TARGET_NOT_HALTED;
2098         }
2099
2100         if (offset + count > bank->size)
2101                 return ERROR_FLASH_DST_OUT_OF_BANK;
2102
2103         if (cfi_info->qry[0] != 'Q')
2104                 return ERROR_FLASH_BANK_NOT_PROBED;
2105
2106         /* start at the first byte of the first word (bus_width size) */
2107         read_p = address & ~(bank->bus_width - 1);
2108         if ((align = address - read_p) != 0)
2109         {
2110                 LOG_INFO("Fixup %d unaligned read head bytes", align);
2111
2112                 /* read a complete word from flash */
2113                 if ((retval = target_read_memory(target, read_p,
2114                                 bank->bus_width, 1, current_word)) != ERROR_OK)
2115                         return retval;
2116
2117                 /* take only bytes we need */
2118                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2119                         *buffer++ = current_word[i];
2120
2121                 read_p += bank->bus_width;
2122         }
2123
2124         align = count / bank->bus_width;
2125         if (align)
2126         {
2127                 if ((retval = target_read_memory(target, read_p,
2128                                 bank->bus_width, align, buffer)) != ERROR_OK)
2129                         return retval;
2130
2131                 read_p += align * bank->bus_width;
2132                 buffer += align * bank->bus_width;
2133                 count -= align * bank->bus_width;
2134         }
2135
2136         if (count)
2137         {
2138                 LOG_INFO("Fixup %d unaligned read tail bytes", count);
2139
2140                 /* read a complete word from flash */
2141                 if ((retval = target_read_memory(target, read_p,
2142                                 bank->bus_width, 1, current_word)) != ERROR_OK)
2143                         return retval;
2144
2145                 /* take only bytes we need */
2146                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2147                         *buffer++ = current_word[i];
2148         }
2149
2150         return ERROR_OK;
2151 }
2152
2153 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2154 {
2155         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2156         struct target *target = bank->target;
2157         uint32_t address = bank->base + offset; /* address of first byte to be programmed */
2158         uint32_t write_p;
2159         int align;      /* number of unaligned bytes */
2160         int blk_count; /* number of bus_width bytes for block copy */
2161         uint8_t current_word[CFI_MAX_BUS_WIDTH * 4];    /* word (bus_width size) currently being programmed */
2162         int i;
2163         int retval;
2164
2165         if (bank->target->state != TARGET_HALTED)
2166         {
2167                 LOG_ERROR("Target not halted");
2168                 return ERROR_TARGET_NOT_HALTED;
2169         }
2170
2171         if (offset + count > bank->size)
2172                 return ERROR_FLASH_DST_OUT_OF_BANK;
2173
2174         if (cfi_info->qry[0] != 'Q')
2175                 return ERROR_FLASH_BANK_NOT_PROBED;
2176
2177         /* start at the first byte of the first word (bus_width size) */
2178         write_p = address & ~(bank->bus_width - 1);
2179         if ((align = address - write_p) != 0)
2180         {
2181                 LOG_INFO("Fixup %d unaligned head bytes", align);
2182
2183                 /* read a complete word from flash */
2184                 if ((retval = target_read_memory(target, write_p,
2185                                 bank->bus_width, 1, current_word)) != ERROR_OK)
2186                         return retval;
2187
2188                 /* replace only bytes that must be written */
2189                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2190                         current_word[i] = *buffer++;
2191
2192                 retval = cfi_write_word(bank, current_word, write_p);
2193                 if (retval != ERROR_OK)
2194                         return retval;
2195                 write_p += bank->bus_width;
2196         }
2197
2198         /* handle blocks of bus_size aligned bytes */
2199         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
2200         switch (cfi_info->pri_id)
2201         {
2202                 /* try block writes (fails without working area) */
2203                 case 1:
2204                 case 3:
2205                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
2206                         break;
2207                 case 2:
2208                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
2209                         break;
2210                 default:
2211                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2212                         retval = ERROR_FLASH_OPERATION_FAILED;
2213                         break;
2214         }
2215         if (retval == ERROR_OK)
2216         {
2217                 /* Increment pointers and decrease count on succesful block write */
2218                 buffer += blk_count;
2219                 write_p += blk_count;
2220                 count -= blk_count;
2221         }
2222         else
2223         {
2224                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
2225                 {
2226                         /* Calculate buffer size and boundary mask */
2227                         /* buffersize is (buffer size per chip) * (number of chips) */
2228                         /* bufferwsize is buffersize in words */
2229                         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2230                         uint32_t buffermask = buffersize-1;
2231                         uint32_t bufferwsize = buffersize / bank->bus_width;
2232
2233                         /* fall back to memory writes */
2234                         while (count >= (uint32_t)bank->bus_width)
2235                         {
2236                                 int fallback;
2237                                 if ((write_p & 0xff) == 0)
2238                                 {
2239                                         LOG_INFO("Programming at 0x%08" PRIx32 ", count 0x%08"
2240                                                         PRIx32 " bytes remaining", write_p, count);
2241                                 }
2242                                 fallback = 1;
2243                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
2244                                 {
2245                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2246                                         if (retval == ERROR_OK)
2247                                         {
2248                                                 buffer += buffersize;
2249                                                 write_p += buffersize;
2250                                                 count -= buffersize;
2251                                                 fallback = 0;
2252                                         }
2253                                         else if (retval != ERROR_FLASH_OPER_UNSUPPORTED)
2254                                                 return retval;
2255                                 }
2256                                 /* try the slow way? */
2257                                 if (fallback)
2258                                 {
2259                                         for (i = 0; i < bank->bus_width; i++)
2260                                                 current_word[i] = *buffer++;
2261
2262                                         retval = cfi_write_word(bank, current_word, write_p);
2263                                         if (retval != ERROR_OK)
2264                                                 return retval;
2265
2266                                         write_p += bank->bus_width;
2267                                         count -= bank->bus_width;
2268                                 }
2269                         }
2270                 }
2271                 else
2272                         return retval;
2273         }
2274
2275         /* return to read array mode, so we can read from flash again for padding */
2276         if ((retval = cfi_reset(bank)) != ERROR_OK)
2277         {
2278                 return retval;
2279         }
2280
2281         /* handle unaligned tail bytes */
2282         if (count > 0)
2283         {
2284                 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2285
2286                 /* read a complete word from flash */
2287                 if ((retval = target_read_memory(target, write_p,
2288                                 bank->bus_width, 1, current_word)) != ERROR_OK)
2289                         return retval;
2290
2291                 /* replace only bytes that must be written */
2292                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2293                         current_word[i] = *buffer++;
2294
2295                 retval = cfi_write_word(bank, current_word, write_p);
2296                 if (retval != ERROR_OK)
2297                         return retval;
2298         }
2299
2300         /* return to read array mode */
2301         return cfi_reset(bank);
2302 }
2303
2304 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param)
2305 {
2306         (void) param;
2307         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2308         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2309
2310         pri_ext->_reversed_geometry = 1;
2311 }
2312
2313 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2314 {
2315         int i;
2316         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2317         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2318         (void) param;
2319
2320         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2321         {
2322                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2323
2324                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2325                 {
2326                         int j = (cfi_info->num_erase_regions - 1) - i;
2327                         uint32_t swap;
2328
2329                         swap = cfi_info->erase_region_info[i];
2330                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2331                         cfi_info->erase_region_info[j] = swap;
2332                 }
2333         }
2334 }
2335
2336 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2337 {
2338         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2339         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2340         struct cfi_unlock_addresses *unlock_addresses = param;
2341
2342         pri_ext->_unlock1 = unlock_addresses->unlock1;
2343         pri_ext->_unlock2 = unlock_addresses->unlock2;
2344 }
2345
2346
2347 static int cfi_query_string(struct flash_bank *bank, int address)
2348 {
2349         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2350         int retval;
2351
2352         if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2353         {
2354                 return retval;
2355         }
2356
2357         retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
2358         if (retval != ERROR_OK)
2359                 return retval;
2360         retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
2361         if (retval != ERROR_OK)
2362                 return retval;
2363         retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
2364         if (retval != ERROR_OK)
2365                 return retval;
2366
2367         LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
2368                         cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2369
2370         if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2371         {
2372                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2373                 {
2374                         return retval;
2375                 }
2376                 LOG_ERROR("Could not probe bank: no QRY");
2377                 return ERROR_FLASH_BANK_INVALID;
2378         }
2379
2380         return ERROR_OK;
2381 }
2382
2383 static int cfi_probe(struct flash_bank *bank)
2384 {
2385         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2386         struct target *target = bank->target;
2387         int num_sectors = 0;
2388         int i;
2389         int sector = 0;
2390         uint32_t unlock1 = 0x555;
2391         uint32_t unlock2 = 0x2aa;
2392         int retval;
2393         uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2394
2395         if (bank->target->state != TARGET_HALTED)
2396         {
2397                 LOG_ERROR("Target not halted");
2398                 return ERROR_TARGET_NOT_HALTED;
2399         }
2400
2401         cfi_info->probed = 0;
2402         if (bank->sectors)
2403         {
2404                 free(bank->sectors);
2405                 bank->sectors = NULL;
2406         }
2407         if(cfi_info->erase_region_info)
2408         {
2409                 free(cfi_info->erase_region_info);
2410                 cfi_info->erase_region_info = NULL;
2411         }
2412
2413         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2414          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2415          */
2416         if (cfi_info->jedec_probe)
2417         {
2418                 unlock1 = 0x5555;
2419                 unlock2 = 0x2aaa;
2420         }
2421
2422         /* switch to read identifier codes mode ("AUTOSELECT") */
2423         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2424         {
2425                 return retval;
2426         }
2427         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2428         {
2429                 return retval;
2430         }
2431         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2432         {
2433                 return retval;
2434         }
2435
2436         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00),
2437                         bank->bus_width, 1, value_buf0)) != ERROR_OK)
2438         {
2439                 return retval;
2440         }
2441         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01),
2442                         bank->bus_width, 1, value_buf1)) != ERROR_OK)
2443         {
2444                 return retval;
2445         }
2446         switch (bank->chip_width) {
2447                 case 1:
2448                         cfi_info->manufacturer = *value_buf0;
2449                         cfi_info->device_id = *value_buf1;
2450                         break;
2451                 case 2:
2452                         cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2453                         cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2454                         break;
2455                 case 4:
2456                         cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2457                         cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2458                         break;
2459                 default:
2460                         LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
2461                         return ERROR_FLASH_OPERATION_FAILED;
2462         }
2463
2464         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x",
2465                         cfi_info->manufacturer, cfi_info->device_id);
2466         /* switch back to read array mode */
2467         if ((retval = cfi_reset(bank)) != ERROR_OK)
2468         {
2469                 return retval;
2470         }
2471
2472         /* check device/manufacturer ID for known non-CFI flashes. */
2473         cfi_fixup_non_cfi(bank);
2474
2475         /* query only if this is a CFI compatible flash,
2476          * otherwise the relevant info has already been filled in
2477          */
2478         if (cfi_info->not_cfi == 0)
2479         {
2480                 /* enter CFI query mode
2481                  * according to JEDEC Standard No. 68.01,
2482                  * a single bus sequence with address = 0x55, data = 0x98 should put
2483                  * the device into CFI query mode.
2484                  *
2485                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2486                  */
2487
2488                 retval = cfi_query_string(bank, 0x55);
2489                 if (retval != ERROR_OK)
2490                 {
2491                         /*
2492                          * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2493                          * be harmless enough:
2494                          *
2495                          * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2496                          */
2497                         LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2498                         retval = cfi_query_string(bank, 0x555);
2499                 }
2500                 if (retval != ERROR_OK)
2501                         return retval;
2502
2503                 retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
2504                 if (retval != ERROR_OK)
2505                         return retval;
2506                 retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
2507                 if (retval != ERROR_OK)
2508                         return retval;
2509                 retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
2510                 if (retval != ERROR_OK)
2511                         return retval;
2512                 retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
2513                 if (retval != ERROR_OK)
2514                         return retval;
2515
2516                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
2517                                 "0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1],
2518                                 cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr,
2519                                 cfi_info->alt_id, cfi_info->alt_addr);
2520
2521                 retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
2522                 if (retval != ERROR_OK)
2523                         return retval;
2524                 retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
2525                 if (retval != ERROR_OK)
2526                         return retval;
2527                 retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
2528                 if (retval != ERROR_OK)
2529                         return retval;
2530                 retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
2531                 if (retval != ERROR_OK)
2532                         return retval;
2533
2534                 retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
2535                 if (retval != ERROR_OK)
2536                         return retval;
2537                 retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
2538                 if (retval != ERROR_OK)
2539                         return retval;
2540                 retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
2541                 if (retval != ERROR_OK)
2542                         return retval;
2543                 retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
2544                 if (retval != ERROR_OK)
2545                         return retval;
2546                 retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
2547                 if (retval != ERROR_OK)
2548                         return retval;
2549                 retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
2550                 if (retval != ERROR_OK)
2551                         return retval;
2552                 retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
2553                 if (retval != ERROR_OK)
2554                         return retval;
2555                 retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
2556                 if (retval != ERROR_OK)
2557                         return retval;
2558
2559                 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2560                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2561                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2562                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2563                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2564
2565                 LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
2566                                 "typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms",
2567                                 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2568                                 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2569
2570                 LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
2571                                 "max. block erase timeout: %u ms, max. chip erase timeout: %u ms",
2572                                 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2573                                 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2574                                 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2575                                 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2576
2577                 /* convert timeouts to real values in ms */
2578                 cfi_info->word_write_timeout = DIV_ROUND_UP((1 << cfi_info->word_write_timeout_typ) *
2579                                                 (1 << cfi_info->word_write_timeout_max), 1000);
2580                 cfi_info->buf_write_timeout = DIV_ROUND_UP((1 << cfi_info->buf_write_timeout_typ) *
2581                                 (1 << cfi_info->buf_write_timeout_max), 1000);
2582                 cfi_info->block_erase_timeout = (1 << cfi_info->block_erase_timeout_typ) *
2583                                 (1 << cfi_info->block_erase_timeout_max);
2584                 cfi_info->chip_erase_timeout = (1 << cfi_info->chip_erase_timeout_typ) *
2585                                 (1 << cfi_info->chip_erase_timeout_max);
2586
2587                 LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
2588                                 "block erase timeout: %u ms, chip erase timeout: %u ms",
2589                                 cfi_info->word_write_timeout, cfi_info->buf_write_timeout,
2590                                 cfi_info->block_erase_timeout, cfi_info->chip_erase_timeout);
2591
2592                 uint8_t data;
2593                 retval = cfi_query_u8(bank, 0, 0x27, &data);
2594                 if (retval != ERROR_OK)
2595                         return retval;
2596                 cfi_info->dev_size = 1 << data;
2597
2598                 retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
2599                 if (retval != ERROR_OK)
2600                         return retval;
2601                 retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
2602                 if (retval != ERROR_OK)
2603                         return retval;
2604                 retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
2605                 if (retval != ERROR_OK)
2606                         return retval;
2607
2608                 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: 0x%x",
2609                                 cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2610
2611                 if (cfi_info->num_erase_regions)
2612                 {
2613                         cfi_info->erase_region_info = malloc(sizeof(*cfi_info->erase_region_info)
2614                                         * cfi_info->num_erase_regions);
2615                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2616                         {
2617                                 retval = cfi_query_u32(bank, 0, 0x2d + (4 * i), &cfi_info->erase_region_info[i]);
2618                                 if (retval != ERROR_OK)
2619                                         return retval;
2620                                 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "", i,
2621                                                 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2622                                                 (cfi_info->erase_region_info[i] >> 16) * 256);
2623                         }
2624                 }
2625                 else
2626                 {
2627                         cfi_info->erase_region_info = NULL;
2628                 }
2629
2630                 /* We need to read the primary algorithm extended query table before calculating
2631                  * the sector layout to be able to apply fixups
2632                  */
2633                 switch (cfi_info->pri_id)
2634                 {
2635                         /* Intel command set (standard and extended) */
2636                         case 0x0001:
2637                         case 0x0003:
2638                                 cfi_read_intel_pri_ext(bank);
2639                                 break;
2640                         /* AMD/Spansion, Atmel, ... command set */
2641                         case 0x0002:
2642                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2643                                 cfi_read_0002_pri_ext(bank);
2644                                 break;
2645                         default:
2646                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2647                                 break;
2648                 }
2649
2650                 /* return to read array mode
2651                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2652                  */
2653                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2654                 {
2655                         return retval;
2656                 }
2657         } /* end CFI case */
2658
2659         /* apply fixups depending on the primary command set */
2660         switch (cfi_info->pri_id)
2661         {
2662                 /* Intel command set (standard and extended) */
2663                 case 0x0001:
2664                 case 0x0003:
2665                         cfi_fixup(bank, cfi_0001_fixups);
2666                         break;
2667                 /* AMD/Spansion, Atmel, ... command set */
2668                 case 0x0002:
2669                         cfi_fixup(bank, cfi_0002_fixups);
2670                         break;
2671                 default:
2672                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2673                         break;
2674         }
2675
2676         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2677         {
2678                 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32
2679                                 " size flash was found", bank->size, cfi_info->dev_size);
2680         }
2681
2682         if (cfi_info->num_erase_regions == 0)
2683         {
2684                 /* a device might have only one erase block, spanning the whole device */
2685                 bank->num_sectors = 1;
2686                 bank->sectors = malloc(sizeof(struct flash_sector));
2687
2688                 bank->sectors[sector].offset = 0x0;
2689                 bank->sectors[sector].size = bank->size;
2690                 bank->sectors[sector].is_erased = -1;
2691                 bank->sectors[sector].is_protected = -1;
2692         }
2693         else
2694         {
2695                 uint32_t offset = 0;
2696
2697                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2698                 {
2699                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2700                 }
2701
2702                 bank->num_sectors = num_sectors;
2703                 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2704
2705                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2706                 {
2707                         uint32_t j;
2708                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2709                         {
2710                                 bank->sectors[sector].offset = offset;
2711                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256)
2712                                                 * bank->bus_width / bank->chip_width;
2713                                 offset += bank->sectors[sector].size;
2714                                 bank->sectors[sector].is_erased = -1;
2715                                 bank->sectors[sector].is_protected = -1;
2716                                 sector++;
2717                         }
2718                 }
2719                 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2720                 {
2721                         LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2722                                 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2723                 }
2724         }
2725
2726         cfi_info->probed = 1;
2727
2728         return ERROR_OK;
2729 }
2730
2731 static int cfi_auto_probe(struct flash_bank *bank)
2732 {
2733         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2734         if (cfi_info->probed)
2735                 return ERROR_OK;
2736         return cfi_probe(bank);
2737 }
2738
2739 static int cfi_intel_protect_check(struct flash_bank *bank)
2740 {
2741         int retval;
2742         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2743         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2744         int i;
2745
2746         /* check if block lock bits are supported on this device */
2747         if (!(pri_ext->blk_status_reg_mask & 0x1))
2748                 return ERROR_FLASH_OPERATION_FAILED;
2749
2750         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2751         {
2752                 return retval;
2753         }
2754
2755         for (i = 0; i < bank->num_sectors; i++)
2756         {
2757                 uint8_t block_status;
2758                 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2759                 if (retval != ERROR_OK)
2760                         return retval;
2761
2762                 if (block_status & 1)
2763                         bank->sectors[i].is_protected = 1;
2764                 else
2765                         bank->sectors[i].is_protected = 0;
2766         }
2767
2768         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2769 }
2770
2771 static int cfi_spansion_protect_check(struct flash_bank *bank)
2772 {
2773         int retval;
2774         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2775         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2776         int i;
2777
2778         if ((retval = cfi_send_command(bank, 0xaa,
2779                         flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2780         {
2781                 return retval;
2782         }
2783
2784         if ((retval = cfi_send_command(bank, 0x55,
2785                         flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2786         {
2787                 return retval;
2788         }
2789
2790         if ((retval = cfi_send_command(bank, 0x90,
2791                         flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2792         {
2793                 return retval;
2794         }
2795
2796         for (i = 0; i < bank->num_sectors; i++)
2797         {
2798                 uint8_t block_status;
2799                 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2800                 if (retval != ERROR_OK)
2801                         return retval;
2802
2803                 if (block_status & 1)
2804                         bank->sectors[i].is_protected = 1;
2805                 else
2806                         bank->sectors[i].is_protected = 0;
2807         }
2808
2809         return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2810 }
2811
2812 static int cfi_protect_check(struct flash_bank *bank)
2813 {
2814         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2815
2816         if (bank->target->state != TARGET_HALTED)
2817         {
2818                 LOG_ERROR("Target not halted");
2819                 return ERROR_TARGET_NOT_HALTED;
2820         }
2821
2822         if (cfi_info->qry[0] != 'Q')
2823                 return ERROR_FLASH_BANK_NOT_PROBED;
2824
2825         switch (cfi_info->pri_id)
2826         {
2827                 case 1:
2828                 case 3:
2829                         return cfi_intel_protect_check(bank);
2830                         break;
2831                 case 2:
2832                         return cfi_spansion_protect_check(bank);
2833                         break;
2834                 default:
2835                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2836                         break;
2837         }
2838
2839         return ERROR_OK;
2840 }
2841
2842 static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2843 {
2844         int printed;
2845         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2846
2847         if (cfi_info->qry[0] == 0xff)
2848         {
2849                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2850                 return ERROR_OK;
2851         }
2852
2853         if (cfi_info->not_cfi == 0)
2854                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2855         else
2856                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2857         buf += printed;
2858         buf_size -= printed;
2859
2860         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2861                 cfi_info->manufacturer, cfi_info->device_id);
2862         buf += printed;
2863         buf_size -= printed;
2864
2865         if (cfi_info->not_cfi == 0)
2866         {
2867                 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
2868                                 "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
2869                                 cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2],
2870                                 cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2871                 buf += printed;
2872                 buf_size -= printed;
2873
2874                 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, "
2875                                 "Vpp min: %u.%x, Vpp max: %u.%x\n",
2876                                 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2877                                 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2878                                 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2879                                 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2880                 buf += printed;
2881                 buf_size -= printed;
2882
2883                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u us, "
2884                                 "typ. buf write timeout: %u us, "
2885                                 "typ. block erase timeout: %u ms, "
2886                                 "typ. chip erase timeout: %u ms\n",
2887                                 1 << cfi_info->word_write_timeout_typ,
2888                                 1 << cfi_info->buf_write_timeout_typ,
2889                                 1 << cfi_info->block_erase_timeout_typ,
2890                                 1 << cfi_info->chip_erase_timeout_typ);
2891                 buf += printed;
2892                 buf_size -= printed;
2893
2894                 printed = snprintf(buf, buf_size, "max. word write timeout: %u us, "
2895                                 "max. buf write timeout: %u us, max. "
2896                                 "block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
2897                                 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2898                                 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2899                                 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2900                                 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2901                 buf += printed;
2902                 buf_size -= printed;
2903
2904                 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, "
2905                                 "max buffer write size: 0x%x\n",
2906                                 cfi_info->dev_size,
2907                                 cfi_info->interface_desc,
2908                                 1 << cfi_info->max_buf_write_size);
2909                 buf += printed;
2910                 buf_size -= printed;
2911
2912                 switch (cfi_info->pri_id)
2913                 {
2914                         case 1:
2915                         case 3:
2916                                 cfi_intel_info(bank, buf, buf_size);
2917                                 break;
2918                         case 2:
2919                                 cfi_spansion_info(bank, buf, buf_size);
2920                                 break;
2921                         default:
2922                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2923                                 break;
2924                 }
2925         }
2926
2927         return ERROR_OK;
2928 }
2929
2930 static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, void *param)
2931 {
2932         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2933
2934         /* disable write buffer for M29W128G */
2935         cfi_info->buf_write_timeout_typ = 0;
2936 }
2937
2938 struct flash_driver cfi_flash = {
2939         .name = "cfi",
2940         .flash_bank_command = cfi_flash_bank_command,
2941         .erase = cfi_erase,
2942         .protect = cfi_protect,
2943         .write = cfi_write,
2944         .read = cfi_read,
2945         .probe = cfi_probe,
2946         .auto_probe = cfi_auto_probe,
2947         /* FIXME: access flash at bus_width size */
2948         .erase_check = default_flash_blank_check,
2949         .protect_check = cfi_protect_check,
2950         .info = get_cfi_info,
2951 };