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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *   Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com>            *
   7  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "imp.h"
  29 #include "cfi.h"
  30 #include "non_cfi.h"
  31 #include <target/arm.h>
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34
  35
  36 #define CFI_MAX_BUS_WIDTH       4
  37 #define CFI_MAX_CHIP_WIDTH      4
  38
  39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  40 #define CFI_MAX_INTEL_CODESIZE 256
  41
  42 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
  43 {
  44         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  45         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  46 };
  47
  48 /* CFI fixups foward declarations */
  49 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
  50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
  51 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
  52
  53 /* fixup after reading cmdset 0002 primary query table */
  54 static const struct cfi_fixup cfi_0002_fixups[] = {
  55         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  56         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  57         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  58         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  59         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  60         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  61    {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  62         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  63         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  64         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  65         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  66         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  67         {0, 0, NULL, NULL}
  68 };
  69
  70 /* fixup after reading cmdset 0001 primary query table */
  71 static const struct cfi_fixup cfi_0001_fixups[] = {
  72         {0, 0, NULL, NULL}
  73 };
  74
  75 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
  76 {
  77         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  78         const struct cfi_fixup *f;
  79
  80         for (f = fixups; f->fixup; f++)
  81         {
  82                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
  83                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
  84                 {
  85                         f->fixup(bank, f->param);
  86                 }
  87         }
  88 }
  89
  90 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
  91 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
  92 {
  93         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  94
  95         if (cfi_info->x16_as_x8) offset *= 2;
  96
  97         /* while the sector list isn't built, only accesses to sector 0 work */
  98         if (sector == 0)
  99                 return bank->base + offset * bank->bus_width;
 100         else
 101         {
 102                 if (!bank->sectors)
 103                 {
 104                         LOG_ERROR("BUG: sector list not yet built");
 105                         exit(-1);
 106                 }
 107                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 108         }
 109 }
 110
 111 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
 112 {
 113         int i;
 114
 115         /* clear whole buffer, to ensure bits that exceed the bus_width
 116          * are set to zero
 117          */
 118         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 119                 cmd_buf[i] = 0;
 120
 121         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 122         {
 123                 for (i = bank->bus_width; i > 0; i--)
 124                 {
 125                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 126                 }
 127         }
 128         else
 129         {
 130                 for (i = 1; i <= bank->bus_width; i++)
 131                 {
 132                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 133                 }
 134         }
 135 }
 136
 137 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
 138 {
 139     uint8_t command[CFI_MAX_BUS_WIDTH];
 140
 141     cfi_command(bank, cmd, command);
 142     return target_write_memory(bank->target, address, bank->bus_width, 1, command);
 143 }
 144
 145 /* read unsigned 8-bit value from the bank
 146  * flash banks are expected to be made of similar chips
 147  * the query result should be the same for all
 148  */
 149 static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
 150 {
 151         struct target *target = bank->target;
 152         uint8_t data[CFI_MAX_BUS_WIDTH];
 153
 154         int retval;
 155         retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 156         if (retval != ERROR_OK)
 157                 return retval;
 158
 159         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 160                 *val = data[0];
 161         else
 162                 *val = data[bank->bus_width - 1];
 163
 164         return ERROR_OK;
 165 }
 166
 167 /* read unsigned 8-bit value from the bank
 168  * in case of a bank made of multiple chips,
 169  * the individual values are ORed
 170  */
 171 static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
 172 {
 173         struct target *target = bank->target;
 174         uint8_t data[CFI_MAX_BUS_WIDTH];
 175         int i;
 176
 177         int retval;
 178         retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 179         if (retval != ERROR_OK)
 180                 return retval;
 181
 182         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 183         {
 184                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 185                         data[0] |= data[i];
 186
 187                 *val = data[0];
 188         }
 189         else
 190         {
 191                 uint8_t value = 0;
 192                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 193                         value |= data[bank->bus_width - 1 - i];
 194
 195                 *val = value;
 196         }
 197         return ERROR_OK;
 198 }
 199
 200 static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
 201 {
 202         struct target *target = bank->target;
 203         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 204         uint8_t data[CFI_MAX_BUS_WIDTH * 2];
 205         int retval;
 206
 207         if (cfi_info->x16_as_x8)
 208         {
 209                 uint8_t i;
 210                 for (i = 0;i < 2;i++)
 211                 {
 212                         retval = target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 213                                 &data[i*bank->bus_width]);
 214                         if (retval != ERROR_OK)
 215                                 return retval;
 216                 }
 217         } else
 218         {
 219                 retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 220                 if (retval != ERROR_OK)
 221                         return retval;
 222         }
 223
 224         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 225                 *val = data[0] | data[bank->bus_width] << 8;
 226         else
 227                 *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 228
 229         return ERROR_OK;
 230 }
 231
 232 static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
 233 {
 234         struct target *target = bank->target;
 235         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 236         uint8_t data[CFI_MAX_BUS_WIDTH * 4];
 237         int retval;
 238
 239         if (cfi_info->x16_as_x8)
 240         {
 241                 uint8_t i;
 242                 for (i = 0;i < 4;i++)
 243                 {
 244                         retval = target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 245                                 &data[i*bank->bus_width]);
 246                         if (retval != ERROR_OK)
 247                                 return retval;
 248                 }
 249         }
 250         else
 251         {
 252                 retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 253                 if (retval != ERROR_OK)
 254                         return retval;
 255         }
 256
 257         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 258                 *val = data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 259         else
 260                 *val = data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 261                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 262
 263         return ERROR_OK;
 264 }
 265
 266 static int cfi_reset(struct flash_bank *bank)
 267 {
 268         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 269         int retval = ERROR_OK;
 270
 271         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 272         {
 273                 return retval;
 274         }
 275
 276         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 277         {
 278                 return retval;
 279         }
 280
 281         if (cfi_info->manufacturer == 0x20 &&
 282                         (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
 283         {
 284                 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
 285                  * so we send an extra 0xF0 reset to fix the bug */
 286                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
 287                 {
 288                         return retval;
 289                 }
 290         }
 291
 292         return retval;
 293 }
 294
 295 static void cfi_intel_clear_status_register(struct flash_bank *bank)
 296 {
 297         struct target *target = bank->target;
 298
 299         if (target->state != TARGET_HALTED)
 300         {
 301                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 302                 exit(-1);
 303         }
 304
 305         cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
 306 }
 307
 308 static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
 309 {
 310         uint8_t status;
 311
 312         int retval = ERROR_OK;
 313
 314         for (;;)
 315         {
 316                 if (timeout-- < 0)
 317                 {
 318                   LOG_ERROR("timeout while waiting for WSM to become ready");
 319                   return ERROR_FAIL;
 320                 }
 321
 322                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 323                 if (retval != ERROR_OK)
 324                         return retval;
 325
 326                 if (status & 0x80)
 327                         break;
 328
 329                 alive_sleep(1);
 330         }
 331
 332         /* mask out bit 0 (reserved) */
 333         status = status & 0xfe;
 334
 335         LOG_DEBUG("status: 0x%x", status);
 336
 337         if (status != 0x80)
 338         {
 339                 LOG_ERROR("status register: 0x%x", status);
 340                 if (status & 0x2)
 341                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 342                 if (status & 0x4)
 343                         LOG_ERROR("Program suspended");
 344                 if (status & 0x8)
 345                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 346                 if (status & 0x10)
 347                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 348                 if (status & 0x20)
 349                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 350                 if (status & 0x40)
 351                         LOG_ERROR("Block Erase Suspended");
 352
 353                 cfi_intel_clear_status_register(bank);
 354
 355                 retval = ERROR_FAIL;
 356         }
 357
 358         *val = status;
 359         return retval;
 360 }
 361
 362 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
 363 {
 364         uint8_t status, oldstatus;
 365         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 366         int retval;
 367
 368         retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
 369         if (retval != ERROR_OK)
 370                 return retval;
 371
 372         do {
 373                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 374
 375                 if (retval != ERROR_OK)
 376                         return retval;
 377
 378                 if ((status ^ oldstatus) & 0x40) {
 379                         if (status & cfi_info->status_poll_mask & 0x20) {
 380                                 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
 381                                 if (retval != ERROR_OK)
 382                                         return retval;
 383                                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 384                                 if (retval != ERROR_OK)
 385                                         return retval;
 386                                 if ((status ^ oldstatus) & 0x40) {
 387                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 388                                         return(ERROR_FLASH_OPERATION_FAILED);
 389                                 } else {
 390                                         LOG_DEBUG("status: 0x%x", status);
 391                                         return(ERROR_OK);
 392                                 }
 393                         }
 394                 } else { /* no toggle: finished, OK */
 395                         LOG_DEBUG("status: 0x%x", status);
 396                         return(ERROR_OK);
 397                 }
 398
 399                 oldstatus = status;
 400                 alive_sleep(1);
 401         } while (timeout-- > 0);
 402
 403         LOG_ERROR("timeout, status: 0x%x", status);
 404
 405         return(ERROR_FLASH_BUSY);
 406 }
 407
 408 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
 409 {
 410         int retval;
 411         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 412         struct cfi_intel_pri_ext *pri_ext;
 413
 414         if (cfi_info->pri_ext)
 415                 free(cfi_info->pri_ext);
 416
 417         pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
 418         if (pri_ext == NULL)
 419         {
 420                 LOG_ERROR("Out of memory");
 421                 return ERROR_FAIL;
 422         }
 423         cfi_info->pri_ext = pri_ext;
 424
 425         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
 426         if (retval != ERROR_OK)
 427                 return retval;
 428         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
 429         if (retval != ERROR_OK)
 430                 return retval;
 431         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
 432         if (retval != ERROR_OK)
 433                 return retval;
 434
 435         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 436         {
 437                 if ((retval = cfi_reset(bank)) != ERROR_OK)
 438                 {
 439                         return retval;
 440                 }
 441                 LOG_ERROR("Could not read bank flash bank information");
 442                 return ERROR_FLASH_BANK_INVALID;
 443         }
 444
 445         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
 446         if (retval != ERROR_OK)
 447                 return retval;
 448         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
 449         if (retval != ERROR_OK)
 450                 return retval;
 451
 452         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 453
 454         retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
 455         if (retval != ERROR_OK)
 456                 return retval;
 457         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
 458         if (retval != ERROR_OK)
 459                 return retval;
 460         retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
 461         if (retval != ERROR_OK)
 462                 return retval;
 463
 464         LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
 465                   pri_ext->feature_support,
 466                   pri_ext->suspend_cmd_support,
 467                   pri_ext->blk_status_reg_mask);
 468
 469         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
 470         if (retval != ERROR_OK)
 471                 return retval;
 472         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
 473         if (retval != ERROR_OK)
 474                 return retval;
 475
 476         LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
 477                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 478                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 479
 480         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
 481         if (retval != ERROR_OK)
 482                 return retval;
 483         if (pri_ext->num_protection_fields != 1)
 484         {
 485                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 486         }
 487
 488         retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
 489         if (retval != ERROR_OK)
 490                 return retval;
 491         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
 492         if (retval != ERROR_OK)
 493                 return retval;
 494         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
 495         if (retval != ERROR_OK)
 496                 return retval;
 497
 498         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 499
 500         return ERROR_OK;
 501 }
 502
 503 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
 504 {
 505         int retval;
 506         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 507         struct cfi_spansion_pri_ext *pri_ext;
 508
 509         if (cfi_info->pri_ext)
 510                 free(cfi_info->pri_ext);
 511
 512         pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 513         if (pri_ext == NULL)
 514         {
 515                 LOG_ERROR("Out of memory");
 516                 return ERROR_FAIL;
 517         }
 518         cfi_info->pri_ext = pri_ext;
 519
 520         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
 521         if (retval != ERROR_OK)
 522                 return retval;
 523         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
 524         if (retval != ERROR_OK)
 525                 return retval;
 526         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
 527         if (retval != ERROR_OK)
 528                 return retval;
 529
 530         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 531         {
 532                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 533                 {
 534                         return retval;
 535                 }
 536                 LOG_ERROR("Could not read spansion bank information");
 537                 return ERROR_FLASH_BANK_INVALID;
 538         }
 539
 540         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
 541         if (retval != ERROR_OK)
 542                 return retval;
 543         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
 544         if (retval != ERROR_OK)
 545                 return retval;
 546
 547         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 548
 549         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
 550         if (retval != ERROR_OK)
 551                 return retval;
 552         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
 553         if (retval != ERROR_OK)
 554                 return retval;
 555         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
 556         if (retval != ERROR_OK)
 557                 return retval;
 558         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
 559         if (retval != ERROR_OK)
 560                 return retval;
 561         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
 562         if (retval != ERROR_OK)
 563                 return retval;
 564         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
 565         if (retval != ERROR_OK)
 566                 return retval;
 567         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
 568         if (retval != ERROR_OK)
 569                 return retval;
 570         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
 571         if (retval != ERROR_OK)
 572                 return retval;
 573         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
 574         if (retval != ERROR_OK)
 575                 return retval;
 576         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
 577         if (retval != ERROR_OK)
 578                 return retval;
 579         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
 580         if (retval != ERROR_OK)
 581                 return retval;
 582
 583         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 584               pri_ext->EraseSuspend, pri_ext->BlkProt);
 585
 586         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 587               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 588
 589         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 590
 591
 592         LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
 593                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 594                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 595
 596         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 597
 598         /* default values for implementation specific workarounds */
 599         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 600         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 601         pri_ext->_reversed_geometry = 0;
 602
 603         return ERROR_OK;
 604 }
 605
 606 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
 607 {
 608         int retval;
 609         struct cfi_atmel_pri_ext atmel_pri_ext;
 610         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 611         struct cfi_spansion_pri_ext *pri_ext;
 612
 613         if (cfi_info->pri_ext)
 614                 free(cfi_info->pri_ext);
 615
 616         pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 617         if (pri_ext == NULL)
 618         {
 619                 LOG_ERROR("Out of memory");
 620                 return ERROR_FAIL;
 621         }
 622
 623         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 624          * but a different primary extended query table.
 625          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 626          */
 627
 628         memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
 629
 630         cfi_info->pri_ext = pri_ext;
 631
 632         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
 633         if (retval != ERROR_OK)
 634                 return retval;
 635         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
 636         if (retval != ERROR_OK)
 637                 return retval;
 638         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
 639         if (retval != ERROR_OK)
 640                 return retval;
 641
 642         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 643         {
 644                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 645                 {
 646                         return retval;
 647                 }
 648                 LOG_ERROR("Could not read atmel bank information");
 649                 return ERROR_FLASH_BANK_INVALID;
 650         }
 651
 652         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 653         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 654         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 655
 656         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
 657         if (retval != ERROR_OK)
 658                 return retval;
 659         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
 660         if (retval != ERROR_OK)
 661                 return retval;
 662
 663         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 664
 665         pri_ext->major_version = atmel_pri_ext.major_version;
 666         pri_ext->minor_version = atmel_pri_ext.minor_version;
 667
 668         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
 669         if (retval != ERROR_OK)
 670                 return retval;
 671         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
 672         if (retval != ERROR_OK)
 673                 return retval;
 674         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
 675         if (retval != ERROR_OK)
 676                 return retval;
 677         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
 678         if (retval != ERROR_OK)
 679                 return retval;
 680
 681         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 682                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 683
 684         if (atmel_pri_ext.features & 0x02)
 685                 pri_ext->EraseSuspend = 2;
 686
 687         if (atmel_pri_ext.bottom_boot)
 688                 pri_ext->TopBottom = 2;
 689         else
 690                 pri_ext->TopBottom = 3;
 691
 692         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 693         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 694
 695         return ERROR_OK;
 696 }
 697
 698 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
 699 {
 700         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 701
 702         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 703         {
 704                 return cfi_read_atmel_pri_ext(bank);
 705         }
 706         else
 707         {
 708                 return cfi_read_spansion_pri_ext(bank);
 709         }
 710 }
 711
 712 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
 713 {
 714         int printed;
 715         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 716         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 717
 718         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 719         buf += printed;
 720         buf_size -= printed;
 721
 722         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 723                            pri_ext->pri[1], pri_ext->pri[2],
 724                            pri_ext->major_version, pri_ext->minor_version);
 725         buf += printed;
 726         buf_size -= printed;
 727
 728         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 729                            (pri_ext->SiliconRevision) >> 2,
 730                            (pri_ext->SiliconRevision) & 0x03);
 731         buf += printed;
 732         buf_size -= printed;
 733
 734         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 735                            pri_ext->EraseSuspend,
 736                            pri_ext->BlkProt);
 737         buf += printed;
 738         buf_size -= printed;
 739
 740         printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
 741                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 742                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 743
 744         return ERROR_OK;
 745 }
 746
 747 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
 748 {
 749         int printed;
 750         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 751         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 752
 753         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 754         buf += printed;
 755         buf_size -= printed;
 756
 757         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 758         buf += printed;
 759         buf_size -= printed;
 760
 761         printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 762         buf += printed;
 763         buf_size -= printed;
 764
 765         printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
 766                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 767                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 768         buf += printed;
 769         buf_size -= printed;
 770
 771         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 772
 773         return ERROR_OK;
 774 }
 775
 776 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 777  */
 778 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
 779 {
 780         struct cfi_flash_bank *cfi_info;
 781
 782         if (CMD_ARGC < 6)
 783         {
 784                 LOG_WARNING("incomplete flash_bank cfi configuration");
 785                 return ERROR_FLASH_BANK_INVALID;
 786         }
 787
 788         /* both widths must:
 789          * - not exceed max value;
 790          * - not be null;
 791          * - be equal to a power of 2.
 792          * bus must be wide enought to hold one chip */
 793         if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
 794                         || (bank->bus_width > CFI_MAX_BUS_WIDTH)
 795                         || (bank->chip_width == 0)
 796                         || (bank->bus_width == 0)
 797                         || (bank->chip_width & (bank->chip_width - 1))
 798                         || (bank->bus_width & (bank->bus_width - 1))
 799                         || (bank->chip_width > bank->bus_width))
 800         {
 801                 LOG_ERROR("chip and bus width have to specified in bytes");
 802                 return ERROR_FLASH_BANK_INVALID;
 803         }
 804
 805         cfi_info = malloc(sizeof(struct cfi_flash_bank));
 806         cfi_info->probed = 0;
 807         cfi_info->erase_region_info = 0;
 808         cfi_info->pri_ext = NULL;
 809         bank->driver_priv = cfi_info;
 810
 811         cfi_info->write_algorithm = NULL;
 812
 813         cfi_info->x16_as_x8 = 0;
 814         cfi_info->jedec_probe = 0;
 815         cfi_info->not_cfi = 0;
 816
 817         for (unsigned i = 6; i < CMD_ARGC; i++)
 818         {
 819                 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
 820                 {
 821                         cfi_info->x16_as_x8 = 1;
 822                 }
 823                 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
 824                 {
 825                         cfi_info->jedec_probe = 1;
 826                 }
 827         }
 828
 829         cfi_info->write_algorithm = NULL;
 830
 831         /* bank wasn't probed yet */
 832         cfi_info->qry[0] = 0xff;
 833
 834         return ERROR_OK;
 835 }
 836
 837 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
 838 {
 839         int retval;
 840         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 841         int i;
 842
 843         cfi_intel_clear_status_register(bank);
 844
 845         for (i = first; i <= last; i++)
 846         {
 847                 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
 848                 {
 849                         return retval;
 850                 }
 851
 852                 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
 853                 {
 854                         return retval;
 855                 }
 856
 857                 uint8_t status;
 858                 retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ), &status);
 859                 if (retval != ERROR_OK)
 860                         return retval;
 861
 862                 if (status == 0x80)
 863                         bank->sectors[i].is_erased = 1;
 864                 else
 865                 {
 866                         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 867                         {
 868                                 return retval;
 869                         }
 870
 871                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
 872                         return ERROR_FLASH_OPERATION_FAILED;
 873                 }
 874         }
 875
 876         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
 877 }
 878
 879 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
 880 {
 881         int retval;
 882         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 883         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 884         int i;
 885
 886         for (i = first; i <= last; i++)
 887         {
 888                 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 889                 {
 890                         return retval;
 891                 }
 892
 893                 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 894                 {
 895                         return retval;
 896                 }
 897
 898                 if ((retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 899                 {
 900                         return retval;
 901                 }
 902
 903                 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 904                 {
 905                         return retval;
 906                 }
 907
 908                 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 909                 {
 910                         return retval;
 911                 }
 912
 913                 if ((retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0))) != ERROR_OK)
 914                 {
 915                         return retval;
 916                 }
 917
 918                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 919                         bank->sectors[i].is_erased = 1;
 920                 else
 921                 {
 922                         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 923                         {
 924                                 return retval;
 925                         }
 926
 927                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
 928                         return ERROR_FLASH_OPERATION_FAILED;
 929                 }
 930         }
 931
 932         return  cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
 933 }
 934
 935 static int cfi_erase(struct flash_bank *bank, int first, int last)
 936 {
 937         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 938
 939         if (bank->target->state != TARGET_HALTED)
 940         {
 941                 LOG_ERROR("Target not halted");
 942                 return ERROR_TARGET_NOT_HALTED;
 943         }
 944
 945         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 946         {
 947                 return ERROR_FLASH_SECTOR_INVALID;
 948         }
 949
 950         if (cfi_info->qry[0] != 'Q')
 951                 return ERROR_FLASH_BANK_NOT_PROBED;
 952
 953         switch (cfi_info->pri_id)
 954         {
 955                 case 1:
 956                 case 3:
 957                         return cfi_intel_erase(bank, first, last);
 958                         break;
 959                 case 2:
 960                         return cfi_spansion_erase(bank, first, last);
 961                         break;
 962                 default:
 963                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 964                         break;
 965         }
 966
 967         return ERROR_OK;
 968 }
 969
 970 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
 971 {
 972         int retval;
 973         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 974         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 975         int retry = 0;
 976         int i;
 977
 978         /* if the device supports neither legacy lock/unlock (bit 3) nor
 979          * instant individual block locking (bit 5).
 980          */
 981         if (!(pri_ext->feature_support & 0x28))
 982         {
 983                 LOG_ERROR("lock/unlock not supported on flash");
 984                 return ERROR_FLASH_OPERATION_FAILED;
 985         }
 986
 987         cfi_intel_clear_status_register(bank);
 988
 989         for (i = first; i <= last; i++)
 990         {
 991                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
 992                 {
 993                         return retval;
 994                 }
 995                 if (set)
 996                 {
 997                         if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
 998                         {
 999                                 return retval;
1000                         }
1001                         bank->sectors[i].is_protected = 1;
1002                 }
1003                 else
1004                 {
1005                         if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
1006                         {
1007                                 return retval;
1008                         }
1009                         bank->sectors[i].is_protected = 0;
1010                 }
1011
1012                 /* instant individual block locking doesn't require reading of the status register */
1013                 if (!(pri_ext->feature_support & 0x20))
1014                 {
1015                         /* Clear lock bits operation may take up to 1.4s */
1016                         uint8_t status;
1017                         retval = cfi_intel_wait_status_busy(bank, 1400, &status);
1018                         if (retval != ERROR_OK)
1019                                 return retval;
1020                 }
1021                 else
1022                 {
1023                         uint8_t block_status;
1024                         /* read block lock bit, to verify status */
1025                         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
1026                         {
1027                                 return retval;
1028                         }
1029                         retval = cfi_get_u8(bank, i, 0x2, &block_status);
1030                         if (retval != ERROR_OK)
1031                                 return retval;
1032
1033                         if ((block_status & 0x1) != set)
1034                         {
1035                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
1036                                 if ((retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55))) != ERROR_OK)
1037                                 {
1038                                         return retval;
1039                                 }
1040                                 uint8_t status;
1041                                 retval = cfi_intel_wait_status_busy(bank, 10, &status);
1042                                 if (retval != ERROR_OK)
1043                                         return retval;
1044
1045                                 if (retry > 10)
1046                                         return ERROR_FLASH_OPERATION_FAILED;
1047                                 else
1048                                 {
1049                                         i--;
1050                                         retry++;
1051                                 }
1052                         }
1053                 }
1054         }
1055
1056         /* if the device doesn't support individual block lock bits set/clear,
1057          * all blocks have been unlocked in parallel, so we set those that should be protected
1058          */
1059         if ((!set) && (!(pri_ext->feature_support & 0x20)))
1060         {
1061                 /* FIX!!! this code path is broken!!!
1062                  *
1063                  * The correct approach is:
1064                  *
1065                  * 1. read out current protection status
1066                  *
1067                  * 2. override read out protection status w/unprotected.
1068                  *
1069                  * 3. re-protect what should be protected.
1070                  *
1071                  */
1072                 for (i = 0; i < bank->num_sectors; i++)
1073                 {
1074                         if (bank->sectors[i].is_protected == 1)
1075                         {
1076                                 cfi_intel_clear_status_register(bank);
1077
1078                                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
1079                                 {
1080                                         return retval;
1081                                 }
1082
1083                                 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
1084                                 {
1085                                         return retval;
1086                                 }
1087
1088                                 uint8_t status;
1089                                 retval = cfi_intel_wait_status_busy(bank, 100, &status);
1090                                 if (retval != ERROR_OK)
1091                                         return retval;
1092                         }
1093                 }
1094         }
1095
1096         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
1097 }
1098
1099 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
1100 {
1101         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1102
1103         if (bank->target->state != TARGET_HALTED)
1104         {
1105                 LOG_ERROR("Target not halted");
1106                 return ERROR_TARGET_NOT_HALTED;
1107         }
1108
1109         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
1110         {
1111                 LOG_ERROR("Invalid sector range");
1112                 return ERROR_FLASH_SECTOR_INVALID;
1113         }
1114
1115         if (cfi_info->qry[0] != 'Q')
1116                 return ERROR_FLASH_BANK_NOT_PROBED;
1117
1118         switch (cfi_info->pri_id)
1119         {
1120                 case 1:
1121                 case 3:
1122                         return cfi_intel_protect(bank, set, first, last);
1123                         break;
1124                 default:
1125                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
1126                         return ERROR_FAIL;
1127         }
1128 }
1129
1130 /* Convert code image to target endian */
1131 /* FIXME create general block conversion fcts in target.c?) */
1132 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
1133 {
1134         uint32_t i;
1135         for (i = 0; i< count; i++)
1136         {
1137                 target_buffer_set_u32(target, dest, *src);
1138                 dest += 4;
1139                 src++;
1140         }
1141 }
1142
1143 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
1144 {
1145         struct target *target = bank->target;
1146
1147         uint8_t buf[CFI_MAX_BUS_WIDTH];
1148         cfi_command(bank, cmd, buf);
1149         switch (bank->bus_width)
1150         {
1151         case 1 :
1152                 return buf[0];
1153                 break;
1154         case 2 :
1155                 return target_buffer_get_u16(target, buf);
1156                 break;
1157         case 4 :
1158                 return target_buffer_get_u32(target, buf);
1159                 break;
1160         default :
1161                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1162                 return 0;
1163         }
1164 }
1165
1166 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1167 {
1168         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1169         struct target *target = bank->target;
1170         struct reg_param reg_params[7];
1171         struct arm_algorithm armv4_5_info;
1172         struct working_area *source;
1173         uint32_t buffer_size = 32768;
1174         uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1175
1176         /* algorithm register usage:
1177          * r0: source address (in RAM)
1178          * r1: target address (in Flash)
1179          * r2: count
1180          * r3: flash write command
1181          * r4: status byte (returned to host)
1182          * r5: busy test pattern
1183          * r6: error test pattern
1184          */
1185
1186         static const uint32_t word_32_code[] = {
1187                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1188                 0xe5813000,   /*                str r3, [r1] */
1189                 0xe5814000,   /*                str r4, [r1] */
1190                 0xe5914000,   /* busy:  ldr r4, [r1] */
1191                 0xe0047005,   /*                and r7, r4, r5 */
1192                 0xe1570005,   /*                cmp r7, r5 */
1193                 0x1afffffb,   /*                bne busy */
1194                 0xe1140006,   /*                tst r4, r6 */
1195                 0x1a000003,   /*                bne done */
1196                 0xe2522001,   /*                subs r2, r2, #1 */
1197                 0x0a000001,   /*                beq done */
1198                 0xe2811004,   /*                add r1, r1 #4 */
1199                 0xeafffff2,   /*                b loop */
1200                 0xeafffffe    /* done:  b -2 */
1201         };
1202
1203         static const uint32_t word_16_code[] = {
1204                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1205                 0xe1c130b0,   /*                strh r3, [r1] */
1206                 0xe1c140b0,   /*                strh r4, [r1] */
1207                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1208                 0xe0047005,   /*                and r7, r4, r5 */
1209                 0xe1570005,   /*                cmp r7, r5 */
1210                 0x1afffffb,   /*                bne busy */
1211                 0xe1140006,   /*                tst r4, r6 */
1212                 0x1a000003,   /*                bne done */
1213                 0xe2522001,   /*                subs r2, r2, #1 */
1214                 0x0a000001,   /*                beq done */
1215                 0xe2811002,   /*                add r1, r1 #2 */
1216                 0xeafffff2,   /*                b loop */
1217                 0xeafffffe    /* done:  b -2 */
1218         };
1219
1220         static const uint32_t word_8_code[] = {
1221                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1222                 0xe5c13000,   /*                strb r3, [r1] */
1223                 0xe5c14000,   /*                strb r4, [r1] */
1224                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1225                 0xe0047005,   /*                and r7, r4, r5 */
1226                 0xe1570005,   /*                cmp r7, r5 */
1227                 0x1afffffb,   /*                bne busy */
1228                 0xe1140006,   /*                tst r4, r6 */
1229                 0x1a000003,   /*                bne done */
1230                 0xe2522001,   /*                subs r2, r2, #1 */
1231                 0x0a000001,   /*                beq done */
1232                 0xe2811001,   /*                add r1, r1 #1 */
1233                 0xeafffff2,   /*                b loop */
1234                 0xeafffffe    /* done:  b -2 */
1235         };
1236         uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1237         const uint32_t *target_code_src;
1238         uint32_t target_code_size;
1239         int retval = ERROR_OK;
1240
1241
1242         cfi_intel_clear_status_register(bank);
1243
1244         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1245         armv4_5_info.core_mode = ARM_MODE_SVC;
1246         armv4_5_info.core_state = ARM_STATE_ARM;
1247
1248         /* If we are setting up the write_algorith, we need target_code_src */
1249         /* if not we only need target_code_size. */
1250
1251         /* However, we don't want to create multiple code paths, so we */
1252         /* do the unecessary evaluation of target_code_src, which the */
1253         /* compiler will probably nicely optimize away if not needed */
1254
1255         /* prepare algorithm code for target endian */
1256         switch (bank->bus_width)
1257         {
1258         case 1 :
1259                 target_code_src = word_8_code;
1260                 target_code_size = sizeof(word_8_code);
1261                 break;
1262         case 2 :
1263                 target_code_src = word_16_code;
1264                 target_code_size = sizeof(word_16_code);
1265                 break;
1266         case 4 :
1267                 target_code_src = word_32_code;
1268                 target_code_size = sizeof(word_32_code);
1269                 break;
1270         default:
1271                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1272                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1273         }
1274
1275         /* flash write code */
1276         if (!cfi_info->write_algorithm)
1277         {
1278                 if (target_code_size > sizeof(target_code))
1279                 {
1280                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1281                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1282                 }
1283                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1284
1285                 /* Get memory for block write handler */
1286                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1287                 if (retval != ERROR_OK)
1288                 {
1289                         LOG_WARNING("No working area available, can't do block memory writes");
1290                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1291                 };
1292
1293                 /* write algorithm code to working area */
1294                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1295                 if (retval != ERROR_OK)
1296                 {
1297                         LOG_ERROR("Unable to write block write code to target");
1298                         goto cleanup;
1299                 }
1300         }
1301
1302         /* Get a workspace buffer for the data to flash starting with 32k size.
1303            Half size until buffer would be smaller 256 Bytem then fail back */
1304         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1305         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1306         {
1307                 buffer_size /= 2;
1308                 if (buffer_size <= 256)
1309                 {
1310                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1311                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1312                         goto cleanup;
1313                 }
1314         };
1315
1316         /* setup algo registers */
1317         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1318         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1319         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1320         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1321         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1322         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1323         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1324
1325         /* prepare command and status register patterns */
1326         write_command_val = cfi_command_val(bank, 0x40);
1327         busy_pattern_val  = cfi_command_val(bank, 0x80);
1328         error_pattern_val = cfi_command_val(bank, 0x7e);
1329
1330         LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1331
1332         /* Programming main loop */
1333         while (count > 0)
1334         {
1335                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1336                 uint32_t wsm_error;
1337
1338                 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1339                 {
1340                         goto cleanup;
1341                 }
1342
1343                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1344                 buf_set_u32(reg_params[1].value, 0, 32, address);
1345                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1346
1347                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1348                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1349                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1350
1351                 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1352
1353                 /* Execute algorithm, assume breakpoint for last instruction */
1354                 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1355                         cfi_info->write_algorithm->address,
1356                         cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1357                         10000, /* 10s should be enough for max. 32k of data */
1358                         &armv4_5_info);
1359
1360                 /* On failure try a fall back to direct word writes */
1361                 if (retval != ERROR_OK)
1362                 {
1363                         cfi_intel_clear_status_register(bank);
1364                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1365                         retval = ERROR_FLASH_OPERATION_FAILED;
1366                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1367                         /* FIXME To allow fall back or recovery, we must save the actual status
1368                            somewhere, so that a higher level code can start recovery. */
1369                         goto cleanup;
1370                 }
1371
1372                 /* Check return value from algo code */
1373                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1374                 if (wsm_error)
1375                 {
1376                         /* read status register (outputs debug inforation) */
1377                         uint8_t status;
1378                         cfi_intel_wait_status_busy(bank, 100, &status);
1379                         cfi_intel_clear_status_register(bank);
1380                         retval = ERROR_FLASH_OPERATION_FAILED;
1381                         goto cleanup;
1382                 }
1383
1384                 buffer += thisrun_count;
1385                 address += thisrun_count;
1386                 count -= thisrun_count;
1387
1388                 keep_alive();
1389         }
1390
1391         /* free up resources */
1392 cleanup:
1393         if (source)
1394                 target_free_working_area(target, source);
1395
1396         if (cfi_info->write_algorithm)
1397         {
1398                 target_free_working_area(target, cfi_info->write_algorithm);
1399                 cfi_info->write_algorithm = NULL;
1400         }
1401
1402         destroy_reg_param(&reg_params[0]);
1403         destroy_reg_param(&reg_params[1]);
1404         destroy_reg_param(&reg_params[2]);
1405         destroy_reg_param(&reg_params[3]);
1406         destroy_reg_param(&reg_params[4]);
1407         destroy_reg_param(&reg_params[5]);
1408         destroy_reg_param(&reg_params[6]);
1409
1410         return retval;
1411 }
1412
1413 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1414 {
1415         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1416         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1417         struct target *target = bank->target;
1418         struct reg_param reg_params[10];
1419         struct arm_algorithm armv4_5_info;
1420         struct working_area *source;
1421         uint32_t buffer_size = 32768;
1422         uint32_t status;
1423         int retval = ERROR_OK;
1424
1425         /* input parameters - */
1426         /*      R0 = source address */
1427         /*      R1 = destination address */
1428         /*      R2 = number of writes */
1429         /*      R3 = flash write command */
1430         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1431         /* output parameters - */
1432         /*      R5 = 0x80 ok 0x00 bad */
1433         /* temp registers - */
1434         /*      R6 = value read from flash to test status */
1435         /*      R7 = holding register */
1436         /* unlock registers - */
1437         /*  R8 = unlock1_addr */
1438         /*  R9 = unlock1_cmd */
1439         /*  R10 = unlock2_addr */
1440         /*  R11 = unlock2_cmd */
1441
1442         static const uint32_t word_32_code[] = {
1443                                                 /* 00008100 <sp_32_code>:               */
1444                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1445                 0xe5889000,     /* str  r9, [r8]                                */
1446                 0xe58ab000,     /* str  r11, [r10]                              */
1447                 0xe5883000,     /* str  r3, [r8]                                */
1448                 0xe5815000,     /* str  r5, [r1]                                */
1449                 0xe1a00000,     /* nop                                                  */
1450                                                 /*                                                              */
1451                                                 /* 00008110 <sp_32_busy>:               */
1452                 0xe5916000,     /* ldr  r6, [r1]                                */
1453                 0xe0257006,     /* eor  r7, r5, r6                              */
1454                 0xe0147007,     /* ands r7, r4, r7                              */
1455                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1456                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1457                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1458                 0xe5916000,     /* ldr  r6, [r1]                                */
1459                 0xe0257006,     /* eor  r7, r5, r6                              */
1460                 0xe0147007,     /* ands r7, r4, r7                              */
1461                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1462                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1463                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1464                                                 /*                                                              */
1465                                 /* 00008140 <sp_32_cont>:                               */
1466                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1467                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1468                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1469                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1470                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1471                                                 /*                                                              */
1472                                                 /* 00008154 <sp_32_done>:               */
1473                 0xeafffffe              /* b    8154 <sp_32_done>               */
1474                 };
1475
1476                 static const uint32_t word_16_code[] = {
1477                                 /* 00008158 <sp_16_code>:              */
1478                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1479                 0xe1c890b0,     /* strh r9, [r8]                                */
1480                 0xe1cab0b0,     /* strh r11, [r10]                              */
1481                 0xe1c830b0,     /* strh r3, [r8]                                */
1482                 0xe1c150b0,     /* strh r5, [r1]                       */
1483                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1484                                 /*                                     */
1485                                 /* 00008168 <sp_16_busy>:              */
1486                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1487                 0xe0257006,     /* eor  r7, r5, r6                     */
1488                 0xe0147007,     /* ands r7, r4, r7                     */
1489                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1490                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1491                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1492                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1493                 0xe0257006,     /* eor  r7, r5, r6                     */
1494                 0xe0147007,     /* ands r7, r4, r7                     */
1495                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1496                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1497                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1498                                 /*                                     */
1499                                 /* 00008198 <sp_16_cont>:              */
1500                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1501                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1502                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1503                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1504                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1505                                 /*                                     */
1506                                 /* 000081ac <sp_16_done>:              */
1507                 0xeafffffe      /* b    81ac <sp_16_done>              */
1508                 };
1509
1510                 static const uint32_t word_16_code_dq7only[] = {
1511                                 /* <sp_16_code>:                       */
1512                 0xe0d050b2,     /* ldrh r5, [r0], #2                   */
1513                 0xe1c890b0,     /* strh r9, [r8]                       */
1514                 0xe1cab0b0,     /* strh r11, [r10]                              */
1515                 0xe1c830b0,     /* strh r3, [r8]                                */
1516                 0xe1c150b0,     /* strh r5, [r1]                       */
1517                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1518                                 /*                                     */
1519                                 /* <sp_16_busy>:                       */
1520                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1521                 0xe0257006,     /* eor  r7, r5, r6                     */
1522                 0xe2177080,     /* ands r7, #0x80                      */
1523                 0x1afffffb,     /* bne  8168 <sp_16_busy>              */
1524                                 /*                                     */
1525                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1526                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1527                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1528                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1529                 0xeafffff0,     /* b    8158 <sp_16_code>              */
1530                                 /*                                     */
1531                                 /* 000081ac <sp_16_done>:              */
1532                 0xeafffffe      /* b    81ac <sp_16_done>              */
1533                 };
1534
1535                 static const uint32_t word_8_code[] = {
1536                                 /* 000081b0 <sp_16_code_end>:          */
1537                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1538                 0xe5c89000,     /* strb r9, [r8]                                */
1539                 0xe5cab000,     /* strb r11, [r10]                              */
1540                 0xe5c83000,     /* strb r3, [r8]                                */
1541                 0xe5c15000,     /* strb r5, [r1]                       */
1542                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1543                                 /*                                     */
1544                                 /* 000081c0 <sp_8_busy>:               */
1545                 0xe5d16000,     /* ldrb r6, [r1]                       */
1546                 0xe0257006,     /* eor  r7, r5, r6                     */
1547                 0xe0147007,     /* ands r7, r4, r7                     */
1548                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1549                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1550                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1551                 0xe5d16000,     /* ldrb r6, [r1]                       */
1552                 0xe0257006,     /* eor  r7, r5, r6                     */
1553                 0xe0147007,     /* ands r7, r4, r7                     */
1554                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1555                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1556                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1557                                 /*                                     */
1558                                 /* 000081f0 <sp_8_cont>:               */
1559                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1560                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1561                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1562                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1563                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1564                                 /*                                     */
1565                                 /* 00008204 <sp_8_done>:               */
1566                 0xeafffffe      /* b    8204 <sp_8_done>               */
1567         };
1568
1569         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1570         armv4_5_info.core_mode = ARM_MODE_SVC;
1571         armv4_5_info.core_state = ARM_STATE_ARM;
1572
1573         int target_code_size;
1574         const uint32_t *target_code_src;
1575
1576         switch (bank->bus_width)
1577         {
1578         case 1 :
1579                 target_code_src = word_8_code;
1580                 target_code_size = sizeof(word_8_code);
1581                 break;
1582         case 2 :
1583                 /* Check for DQ5 support */
1584                 if( cfi_info->status_poll_mask & (1 << 5) )
1585                 {
1586                         target_code_src = word_16_code;
1587                         target_code_size = sizeof(word_16_code);
1588                 }
1589                 else
1590                 {
1591                         /* No DQ5 support. Use DQ7 DATA# polling only. */
1592                         target_code_src = word_16_code_dq7only;
1593                         target_code_size = sizeof(word_16_code_dq7only);
1594                 }
1595                 break;
1596         case 4 :
1597                 target_code_src = word_32_code;
1598                 target_code_size = sizeof(word_32_code);
1599                 break;
1600         default:
1601                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1602                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1603         }
1604
1605         /* flash write code */
1606         if (!cfi_info->write_algorithm)
1607         {
1608                 uint8_t *target_code;
1609
1610                 /* convert bus-width dependent algorithm code to correct endiannes */
1611                 target_code = malloc(target_code_size);
1612                 if (target_code == NULL)
1613                 {
1614                         LOG_ERROR("Out of memory");
1615                         return ERROR_FAIL;
1616                 }
1617                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1618
1619                 /* allocate working area */
1620                 retval = target_alloc_working_area(target, target_code_size,
1621                                 &cfi_info->write_algorithm);
1622                 if (retval != ERROR_OK)
1623                 {
1624                         free(target_code);
1625                         return retval;
1626                 }
1627
1628                 /* write algorithm code to working area */
1629                 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1630                                     target_code_size, target_code)) != ERROR_OK)
1631                 {
1632                         free(target_code);
1633                         return retval;
1634                 }
1635
1636                 free(target_code);
1637         }
1638         /* the following code still assumes target code is fixed 24*4 bytes */
1639
1640         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1641         {
1642                 buffer_size /= 2;
1643                 if (buffer_size <= 256)
1644                 {
1645                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1646                         if (cfi_info->write_algorithm)
1647                                 target_free_working_area(target, cfi_info->write_algorithm);
1648
1649                         LOG_WARNING("not enough working area available, can't do block memory writes");
1650                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1651                 }
1652         };
1653
1654         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1655         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1656         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1657         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1658         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1659         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1660         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1661         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1662         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1663         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1664
1665         while (count > 0)
1666         {
1667                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1668
1669                 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1670                 if (retval != ERROR_OK)
1671                 {
1672                         break;
1673                 }
1674
1675                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1676                 buf_set_u32(reg_params[1].value, 0, 32, address);
1677                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1678                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1679                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1680                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1681                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1682                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1683                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1684
1685                 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1686                                                      cfi_info->write_algorithm->address,
1687                                                      cfi_info->write_algorithm->address + ((target_code_size) - 4),
1688                                                      10000, &armv4_5_info);
1689                 if (retval != ERROR_OK)
1690                 {
1691                         break;
1692                 }
1693
1694                 status = buf_get_u32(reg_params[5].value, 0, 32);
1695                 if (status != 0x80)
1696                 {
1697                         LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
1698                         retval = ERROR_FLASH_OPERATION_FAILED;
1699                         break;
1700                 }
1701
1702                 buffer += thisrun_count;
1703                 address += thisrun_count;
1704                 count -= thisrun_count;
1705         }
1706
1707         target_free_all_working_areas(target);
1708
1709         destroy_reg_param(&reg_params[0]);
1710         destroy_reg_param(&reg_params[1]);
1711         destroy_reg_param(&reg_params[2]);
1712         destroy_reg_param(&reg_params[3]);
1713         destroy_reg_param(&reg_params[4]);
1714         destroy_reg_param(&reg_params[5]);
1715         destroy_reg_param(&reg_params[6]);
1716         destroy_reg_param(&reg_params[7]);
1717         destroy_reg_param(&reg_params[8]);
1718         destroy_reg_param(&reg_params[9]);
1719
1720         return retval;
1721 }
1722
1723 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1724 {
1725         int retval;
1726         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1727         struct target *target = bank->target;
1728
1729         cfi_intel_clear_status_register(bank);
1730         if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1731         {
1732                 return retval;
1733         }
1734
1735         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1736         {
1737                 return retval;
1738         }
1739
1740         uint8_t status;
1741         retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max), &status);
1742         if (retval != 0x80)
1743         {
1744                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1745                 {
1746                         return retval;
1747                 }
1748
1749                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1750                 return ERROR_FLASH_OPERATION_FAILED;
1751         }
1752
1753         return ERROR_OK;
1754 }
1755
1756 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1757 {
1758         int retval;
1759         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1760         struct target *target = bank->target;
1761
1762         /* Calculate buffer size and boundary mask */
1763         /* buffersize is (buffer size per chip) * (number of chips) */
1764         /* bufferwsize is buffersize in words */
1765         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1766         uint32_t buffermask = buffersize-1;
1767         uint32_t bufferwsize = buffersize / bank->bus_width;
1768
1769         /* Check for valid range */
1770         if (address & buffermask)
1771         {
1772                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1773                           bank->base, address, cfi_info->max_buf_write_size);
1774                 return ERROR_FLASH_OPERATION_FAILED;
1775         }
1776
1777         /* Check for valid size */
1778         if (wordcount > bufferwsize)
1779         {
1780                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1781                 return ERROR_FLASH_OPERATION_FAILED;
1782         }
1783
1784         /* Write to flash buffer */
1785         cfi_intel_clear_status_register(bank);
1786
1787         /* Initiate buffer operation _*/
1788         if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1789         {
1790                 return retval;
1791         }
1792         uint8_t status;
1793         retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max), &status);
1794         if (retval != ERROR_OK)
1795                 return retval;
1796         if (status != 0x80)
1797         {
1798                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1799                 {
1800                         return retval;
1801                 }
1802
1803                 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1804                 return ERROR_FLASH_OPERATION_FAILED;
1805         }
1806
1807         /* Write buffer wordcount-1 and data words */
1808         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1809         {
1810                 return retval;
1811         }
1812
1813         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1814         {
1815                 return retval;
1816         }
1817
1818         /* Commit write operation */
1819         if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1820         {
1821                 return retval;
1822         }
1823
1824         retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max), &status);
1825         if (retval != ERROR_OK)
1826                 return retval;
1827
1828         if (status != 0x80)
1829         {
1830                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1831                 {
1832                         return retval;
1833                 }
1834
1835                 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1836                 return ERROR_FLASH_OPERATION_FAILED;
1837         }
1838
1839         return ERROR_OK;
1840 }
1841
1842 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1843 {
1844         int retval;
1845         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1846         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1847         struct target *target = bank->target;
1848
1849         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1850         {
1851                 return retval;
1852         }
1853
1854         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1855         {
1856                 return retval;
1857         }
1858
1859         if ((retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1860         {
1861                 return retval;
1862         }
1863
1864         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1865         {
1866                 return retval;
1867         }
1868
1869         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1870         {
1871                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1872                 {
1873                         return retval;
1874                 }
1875
1876                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1877                 return ERROR_FLASH_OPERATION_FAILED;
1878         }
1879
1880         return ERROR_OK;
1881 }
1882
1883 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1884 {
1885         int retval;
1886         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1887         struct target *target = bank->target;
1888         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1889
1890         /* Calculate buffer size and boundary mask */
1891         /* buffersize is (buffer size per chip) * (number of chips) */
1892         /* bufferwsize is buffersize in words */
1893         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1894         uint32_t buffermask = buffersize-1;
1895         uint32_t bufferwsize = buffersize / bank->bus_width;
1896
1897         /* Check for valid range */
1898         if (address & buffermask)
1899         {
1900                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1901                 return ERROR_FLASH_OPERATION_FAILED;
1902         }
1903
1904         /* Check for valid size */
1905         if (wordcount > bufferwsize)
1906         {
1907                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1908                 return ERROR_FLASH_OPERATION_FAILED;
1909         }
1910
1911         // Unlock
1912         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1913         {
1914                 return retval;
1915         }
1916
1917         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1918         {
1919                 return retval;
1920         }
1921
1922         // Buffer load command
1923         if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1924         {
1925                 return retval;
1926         }
1927
1928         /* Write buffer wordcount-1 and data words */
1929         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1930         {
1931                 return retval;
1932         }
1933
1934         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1935         {
1936                 return retval;
1937         }
1938
1939         /* Commit write operation */
1940         if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
1941         {
1942                 return retval;
1943         }
1944
1945         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1946         {
1947                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1948                 {
1949                         return retval;
1950                 }
1951
1952                 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1953                 return ERROR_FLASH_OPERATION_FAILED;
1954         }
1955
1956         return ERROR_OK;
1957 }
1958
1959 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1960 {
1961         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1962
1963         switch (cfi_info->pri_id)
1964         {
1965                 case 1:
1966                 case 3:
1967                         return cfi_intel_write_word(bank, word, address);
1968                         break;
1969                 case 2:
1970                         return cfi_spansion_write_word(bank, word, address);
1971                         break;
1972                 default:
1973                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1974                         break;
1975         }
1976
1977         return ERROR_FLASH_OPERATION_FAILED;
1978 }
1979
1980 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1981 {
1982         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1983
1984         switch (cfi_info->pri_id)
1985         {
1986                 case 1:
1987                 case 3:
1988                         return cfi_intel_write_words(bank, word, wordcount, address);
1989                         break;
1990                 case 2:
1991                         return cfi_spansion_write_words(bank, word, wordcount, address);
1992                         break;
1993                 default:
1994                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1995                         break;
1996         }
1997
1998         return ERROR_FLASH_OPERATION_FAILED;
1999 }
2000
2001 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2002 {
2003         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2004         struct target *target = bank->target;
2005         uint32_t address = bank->base + offset;
2006         uint32_t read_p;
2007         int align;      /* number of unaligned bytes */
2008         uint8_t current_word[CFI_MAX_BUS_WIDTH];
2009         int i;
2010         int retval;
2011
2012         LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2013                 (int)count, (unsigned)offset);
2014
2015         if (bank->target->state != TARGET_HALTED)
2016         {
2017                 LOG_ERROR("Target not halted");
2018                 return ERROR_TARGET_NOT_HALTED;
2019         }
2020
2021         if (offset + count > bank->size)
2022                 return ERROR_FLASH_DST_OUT_OF_BANK;
2023
2024         if (cfi_info->qry[0] != 'Q')
2025                 return ERROR_FLASH_BANK_NOT_PROBED;
2026
2027         /* start at the first byte of the first word (bus_width size) */
2028         read_p = address & ~(bank->bus_width - 1);
2029         if ((align = address - read_p) != 0)
2030         {
2031                 LOG_INFO("Fixup %d unaligned read head bytes", align);
2032
2033                 /* read a complete word from flash */
2034                 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2035                         return retval;
2036
2037                 /* take only bytes we need */
2038                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2039                         *buffer++ = current_word[i];
2040
2041                 read_p += bank->bus_width;
2042         }
2043
2044         align = count / bank->bus_width;
2045         if (align)
2046         {
2047                 if ((retval = target_read_memory(target, read_p, bank->bus_width, align, buffer)) != ERROR_OK)
2048                         return retval;
2049
2050                 read_p += align * bank->bus_width;
2051                 buffer += align * bank->bus_width;
2052                 count -= align * bank->bus_width;
2053         }
2054
2055         if (count)
2056         {
2057                 LOG_INFO("Fixup %d unaligned read tail bytes", count);
2058
2059                 /* read a complete word from flash */
2060                 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2061                         return retval;
2062
2063                 /* take only bytes we need */
2064                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2065                         *buffer++ = current_word[i];
2066         }
2067
2068         return ERROR_OK;
2069 }
2070
2071 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2072 {
2073         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2074         struct target *target = bank->target;
2075         uint32_t address = bank->base + offset; /* address of first byte to be programmed */
2076         uint32_t write_p;
2077         int align;      /* number of unaligned bytes */
2078         int blk_count; /* number of bus_width bytes for block copy */
2079         uint8_t current_word[CFI_MAX_BUS_WIDTH * 4];    /* word (bus_width size) currently being programmed */
2080         int i;
2081         int retval;
2082
2083         if (bank->target->state != TARGET_HALTED)
2084         {
2085                 LOG_ERROR("Target not halted");
2086                 return ERROR_TARGET_NOT_HALTED;
2087         }
2088
2089         if (offset + count > bank->size)
2090                 return ERROR_FLASH_DST_OUT_OF_BANK;
2091
2092         if (cfi_info->qry[0] != 'Q')
2093                 return ERROR_FLASH_BANK_NOT_PROBED;
2094
2095         /* start at the first byte of the first word (bus_width size) */
2096         write_p = address & ~(bank->bus_width - 1);
2097         if ((align = address - write_p) != 0)
2098         {
2099                 LOG_INFO("Fixup %d unaligned head bytes", align);
2100
2101                 /* read a complete word from flash */
2102                 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2103                         return retval;
2104
2105                 /* replace only bytes that must be written */
2106                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2107                         current_word[i] = *buffer++;
2108
2109                 retval = cfi_write_word(bank, current_word, write_p);
2110                 if (retval != ERROR_OK)
2111                         return retval;
2112                 write_p += bank->bus_width;
2113         }
2114
2115         /* handle blocks of bus_size aligned bytes */
2116         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
2117         switch (cfi_info->pri_id)
2118         {
2119                 /* try block writes (fails without working area) */
2120                 case 1:
2121                 case 3:
2122                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
2123                         break;
2124                 case 2:
2125                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
2126                         break;
2127                 default:
2128                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2129                         retval = ERROR_FLASH_OPERATION_FAILED;
2130                         break;
2131         }
2132         if (retval == ERROR_OK)
2133         {
2134                 /* Increment pointers and decrease count on succesful block write */
2135                 buffer += blk_count;
2136                 write_p += blk_count;
2137                 count -= blk_count;
2138         }
2139         else
2140         {
2141                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
2142                 {
2143                         /* Calculate buffer size and boundary mask */
2144                         /* buffersize is (buffer size per chip) * (number of chips) */
2145                         /* bufferwsize is buffersize in words */
2146                         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2147                         uint32_t buffermask = buffersize-1;
2148                         uint32_t bufferwsize = buffersize / bank->bus_width;
2149
2150                         /* fall back to memory writes */
2151                         while (count >= (uint32_t)bank->bus_width)
2152                         {
2153                                 int fallback;
2154                                 if ((write_p & 0xff) == 0)
2155                                 {
2156                                         LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
2157                                 }
2158                                 fallback = 1;
2159                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
2160                                 {
2161                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2162                                         if (retval == ERROR_OK)
2163                                         {
2164                                                 buffer += buffersize;
2165                                                 write_p += buffersize;
2166                                                 count -= buffersize;
2167                                                 fallback = 0;
2168                                         }
2169                                 }
2170                                 /* try the slow way? */
2171                                 if (fallback)
2172                                 {
2173                                         for (i = 0; i < bank->bus_width; i++)
2174                                                 current_word[i] = *buffer++;
2175
2176                                         retval = cfi_write_word(bank, current_word, write_p);
2177                                         if (retval != ERROR_OK)
2178                                                 return retval;
2179
2180                                         write_p += bank->bus_width;
2181                                         count -= bank->bus_width;
2182                                 }
2183                         }
2184                 }
2185                 else
2186                         return retval;
2187         }
2188
2189         /* return to read array mode, so we can read from flash again for padding */
2190         if ((retval = cfi_reset(bank)) != ERROR_OK)
2191         {
2192                 return retval;
2193         }
2194
2195         /* handle unaligned tail bytes */
2196         if (count > 0)
2197         {
2198                 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2199
2200                 /* read a complete word from flash */
2201                 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2202                         return retval;
2203
2204                 /* replace only bytes that must be written */
2205                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2206                         current_word[i] = *buffer++;
2207
2208                 retval = cfi_write_word(bank, current_word, write_p);
2209                 if (retval != ERROR_OK)
2210                         return retval;
2211         }
2212
2213         /* return to read array mode */
2214         return cfi_reset(bank);
2215 }
2216
2217 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
2218 {
2219         (void) param;
2220         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2221         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2222
2223         pri_ext->_reversed_geometry = 1;
2224 }
2225
2226 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2227 {
2228         int i;
2229         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2230         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2231         (void) param;
2232
2233         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2234         {
2235                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2236
2237                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2238                 {
2239                         int j = (cfi_info->num_erase_regions - 1) - i;
2240                         uint32_t swap;
2241
2242                         swap = cfi_info->erase_region_info[i];
2243                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2244                         cfi_info->erase_region_info[j] = swap;
2245                 }
2246         }
2247 }
2248
2249 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2250 {
2251         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2252         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2253         struct cfi_unlock_addresses *unlock_addresses = param;
2254
2255         pri_ext->_unlock1 = unlock_addresses->unlock1;
2256         pri_ext->_unlock2 = unlock_addresses->unlock2;
2257 }
2258
2259
2260 static int cfi_query_string(struct flash_bank *bank, int address)
2261 {
2262         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2263         int retval;
2264
2265         if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2266         {
2267                 return retval;
2268         }
2269
2270         retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
2271         if (retval != ERROR_OK)
2272                 return retval;
2273         retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
2274         if (retval != ERROR_OK)
2275                 return retval;
2276         retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
2277         if (retval != ERROR_OK)
2278                 return retval;
2279
2280         LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2281
2282         if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2283         {
2284                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2285                 {
2286                         return retval;
2287                 }
2288                 LOG_ERROR("Could not probe bank: no QRY");
2289                 return ERROR_FLASH_BANK_INVALID;
2290         }
2291
2292         return ERROR_OK;
2293 }
2294
2295 static int cfi_probe(struct flash_bank *bank)
2296 {
2297         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2298         struct target *target = bank->target;
2299         int num_sectors = 0;
2300         int i;
2301         int sector = 0;
2302         uint32_t unlock1 = 0x555;
2303         uint32_t unlock2 = 0x2aa;
2304         int retval;
2305         uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2306
2307         if (bank->target->state != TARGET_HALTED)
2308         {
2309                 LOG_ERROR("Target not halted");
2310                 return ERROR_TARGET_NOT_HALTED;
2311         }
2312
2313         cfi_info->probed = 0;
2314         if (bank->sectors)
2315         {
2316                 free(bank->sectors);
2317                 bank->sectors = NULL;
2318         }
2319         if(cfi_info->erase_region_info)
2320         {
2321                 free(cfi_info->erase_region_info);
2322                 cfi_info->erase_region_info = NULL;
2323         }
2324
2325         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2326          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2327          */
2328         if (cfi_info->jedec_probe)
2329         {
2330                 unlock1 = 0x5555;
2331                 unlock2 = 0x2aaa;
2332         }
2333
2334         /* switch to read identifier codes mode ("AUTOSELECT") */
2335         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2336         {
2337                 return retval;
2338         }
2339         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2340         {
2341                 return retval;
2342         }
2343         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2344         {
2345                 return retval;
2346         }
2347
2348         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, value_buf0)) != ERROR_OK)
2349         {
2350                 return retval;
2351         }
2352         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01), bank->bus_width, 1, value_buf1)) != ERROR_OK)
2353         {
2354                 return retval;
2355         }
2356         switch (bank->chip_width) {
2357                 case 1:
2358                         cfi_info->manufacturer = *value_buf0;
2359                         cfi_info->device_id = *value_buf1;
2360                         break;
2361                 case 2:
2362                         cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2363                         cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2364                         break;
2365                 case 4:
2366                         cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2367                         cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2368                         break;
2369                 default:
2370                         LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
2371                         return ERROR_FLASH_OPERATION_FAILED;
2372         }
2373
2374         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2375         /* switch back to read array mode */
2376         if ((retval = cfi_reset(bank)) != ERROR_OK)
2377         {
2378                 return retval;
2379         }
2380
2381         /* check device/manufacturer ID for known non-CFI flashes. */
2382         cfi_fixup_non_cfi(bank);
2383
2384         /* query only if this is a CFI compatible flash,
2385          * otherwise the relevant info has already been filled in
2386          */
2387         if (cfi_info->not_cfi == 0)
2388         {
2389                 /* enter CFI query mode
2390                  * according to JEDEC Standard No. 68.01,
2391                  * a single bus sequence with address = 0x55, data = 0x98 should put
2392                  * the device into CFI query mode.
2393                  *
2394                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2395                  */
2396
2397                 retval = cfi_query_string(bank, 0x55);
2398                 if (retval != ERROR_OK)
2399                 {
2400                         /*
2401                          * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2402                          * be harmless enough:
2403                          *
2404                          * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2405                          */
2406                         LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2407                         retval = cfi_query_string(bank, 0x555);
2408                 }
2409                 if (retval != ERROR_OK)
2410                         return retval;
2411
2412                 retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
2413                 if (retval != ERROR_OK)
2414                         return retval;
2415                 retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
2416                 if (retval != ERROR_OK)
2417                         return retval;
2418                 retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
2419                 if (retval != ERROR_OK)
2420                         return retval;
2421                 retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
2422                 if (retval != ERROR_OK)
2423                         return retval;
2424
2425                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2426
2427                 retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
2428                 if (retval != ERROR_OK)
2429                         return retval;
2430                 retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
2431                 if (retval != ERROR_OK)
2432                         return retval;
2433                 retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
2434                 if (retval != ERROR_OK)
2435                         return retval;
2436                 retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
2437                 if (retval != ERROR_OK)
2438                         return retval;
2439                 retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
2440                 if (retval != ERROR_OK)
2441                         return retval;
2442                 retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
2443                 if (retval != ERROR_OK)
2444                         return retval;
2445                 retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
2446                 if (retval != ERROR_OK)
2447                         return retval;
2448                 retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
2449                 if (retval != ERROR_OK)
2450                         return retval;
2451                 retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
2452                 if (retval != ERROR_OK)
2453                         return retval;
2454                 retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
2455                 if (retval != ERROR_OK)
2456                         return retval;
2457                 retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
2458                 if (retval != ERROR_OK)
2459                         return retval;
2460                 retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
2461                 if (retval != ERROR_OK)
2462                         return retval;
2463
2464                 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2465                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2466                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2467                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2468                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2469                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2470                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2471                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2472                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2473                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2474                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2475
2476                 uint8_t data;
2477                 retval = cfi_query_u8(bank, 0, 0x27, &data);
2478                 if (retval != ERROR_OK)
2479                         return retval;
2480                 cfi_info->dev_size = 1 << data;
2481
2482                 retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
2483                 if (retval != ERROR_OK)
2484                         return retval;
2485                 retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
2486                 if (retval != ERROR_OK)
2487                         return retval;
2488                 retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
2489                 if (retval != ERROR_OK)
2490                         return retval;
2491
2492                 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2493
2494                 if (cfi_info->num_erase_regions)
2495                 {
2496                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2497                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2498                         {
2499                                 retval = cfi_query_u32(bank, 0, 0x2d + (4 * i), &cfi_info->erase_region_info[i]);
2500                                 if (retval != ERROR_OK)
2501                                         return retval;
2502                                 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2503                                           i,
2504                                           (cfi_info->erase_region_info[i] & 0xffff) + 1,
2505                                           (cfi_info->erase_region_info[i] >> 16) * 256);
2506                         }
2507                 }
2508                 else
2509                 {
2510                         cfi_info->erase_region_info = NULL;
2511                 }
2512
2513                 /* We need to read the primary algorithm extended query table before calculating
2514                  * the sector layout to be able to apply fixups
2515                  */
2516                 switch (cfi_info->pri_id)
2517                 {
2518                         /* Intel command set (standard and extended) */
2519                         case 0x0001:
2520                         case 0x0003:
2521                                 cfi_read_intel_pri_ext(bank);
2522                                 break;
2523                         /* AMD/Spansion, Atmel, ... command set */
2524                         case 0x0002:
2525                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2526                                 cfi_read_0002_pri_ext(bank);
2527                                 break;
2528                         default:
2529                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2530                                 break;
2531                 }
2532
2533                 /* return to read array mode
2534                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2535                  */
2536                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2537                 {
2538                         return retval;
2539                 }
2540         } /* end CFI case */
2541
2542         /* apply fixups depending on the primary command set */
2543         switch (cfi_info->pri_id)
2544         {
2545                 /* Intel command set (standard and extended) */
2546                 case 0x0001:
2547                 case 0x0003:
2548                         cfi_fixup(bank, cfi_0001_fixups);
2549                         break;
2550                 /* AMD/Spansion, Atmel, ... command set */
2551                 case 0x0002:
2552                         cfi_fixup(bank, cfi_0002_fixups);
2553                         break;
2554                 default:
2555                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2556                         break;
2557         }
2558
2559         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2560         {
2561                 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2562         }
2563
2564         if (cfi_info->num_erase_regions == 0)
2565         {
2566                 /* a device might have only one erase block, spanning the whole device */
2567                 bank->num_sectors = 1;
2568                 bank->sectors = malloc(sizeof(struct flash_sector));
2569
2570                 bank->sectors[sector].offset = 0x0;
2571                 bank->sectors[sector].size = bank->size;
2572                 bank->sectors[sector].is_erased = -1;
2573                 bank->sectors[sector].is_protected = -1;
2574         }
2575         else
2576         {
2577                 uint32_t offset = 0;
2578
2579                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2580                 {
2581                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2582                 }
2583
2584                 bank->num_sectors = num_sectors;
2585                 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2586
2587                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2588                 {
2589                         uint32_t j;
2590                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2591                         {
2592                                 bank->sectors[sector].offset = offset;
2593                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2594                                 offset += bank->sectors[sector].size;
2595                                 bank->sectors[sector].is_erased = -1;
2596                                 bank->sectors[sector].is_protected = -1;
2597                                 sector++;
2598                         }
2599                 }
2600                 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2601                 {
2602                         LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2603                                 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2604                 }
2605         }
2606
2607         cfi_info->probed = 1;
2608
2609         return ERROR_OK;
2610 }
2611
2612 static int cfi_auto_probe(struct flash_bank *bank)
2613 {
2614         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2615         if (cfi_info->probed)
2616                 return ERROR_OK;
2617         return cfi_probe(bank);
2618 }
2619
2620 static int cfi_intel_protect_check(struct flash_bank *bank)
2621 {
2622         int retval;
2623         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2624         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2625         int i;
2626
2627         /* check if block lock bits are supported on this device */
2628         if (!(pri_ext->blk_status_reg_mask & 0x1))
2629                 return ERROR_FLASH_OPERATION_FAILED;
2630
2631         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2632         {
2633                 return retval;
2634         }
2635
2636         for (i = 0; i < bank->num_sectors; i++)
2637         {
2638                 uint8_t block_status;
2639                 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2640                 if (retval != ERROR_OK)
2641                         return retval;
2642
2643                 if (block_status & 1)
2644                         bank->sectors[i].is_protected = 1;
2645                 else
2646                         bank->sectors[i].is_protected = 0;
2647         }
2648
2649         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2650 }
2651
2652 static int cfi_spansion_protect_check(struct flash_bank *bank)
2653 {
2654         int retval;
2655         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2656         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2657         int i;
2658
2659         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2660         {
2661                 return retval;
2662         }
2663
2664         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2665         {
2666                 return retval;
2667         }
2668
2669         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2670         {
2671                 return retval;
2672         }
2673
2674         for (i = 0; i < bank->num_sectors; i++)
2675         {
2676                 uint8_t block_status;
2677                 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2678                 if (retval != ERROR_OK)
2679                         return retval;
2680
2681                 if (block_status & 1)
2682                         bank->sectors[i].is_protected = 1;
2683                 else
2684                         bank->sectors[i].is_protected = 0;
2685         }
2686
2687         return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2688 }
2689
2690 static int cfi_protect_check(struct flash_bank *bank)
2691 {
2692         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2693
2694         if (bank->target->state != TARGET_HALTED)
2695         {
2696                 LOG_ERROR("Target not halted");
2697                 return ERROR_TARGET_NOT_HALTED;
2698         }
2699
2700         if (cfi_info->qry[0] != 'Q')
2701                 return ERROR_FLASH_BANK_NOT_PROBED;
2702
2703         switch (cfi_info->pri_id)
2704         {
2705                 case 1:
2706                 case 3:
2707                         return cfi_intel_protect_check(bank);
2708                         break;
2709                 case 2:
2710                         return cfi_spansion_protect_check(bank);
2711                         break;
2712                 default:
2713                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2714                         break;
2715         }
2716
2717         return ERROR_OK;
2718 }
2719
2720 static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2721 {
2722         int printed;
2723         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2724
2725         if (cfi_info->qry[0] == 0xff)
2726         {
2727                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2728                 return ERROR_OK;
2729         }
2730
2731         if (cfi_info->not_cfi == 0)
2732                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2733         else
2734                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2735         buf += printed;
2736         buf_size -= printed;
2737
2738         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2739                 cfi_info->manufacturer, cfi_info->device_id);
2740         buf += printed;
2741         buf_size -= printed;
2742
2743         if (cfi_info->not_cfi == 0)
2744         {
2745         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2746         buf += printed;
2747         buf_size -= printed;
2748
2749                 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2750                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2751         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2752         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2753         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2754         buf += printed;
2755         buf_size -= printed;
2756
2757                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2758                                    1 << cfi_info->word_write_timeout_typ,
2759                                    1 << cfi_info->buf_write_timeout_typ,
2760                                    1 << cfi_info->block_erase_timeout_typ,
2761                                    1 << cfi_info->chip_erase_timeout_typ);
2762         buf += printed;
2763         buf_size -= printed;
2764
2765                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2766                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2767                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2768                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2769                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2770         buf += printed;
2771         buf_size -= printed;
2772
2773                 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2774                                    cfi_info->dev_size,
2775                                    cfi_info->interface_desc,
2776                                    1 << cfi_info->max_buf_write_size);
2777         buf += printed;
2778         buf_size -= printed;
2779
2780         switch (cfi_info->pri_id)
2781         {
2782                 case 1:
2783                 case 3:
2784                         cfi_intel_info(bank, buf, buf_size);
2785                         break;
2786                 case 2:
2787                         cfi_spansion_info(bank, buf, buf_size);
2788                         break;
2789                 default:
2790                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2791                         break;
2792         }
2793         }
2794
2795         return ERROR_OK;
2796 }
2797
2798 struct flash_driver cfi_flash = {
2799         .name = "cfi",
2800         .flash_bank_command = cfi_flash_bank_command,
2801         .erase = cfi_erase,
2802         .protect = cfi_protect,
2803         .write = cfi_write,
2804         .read = cfi_read,
2805         .probe = cfi_probe,
2806         .auto_probe = cfi_auto_probe,
2807         /* FIXME: access flash at bus_width size */
2808         .erase_check = default_flash_blank_check,
2809         .protect_check = cfi_protect_check,
2810         .info = get_cfi_info,
2811 };