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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *   Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com>            *
   7  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "imp.h"
  29 #include "cfi.h"
  30 #include "non_cfi.h"
  31 #include <target/arm.h>
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34
  35
  36 #define CFI_MAX_BUS_WIDTH       4
  37 #define CFI_MAX_CHIP_WIDTH      4
  38
  39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  40 #define CFI_MAX_INTEL_CODESIZE 256
  41
  42 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
  43 {
  44         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  45         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  46 };
  47
  48 /* CFI fixups foward declarations */
  49 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
  50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
  51 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
  52
  53 /* fixup after reading cmdset 0002 primary query table */
  54 static const struct cfi_fixup cfi_0002_fixups[] = {
  55         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  56         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  57         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  58         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  59         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  60         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  61    {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  62         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  63         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  64         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  65         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  66         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  67         {0, 0, NULL, NULL}
  68 };
  69
  70 /* fixup after reading cmdset 0001 primary query table */
  71 static const struct cfi_fixup cfi_0001_fixups[] = {
  72         {0, 0, NULL, NULL}
  73 };
  74
  75 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
  76 {
  77         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  78         const struct cfi_fixup *f;
  79
  80         for (f = fixups; f->fixup; f++)
  81         {
  82                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
  83                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
  84                 {
  85                         f->fixup(bank, f->param);
  86                 }
  87         }
  88 }
  89
  90 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
  91 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
  92 {
  93         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  94
  95         if (cfi_info->x16_as_x8) offset *= 2;
  96
  97         /* while the sector list isn't built, only accesses to sector 0 work */
  98         if (sector == 0)
  99                 return bank->base + offset * bank->bus_width;
 100         else
 101         {
 102                 if (!bank->sectors)
 103                 {
 104                         LOG_ERROR("BUG: sector list not yet built");
 105                         exit(-1);
 106                 }
 107                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 108         }
 109 }
 110
 111 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
 112 {
 113         int i;
 114
 115         /* clear whole buffer, to ensure bits that exceed the bus_width
 116          * are set to zero
 117          */
 118         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 119                 cmd_buf[i] = 0;
 120
 121         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 122         {
 123                 for (i = bank->bus_width; i > 0; i--)
 124                 {
 125                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 126                 }
 127         }
 128         else
 129         {
 130                 for (i = 1; i <= bank->bus_width; i++)
 131                 {
 132                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 133                 }
 134         }
 135 }
 136
 137 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
 138 {
 139     uint8_t command[CFI_MAX_BUS_WIDTH];
 140
 141     cfi_command(bank, cmd, command);
 142     return target_write_memory(bank->target, address, bank->bus_width, 1, command);
 143 }
 144
 145 /* read unsigned 8-bit value from the bank
 146  * flash banks are expected to be made of similar chips
 147  * the query result should be the same for all
 148  */
 149 static uint8_t cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset)
 150 {
 151         struct target *target = bank->target;
 152         uint8_t data[CFI_MAX_BUS_WIDTH];
 153
 154         target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 155
 156         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 157                 return data[0];
 158         else
 159                 return data[bank->bus_width - 1];
 160 }
 161
 162 /* read unsigned 8-bit value from the bank
 163  * in case of a bank made of multiple chips,
 164  * the individual values are ORed
 165  */
 166 static uint8_t cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset)
 167 {
 168         struct target *target = bank->target;
 169         uint8_t data[CFI_MAX_BUS_WIDTH];
 170         int i;
 171
 172         target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 173
 174         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 175         {
 176                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 177                         data[0] |= data[i];
 178
 179                 return data[0];
 180         }
 181         else
 182         {
 183                 uint8_t value = 0;
 184                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 185                         value |= data[bank->bus_width - 1 - i];
 186
 187                 return value;
 188         }
 189 }
 190
 191 static uint16_t cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset)
 192 {
 193         struct target *target = bank->target;
 194         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 195         uint8_t data[CFI_MAX_BUS_WIDTH * 2];
 196
 197         if (cfi_info->x16_as_x8)
 198         {
 199                 uint8_t i;
 200                 for (i = 0;i < 2;i++)
 201                         target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 202                                 &data[i*bank->bus_width]);
 203         }
 204         else
 205                 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 206
 207         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 208                 return data[0] | data[bank->bus_width] << 8;
 209         else
 210                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 211 }
 212
 213 static uint32_t cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset)
 214 {
 215         struct target *target = bank->target;
 216         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 217         uint8_t data[CFI_MAX_BUS_WIDTH * 4];
 218
 219         if (cfi_info->x16_as_x8)
 220         {
 221                 uint8_t i;
 222                 for (i = 0;i < 4;i++)
 223                         target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 224                                 &data[i*bank->bus_width]);
 225         }
 226         else
 227                 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 228
 229         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 230                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 231         else
 232                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 233                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 234 }
 235
 236 static int cfi_reset(struct flash_bank *bank)
 237 {
 238         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 239         int retval = ERROR_OK;
 240
 241         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 242         {
 243                 return retval;
 244         }
 245
 246         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 247         {
 248                 return retval;
 249         }
 250
 251         if (cfi_info->manufacturer == 0x20 &&
 252                         (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
 253         {
 254                 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
 255                  * so we send an extra 0xF0 reset to fix the bug */
 256                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
 257                 {
 258                         return retval;
 259                 }
 260         }
 261
 262         return retval;
 263 }
 264
 265 static void cfi_intel_clear_status_register(struct flash_bank *bank)
 266 {
 267         struct target *target = bank->target;
 268
 269         if (target->state != TARGET_HALTED)
 270         {
 271                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 272                 exit(-1);
 273         }
 274
 275         cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
 276 }
 277
 278 static uint8_t cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout)
 279 {
 280         uint8_t status;
 281
 282         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 283         {
 284                 LOG_DEBUG("status: 0x%x", status);
 285                 alive_sleep(1);
 286         }
 287
 288         /* mask out bit 0 (reserved) */
 289         status = status & 0xfe;
 290
 291         LOG_DEBUG("status: 0x%x", status);
 292
 293         if ((status & 0x80) != 0x80)
 294         {
 295                 LOG_ERROR("timeout while waiting for WSM to become ready");
 296         }
 297         else if (status != 0x80)
 298         {
 299                 LOG_ERROR("status register: 0x%x", status);
 300                 if (status & 0x2)
 301                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 302                 if (status & 0x4)
 303                         LOG_ERROR("Program suspended");
 304                 if (status & 0x8)
 305                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 306                 if (status & 0x10)
 307                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 308                 if (status & 0x20)
 309                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 310                 if (status & 0x40)
 311                         LOG_ERROR("Block Erase Suspended");
 312
 313                 cfi_intel_clear_status_register(bank);
 314         }
 315
 316         return status;
 317 }
 318
 319 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
 320 {
 321         uint8_t status, oldstatus;
 322         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 323
 324         oldstatus = cfi_get_u8(bank, 0, 0x0);
 325
 326         do {
 327                 status = cfi_get_u8(bank, 0, 0x0);
 328                 if ((status ^ oldstatus) & 0x40) {
 329                         if (status & cfi_info->status_poll_mask & 0x20) {
 330                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 331                                 status = cfi_get_u8(bank, 0, 0x0);
 332                                 if ((status ^ oldstatus) & 0x40) {
 333                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 334                                         return(ERROR_FLASH_OPERATION_FAILED);
 335                                 } else {
 336                                         LOG_DEBUG("status: 0x%x", status);
 337                                         return(ERROR_OK);
 338                                 }
 339                         }
 340                 } else { /* no toggle: finished, OK */
 341                         LOG_DEBUG("status: 0x%x", status);
 342                         return(ERROR_OK);
 343                 }
 344
 345                 oldstatus = status;
 346                 alive_sleep(1);
 347         } while (timeout-- > 0);
 348
 349         LOG_ERROR("timeout, status: 0x%x", status);
 350
 351         return(ERROR_FLASH_BUSY);
 352 }
 353
 354 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
 355 {
 356         int retval;
 357         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 358         struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
 359
 360         cfi_info->pri_ext = pri_ext;
 361
 362         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 363         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 364         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 365
 366         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 367         {
 368                 if ((retval = cfi_reset(bank)) != ERROR_OK)
 369                 {
 370                         return retval;
 371                 }
 372                 LOG_ERROR("Could not read bank flash bank information");
 373                 return ERROR_FLASH_BANK_INVALID;
 374         }
 375
 376         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 377         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 378
 379         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 380
 381         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 382         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 383         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 384
 385         LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
 386                   pri_ext->feature_support,
 387                   pri_ext->suspend_cmd_support,
 388                   pri_ext->blk_status_reg_mask);
 389
 390         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 391         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 392
 393         LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
 394                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 395                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 396
 397         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 398         if (pri_ext->num_protection_fields != 1)
 399         {
 400                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 401         }
 402
 403         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 404         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 405         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 406
 407         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 408
 409         return ERROR_OK;
 410 }
 411
 412 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
 413 {
 414         int retval;
 415         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 416         struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 417
 418         cfi_info->pri_ext = pri_ext;
 419
 420         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 421         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 422         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 423
 424         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 425         {
 426                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 427                 {
 428                         return retval;
 429                 }
 430                 LOG_ERROR("Could not read spansion bank information");
 431                 return ERROR_FLASH_BANK_INVALID;
 432         }
 433
 434         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 435         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 436
 437         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 438
 439         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 440         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 441         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 442         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 443         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 444         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 445         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 446         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 447         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 448         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 449         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 450
 451         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 452               pri_ext->EraseSuspend, pri_ext->BlkProt);
 453
 454         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 455               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 456
 457         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 458
 459
 460         LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
 461                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 462                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 463
 464         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 465
 466         /* default values for implementation specific workarounds */
 467         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 468         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 469         pri_ext->_reversed_geometry = 0;
 470
 471         return ERROR_OK;
 472 }
 473
 474 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
 475 {
 476         int retval;
 477         struct cfi_atmel_pri_ext atmel_pri_ext;
 478         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 479         struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 480
 481         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 482          * but a different primary extended query table.
 483          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 484          */
 485
 486         memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
 487
 488         cfi_info->pri_ext = pri_ext;
 489
 490         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 491         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 492         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 493
 494         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 495         {
 496                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 497                 {
 498                         return retval;
 499                 }
 500                 LOG_ERROR("Could not read atmel bank information");
 501                 return ERROR_FLASH_BANK_INVALID;
 502         }
 503
 504         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 505         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 506         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 507
 508         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 509         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 510
 511         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 512
 513         pri_ext->major_version = atmel_pri_ext.major_version;
 514         pri_ext->minor_version = atmel_pri_ext.minor_version;
 515
 516         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 517         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 518         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 519         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 520
 521         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 522                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 523
 524         if (atmel_pri_ext.features & 0x02)
 525                 pri_ext->EraseSuspend = 2;
 526
 527         if (atmel_pri_ext.bottom_boot)
 528                 pri_ext->TopBottom = 2;
 529         else
 530                 pri_ext->TopBottom = 3;
 531
 532         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 533         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 534
 535         return ERROR_OK;
 536 }
 537
 538 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
 539 {
 540         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 541
 542         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 543         {
 544                 return cfi_read_atmel_pri_ext(bank);
 545         }
 546         else
 547         {
 548                 return cfi_read_spansion_pri_ext(bank);
 549         }
 550 }
 551
 552 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
 553 {
 554         int printed;
 555         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 556         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 557
 558         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 559         buf += printed;
 560         buf_size -= printed;
 561
 562         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 563                            pri_ext->pri[1], pri_ext->pri[2],
 564                            pri_ext->major_version, pri_ext->minor_version);
 565         buf += printed;
 566         buf_size -= printed;
 567
 568         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 569                            (pri_ext->SiliconRevision) >> 2,
 570                            (pri_ext->SiliconRevision) & 0x03);
 571         buf += printed;
 572         buf_size -= printed;
 573
 574         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 575                            pri_ext->EraseSuspend,
 576                            pri_ext->BlkProt);
 577         buf += printed;
 578         buf_size -= printed;
 579
 580         printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
 581                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 582                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 583
 584         return ERROR_OK;
 585 }
 586
 587 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
 588 {
 589         int printed;
 590         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 591         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 592
 593         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 594         buf += printed;
 595         buf_size -= printed;
 596
 597         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 598         buf += printed;
 599         buf_size -= printed;
 600
 601         printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 602         buf += printed;
 603         buf_size -= printed;
 604
 605         printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
 606                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 607                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 608         buf += printed;
 609         buf_size -= printed;
 610
 611         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 612
 613         return ERROR_OK;
 614 }
 615
 616 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 617  */
 618 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
 619 {
 620         struct cfi_flash_bank *cfi_info;
 621
 622         if (CMD_ARGC < 6)
 623         {
 624                 LOG_WARNING("incomplete flash_bank cfi configuration");
 625                 return ERROR_FLASH_BANK_INVALID;
 626         }
 627
 628         /* both widths must:
 629          * - not exceed max value;
 630          * - not be null;
 631          * - be equal to a power of 2.
 632          * bus must be wide enought to hold one chip */
 633         if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
 634                         || (bank->bus_width > CFI_MAX_BUS_WIDTH)
 635                         || (bank->chip_width == 0)
 636                         || (bank->bus_width == 0)
 637                         || (bank->chip_width & (bank->chip_width - 1))
 638                         || (bank->bus_width & (bank->bus_width - 1))
 639                         || (bank->chip_width > bank->bus_width))
 640         {
 641                 LOG_ERROR("chip and bus width have to specified in bytes");
 642                 return ERROR_FLASH_BANK_INVALID;
 643         }
 644
 645         cfi_info = malloc(sizeof(struct cfi_flash_bank));
 646         cfi_info->probed = 0;
 647         bank->driver_priv = cfi_info;
 648
 649         cfi_info->write_algorithm = NULL;
 650
 651         cfi_info->x16_as_x8 = 0;
 652         cfi_info->jedec_probe = 0;
 653         cfi_info->not_cfi = 0;
 654
 655         for (unsigned i = 6; i < CMD_ARGC; i++)
 656         {
 657                 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
 658                 {
 659                         cfi_info->x16_as_x8 = 1;
 660                 }
 661                 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
 662                 {
 663                         cfi_info->jedec_probe = 1;
 664                 }
 665         }
 666
 667         cfi_info->write_algorithm = NULL;
 668
 669         /* bank wasn't probed yet */
 670         cfi_info->qry[0] = -1;
 671
 672         return ERROR_OK;
 673 }
 674
 675 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
 676 {
 677         int retval;
 678         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 679         int i;
 680
 681         cfi_intel_clear_status_register(bank);
 682
 683         for (i = first; i <= last; i++)
 684         {
 685                 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
 686                 {
 687                         return retval;
 688                 }
 689
 690                 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
 691                 {
 692                         return retval;
 693                 }
 694
 695                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 696                         bank->sectors[i].is_erased = 1;
 697                 else
 698                 {
 699                         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 700                         {
 701                                 return retval;
 702                         }
 703
 704                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
 705                         return ERROR_FLASH_OPERATION_FAILED;
 706                 }
 707         }
 708
 709         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
 710 }
 711
 712 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
 713 {
 714         int retval;
 715         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 716         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 717         int i;
 718
 719         for (i = first; i <= last; i++)
 720         {
 721                 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 722                 {
 723                         return retval;
 724                 }
 725
 726                 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 727                 {
 728                         return retval;
 729                 }
 730
 731                 if ((retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 732                 {
 733                         return retval;
 734                 }
 735
 736                 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 737                 {
 738                         return retval;
 739                 }
 740
 741                 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 742                 {
 743                         return retval;
 744                 }
 745
 746                 if ((retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0))) != ERROR_OK)
 747                 {
 748                         return retval;
 749                 }
 750
 751                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 752                         bank->sectors[i].is_erased = 1;
 753                 else
 754                 {
 755                         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 756                         {
 757                                 return retval;
 758                         }
 759
 760                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
 761                         return ERROR_FLASH_OPERATION_FAILED;
 762                 }
 763         }
 764
 765         return  cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
 766 }
 767
 768 static int cfi_erase(struct flash_bank *bank, int first, int last)
 769 {
 770         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 771
 772         if (bank->target->state != TARGET_HALTED)
 773         {
 774                 LOG_ERROR("Target not halted");
 775                 return ERROR_TARGET_NOT_HALTED;
 776         }
 777
 778         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 779         {
 780                 return ERROR_FLASH_SECTOR_INVALID;
 781         }
 782
 783         if (cfi_info->qry[0] != 'Q')
 784                 return ERROR_FLASH_BANK_NOT_PROBED;
 785
 786         switch (cfi_info->pri_id)
 787         {
 788                 case 1:
 789                 case 3:
 790                         return cfi_intel_erase(bank, first, last);
 791                         break;
 792                 case 2:
 793                         return cfi_spansion_erase(bank, first, last);
 794                         break;
 795                 default:
 796                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 797                         break;
 798         }
 799
 800         return ERROR_OK;
 801 }
 802
 803 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
 804 {
 805         int retval;
 806         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 807         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 808         int retry = 0;
 809         int i;
 810
 811         /* if the device supports neither legacy lock/unlock (bit 3) nor
 812          * instant individual block locking (bit 5).
 813          */
 814         if (!(pri_ext->feature_support & 0x28))
 815                 return ERROR_FLASH_OPERATION_FAILED;
 816
 817         cfi_intel_clear_status_register(bank);
 818
 819         for (i = first; i <= last; i++)
 820         {
 821                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
 822                 {
 823                         return retval;
 824                 }
 825                 if (set)
 826                 {
 827                         if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
 828                         {
 829                                 return retval;
 830                         }
 831                         bank->sectors[i].is_protected = 1;
 832                 }
 833                 else
 834                 {
 835                         if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
 836                         {
 837                                 return retval;
 838                         }
 839                         bank->sectors[i].is_protected = 0;
 840                 }
 841
 842                 /* instant individual block locking doesn't require reading of the status register */
 843                 if (!(pri_ext->feature_support & 0x20))
 844                 {
 845                         /* Clear lock bits operation may take up to 1.4s */
 846                         cfi_intel_wait_status_busy(bank, 1400);
 847                 }
 848                 else
 849                 {
 850                         uint8_t block_status;
 851                         /* read block lock bit, to verify status */
 852                         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
 853                         {
 854                                 return retval;
 855                         }
 856                         block_status = cfi_get_u8(bank, i, 0x2);
 857
 858                         if ((block_status & 0x1) != set)
 859                         {
 860                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 861                                 if ((retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55))) != ERROR_OK)
 862                                 {
 863                                         return retval;
 864                                 }
 865                                 cfi_intel_wait_status_busy(bank, 10);
 866
 867                                 if (retry > 10)
 868                                         return ERROR_FLASH_OPERATION_FAILED;
 869                                 else
 870                                 {
 871                                         i--;
 872                                         retry++;
 873                                 }
 874                         }
 875                 }
 876         }
 877
 878         /* if the device doesn't support individual block lock bits set/clear,
 879          * all blocks have been unlocked in parallel, so we set those that should be protected
 880          */
 881         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 882         {
 883                 /* FIX!!! this code path is broken!!!
 884                  *
 885                  * The correct approach is:
 886                  *
 887                  * 1. read out current protection status
 888                  *
 889                  * 2. override read out protection status w/unprotected.
 890                  *
 891                  * 3. re-protect what should be protected.
 892                  *
 893                  */
 894                 for (i = 0; i < bank->num_sectors; i++)
 895                 {
 896                         if (bank->sectors[i].is_protected == 1)
 897                         {
 898                                 cfi_intel_clear_status_register(bank);
 899
 900                                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
 901                                 {
 902                                         return retval;
 903                                 }
 904
 905                                 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
 906                                 {
 907                                         return retval;
 908                                 }
 909
 910                                 cfi_intel_wait_status_busy(bank, 100);
 911                         }
 912                 }
 913         }
 914
 915         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
 916 }
 917
 918 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
 919 {
 920         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 921
 922         if (bank->target->state != TARGET_HALTED)
 923         {
 924                 LOG_ERROR("Target not halted");
 925                 return ERROR_TARGET_NOT_HALTED;
 926         }
 927
 928         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 929         {
 930                 LOG_ERROR("Invalid sector range");
 931                 return ERROR_FLASH_SECTOR_INVALID;
 932         }
 933
 934         if (cfi_info->qry[0] != 'Q')
 935                 return ERROR_FLASH_BANK_NOT_PROBED;
 936
 937         switch (cfi_info->pri_id)
 938         {
 939                 case 1:
 940                 case 3:
 941                         return cfi_intel_protect(bank, set, first, last);
 942                         break;
 943                 default:
 944                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
 945                         return ERROR_FAIL;
 946         }
 947 }
 948
 949 /* Convert code image to target endian */
 950 /* FIXME create general block conversion fcts in target.c?) */
 951 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
 952 {
 953         uint32_t i;
 954         for (i = 0; i< count; i++)
 955         {
 956                 target_buffer_set_u32(target, dest, *src);
 957                 dest += 4;
 958                 src++;
 959         }
 960 }
 961
 962 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
 963 {
 964         struct target *target = bank->target;
 965
 966         uint8_t buf[CFI_MAX_BUS_WIDTH];
 967         cfi_command(bank, cmd, buf);
 968         switch (bank->bus_width)
 969         {
 970         case 1 :
 971                 return buf[0];
 972                 break;
 973         case 2 :
 974                 return target_buffer_get_u16(target, buf);
 975                 break;
 976         case 4 :
 977                 return target_buffer_get_u32(target, buf);
 978                 break;
 979         default :
 980                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
 981                 return 0;
 982         }
 983 }
 984
 985 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
 986 {
 987         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 988         struct target *target = bank->target;
 989         struct reg_param reg_params[7];
 990         struct arm_algorithm armv4_5_info;
 991         struct working_area *source;
 992         uint32_t buffer_size = 32768;
 993         uint32_t write_command_val, busy_pattern_val, error_pattern_val;
 994
 995         /* algorithm register usage:
 996          * r0: source address (in RAM)
 997          * r1: target address (in Flash)
 998          * r2: count
 999          * r3: flash write command
1000          * r4: status byte (returned to host)
1001          * r5: busy test pattern
1002          * r6: error test pattern
1003          */
1004
1005         static const uint32_t word_32_code[] = {
1006                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1007                 0xe5813000,   /*                str r3, [r1] */
1008                 0xe5814000,   /*                str r4, [r1] */
1009                 0xe5914000,   /* busy:  ldr r4, [r1] */
1010                 0xe0047005,   /*                and r7, r4, r5 */
1011                 0xe1570005,   /*                cmp r7, r5 */
1012                 0x1afffffb,   /*                bne busy */
1013                 0xe1140006,   /*                tst r4, r6 */
1014                 0x1a000003,   /*                bne done */
1015                 0xe2522001,   /*                subs r2, r2, #1 */
1016                 0x0a000001,   /*                beq done */
1017                 0xe2811004,   /*                add r1, r1 #4 */
1018                 0xeafffff2,   /*                b loop */
1019                 0xeafffffe    /* done:  b -2 */
1020         };
1021
1022         static const uint32_t word_16_code[] = {
1023                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1024                 0xe1c130b0,   /*                strh r3, [r1] */
1025                 0xe1c140b0,   /*                strh r4, [r1] */
1026                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1027                 0xe0047005,   /*                and r7, r4, r5 */
1028                 0xe1570005,   /*                cmp r7, r5 */
1029                 0x1afffffb,   /*                bne busy */
1030                 0xe1140006,   /*                tst r4, r6 */
1031                 0x1a000003,   /*                bne done */
1032                 0xe2522001,   /*                subs r2, r2, #1 */
1033                 0x0a000001,   /*                beq done */
1034                 0xe2811002,   /*                add r1, r1 #2 */
1035                 0xeafffff2,   /*                b loop */
1036                 0xeafffffe    /* done:  b -2 */
1037         };
1038
1039         static const uint32_t word_8_code[] = {
1040                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1041                 0xe5c13000,   /*                strb r3, [r1] */
1042                 0xe5c14000,   /*                strb r4, [r1] */
1043                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1044                 0xe0047005,   /*                and r7, r4, r5 */
1045                 0xe1570005,   /*                cmp r7, r5 */
1046                 0x1afffffb,   /*                bne busy */
1047                 0xe1140006,   /*                tst r4, r6 */
1048                 0x1a000003,   /*                bne done */
1049                 0xe2522001,   /*                subs r2, r2, #1 */
1050                 0x0a000001,   /*                beq done */
1051                 0xe2811001,   /*                add r1, r1 #1 */
1052                 0xeafffff2,   /*                b loop */
1053                 0xeafffffe    /* done:  b -2 */
1054         };
1055         uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1056         const uint32_t *target_code_src;
1057         uint32_t target_code_size;
1058         int retval = ERROR_OK;
1059
1060
1061         cfi_intel_clear_status_register(bank);
1062
1063         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1064         armv4_5_info.core_mode = ARM_MODE_SVC;
1065         armv4_5_info.core_state = ARM_STATE_ARM;
1066
1067         /* If we are setting up the write_algorith, we need target_code_src */
1068         /* if not we only need target_code_size. */
1069
1070         /* However, we don't want to create multiple code paths, so we */
1071         /* do the unecessary evaluation of target_code_src, which the */
1072         /* compiler will probably nicely optimize away if not needed */
1073
1074         /* prepare algorithm code for target endian */
1075         switch (bank->bus_width)
1076         {
1077         case 1 :
1078                 target_code_src = word_8_code;
1079                 target_code_size = sizeof(word_8_code);
1080                 break;
1081         case 2 :
1082                 target_code_src = word_16_code;
1083                 target_code_size = sizeof(word_16_code);
1084                 break;
1085         case 4 :
1086                 target_code_src = word_32_code;
1087                 target_code_size = sizeof(word_32_code);
1088                 break;
1089         default:
1090                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1091                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1092         }
1093
1094         /* flash write code */
1095         if (!cfi_info->write_algorithm)
1096         {
1097                 if (target_code_size > sizeof(target_code))
1098                 {
1099                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1100                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1101                 }
1102                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1103
1104                 /* Get memory for block write handler */
1105                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1106                 if (retval != ERROR_OK)
1107                 {
1108                         LOG_WARNING("No working area available, can't do block memory writes");
1109                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1110                 };
1111
1112                 /* write algorithm code to working area */
1113                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1114                 if (retval != ERROR_OK)
1115                 {
1116                         LOG_ERROR("Unable to write block write code to target");
1117                         goto cleanup;
1118                 }
1119         }
1120
1121         /* Get a workspace buffer for the data to flash starting with 32k size.
1122            Half size until buffer would be smaller 256 Bytem then fail back */
1123         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1124         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1125         {
1126                 buffer_size /= 2;
1127                 if (buffer_size <= 256)
1128                 {
1129                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1130                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1131                         goto cleanup;
1132                 }
1133         };
1134
1135         /* setup algo registers */
1136         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1137         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1138         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1139         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1140         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1141         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1142         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1143
1144         /* prepare command and status register patterns */
1145         write_command_val = cfi_command_val(bank, 0x40);
1146         busy_pattern_val  = cfi_command_val(bank, 0x80);
1147         error_pattern_val = cfi_command_val(bank, 0x7e);
1148
1149         LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1150
1151         /* Programming main loop */
1152         while (count > 0)
1153         {
1154                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1155                 uint32_t wsm_error;
1156
1157                 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1158                 {
1159                         goto cleanup;
1160                 }
1161
1162                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1163                 buf_set_u32(reg_params[1].value, 0, 32, address);
1164                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1165
1166                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1167                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1168                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1169
1170                 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1171
1172                 /* Execute algorithm, assume breakpoint for last instruction */
1173                 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1174                         cfi_info->write_algorithm->address,
1175                         cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1176                         10000, /* 10s should be enough for max. 32k of data */
1177                         &armv4_5_info);
1178
1179                 /* On failure try a fall back to direct word writes */
1180                 if (retval != ERROR_OK)
1181                 {
1182                         cfi_intel_clear_status_register(bank);
1183                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1184                         retval = ERROR_FLASH_OPERATION_FAILED;
1185                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1186                         /* FIXME To allow fall back or recovery, we must save the actual status
1187                            somewhere, so that a higher level code can start recovery. */
1188                         goto cleanup;
1189                 }
1190
1191                 /* Check return value from algo code */
1192                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1193                 if (wsm_error)
1194                 {
1195                         /* read status register (outputs debug inforation) */
1196                         cfi_intel_wait_status_busy(bank, 100);
1197                         cfi_intel_clear_status_register(bank);
1198                         retval = ERROR_FLASH_OPERATION_FAILED;
1199                         goto cleanup;
1200                 }
1201
1202                 buffer += thisrun_count;
1203                 address += thisrun_count;
1204                 count -= thisrun_count;
1205         }
1206
1207         /* free up resources */
1208 cleanup:
1209         if (source)
1210                 target_free_working_area(target, source);
1211
1212         if (cfi_info->write_algorithm)
1213         {
1214                 target_free_working_area(target, cfi_info->write_algorithm);
1215                 cfi_info->write_algorithm = NULL;
1216         }
1217
1218         destroy_reg_param(&reg_params[0]);
1219         destroy_reg_param(&reg_params[1]);
1220         destroy_reg_param(&reg_params[2]);
1221         destroy_reg_param(&reg_params[3]);
1222         destroy_reg_param(&reg_params[4]);
1223         destroy_reg_param(&reg_params[5]);
1224         destroy_reg_param(&reg_params[6]);
1225
1226         return retval;
1227 }
1228
1229 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1230 {
1231         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1232         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1233         struct target *target = bank->target;
1234         struct reg_param reg_params[10];
1235         struct arm_algorithm armv4_5_info;
1236         struct working_area *source;
1237         uint32_t buffer_size = 32768;
1238         uint32_t status;
1239         int retval, retvaltemp;
1240         int exit_code = ERROR_OK;
1241
1242         /* input parameters - */
1243         /*      R0 = source address */
1244         /*      R1 = destination address */
1245         /*      R2 = number of writes */
1246         /*      R3 = flash write command */
1247         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1248         /* output parameters - */
1249         /*      R5 = 0x80 ok 0x00 bad */
1250         /* temp registers - */
1251         /*      R6 = value read from flash to test status */
1252         /*      R7 = holding register */
1253         /* unlock registers - */
1254         /*  R8 = unlock1_addr */
1255         /*  R9 = unlock1_cmd */
1256         /*  R10 = unlock2_addr */
1257         /*  R11 = unlock2_cmd */
1258
1259         static const uint32_t word_32_code[] = {
1260                                                 /* 00008100 <sp_32_code>:               */
1261                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1262                 0xe5889000,     /* str  r9, [r8]                                */
1263                 0xe58ab000,     /* str  r11, [r10]                              */
1264                 0xe5883000,     /* str  r3, [r8]                                */
1265                 0xe5815000,     /* str  r5, [r1]                                */
1266                 0xe1a00000,     /* nop                                                  */
1267                                                 /*                                                              */
1268                                                 /* 00008110 <sp_32_busy>:               */
1269                 0xe5916000,     /* ldr  r6, [r1]                                */
1270                 0xe0257006,     /* eor  r7, r5, r6                              */
1271                 0xe0147007,     /* ands r7, r4, r7                              */
1272                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1273                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1274                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1275                 0xe5916000,     /* ldr  r6, [r1]                                */
1276                 0xe0257006,     /* eor  r7, r5, r6                              */
1277                 0xe0147007,     /* ands r7, r4, r7                              */
1278                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1279                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1280                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1281                                                 /*                                                              */
1282                                 /* 00008140 <sp_32_cont>:                               */
1283                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1284                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1285                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1286                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1287                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1288                                                 /*                                                              */
1289                                                 /* 00008154 <sp_32_done>:               */
1290                 0xeafffffe              /* b    8154 <sp_32_done>               */
1291                 };
1292
1293                 static const uint32_t word_16_code[] = {
1294                                 /* 00008158 <sp_16_code>:              */
1295                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1296                 0xe1c890b0,     /* strh r9, [r8]                                */
1297                 0xe1cab0b0,     /* strh r11, [r10]                              */
1298                 0xe1c830b0,     /* strh r3, [r8]                                */
1299                 0xe1c150b0,     /* strh r5, [r1]                       */
1300                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1301                                 /*                                     */
1302                                 /* 00008168 <sp_16_busy>:              */
1303                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1304                 0xe0257006,     /* eor  r7, r5, r6                     */
1305                 0xe0147007,     /* ands r7, r4, r7                     */
1306                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1307                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1308                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1309                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1310                 0xe0257006,     /* eor  r7, r5, r6                     */
1311                 0xe0147007,     /* ands r7, r4, r7                     */
1312                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1313                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1314                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1315                                 /*                                     */
1316                                 /* 00008198 <sp_16_cont>:              */
1317                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1318                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1319                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1320                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1321                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1322                                 /*                                     */
1323                                 /* 000081ac <sp_16_done>:              */
1324                 0xeafffffe      /* b    81ac <sp_16_done>              */
1325                 };
1326
1327                 static const uint32_t word_16_code_dq7only[] = {
1328                                 /* <sp_16_code>:                       */
1329                 0xe0d050b2,     /* ldrh r5, [r0], #2                   */
1330                 0xe1c890b0,     /* strh r9, [r8]                       */
1331                 0xe1cab0b0,     /* strh r11, [r10]                              */
1332                 0xe1c830b0,     /* strh r3, [r8]                                */
1333                 0xe1c150b0,     /* strh r5, [r1]                       */
1334                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1335                                 /*                                     */
1336                                 /* <sp_16_busy>:                       */
1337                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1338                 0xe0257006,     /* eor  r7, r5, r6                     */
1339                 0xe2177080,     /* ands r7, #0x80                      */
1340                 0x1afffffb,     /* bne  8168 <sp_16_busy>              */
1341                                 /*                                     */
1342                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1343                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1344                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1345                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1346                 0xeafffff0,     /* b    8158 <sp_16_code>              */
1347                                 /*                                     */
1348                                 /* 000081ac <sp_16_done>:              */
1349                 0xeafffffe      /* b    81ac <sp_16_done>              */
1350                 };
1351
1352                 static const uint32_t word_8_code[] = {
1353                                 /* 000081b0 <sp_16_code_end>:          */
1354                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1355                 0xe5c89000,     /* strb r9, [r8]                                */
1356                 0xe5cab000,     /* strb r11, [r10]                              */
1357                 0xe5c83000,     /* strb r3, [r8]                                */
1358                 0xe5c15000,     /* strb r5, [r1]                       */
1359                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1360                                 /*                                     */
1361                                 /* 000081c0 <sp_8_busy>:               */
1362                 0xe5d16000,     /* ldrb r6, [r1]                       */
1363                 0xe0257006,     /* eor  r7, r5, r6                     */
1364                 0xe0147007,     /* ands r7, r4, r7                     */
1365                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1366                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1367                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1368                 0xe5d16000,     /* ldrb r6, [r1]                       */
1369                 0xe0257006,     /* eor  r7, r5, r6                     */
1370                 0xe0147007,     /* ands r7, r4, r7                     */
1371                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1372                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1373                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1374                                 /*                                     */
1375                                 /* 000081f0 <sp_8_cont>:               */
1376                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1377                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1378                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1379                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1380                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1381                                 /*                                     */
1382                                 /* 00008204 <sp_8_done>:               */
1383                 0xeafffffe      /* b    8204 <sp_8_done>               */
1384         };
1385
1386         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1387         armv4_5_info.core_mode = ARM_MODE_SVC;
1388         armv4_5_info.core_state = ARM_STATE_ARM;
1389
1390         int target_code_size;
1391         const uint32_t *target_code_src;
1392
1393         switch (bank->bus_width)
1394         {
1395         case 1 :
1396                 target_code_src = word_8_code;
1397                 target_code_size = sizeof(word_8_code);
1398                 break;
1399         case 2 :
1400                 /* Check for DQ5 support */
1401                 if( cfi_info->status_poll_mask & (1 << 5) )
1402                 {
1403                         target_code_src = word_16_code;
1404                         target_code_size = sizeof(word_16_code);
1405                 }
1406                 else
1407                 {
1408                         /* No DQ5 support. Use DQ7 DATA# polling only. */
1409                         target_code_src = word_16_code_dq7only;
1410                         target_code_size = sizeof(word_16_code_dq7only);
1411                 }
1412                 break;
1413         case 4 :
1414                 target_code_src = word_32_code;
1415                 target_code_size = sizeof(word_32_code);
1416                 break;
1417         default:
1418                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1419                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1420         }
1421
1422         /* flash write code */
1423         if (!cfi_info->write_algorithm)
1424         {
1425                 uint8_t *target_code;
1426
1427                 /* convert bus-width dependent algorithm code to correct endiannes */
1428                 target_code = malloc(target_code_size);
1429                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1430
1431                 /* allocate working area */
1432                 retval = target_alloc_working_area(target, target_code_size,
1433                                 &cfi_info->write_algorithm);
1434                 if (retval != ERROR_OK)
1435                 {
1436                         free(target_code);
1437                         return retval;
1438                 }
1439
1440                 /* write algorithm code to working area */
1441                 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1442                                     target_code_size, target_code)) != ERROR_OK)
1443                 {
1444                         free(target_code);
1445                         return retval;
1446                 }
1447
1448                 free(target_code);
1449         }
1450         /* the following code still assumes target code is fixed 24*4 bytes */
1451
1452         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1453         {
1454                 buffer_size /= 2;
1455                 if (buffer_size <= 256)
1456                 {
1457                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1458                         if (cfi_info->write_algorithm)
1459                                 target_free_working_area(target, cfi_info->write_algorithm);
1460
1461                         LOG_WARNING("not enough working area available, can't do block memory writes");
1462                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1463                 }
1464         };
1465
1466         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1467         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1468         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1469         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1470         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1471         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1472         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1473         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1474         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1475         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1476
1477         while (count > 0)
1478         {
1479                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1480
1481                 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1482
1483                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1484                 buf_set_u32(reg_params[1].value, 0, 32, address);
1485                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1486                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1487                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1488                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1489                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1490                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1491                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1492
1493                 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1494                                                      cfi_info->write_algorithm->address,
1495                                                      cfi_info->write_algorithm->address + ((target_code_size) - 4),
1496                                                      10000, &armv4_5_info);
1497
1498                 status = buf_get_u32(reg_params[5].value, 0, 32);
1499
1500                 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1501                 {
1502                         LOG_DEBUG("status: 0x%" PRIx32 , status);
1503                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1504                         break;
1505                 }
1506
1507                 buffer += thisrun_count;
1508                 address += thisrun_count;
1509                 count -= thisrun_count;
1510         }
1511
1512         target_free_all_working_areas(target);
1513
1514         destroy_reg_param(&reg_params[0]);
1515         destroy_reg_param(&reg_params[1]);
1516         destroy_reg_param(&reg_params[2]);
1517         destroy_reg_param(&reg_params[3]);
1518         destroy_reg_param(&reg_params[4]);
1519         destroy_reg_param(&reg_params[5]);
1520         destroy_reg_param(&reg_params[6]);
1521         destroy_reg_param(&reg_params[7]);
1522         destroy_reg_param(&reg_params[8]);
1523         destroy_reg_param(&reg_params[9]);
1524
1525         return exit_code;
1526 }
1527
1528 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1529 {
1530         int retval;
1531         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1532         struct target *target = bank->target;
1533
1534         cfi_intel_clear_status_register(bank);
1535         if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1536         {
1537                 return retval;
1538         }
1539
1540         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1541         {
1542                 return retval;
1543         }
1544
1545         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1546         {
1547                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1548                 {
1549                         return retval;
1550                 }
1551
1552                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1553                 return ERROR_FLASH_OPERATION_FAILED;
1554         }
1555
1556         return ERROR_OK;
1557 }
1558
1559 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1560 {
1561         int retval;
1562         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1563         struct target *target = bank->target;
1564
1565         /* Calculate buffer size and boundary mask */
1566         /* buffersize is (buffer size per chip) * (number of chips) */
1567         /* bufferwsize is buffersize in words */
1568         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1569         uint32_t buffermask = buffersize-1;
1570         uint32_t bufferwsize = buffersize / bank->bus_width;
1571
1572         /* Check for valid range */
1573         if (address & buffermask)
1574         {
1575                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1576                           bank->base, address, cfi_info->max_buf_write_size);
1577                 return ERROR_FLASH_OPERATION_FAILED;
1578         }
1579
1580         /* Check for valid size */
1581         if (wordcount > bufferwsize)
1582         {
1583                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1584                 return ERROR_FLASH_OPERATION_FAILED;
1585         }
1586
1587         /* Write to flash buffer */
1588         cfi_intel_clear_status_register(bank);
1589
1590         /* Initiate buffer operation _*/
1591         if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1592         {
1593                 return retval;
1594         }
1595         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1596         {
1597                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1598                 {
1599                         return retval;
1600                 }
1601
1602                 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1603                 return ERROR_FLASH_OPERATION_FAILED;
1604         }
1605
1606         /* Write buffer wordcount-1 and data words */
1607         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1608         {
1609                 return retval;
1610         }
1611
1612         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1613         {
1614                 return retval;
1615         }
1616
1617         /* Commit write operation */
1618         if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1619         {
1620                 return retval;
1621         }
1622         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1623         {
1624                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1625                 {
1626                         return retval;
1627                 }
1628
1629                 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1630                 return ERROR_FLASH_OPERATION_FAILED;
1631         }
1632
1633         return ERROR_OK;
1634 }
1635
1636 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1637 {
1638         int retval;
1639         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1640         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1641         struct target *target = bank->target;
1642
1643         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1644         {
1645                 return retval;
1646         }
1647
1648         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1649         {
1650                 return retval;
1651         }
1652
1653         if ((retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1654         {
1655                 return retval;
1656         }
1657
1658         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1659         {
1660                 return retval;
1661         }
1662
1663         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1664         {
1665                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1666                 {
1667                         return retval;
1668                 }
1669
1670                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1671                 return ERROR_FLASH_OPERATION_FAILED;
1672         }
1673
1674         return ERROR_OK;
1675 }
1676
1677 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1678 {
1679         int retval;
1680         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1681         struct target *target = bank->target;
1682         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1683
1684         /* Calculate buffer size and boundary mask */
1685         /* buffersize is (buffer size per chip) * (number of chips) */
1686         /* bufferwsize is buffersize in words */
1687         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1688         uint32_t buffermask = buffersize-1;
1689         uint32_t bufferwsize = buffersize / bank->bus_width;
1690
1691         /* Check for valid range */
1692         if (address & buffermask)
1693         {
1694                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1695                 return ERROR_FLASH_OPERATION_FAILED;
1696         }
1697
1698         /* Check for valid size */
1699         if (wordcount > bufferwsize)
1700         {
1701                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1702                 return ERROR_FLASH_OPERATION_FAILED;
1703         }
1704
1705         // Unlock
1706         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1707         {
1708                 return retval;
1709         }
1710
1711         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1712         {
1713                 return retval;
1714         }
1715
1716         // Buffer load command
1717         if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1718         {
1719                 return retval;
1720         }
1721
1722         /* Write buffer wordcount-1 and data words */
1723         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1724         {
1725                 return retval;
1726         }
1727
1728         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1729         {
1730                 return retval;
1731         }
1732
1733         /* Commit write operation */
1734         if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
1735         {
1736                 return retval;
1737         }
1738
1739         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1740         {
1741                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1742                 {
1743                         return retval;
1744                 }
1745
1746                 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1747                 return ERROR_FLASH_OPERATION_FAILED;
1748         }
1749
1750         return ERROR_OK;
1751 }
1752
1753 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1754 {
1755         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1756
1757         switch (cfi_info->pri_id)
1758         {
1759                 case 1:
1760                 case 3:
1761                         return cfi_intel_write_word(bank, word, address);
1762                         break;
1763                 case 2:
1764                         return cfi_spansion_write_word(bank, word, address);
1765                         break;
1766                 default:
1767                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1768                         break;
1769         }
1770
1771         return ERROR_FLASH_OPERATION_FAILED;
1772 }
1773
1774 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1775 {
1776         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1777
1778         switch (cfi_info->pri_id)
1779         {
1780                 case 1:
1781                 case 3:
1782                         return cfi_intel_write_words(bank, word, wordcount, address);
1783                         break;
1784                 case 2:
1785                         return cfi_spansion_write_words(bank, word, wordcount, address);
1786                         break;
1787                 default:
1788                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1789                         break;
1790         }
1791
1792         return ERROR_FLASH_OPERATION_FAILED;
1793 }
1794
1795 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1796 {
1797         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1798         struct target *target = bank->target;
1799         uint32_t address = bank->base + offset;
1800         uint32_t read_p;
1801         int align;      /* number of unaligned bytes */
1802         uint8_t current_word[CFI_MAX_BUS_WIDTH];
1803         int i;
1804         int retval;
1805
1806         LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
1807                 (int)count, (unsigned)offset);
1808
1809         if (bank->target->state != TARGET_HALTED)
1810         {
1811                 LOG_ERROR("Target not halted");
1812                 return ERROR_TARGET_NOT_HALTED;
1813         }
1814
1815         if (offset + count > bank->size)
1816                 return ERROR_FLASH_DST_OUT_OF_BANK;
1817
1818         if (cfi_info->qry[0] != 'Q')
1819                 return ERROR_FLASH_BANK_NOT_PROBED;
1820
1821         /* start at the first byte of the first word (bus_width size) */
1822         read_p = address & ~(bank->bus_width - 1);
1823         if ((align = address - read_p) != 0)
1824         {
1825                 LOG_INFO("Fixup %d unaligned read head bytes", align);
1826
1827                 /* read a complete word from flash */
1828                 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
1829                         return retval;
1830
1831                 /* take only bytes we need */
1832                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
1833                         *buffer++ = current_word[i];
1834
1835                 read_p += bank->bus_width;
1836         }
1837
1838         align = count / bank->bus_width;
1839         if (align)
1840         {
1841                 if ((retval = target_read_memory(target, read_p, bank->bus_width, align, buffer)) != ERROR_OK)
1842                         return retval;
1843
1844                 read_p += align * bank->bus_width;
1845                 buffer += align * bank->bus_width;
1846                 count -= align * bank->bus_width;
1847         }
1848
1849         if (count)
1850         {
1851                 LOG_INFO("Fixup %d unaligned read tail bytes", count);
1852
1853                 /* read a complete word from flash */
1854                 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
1855                         return retval;
1856
1857                 /* take only bytes we need */
1858                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
1859                         *buffer++ = current_word[i];
1860         }
1861
1862         return ERROR_OK;
1863 }
1864
1865 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1866 {
1867         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1868         struct target *target = bank->target;
1869         uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1870         uint32_t write_p;
1871         int align;      /* number of unaligned bytes */
1872         int blk_count; /* number of bus_width bytes for block copy */
1873         uint8_t current_word[CFI_MAX_BUS_WIDTH * 4];    /* word (bus_width size) currently being programmed */
1874         int i;
1875         int retval;
1876
1877         if (bank->target->state != TARGET_HALTED)
1878         {
1879                 LOG_ERROR("Target not halted");
1880                 return ERROR_TARGET_NOT_HALTED;
1881         }
1882
1883         if (offset + count > bank->size)
1884                 return ERROR_FLASH_DST_OUT_OF_BANK;
1885
1886         if (cfi_info->qry[0] != 'Q')
1887                 return ERROR_FLASH_BANK_NOT_PROBED;
1888
1889         /* start at the first byte of the first word (bus_width size) */
1890         write_p = address & ~(bank->bus_width - 1);
1891         if ((align = address - write_p) != 0)
1892         {
1893                 LOG_INFO("Fixup %d unaligned head bytes", align);
1894
1895                 /* read a complete word from flash */
1896                 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
1897                         return retval;
1898
1899                 /* replace only bytes that must be written */
1900                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
1901                         current_word[i] = *buffer++;
1902
1903                 retval = cfi_write_word(bank, current_word, write_p);
1904                 if (retval != ERROR_OK)
1905                         return retval;
1906                 write_p += bank->bus_width;
1907         }
1908
1909         /* handle blocks of bus_size aligned bytes */
1910         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1911         switch (cfi_info->pri_id)
1912         {
1913                 /* try block writes (fails without working area) */
1914                 case 1:
1915                 case 3:
1916                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1917                         break;
1918                 case 2:
1919                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1920                         break;
1921                 default:
1922                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1923                         retval = ERROR_FLASH_OPERATION_FAILED;
1924                         break;
1925         }
1926         if (retval == ERROR_OK)
1927         {
1928                 /* Increment pointers and decrease count on succesful block write */
1929                 buffer += blk_count;
1930                 write_p += blk_count;
1931                 count -= blk_count;
1932         }
1933         else
1934         {
1935                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1936                 {
1937                         /* Calculate buffer size and boundary mask */
1938                         /* buffersize is (buffer size per chip) * (number of chips) */
1939                         /* bufferwsize is buffersize in words */
1940                         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1941                         uint32_t buffermask = buffersize-1;
1942                         uint32_t bufferwsize = buffersize / bank->bus_width;
1943
1944                         /* fall back to memory writes */
1945                         while (count >= (uint32_t)bank->bus_width)
1946                         {
1947                                 int fallback;
1948                                 if ((write_p & 0xff) == 0)
1949                                 {
1950                                         LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
1951                                 }
1952                                 fallback = 1;
1953                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1954                                 {
1955                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1956                                         if (retval == ERROR_OK)
1957                                         {
1958                                                 buffer += buffersize;
1959                                                 write_p += buffersize;
1960                                                 count -= buffersize;
1961                                                 fallback = 0;
1962                                         }
1963                                 }
1964                                 /* try the slow way? */
1965                                 if (fallback)
1966                                 {
1967                                         for (i = 0; i < bank->bus_width; i++)
1968                                                 current_word[i] = *buffer++;
1969
1970                                         retval = cfi_write_word(bank, current_word, write_p);
1971                                         if (retval != ERROR_OK)
1972                                                 return retval;
1973
1974                                         write_p += bank->bus_width;
1975                                         count -= bank->bus_width;
1976                                 }
1977                         }
1978                 }
1979                 else
1980                         return retval;
1981         }
1982
1983         /* return to read array mode, so we can read from flash again for padding */
1984         if ((retval = cfi_reset(bank)) != ERROR_OK)
1985         {
1986                 return retval;
1987         }
1988
1989         /* handle unaligned tail bytes */
1990         if (count > 0)
1991         {
1992                 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
1993
1994                 /* read a complete word from flash */
1995                 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
1996                         return retval;
1997
1998                 /* replace only bytes that must be written */
1999                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2000                         current_word[i] = *buffer++;
2001
2002                 retval = cfi_write_word(bank, current_word, write_p);
2003                 if (retval != ERROR_OK)
2004                         return retval;
2005         }
2006
2007         /* return to read array mode */
2008         return cfi_reset(bank);
2009 }
2010
2011 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
2012 {
2013         (void) param;
2014         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2015         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2016
2017         pri_ext->_reversed_geometry = 1;
2018 }
2019
2020 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2021 {
2022         int i;
2023         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2024         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2025         (void) param;
2026
2027         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2028         {
2029                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2030
2031                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2032                 {
2033                         int j = (cfi_info->num_erase_regions - 1) - i;
2034                         uint32_t swap;
2035
2036                         swap = cfi_info->erase_region_info[i];
2037                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2038                         cfi_info->erase_region_info[j] = swap;
2039                 }
2040         }
2041 }
2042
2043 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2044 {
2045         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2046         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2047         struct cfi_unlock_addresses *unlock_addresses = param;
2048
2049         pri_ext->_unlock1 = unlock_addresses->unlock1;
2050         pri_ext->_unlock2 = unlock_addresses->unlock2;
2051 }
2052
2053
2054 static int cfi_query_string(struct flash_bank *bank, int address)
2055 {
2056         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2057         int retval;
2058
2059         if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2060         {
2061                 return retval;
2062         }
2063
2064         cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2065         cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2066         cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2067
2068         LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2069
2070         if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2071         {
2072                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2073                 {
2074                         return retval;
2075                 }
2076                 LOG_ERROR("Could not probe bank: no QRY");
2077                 return ERROR_FLASH_BANK_INVALID;
2078         }
2079
2080         return ERROR_OK;
2081 }
2082
2083 static int cfi_probe(struct flash_bank *bank)
2084 {
2085         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2086         struct target *target = bank->target;
2087         int num_sectors = 0;
2088         int i;
2089         int sector = 0;
2090         uint32_t unlock1 = 0x555;
2091         uint32_t unlock2 = 0x2aa;
2092         int retval;
2093         uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2094
2095         if (bank->target->state != TARGET_HALTED)
2096         {
2097                 LOG_ERROR("Target not halted");
2098                 return ERROR_TARGET_NOT_HALTED;
2099         }
2100
2101         cfi_info->probed = 0;
2102
2103         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2104          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2105          */
2106         if (cfi_info->jedec_probe)
2107         {
2108                 unlock1 = 0x5555;
2109                 unlock2 = 0x2aaa;
2110         }
2111
2112         /* switch to read identifier codes mode ("AUTOSELECT") */
2113         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2114         {
2115                 return retval;
2116         }
2117         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2118         {
2119                 return retval;
2120         }
2121         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2122         {
2123                 return retval;
2124         }
2125
2126         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, value_buf0)) != ERROR_OK)
2127         {
2128                 return retval;
2129         }
2130         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01), bank->bus_width, 1, value_buf1)) != ERROR_OK)
2131         {
2132                 return retval;
2133         }
2134         switch (bank->chip_width) {
2135                 case 1:
2136                         cfi_info->manufacturer = *value_buf0;
2137                         cfi_info->device_id = *value_buf1;
2138                         break;
2139                 case 2:
2140                         cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2141                         cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2142                         break;
2143                 case 4:
2144                         cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2145                         cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2146                         break;
2147                 default:
2148                         LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
2149                         return ERROR_FLASH_OPERATION_FAILED;
2150         }
2151
2152         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2153         /* switch back to read array mode */
2154         if ((retval = cfi_reset(bank)) != ERROR_OK)
2155         {
2156                 return retval;
2157         }
2158
2159         /* check device/manufacturer ID for known non-CFI flashes. */
2160         cfi_fixup_non_cfi(bank);
2161
2162         /* query only if this is a CFI compatible flash,
2163          * otherwise the relevant info has already been filled in
2164          */
2165         if (cfi_info->not_cfi == 0)
2166         {
2167                 int retval;
2168
2169                 /* enter CFI query mode
2170                  * according to JEDEC Standard No. 68.01,
2171                  * a single bus sequence with address = 0x55, data = 0x98 should put
2172                  * the device into CFI query mode.
2173                  *
2174                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2175                  */
2176
2177                 retval = cfi_query_string(bank, 0x55);
2178                 if (retval != ERROR_OK)
2179                 {
2180                         /*
2181                          * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2182                          * be harmless enough:
2183                          *
2184                          * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2185                          */
2186                         LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2187                         retval = cfi_query_string(bank, 0x555);
2188                 }
2189                 if (retval != ERROR_OK)
2190                         return retval;
2191
2192                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2193                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2194                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2195                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2196
2197                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2198
2199                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2200                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2201                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2202                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2203                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2204                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2205                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2206                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2207                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2208                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2209                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2210                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2211
2212                 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2213                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2214                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2215                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2216                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2217                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2218                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2219                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2220                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2221                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2222                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2223
2224                 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2225                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2226                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2227                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2228
2229                 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2230
2231                 if (cfi_info->num_erase_regions)
2232                 {
2233                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2234                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2235                         {
2236                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2237                                 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2238                                           i,
2239                                           (cfi_info->erase_region_info[i] & 0xffff) + 1,
2240                                           (cfi_info->erase_region_info[i] >> 16) * 256);
2241                         }
2242                 }
2243                 else
2244                 {
2245                         cfi_info->erase_region_info = NULL;
2246                 }
2247
2248                 /* We need to read the primary algorithm extended query table before calculating
2249                  * the sector layout to be able to apply fixups
2250                  */
2251                 switch (cfi_info->pri_id)
2252                 {
2253                         /* Intel command set (standard and extended) */
2254                         case 0x0001:
2255                         case 0x0003:
2256                                 cfi_read_intel_pri_ext(bank);
2257                                 break;
2258                         /* AMD/Spansion, Atmel, ... command set */
2259                         case 0x0002:
2260                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2261                                 cfi_read_0002_pri_ext(bank);
2262                                 break;
2263                         default:
2264                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2265                                 break;
2266                 }
2267
2268                 /* return to read array mode
2269                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2270                  */
2271                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2272                 {
2273                         return retval;
2274                 }
2275         } /* end CFI case */
2276
2277         /* apply fixups depending on the primary command set */
2278         switch (cfi_info->pri_id)
2279         {
2280                 /* Intel command set (standard and extended) */
2281                 case 0x0001:
2282                 case 0x0003:
2283                         cfi_fixup(bank, cfi_0001_fixups);
2284                         break;
2285                 /* AMD/Spansion, Atmel, ... command set */
2286                 case 0x0002:
2287                         cfi_fixup(bank, cfi_0002_fixups);
2288                         break;
2289                 default:
2290                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2291                         break;
2292         }
2293
2294         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2295         {
2296                 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2297         }
2298
2299         if (cfi_info->num_erase_regions == 0)
2300         {
2301                 /* a device might have only one erase block, spanning the whole device */
2302                 bank->num_sectors = 1;
2303                 bank->sectors = malloc(sizeof(struct flash_sector));
2304
2305                 bank->sectors[sector].offset = 0x0;
2306                 bank->sectors[sector].size = bank->size;
2307                 bank->sectors[sector].is_erased = -1;
2308                 bank->sectors[sector].is_protected = -1;
2309         }
2310         else
2311         {
2312                 uint32_t offset = 0;
2313
2314                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2315                 {
2316                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2317                 }
2318
2319                 bank->num_sectors = num_sectors;
2320                 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2321
2322                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2323                 {
2324                         uint32_t j;
2325                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2326                         {
2327                                 bank->sectors[sector].offset = offset;
2328                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2329                                 offset += bank->sectors[sector].size;
2330                                 bank->sectors[sector].is_erased = -1;
2331                                 bank->sectors[sector].is_protected = -1;
2332                                 sector++;
2333                         }
2334                 }
2335                 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2336                 {
2337                         LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2338                                 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2339                 }
2340         }
2341
2342         cfi_info->probed = 1;
2343
2344         return ERROR_OK;
2345 }
2346
2347 static int cfi_auto_probe(struct flash_bank *bank)
2348 {
2349         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2350         if (cfi_info->probed)
2351                 return ERROR_OK;
2352         return cfi_probe(bank);
2353 }
2354
2355 static int cfi_intel_protect_check(struct flash_bank *bank)
2356 {
2357         int retval;
2358         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2359         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2360         int i;
2361
2362         /* check if block lock bits are supported on this device */
2363         if (!(pri_ext->blk_status_reg_mask & 0x1))
2364                 return ERROR_FLASH_OPERATION_FAILED;
2365
2366         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2367         {
2368                 return retval;
2369         }
2370
2371         for (i = 0; i < bank->num_sectors; i++)
2372         {
2373                 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2374
2375                 if (block_status & 1)
2376                         bank->sectors[i].is_protected = 1;
2377                 else
2378                         bank->sectors[i].is_protected = 0;
2379         }
2380
2381         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2382 }
2383
2384 static int cfi_spansion_protect_check(struct flash_bank *bank)
2385 {
2386         int retval;
2387         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2388         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2389         int i;
2390
2391         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2392         {
2393                 return retval;
2394         }
2395
2396         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2397         {
2398                 return retval;
2399         }
2400
2401         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2402         {
2403                 return retval;
2404         }
2405
2406         for (i = 0; i < bank->num_sectors; i++)
2407         {
2408                 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2409
2410                 if (block_status & 1)
2411                         bank->sectors[i].is_protected = 1;
2412                 else
2413                         bank->sectors[i].is_protected = 0;
2414         }
2415
2416         return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2417 }
2418
2419 static int cfi_protect_check(struct flash_bank *bank)
2420 {
2421         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2422
2423         if (bank->target->state != TARGET_HALTED)
2424         {
2425                 LOG_ERROR("Target not halted");
2426                 return ERROR_TARGET_NOT_HALTED;
2427         }
2428
2429         if (cfi_info->qry[0] != 'Q')
2430                 return ERROR_FLASH_BANK_NOT_PROBED;
2431
2432         switch (cfi_info->pri_id)
2433         {
2434                 case 1:
2435                 case 3:
2436                         return cfi_intel_protect_check(bank);
2437                         break;
2438                 case 2:
2439                         return cfi_spansion_protect_check(bank);
2440                         break;
2441                 default:
2442                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2443                         break;
2444         }
2445
2446         return ERROR_OK;
2447 }
2448
2449 static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2450 {
2451         int printed;
2452         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2453
2454         if (cfi_info->qry[0] == (char)-1)
2455         {
2456                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2457                 return ERROR_OK;
2458         }
2459
2460         if (cfi_info->not_cfi == 0)
2461                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2462         else
2463                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2464         buf += printed;
2465         buf_size -= printed;
2466
2467         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2468                 cfi_info->manufacturer, cfi_info->device_id);
2469         buf += printed;
2470         buf_size -= printed;
2471
2472         if (cfi_info->not_cfi == 0)
2473         {
2474         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2475         buf += printed;
2476         buf_size -= printed;
2477
2478                 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2479                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2480         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2481         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2482         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2483         buf += printed;
2484         buf_size -= printed;
2485
2486                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2487                                    1 << cfi_info->word_write_timeout_typ,
2488                                    1 << cfi_info->buf_write_timeout_typ,
2489                                    1 << cfi_info->block_erase_timeout_typ,
2490                                    1 << cfi_info->chip_erase_timeout_typ);
2491         buf += printed;
2492         buf_size -= printed;
2493
2494                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2495                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2496                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2497                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2498                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2499         buf += printed;
2500         buf_size -= printed;
2501
2502                 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2503                                    cfi_info->dev_size,
2504                                    cfi_info->interface_desc,
2505                                    1 << cfi_info->max_buf_write_size);
2506         buf += printed;
2507         buf_size -= printed;
2508
2509         switch (cfi_info->pri_id)
2510         {
2511                 case 1:
2512                 case 3:
2513                         cfi_intel_info(bank, buf, buf_size);
2514                         break;
2515                 case 2:
2516                         cfi_spansion_info(bank, buf, buf_size);
2517                         break;
2518                 default:
2519                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2520                         break;
2521         }
2522         }
2523
2524         return ERROR_OK;
2525 }
2526
2527 struct flash_driver cfi_flash = {
2528         .name = "cfi",
2529         .flash_bank_command = cfi_flash_bank_command,
2530         .erase = cfi_erase,
2531         .protect = cfi_protect,
2532         .write = cfi_write,
2533         .read = cfi_read,
2534         .probe = cfi_probe,
2535         .auto_probe = cfi_auto_probe,
2536         /* FIXME: access flash at bus_width size */
2537         .erase_check = default_flash_blank_check,
2538         .protect_check = cfi_protect_check,
2539         .info = cfi_info,
2540 };