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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *   Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com>            *
   7  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "imp.h"
  29 #include "cfi.h"
  30 #include "non_cfi.h"
  31 #include <target/arm.h>
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34
  35
  36 #define CFI_MAX_BUS_WIDTH       4
  37 #define CFI_MAX_CHIP_WIDTH      4
  38
  39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  40 #define CFI_MAX_INTEL_CODESIZE 256
  41
  42 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
  43 {
  44         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  45         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  46 };
  47
  48 /* CFI fixups foward declarations */
  49 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
  50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
  51 static void cfi_fixup_reversed_erase_regions(struct flash_bank *flash, void *param);
  52
  53 /* fixup after reading cmdset 0002 primary query table */
  54 static const struct cfi_fixup cfi_0002_fixups[] = {
  55         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  56         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  57         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  58         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  59         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  60         {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  61         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
  62         {CFI_MFR_ST,  0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
  63         {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  64         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  65         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  66         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  67         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  68         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  69         {0, 0, NULL, NULL}
  70 };
  71
  72 /* fixup after reading cmdset 0001 primary query table */
  73 static const struct cfi_fixup cfi_0001_fixups[] = {
  74         {0, 0, NULL, NULL}
  75 };
  76
  77 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
  78 {
  79         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  80         const struct cfi_fixup *f;
  81
  82         for (f = fixups; f->fixup; f++)
  83         {
  84                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
  85                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
  86                 {
  87                         f->fixup(bank, f->param);
  88                 }
  89         }
  90 }
  91
  92 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
  93 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
  94 {
  95         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  96
  97         if (cfi_info->x16_as_x8) offset *= 2;
  98
  99         /* while the sector list isn't built, only accesses to sector 0 work */
 100         if (sector == 0)
 101                 return bank->base + offset * bank->bus_width;
 102         else
 103         {
 104                 if (!bank->sectors)
 105                 {
 106                         LOG_ERROR("BUG: sector list not yet built");
 107                         exit(-1);
 108                 }
 109                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 110         }
 111 }
 112
 113 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
 114 {
 115         int i;
 116
 117         /* clear whole buffer, to ensure bits that exceed the bus_width
 118          * are set to zero
 119          */
 120         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 121                 cmd_buf[i] = 0;
 122
 123         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 124         {
 125                 for (i = bank->bus_width; i > 0; i--)
 126                 {
 127                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 128                 }
 129         }
 130         else
 131         {
 132                 for (i = 1; i <= bank->bus_width; i++)
 133                 {
 134                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 135                 }
 136         }
 137 }
 138
 139 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
 140 {
 141         uint8_t command[CFI_MAX_BUS_WIDTH];
 142
 143         cfi_command(bank, cmd, command);
 144         return target_write_memory(bank->target, address, bank->bus_width, 1, command);
 145 }
 146
 147 /* read unsigned 8-bit value from the bank
 148  * flash banks are expected to be made of similar chips
 149  * the query result should be the same for all
 150  */
 151 static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
 152 {
 153         struct target *target = bank->target;
 154         uint8_t data[CFI_MAX_BUS_WIDTH];
 155
 156         int retval;
 157         retval = target_read_memory(target, flash_address(bank, sector, offset),
 158                         bank->bus_width, 1, data);
 159         if (retval != ERROR_OK)
 160                 return retval;
 161
 162         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 163                 *val = data[0];
 164         else
 165                 *val = data[bank->bus_width - 1];
 166
 167         return ERROR_OK;
 168 }
 169
 170 /* read unsigned 8-bit value from the bank
 171  * in case of a bank made of multiple chips,
 172  * the individual values are ORed
 173  */
 174 static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
 175 {
 176         struct target *target = bank->target;
 177         uint8_t data[CFI_MAX_BUS_WIDTH];
 178         int i;
 179
 180         int retval;
 181         retval = target_read_memory(target, flash_address(bank, sector, offset),
 182                         bank->bus_width, 1, data);
 183         if (retval != ERROR_OK)
 184                 return retval;
 185
 186         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 187         {
 188                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 189                         data[0] |= data[i];
 190
 191                 *val = data[0];
 192         }
 193         else
 194         {
 195                 uint8_t value = 0;
 196                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 197                         value |= data[bank->bus_width - 1 - i];
 198
 199                 *val = value;
 200         }
 201         return ERROR_OK;
 202 }
 203
 204 static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
 205 {
 206         struct target *target = bank->target;
 207         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 208         uint8_t data[CFI_MAX_BUS_WIDTH * 2];
 209         int retval;
 210
 211         if (cfi_info->x16_as_x8)
 212         {
 213                 uint8_t i;
 214                 for (i = 0;i < 2;i++)
 215                 {
 216                         retval = target_read_memory(target, flash_address(bank, sector, offset + i),
 217                                         bank->bus_width, 1, &data[i * bank->bus_width]);
 218                         if (retval != ERROR_OK)
 219                                 return retval;
 220                 }
 221         } else
 222         {
 223                 retval = target_read_memory(target, flash_address(bank, sector, offset),
 224                                 bank->bus_width, 2, data);
 225                 if (retval != ERROR_OK)
 226                         return retval;
 227         }
 228
 229         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 230                 *val = data[0] | data[bank->bus_width] << 8;
 231         else
 232                 *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 233
 234         return ERROR_OK;
 235 }
 236
 237 static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
 238 {
 239         struct target *target = bank->target;
 240         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 241         uint8_t data[CFI_MAX_BUS_WIDTH * 4];
 242         int retval;
 243
 244         if (cfi_info->x16_as_x8)
 245         {
 246                 uint8_t i;
 247                 for (i = 0;i < 4;i++)
 248                 {
 249                         retval = target_read_memory(target, flash_address(bank, sector, offset + i),
 250                                         bank->bus_width, 1, &data[i * bank->bus_width]);
 251                         if (retval != ERROR_OK)
 252                                 return retval;
 253                 }
 254         }
 255         else
 256         {
 257                 retval = target_read_memory(target, flash_address(bank, sector, offset),
 258                                 bank->bus_width, 4, data);
 259                 if (retval != ERROR_OK)
 260                         return retval;
 261         }
 262
 263         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 264                 *val = data[0] | data[bank->bus_width] << 8 |
 265                                 data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 266         else
 267                 *val = data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 268                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 269
 270         return ERROR_OK;
 271 }
 272
 273 static int cfi_reset(struct flash_bank *bank)
 274 {
 275         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 276         int retval = ERROR_OK;
 277
 278         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 279         {
 280                 return retval;
 281         }
 282
 283         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 284         {
 285                 return retval;
 286         }
 287
 288         if (cfi_info->manufacturer == 0x20 &&
 289                         (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
 290         {
 291                 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
 292                  * so we send an extra 0xF0 reset to fix the bug */
 293                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
 294                 {
 295                         return retval;
 296                 }
 297         }
 298
 299         return retval;
 300 }
 301
 302 static void cfi_intel_clear_status_register(struct flash_bank *bank)
 303 {
 304         struct target *target = bank->target;
 305
 306         if (target->state != TARGET_HALTED)
 307         {
 308                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 309                 exit(-1);
 310         }
 311
 312         cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
 313 }
 314
 315 static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
 316 {
 317         uint8_t status;
 318
 319         int retval = ERROR_OK;
 320
 321         for (;;)
 322         {
 323                 if (timeout-- < 0)
 324                 {
 325                         LOG_ERROR("timeout while waiting for WSM to become ready");
 326                         return ERROR_FAIL;
 327                 }
 328
 329                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 330                 if (retval != ERROR_OK)
 331                         return retval;
 332
 333                 if (status & 0x80)
 334                         break;
 335
 336                 alive_sleep(1);
 337         }
 338
 339         /* mask out bit 0 (reserved) */
 340         status = status & 0xfe;
 341
 342         LOG_DEBUG("status: 0x%x", status);
 343
 344         if (status != 0x80)
 345         {
 346                 LOG_ERROR("status register: 0x%x", status);
 347                 if (status & 0x2)
 348                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 349                 if (status & 0x4)
 350                         LOG_ERROR("Program suspended");
 351                 if (status & 0x8)
 352                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 353                 if (status & 0x10)
 354                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 355                 if (status & 0x20)
 356                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 357                 if (status & 0x40)
 358                         LOG_ERROR("Block Erase Suspended");
 359
 360                 cfi_intel_clear_status_register(bank);
 361
 362                 retval = ERROR_FAIL;
 363         }
 364
 365         *val = status;
 366         return retval;
 367 }
 368
 369 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
 370 {
 371         uint8_t status, oldstatus;
 372         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 373         int retval;
 374
 375         retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
 376         if (retval != ERROR_OK)
 377                 return retval;
 378
 379         do {
 380                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 381
 382                 if (retval != ERROR_OK)
 383                         return retval;
 384
 385                 if ((status ^ oldstatus) & 0x40) {
 386                         if (status & cfi_info->status_poll_mask & 0x20) {
 387                                 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
 388                                 if (retval != ERROR_OK)
 389                                         return retval;
 390                                 retval = cfi_get_u8(bank, 0, 0x0, &status);
 391                                 if (retval != ERROR_OK)
 392                                         return retval;
 393                                 if ((status ^ oldstatus) & 0x40) {
 394                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 395                                         return(ERROR_FLASH_OPERATION_FAILED);
 396                                 } else {
 397                                         LOG_DEBUG("status: 0x%x", status);
 398                                         return(ERROR_OK);
 399                                 }
 400                         }
 401                 } else { /* no toggle: finished, OK */
 402                         LOG_DEBUG("status: 0x%x", status);
 403                         return(ERROR_OK);
 404                 }
 405
 406                 oldstatus = status;
 407                 alive_sleep(1);
 408         } while (timeout-- > 0);
 409
 410         LOG_ERROR("timeout, status: 0x%x", status);
 411
 412         return(ERROR_FLASH_BUSY);
 413 }
 414
 415 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
 416 {
 417         int retval;
 418         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 419         struct cfi_intel_pri_ext *pri_ext;
 420
 421         if (cfi_info->pri_ext)
 422                 free(cfi_info->pri_ext);
 423
 424         pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
 425         if (pri_ext == NULL)
 426         {
 427                 LOG_ERROR("Out of memory");
 428                 return ERROR_FAIL;
 429         }
 430         cfi_info->pri_ext = pri_ext;
 431
 432         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
 433         if (retval != ERROR_OK)
 434                 return retval;
 435         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
 436         if (retval != ERROR_OK)
 437                 return retval;
 438         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
 439         if (retval != ERROR_OK)
 440                 return retval;
 441
 442         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 443         {
 444                 if ((retval = cfi_reset(bank)) != ERROR_OK)
 445                 {
 446                         return retval;
 447                 }
 448                 LOG_ERROR("Could not read bank flash bank information");
 449                 return ERROR_FLASH_BANK_INVALID;
 450         }
 451
 452         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
 453         if (retval != ERROR_OK)
 454                 return retval;
 455         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
 456         if (retval != ERROR_OK)
 457                 return retval;
 458
 459         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
 460                         pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 461
 462         retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
 463         if (retval != ERROR_OK)
 464                 return retval;
 465         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
 466         if (retval != ERROR_OK)
 467                 return retval;
 468         retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
 469         if (retval != ERROR_OK)
 470                 return retval;
 471
 472         LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: "
 473                         "0x%x, blk_status_reg_mask: 0x%x",
 474                         pri_ext->feature_support,
 475                         pri_ext->suspend_cmd_support,
 476                         pri_ext->blk_status_reg_mask);
 477
 478         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
 479         if (retval != ERROR_OK)
 480                 return retval;
 481         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
 482         if (retval != ERROR_OK)
 483                 return retval;
 484
 485         LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
 486                         (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 487                         (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 488
 489         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
 490         if (retval != ERROR_OK)
 491                 return retval;
 492         if (pri_ext->num_protection_fields != 1)
 493         {
 494                 LOG_WARNING("expected one protection register field, but found %i",
 495                                 pri_ext->num_protection_fields);
 496         }
 497
 498         retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
 499         if (retval != ERROR_OK)
 500                 return retval;
 501         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
 502         if (retval != ERROR_OK)
 503                 return retval;
 504         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
 505         if (retval != ERROR_OK)
 506                 return retval;
 507
 508         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
 509                         "factory pre-programmed: %i, user programmable: %i",
 510                         pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
 511                         1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 512
 513         return ERROR_OK;
 514 }
 515
 516 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
 517 {
 518         int retval;
 519         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 520         struct cfi_spansion_pri_ext *pri_ext;
 521
 522         if (cfi_info->pri_ext)
 523                 free(cfi_info->pri_ext);
 524
 525         pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 526         if (pri_ext == NULL)
 527         {
 528                 LOG_ERROR("Out of memory");
 529                 return ERROR_FAIL;
 530         }
 531         cfi_info->pri_ext = pri_ext;
 532
 533         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
 534         if (retval != ERROR_OK)
 535                 return retval;
 536         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
 537         if (retval != ERROR_OK)
 538                 return retval;
 539         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
 540         if (retval != ERROR_OK)
 541                 return retval;
 542
 543         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 544         {
 545                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 546                 {
 547                         return retval;
 548                 }
 549                 LOG_ERROR("Could not read spansion bank information");
 550                 return ERROR_FLASH_BANK_INVALID;
 551         }
 552
 553         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
 554         if (retval != ERROR_OK)
 555                 return retval;
 556         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
 557         if (retval != ERROR_OK)
 558                 return retval;
 559
 560         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
 561                         pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 562
 563         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
 564         if (retval != ERROR_OK)
 565                 return retval;
 566         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
 567         if (retval != ERROR_OK)
 568                 return retval;
 569         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
 570         if (retval != ERROR_OK)
 571                 return retval;
 572         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
 573         if (retval != ERROR_OK)
 574                 return retval;
 575         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
 576         if (retval != ERROR_OK)
 577                 return retval;
 578         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
 579         if (retval != ERROR_OK)
 580                 return retval;
 581         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
 582         if (retval != ERROR_OK)
 583                 return retval;
 584         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
 585         if (retval != ERROR_OK)
 586                 return retval;
 587         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
 588         if (retval != ERROR_OK)
 589                 return retval;
 590         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
 591         if (retval != ERROR_OK)
 592                 return retval;
 593         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
 594         if (retval != ERROR_OK)
 595                 return retval;
 596
 597         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
 598                         pri_ext->SiliconRevision, pri_ext->EraseSuspend, pri_ext->BlkProt);
 599
 600         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
 601                         "Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 602                         pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 603
 604         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 605
 606
 607         LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
 608                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 609                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 610
 611         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 612
 613         /* default values for implementation specific workarounds */
 614         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 615         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 616         pri_ext->_reversed_geometry = 0;
 617
 618         return ERROR_OK;
 619 }
 620
 621 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
 622 {
 623         int retval;
 624         struct cfi_atmel_pri_ext atmel_pri_ext;
 625         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 626         struct cfi_spansion_pri_ext *pri_ext;
 627
 628         if (cfi_info->pri_ext)
 629                 free(cfi_info->pri_ext);
 630
 631         pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 632         if (pri_ext == NULL)
 633         {
 634                 LOG_ERROR("Out of memory");
 635                 return ERROR_FAIL;
 636         }
 637
 638         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 639          * but a different primary extended query table.
 640          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 641          */
 642
 643         memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
 644
 645         cfi_info->pri_ext = pri_ext;
 646
 647         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
 648         if (retval != ERROR_OK)
 649                 return retval;
 650         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
 651         if (retval != ERROR_OK)
 652                 return retval;
 653         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
 654         if (retval != ERROR_OK)
 655                 return retval;
 656
 657         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R')
 658                         || (atmel_pri_ext.pri[2] != 'I'))
 659         {
 660                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 661                 {
 662                         return retval;
 663                 }
 664                 LOG_ERROR("Could not read atmel bank information");
 665                 return ERROR_FLASH_BANK_INVALID;
 666         }
 667
 668         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 669         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 670         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 671
 672         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
 673         if (retval != ERROR_OK)
 674                 return retval;
 675         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
 676         if (retval != ERROR_OK)
 677                 return retval;
 678
 679         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0],
 680                         atmel_pri_ext.pri[1], atmel_pri_ext.pri[2],
 681                         atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 682
 683         pri_ext->major_version = atmel_pri_ext.major_version;
 684         pri_ext->minor_version = atmel_pri_ext.minor_version;
 685
 686         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
 687         if (retval != ERROR_OK)
 688                 return retval;
 689         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
 690         if (retval != ERROR_OK)
 691                 return retval;
 692         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
 693         if (retval != ERROR_OK)
 694                 return retval;
 695         retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
 696         if (retval != ERROR_OK)
 697                 return retval;
 698
 699         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 700                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot,
 701                 atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 702
 703         if (atmel_pri_ext.features & 0x02)
 704                 pri_ext->EraseSuspend = 2;
 705
 706         if (atmel_pri_ext.bottom_boot)
 707                 pri_ext->TopBottom = 2;
 708         else
 709                 pri_ext->TopBottom = 3;
 710
 711         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 712         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 713
 714         return ERROR_OK;
 715 }
 716
 717 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
 718 {
 719         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 720
 721         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 722         {
 723                 return cfi_read_atmel_pri_ext(bank);
 724         }
 725         else
 726         {
 727                 return cfi_read_spansion_pri_ext(bank);
 728         }
 729 }
 730
 731 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
 732 {
 733         int printed;
 734         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 735         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 736
 737         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 738         buf += printed;
 739         buf_size -= printed;
 740
 741         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 742                         pri_ext->pri[1], pri_ext->pri[2],
 743                         pri_ext->major_version, pri_ext->minor_version);
 744         buf += printed;
 745         buf_size -= printed;
 746
 747         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 748                         (pri_ext->SiliconRevision) >> 2,
 749                         (pri_ext->SiliconRevision) & 0x03);
 750         buf += printed;
 751         buf_size -= printed;
 752
 753         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 754                         pri_ext->EraseSuspend,
 755                         pri_ext->BlkProt);
 756         buf += printed;
 757         buf_size -= printed;
 758
 759         printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
 760                         (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 761                         (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 762
 763         return ERROR_OK;
 764 }
 765
 766 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
 767 {
 768         int printed;
 769         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 770         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 771
 772         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 773         buf += printed;
 774         buf_size -= printed;
 775
 776         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 777                         pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 778         buf += printed;
 779         buf_size -= printed;
 780
 781         printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", "
 782                         "suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
 783                         pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 784         buf += printed;
 785         buf_size -= printed;
 786
 787         printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
 788                         (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 789                         (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 790         buf += printed;
 791         buf_size -= printed;
 792
 793         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, "
 794                         "factory pre-programmed: %i, user programmable: %i\n",
 795                         pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
 796                         1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 797
 798         return ERROR_OK;
 799 }
 800
 801 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 802  */
 803 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
 804 {
 805         struct cfi_flash_bank *cfi_info;
 806
 807         if (CMD_ARGC < 6)
 808         {
 809                 LOG_WARNING("incomplete flash_bank cfi configuration");
 810                 return ERROR_FLASH_BANK_INVALID;
 811         }
 812
 813         /* both widths must:
 814          * - not exceed max value;
 815          * - not be null;
 816          * - be equal to a power of 2.
 817          * bus must be wide enought to hold one chip */
 818         if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
 819                         || (bank->bus_width > CFI_MAX_BUS_WIDTH)
 820                         || (bank->chip_width == 0)
 821                         || (bank->bus_width == 0)
 822                         || (bank->chip_width & (bank->chip_width - 1))
 823                         || (bank->bus_width & (bank->bus_width - 1))
 824                         || (bank->chip_width > bank->bus_width))
 825         {
 826                 LOG_ERROR("chip and bus width have to specified in bytes");
 827                 return ERROR_FLASH_BANK_INVALID;
 828         }
 829
 830         cfi_info = malloc(sizeof(struct cfi_flash_bank));
 831         cfi_info->probed = 0;
 832         cfi_info->erase_region_info = NULL;
 833         cfi_info->pri_ext = NULL;
 834         bank->driver_priv = cfi_info;
 835
 836         cfi_info->write_algorithm = NULL;
 837
 838         cfi_info->x16_as_x8 = 0;
 839         cfi_info->jedec_probe = 0;
 840         cfi_info->not_cfi = 0;
 841
 842         for (unsigned i = 6; i < CMD_ARGC; i++)
 843         {
 844                 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
 845                 {
 846                         cfi_info->x16_as_x8 = 1;
 847                 }
 848                 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
 849                 {
 850                         cfi_info->jedec_probe = 1;
 851                 }
 852         }
 853
 854         cfi_info->write_algorithm = NULL;
 855
 856         /* bank wasn't probed yet */
 857         cfi_info->qry[0] = 0xff;
 858
 859         return ERROR_OK;
 860 }
 861
 862 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
 863 {
 864         int retval;
 865         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 866         int i;
 867
 868         cfi_intel_clear_status_register(bank);
 869
 870         for (i = first; i <= last; i++)
 871         {
 872                 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
 873                 {
 874                         return retval;
 875                 }
 876
 877                 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
 878                 {
 879                         return retval;
 880                 }
 881
 882                 uint8_t status;
 883                 retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ),
 884                                 &status);
 885                 if (retval != ERROR_OK)
 886                         return retval;
 887
 888                 if (status == 0x80)
 889                         bank->sectors[i].is_erased = 1;
 890                 else
 891                 {
 892                         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 893                         {
 894                                 return retval;
 895                         }
 896
 897                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
 898                         return ERROR_FLASH_OPERATION_FAILED;
 899                 }
 900         }
 901
 902         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
 903 }
 904
 905 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
 906 {
 907         int retval;
 908         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 909         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 910         int i;
 911
 912         for (i = first; i <= last; i++)
 913         {
 914                 if ((retval = cfi_send_command(bank, 0xaa,
 915                                 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 916                 {
 917                         return retval;
 918                 }
 919
 920                 if ((retval = cfi_send_command(bank, 0x55,
 921                                 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 922                 {
 923                         return retval;
 924                 }
 925
 926                 if ((retval = cfi_send_command(bank, 0x80,
 927                                 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 928                 {
 929                         return retval;
 930                 }
 931
 932                 if ((retval = cfi_send_command(bank, 0xaa,
 933                                 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 934                 {
 935                         return retval;
 936                 }
 937
 938                 if ((retval = cfi_send_command(bank, 0x55,
 939                                 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 940                 {
 941                         return retval;
 942                 }
 943
 944                 if ((retval = cfi_send_command(bank, 0x30,
 945                                 flash_address(bank, i, 0x0))) != ERROR_OK)
 946                 {
 947                         return retval;
 948                 }
 949
 950                 if (cfi_spansion_wait_status_busy(bank,
 951                                 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 952                 {
 953                         bank->sectors[i].is_erased = 1;
 954                 }
 955                 else
 956                 {
 957                         if ((retval = cfi_send_command(bank, 0xf0,
 958                                         flash_address(bank, 0, 0x0))) != ERROR_OK)
 959                         {
 960                                 return retval;
 961                         }
 962
 963                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
 964                                         PRIx32, i, bank->base);
 965                         return ERROR_FLASH_OPERATION_FAILED;
 966                 }
 967         }
 968
 969         return  cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
 970 }
 971
 972 static int cfi_erase(struct flash_bank *bank, int first, int last)
 973 {
 974         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 975
 976         if (bank->target->state != TARGET_HALTED)
 977         {
 978                 LOG_ERROR("Target not halted");
 979                 return ERROR_TARGET_NOT_HALTED;
 980         }
 981
 982         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 983         {
 984                 return ERROR_FLASH_SECTOR_INVALID;
 985         }
 986
 987         if (cfi_info->qry[0] != 'Q')
 988                 return ERROR_FLASH_BANK_NOT_PROBED;
 989
 990         switch (cfi_info->pri_id)
 991         {
 992                 case 1:
 993                 case 3:
 994                         return cfi_intel_erase(bank, first, last);
 995                         break;
 996                 case 2:
 997                         return cfi_spansion_erase(bank, first, last);
 998                         break;
 999                 default:
1000                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1001                         break;
1002         }
1003
1004         return ERROR_OK;
1005 }
1006
1007 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
1008 {
1009         int retval;
1010         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1011         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
1012         int retry = 0;
1013         int i;
1014
1015         /* if the device supports neither legacy lock/unlock (bit 3) nor
1016          * instant individual block locking (bit 5).
1017          */
1018         if (!(pri_ext->feature_support & 0x28))
1019         {
1020                 LOG_ERROR("lock/unlock not supported on flash");
1021                 return ERROR_FLASH_OPERATION_FAILED;
1022         }
1023
1024         cfi_intel_clear_status_register(bank);
1025
1026         for (i = first; i <= last; i++)
1027         {
1028                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
1029                 {
1030                         return retval;
1031                 }
1032                 if (set)
1033                 {
1034                         if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
1035                         {
1036                                 return retval;
1037                         }
1038                         bank->sectors[i].is_protected = 1;
1039                 }
1040                 else
1041                 {
1042                         if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
1043                         {
1044                                 return retval;
1045                         }
1046                         bank->sectors[i].is_protected = 0;
1047                 }
1048
1049                 /* instant individual block locking doesn't require reading of the status register */
1050                 if (!(pri_ext->feature_support & 0x20))
1051                 {
1052                         /* Clear lock bits operation may take up to 1.4s */
1053                         uint8_t status;
1054                         retval = cfi_intel_wait_status_busy(bank, 1400, &status);
1055                         if (retval != ERROR_OK)
1056                                 return retval;
1057                 }
1058                 else
1059                 {
1060                         uint8_t block_status;
1061                         /* read block lock bit, to verify status */
1062                         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
1063                         {
1064                                 return retval;
1065                         }
1066                         retval = cfi_get_u8(bank, i, 0x2, &block_status);
1067                         if (retval != ERROR_OK)
1068                                 return retval;
1069
1070                         if ((block_status & 0x1) != set)
1071                         {
1072                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)",
1073                                                 set, block_status);
1074                                 if ((retval = cfi_send_command(bank, 0x70,
1075                                                 flash_address(bank, 0, 0x55))) != ERROR_OK)
1076                                 {
1077                                         return retval;
1078                                 }
1079                                 uint8_t status;
1080                                 retval = cfi_intel_wait_status_busy(bank, 10, &status);
1081                                 if (retval != ERROR_OK)
1082                                         return retval;
1083
1084                                 if (retry > 10)
1085                                         return ERROR_FLASH_OPERATION_FAILED;
1086                                 else
1087                                 {
1088                                         i--;
1089                                         retry++;
1090                                 }
1091                         }
1092                 }
1093         }
1094
1095         /* if the device doesn't support individual block lock bits set/clear,
1096          * all blocks have been unlocked in parallel, so we set those that should be protected
1097          */
1098         if ((!set) && (!(pri_ext->feature_support & 0x20)))
1099         {
1100                 /* FIX!!! this code path is broken!!!
1101                  *
1102                  * The correct approach is:
1103                  *
1104                  * 1. read out current protection status
1105                  *
1106                  * 2. override read out protection status w/unprotected.
1107                  *
1108                  * 3. re-protect what should be protected.
1109                  *
1110                  */
1111                 for (i = 0; i < bank->num_sectors; i++)
1112                 {
1113                         if (bank->sectors[i].is_protected == 1)
1114                         {
1115                                 cfi_intel_clear_status_register(bank);
1116
1117                                 if ((retval = cfi_send_command(bank, 0x60,
1118                                                 flash_address(bank, i, 0x0))) != ERROR_OK)
1119                                 {
1120                                         return retval;
1121                                 }
1122
1123                                 if ((retval = cfi_send_command(bank, 0x01,
1124                                                 flash_address(bank, i, 0x0))) != ERROR_OK)
1125                                 {
1126                                         return retval;
1127                                 }
1128
1129                                 uint8_t status;
1130                                 retval = cfi_intel_wait_status_busy(bank, 100, &status);
1131                                 if (retval != ERROR_OK)
1132                                         return retval;
1133                         }
1134                 }
1135         }
1136
1137         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
1138 }
1139
1140 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
1141 {
1142         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1143
1144         if (bank->target->state != TARGET_HALTED)
1145         {
1146                 LOG_ERROR("Target not halted");
1147                 return ERROR_TARGET_NOT_HALTED;
1148         }
1149
1150         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
1151         {
1152                 LOG_ERROR("Invalid sector range");
1153                 return ERROR_FLASH_SECTOR_INVALID;
1154         }
1155
1156         if (cfi_info->qry[0] != 'Q')
1157                 return ERROR_FLASH_BANK_NOT_PROBED;
1158
1159         switch (cfi_info->pri_id)
1160         {
1161                 case 1:
1162                 case 3:
1163                         return cfi_intel_protect(bank, set, first, last);
1164                         break;
1165                 default:
1166                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
1167                         return ERROR_FAIL;
1168         }
1169 }
1170
1171 /* Convert code image to target endian */
1172 /* FIXME create general block conversion fcts in target.c?) */
1173 static void cfi_fix_code_endian(struct target *target, uint8_t *dest,
1174                 const uint32_t *src, uint32_t count)
1175 {
1176         uint32_t i;
1177         for (i = 0; i< count; i++)
1178         {
1179                 target_buffer_set_u32(target, dest, *src);
1180                 dest += 4;
1181                 src++;
1182         }
1183 }
1184
1185 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
1186 {
1187         struct target *target = bank->target;
1188
1189         uint8_t buf[CFI_MAX_BUS_WIDTH];
1190         cfi_command(bank, cmd, buf);
1191         switch (bank->bus_width)
1192         {
1193         case 1 :
1194                 return buf[0];
1195                 break;
1196         case 2 :
1197                 return target_buffer_get_u16(target, buf);
1198                 break;
1199         case 4 :
1200                 return target_buffer_get_u32(target, buf);
1201                 break;
1202         default :
1203                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1204                 return 0;
1205         }
1206 }
1207
1208 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
1209                 uint32_t address, uint32_t count)
1210 {
1211         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1212         struct target *target = bank->target;
1213         struct reg_param reg_params[7];
1214         struct arm_algorithm armv4_5_info;
1215         struct working_area *source;
1216         uint32_t buffer_size = 32768;
1217         uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1218
1219         /* algorithm register usage:
1220          * r0: source address (in RAM)
1221          * r1: target address (in Flash)
1222          * r2: count
1223          * r3: flash write command
1224          * r4: status byte (returned to host)
1225          * r5: busy test pattern
1226          * r6: error test pattern
1227          */
1228
1229         static const uint32_t word_32_code[] = {
1230                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1231                 0xe5813000,   /*                str r3, [r1] */
1232                 0xe5814000,   /*                str r4, [r1] */
1233                 0xe5914000,   /* busy:  ldr r4, [r1] */
1234                 0xe0047005,   /*                and r7, r4, r5 */
1235                 0xe1570005,   /*                cmp r7, r5 */
1236                 0x1afffffb,   /*                bne busy */
1237                 0xe1140006,   /*                tst r4, r6 */
1238                 0x1a000003,   /*                bne done */
1239                 0xe2522001,   /*                subs r2, r2, #1 */
1240                 0x0a000001,   /*                beq done */
1241                 0xe2811004,   /*                add r1, r1 #4 */
1242                 0xeafffff2,   /*                b loop */
1243                 0xeafffffe    /* done:  b -2 */
1244         };
1245
1246         static const uint32_t word_16_code[] = {
1247                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1248                 0xe1c130b0,   /*                strh r3, [r1] */
1249                 0xe1c140b0,   /*                strh r4, [r1] */
1250                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1251                 0xe0047005,   /*                and r7, r4, r5 */
1252                 0xe1570005,   /*                cmp r7, r5 */
1253                 0x1afffffb,   /*                bne busy */
1254                 0xe1140006,   /*                tst r4, r6 */
1255                 0x1a000003,   /*                bne done */
1256                 0xe2522001,   /*                subs r2, r2, #1 */
1257                 0x0a000001,   /*                beq done */
1258                 0xe2811002,   /*                add r1, r1 #2 */
1259                 0xeafffff2,   /*                b loop */
1260                 0xeafffffe    /* done:  b -2 */
1261         };
1262
1263         static const uint32_t word_8_code[] = {
1264                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1265                 0xe5c13000,   /*                strb r3, [r1] */
1266                 0xe5c14000,   /*                strb r4, [r1] */
1267                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1268                 0xe0047005,   /*                and r7, r4, r5 */
1269                 0xe1570005,   /*                cmp r7, r5 */
1270                 0x1afffffb,   /*                bne busy */
1271                 0xe1140006,   /*                tst r4, r6 */
1272                 0x1a000003,   /*                bne done */
1273                 0xe2522001,   /*                subs r2, r2, #1 */
1274                 0x0a000001,   /*                beq done */
1275                 0xe2811001,   /*                add r1, r1 #1 */
1276                 0xeafffff2,   /*                b loop */
1277                 0xeafffffe    /* done:  b -2 */
1278         };
1279         uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1280         const uint32_t *target_code_src;
1281         uint32_t target_code_size;
1282         int retval = ERROR_OK;
1283
1284
1285         cfi_intel_clear_status_register(bank);
1286
1287         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1288         armv4_5_info.core_mode = ARM_MODE_SVC;
1289         armv4_5_info.core_state = ARM_STATE_ARM;
1290
1291         /* If we are setting up the write_algorith, we need target_code_src */
1292         /* if not we only need target_code_size. */
1293
1294         /* However, we don't want to create multiple code paths, so we */
1295         /* do the unecessary evaluation of target_code_src, which the */
1296         /* compiler will probably nicely optimize away if not needed */
1297
1298         /* prepare algorithm code for target endian */
1299         switch (bank->bus_width)
1300         {
1301         case 1 :
1302                 target_code_src = word_8_code;
1303                 target_code_size = sizeof(word_8_code);
1304                 break;
1305         case 2 :
1306                 target_code_src = word_16_code;
1307                 target_code_size = sizeof(word_16_code);
1308                 break;
1309         case 4 :
1310                 target_code_src = word_32_code;
1311                 target_code_size = sizeof(word_32_code);
1312                 break;
1313         default:
1314                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1315                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1316         }
1317
1318         /* flash write code */
1319         if (!cfi_info->write_algorithm)
1320         {
1321                 if (target_code_size > sizeof(target_code))
1322                 {
1323                         LOG_WARNING("Internal error - target code buffer to small. "
1324                                         "Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1325                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1326                 }
1327                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1328
1329                 /* Get memory for block write handler */
1330                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1331                 if (retval != ERROR_OK)
1332                 {
1333                         LOG_WARNING("No working area available, can't do block memory writes");
1334                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1335                 };
1336
1337                 /* write algorithm code to working area */
1338                 retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1339                                 target_code_size, target_code);
1340                 if (retval != ERROR_OK)
1341                 {
1342                         LOG_ERROR("Unable to write block write code to target");
1343                         goto cleanup;
1344                 }
1345         }
1346
1347         /* Get a workspace buffer for the data to flash starting with 32k size.
1348            Half size until buffer would be smaller 256 Bytem then fail back */
1349         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1350         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1351         {
1352                 buffer_size /= 2;
1353                 if (buffer_size <= 256)
1354                 {
1355                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1356                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1357                         goto cleanup;
1358                 }
1359         };
1360
1361         /* setup algo registers */
1362         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1363         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1364         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1365         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1366         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1367         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1368         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1369
1370         /* prepare command and status register patterns */
1371         write_command_val = cfi_command_val(bank, 0x40);
1372         busy_pattern_val  = cfi_command_val(bank, 0x80);
1373         error_pattern_val = cfi_command_val(bank, 0x7e);
1374
1375         LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32,
1376                         source->address, buffer_size);
1377
1378         /* Programming main loop */
1379         while (count > 0)
1380         {
1381                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1382                 uint32_t wsm_error;
1383
1384                 if ((retval = target_write_buffer(target, source->address,
1385                                 thisrun_count, buffer)) != ERROR_OK)
1386                 {
1387                         goto cleanup;
1388                 }
1389
1390                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1391                 buf_set_u32(reg_params[1].value, 0, 32, address);
1392                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1393
1394                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1395                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1396                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1397
1398                 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1399
1400                 /* Execute algorithm, assume breakpoint for last instruction */
1401                 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1402                         cfi_info->write_algorithm->address,
1403                         cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1404                         10000, /* 10s should be enough for max. 32k of data */
1405                         &armv4_5_info);
1406
1407                 /* On failure try a fall back to direct word writes */
1408                 if (retval != ERROR_OK)
1409                 {
1410                         cfi_intel_clear_status_register(bank);
1411                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1412                         retval = ERROR_FLASH_OPERATION_FAILED;
1413                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1414                         /* FIXME To allow fall back or recovery, we must save the actual status
1415                          * somewhere, so that a higher level code can start recovery. */
1416                         goto cleanup;
1417                 }
1418
1419                 /* Check return value from algo code */
1420                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1421                 if (wsm_error)
1422                 {
1423                         /* read status register (outputs debug inforation) */
1424                         uint8_t status;
1425                         cfi_intel_wait_status_busy(bank, 100, &status);
1426                         cfi_intel_clear_status_register(bank);
1427                         retval = ERROR_FLASH_OPERATION_FAILED;
1428                         goto cleanup;
1429                 }
1430
1431                 buffer += thisrun_count;
1432                 address += thisrun_count;
1433                 count -= thisrun_count;
1434
1435                 keep_alive();
1436         }
1437
1438         /* free up resources */
1439 cleanup:
1440         if (source)
1441                 target_free_working_area(target, source);
1442
1443         if (cfi_info->write_algorithm)
1444         {
1445                 target_free_working_area(target, cfi_info->write_algorithm);
1446                 cfi_info->write_algorithm = NULL;
1447         }
1448
1449         destroy_reg_param(&reg_params[0]);
1450         destroy_reg_param(&reg_params[1]);
1451         destroy_reg_param(&reg_params[2]);
1452         destroy_reg_param(&reg_params[3]);
1453         destroy_reg_param(&reg_params[4]);
1454         destroy_reg_param(&reg_params[5]);
1455         destroy_reg_param(&reg_params[6]);
1456
1457         return retval;
1458 }
1459
1460 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
1461                 uint32_t address, uint32_t count)
1462 {
1463         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1464         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1465         struct target *target = bank->target;
1466         struct reg_param reg_params[10];
1467         struct arm_algorithm armv4_5_info;
1468         struct working_area *source;
1469         uint32_t buffer_size = 32768;
1470         uint32_t status;
1471         int retval = ERROR_OK;
1472
1473         /* input parameters - */
1474         /*      R0 = source address */
1475         /*      R1 = destination address */
1476         /*      R2 = number of writes */
1477         /*      R3 = flash write command */
1478         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1479         /* output parameters - */
1480         /*      R5 = 0x80 ok 0x00 bad */
1481         /* temp registers - */
1482         /*      R6 = value read from flash to test status */
1483         /*      R7 = holding register */
1484         /* unlock registers - */
1485         /*  R8 = unlock1_addr */
1486         /*  R9 = unlock1_cmd */
1487         /*  R10 = unlock2_addr */
1488         /*  R11 = unlock2_cmd */
1489
1490         static const uint32_t word_32_code[] = {
1491                                                 /* 00008100 <sp_32_code>:               */
1492                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1493                 0xe5889000,             /* str  r9, [r8]                                */
1494                 0xe58ab000,             /* str  r11, [r10]                              */
1495                 0xe5883000,             /* str  r3, [r8]                                */
1496                 0xe5815000,             /* str  r5, [r1]                                */
1497                 0xe1a00000,             /* nop                                                  */
1498                                                 /*                                                              */
1499                                                 /* 00008110 <sp_32_busy>:               */
1500                 0xe5916000,             /* ldr  r6, [r1]                                */
1501                 0xe0257006,             /* eor  r7, r5, r6                              */
1502                 0xe0147007,             /* ands r7, r4, r7                              */
1503                 0x0a000007,             /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1504                 0xe0166124,             /* ands r6, r6, r4, lsr #2              */
1505                 0x0afffff9,             /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1506                 0xe5916000,             /* ldr  r6, [r1]                                */
1507                 0xe0257006,             /* eor  r7, r5, r6                              */
1508                 0xe0147007,             /* ands r7, r4, r7                              */
1509                 0x0a000001,             /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1510                 0xe3a05000,             /* mov  r5, #0  ; 0x0 - return 0x00, error */
1511                 0x1a000004,             /* bne  8154 <sp_32_done>               */
1512                                                 /*                                                              */
1513                                                 /* 00008140 <sp_32_cont>:               */
1514                 0xe2522001,             /* subs r2, r2, #1      ; 0x1           */
1515                 0x03a05080,             /* moveq        r5, #128        ; 0x80  */
1516                 0x0a000001,             /* beq  8154 <sp_32_done>               */
1517                 0xe2811004,             /* add  r1, r1, #4      ; 0x4           */
1518                 0xeaffffe8,             /* b    8100 <sp_32_code>               */
1519                                                 /*                                                              */
1520                                                 /* 00008154 <sp_32_done>:               */
1521                 0xeafffffe              /* b    8154 <sp_32_done>               */
1522                 };
1523
1524                 static const uint32_t word_16_code[] = {
1525                                                 /* 00008158 <sp_16_code>:               */
1526                 0xe0d050b2,             /* ldrh r5, [r0], #2                    */
1527                 0xe1c890b0,             /* strh r9, [r8]                                */
1528                 0xe1cab0b0,             /* strh r11, [r10]                              */
1529                 0xe1c830b0,             /* strh r3, [r8]                                */
1530                 0xe1c150b0,             /* strh r5, [r1]                                */
1531                 0xe1a00000,             /* nop                  (mov r0,r0)             */
1532                                                 /*                                                              */
1533                                                 /* 00008168 <sp_16_busy>:               */
1534                 0xe1d160b0,             /* ldrh r6, [r1]                                */
1535                 0xe0257006,             /* eor  r7, r5, r6                              */
1536                 0xe0147007,             /* ands r7, r4, r7                              */
1537                 0x0a000007,             /* beq  8198 <sp_16_cont>               */
1538                 0xe0166124,             /* ands r6, r6, r4, lsr #2              */
1539                 0x0afffff9,             /* beq  8168 <sp_16_busy>               */
1540                 0xe1d160b0,             /* ldrh r6, [r1]                                */
1541                 0xe0257006,             /* eor  r7, r5, r6                              */
1542                 0xe0147007,             /* ands r7, r4, r7                              */
1543                 0x0a000001,             /* beq  8198 <sp_16_cont>               */
1544                 0xe3a05000,             /* mov  r5, #0  ; 0x0                   */
1545                 0x1a000004,             /* bne  81ac <sp_16_done>               */
1546                                                 /*                                                              */
1547                                                 /* 00008198 <sp_16_cont>:               */
1548                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1549                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1550                 0x0a000001,     /* beq  81ac <sp_16_done>               */
1551                 0xe2811002,     /* add  r1, r1, #2      ; 0x2           */
1552                 0xeaffffe8,     /* b    8158 <sp_16_code>               */
1553                                                 /*                                                              */
1554                                                 /* 000081ac <sp_16_done>:               */
1555                 0xeafffffe              /* b    81ac <sp_16_done>               */
1556                 };
1557
1558                 static const uint32_t word_16_code_dq7only[] = {
1559                                                 /* <sp_16_code>:                                */
1560                 0xe0d050b2,             /* ldrh r5, [r0], #2                    */
1561                 0xe1c890b0,             /* strh r9, [r8]                                */
1562                 0xe1cab0b0,             /* strh r11, [r10]                              */
1563                 0xe1c830b0,             /* strh r3, [r8]                                */
1564                 0xe1c150b0,             /* strh r5, [r1]                                */
1565                 0xe1a00000,             /* nop                  (mov r0,r0)             */
1566                                                 /*                                                              */
1567                                                 /* <sp_16_busy>:                                */
1568                 0xe1d160b0,             /* ldrh r6, [r1]                                */
1569                 0xe0257006,             /* eor  r7, r5, r6                              */
1570                 0xe2177080,             /* ands r7, #0x80                               */
1571                 0x1afffffb,             /* bne  8168 <sp_16_busy>               */
1572                                                 /*                                                              */
1573                 0xe2522001,             /* subs r2, r2, #1      ; 0x1           */
1574                 0x03a05080,             /* moveq        r5, #128        ; 0x80  */
1575                 0x0a000001,             /* beq  81ac <sp_16_done>               */
1576                 0xe2811002,             /* add  r1, r1, #2      ; 0x2           */
1577                 0xeafffff0,             /* b    8158 <sp_16_code>               */
1578                                                 /*                                                              */
1579                                                 /* 000081ac <sp_16_done>:               */
1580                 0xeafffffe              /* b    81ac <sp_16_done>               */
1581                 };
1582
1583                 static const uint32_t word_8_code[] = {
1584                                                 /* 000081b0 <sp_16_code_end>:   */
1585                 0xe4d05001,             /* ldrb r5, [r0], #1                    */
1586                 0xe5c89000,             /* strb r9, [r8]                                */
1587                 0xe5cab000,             /* strb r11, [r10]                              */
1588                 0xe5c83000,             /* strb r3, [r8]                                */
1589                 0xe5c15000,             /* strb r5, [r1]                                */
1590                 0xe1a00000,             /* nop                  (mov r0,r0)             */
1591                                                 /*                                                              */
1592                                                 /* 000081c0 <sp_8_busy>:                */
1593                 0xe5d16000,             /* ldrb r6, [r1]                                */
1594                 0xe0257006,             /* eor  r7, r5, r6                              */
1595                 0xe0147007,             /* ands r7, r4, r7                              */
1596                 0x0a000007,             /* beq  81f0 <sp_8_cont>                */
1597                 0xe0166124,             /* ands r6, r6, r4, lsr #2              */
1598                 0x0afffff9,             /* beq  81c0 <sp_8_busy>                */
1599                 0xe5d16000,             /* ldrb r6, [r1]                                */
1600                 0xe0257006,             /* eor  r7, r5, r6                              */
1601                 0xe0147007,             /* ands r7, r4, r7                              */
1602                 0x0a000001,             /* beq  81f0 <sp_8_cont>                */
1603                 0xe3a05000,             /* mov  r5, #0  ; 0x0                   */
1604                 0x1a000004,             /* bne  8204 <sp_8_done>                */
1605                                                 /*                                                              */
1606                                                 /* 000081f0 <sp_8_cont>:                */
1607                 0xe2522001,             /* subs r2, r2, #1      ; 0x1           */
1608                 0x03a05080,             /* moveq        r5, #128        ; 0x80  */
1609                 0x0a000001,             /* beq  8204 <sp_8_done>                */
1610                 0xe2811001,             /* add  r1, r1, #1      ; 0x1           */
1611                 0xeaffffe8,             /* b    81b0 <sp_16_code_end>   */
1612                                                 /*                                                              */
1613                                                 /* 00008204 <sp_8_done>:                */
1614                 0xeafffffe              /* b    8204 <sp_8_done>                */
1615         };
1616
1617         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1618         armv4_5_info.core_mode = ARM_MODE_SVC;
1619         armv4_5_info.core_state = ARM_STATE_ARM;
1620
1621         int target_code_size;
1622         const uint32_t *target_code_src;
1623
1624         switch (bank->bus_width)
1625         {
1626         case 1 :
1627                 target_code_src = word_8_code;
1628                 target_code_size = sizeof(word_8_code);
1629                 break;
1630         case 2 :
1631                 /* Check for DQ5 support */
1632                 if( cfi_info->status_poll_mask & (1 << 5) )
1633                 {
1634                         target_code_src = word_16_code;
1635                         target_code_size = sizeof(word_16_code);
1636                 }
1637                 else
1638                 {
1639                         /* No DQ5 support. Use DQ7 DATA# polling only. */
1640                         target_code_src = word_16_code_dq7only;
1641                         target_code_size = sizeof(word_16_code_dq7only);
1642                 }
1643                 break;
1644         case 4 :
1645                 target_code_src = word_32_code;
1646                 target_code_size = sizeof(word_32_code);
1647                 break;
1648         default:
1649                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1650                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1651         }
1652
1653         /* flash write code */
1654         if (!cfi_info->write_algorithm)
1655         {
1656                 uint8_t *target_code;
1657
1658                 /* convert bus-width dependent algorithm code to correct endiannes */
1659                 target_code = malloc(target_code_size);
1660                 if (target_code == NULL)
1661                 {
1662                         LOG_ERROR("Out of memory");
1663                         return ERROR_FAIL;
1664                 }
1665                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1666
1667                 /* allocate working area */
1668                 retval = target_alloc_working_area(target, target_code_size,
1669                                 &cfi_info->write_algorithm);
1670                 if (retval != ERROR_OK)
1671                 {
1672                         free(target_code);
1673                         return retval;
1674                 }
1675
1676                 /* write algorithm code to working area */
1677                 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1678                                 target_code_size, target_code)) != ERROR_OK)
1679                 {
1680                         free(target_code);
1681                         return retval;
1682                 }
1683
1684                 free(target_code);
1685         }
1686         /* the following code still assumes target code is fixed 24*4 bytes */
1687
1688         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1689         {
1690                 buffer_size /= 2;
1691                 if (buffer_size <= 256)
1692                 {
1693                         /* if we already allocated the writing code, but failed to get a
1694                          * buffer, free the algorithm */
1695                         if (cfi_info->write_algorithm)
1696                                 target_free_working_area(target, cfi_info->write_algorithm);
1697
1698                         LOG_WARNING("not enough working area available, can't do block memory writes");
1699                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1700                 }
1701         };
1702
1703         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1704         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1705         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1706         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1707         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1708         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1709         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1710         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1711         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1712         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1713
1714         while (count > 0)
1715         {
1716                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1717
1718                 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1719                 if (retval != ERROR_OK)
1720                 {
1721                         break;
1722                 }
1723
1724                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1725                 buf_set_u32(reg_params[1].value, 0, 32, address);
1726                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1727                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1728                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1729                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1730                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1731                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1732                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1733
1734                 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1735                                 cfi_info->write_algorithm->address,
1736                                 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1737                                 10000, &armv4_5_info);
1738                 if (retval != ERROR_OK)
1739                 {
1740                         break;
1741                 }
1742
1743                 status = buf_get_u32(reg_params[5].value, 0, 32);
1744                 if (status != 0x80)
1745                 {
1746                         LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
1747                         retval = ERROR_FLASH_OPERATION_FAILED;
1748                         break;
1749                 }
1750
1751                 buffer += thisrun_count;
1752                 address += thisrun_count;
1753                 count -= thisrun_count;
1754         }
1755
1756         target_free_all_working_areas(target);
1757
1758         destroy_reg_param(&reg_params[0]);
1759         destroy_reg_param(&reg_params[1]);
1760         destroy_reg_param(&reg_params[2]);
1761         destroy_reg_param(&reg_params[3]);
1762         destroy_reg_param(&reg_params[4]);
1763         destroy_reg_param(&reg_params[5]);
1764         destroy_reg_param(&reg_params[6]);
1765         destroy_reg_param(&reg_params[7]);
1766         destroy_reg_param(&reg_params[8]);
1767         destroy_reg_param(&reg_params[9]);
1768
1769         return retval;
1770 }
1771
1772 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1773 {
1774         int retval;
1775         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1776         struct target *target = bank->target;
1777
1778         cfi_intel_clear_status_register(bank);
1779         if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1780         {
1781                 return retval;
1782         }
1783
1784         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1785         {
1786                 return retval;
1787         }
1788
1789         uint8_t status;
1790         retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max),
1791                         &status);
1792         if (retval != 0x80)
1793         {
1794                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1795                 {
1796                         return retval;
1797                 }
1798
1799                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32,
1800                                 bank->base, address);
1801                 return ERROR_FLASH_OPERATION_FAILED;
1802         }
1803
1804         return ERROR_OK;
1805 }
1806
1807 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word,
1808                 uint32_t wordcount, uint32_t address)
1809 {
1810         int retval;
1811         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1812         struct target *target = bank->target;
1813
1814         /* Calculate buffer size and boundary mask */
1815         /* buffersize is (buffer size per chip) * (number of chips) */
1816         /* bufferwsize is buffersize in words */
1817         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1818         uint32_t buffermask = buffersize-1;
1819         uint32_t bufferwsize = buffersize / bank->bus_width;
1820
1821         /* Check for valid range */
1822         if (address & buffermask)
1823         {
1824                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32
1825                                 " not aligned to 2^%d boundary",
1826                                 bank->base, address, cfi_info->max_buf_write_size);
1827                 return ERROR_FLASH_OPERATION_FAILED;
1828         }
1829
1830         /* Check for valid size */
1831         if (wordcount > bufferwsize)
1832         {
1833                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32,
1834                                 wordcount, buffersize);
1835                 return ERROR_FLASH_OPERATION_FAILED;
1836         }
1837
1838         /* Write to flash buffer */
1839         cfi_intel_clear_status_register(bank);
1840
1841         /* Initiate buffer operation _*/
1842         if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1843         {
1844                 return retval;
1845         }
1846         uint8_t status;
1847         retval = cfi_intel_wait_status_busy(bank,
1848                         1000 * (1 << cfi_info->buf_write_timeout_max), &status);
1849         if (retval != ERROR_OK)
1850                 return retval;
1851         if (status != 0x80)
1852         {
1853                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1854                 {
1855                         return retval;
1856                 }
1857
1858                 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32,
1859                                 bank->base, address);
1860                 return ERROR_FLASH_OPERATION_FAILED;
1861         }
1862
1863         /* Write buffer wordcount-1 and data words */
1864         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1865         {
1866                 return retval;
1867         }
1868
1869         if ((retval = target_write_memory(target,
1870                         address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1871         {
1872                 return retval;
1873         }
1874
1875         /* Commit write operation */
1876         if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1877         {
1878                 return retval;
1879         }
1880
1881         retval = cfi_intel_wait_status_busy(bank,
1882                         1000 * (1 << cfi_info->buf_write_timeout_max), &status);
1883         if (retval != ERROR_OK)
1884                 return retval;
1885
1886         if (status != 0x80)
1887         {
1888                 if ((retval = cfi_send_command(bank, 0xff,
1889                                 flash_address(bank, 0, 0x0))) != ERROR_OK)
1890                 {
1891                         return retval;
1892                 }
1893
1894                 LOG_ERROR("Buffer write at base 0x%" PRIx32
1895                                 ", address %" PRIx32 " failed.", bank->base, address);
1896                 return ERROR_FLASH_OPERATION_FAILED;
1897         }
1898
1899         return ERROR_OK;
1900 }
1901
1902 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1903 {
1904         int retval;
1905         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1906         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1907         struct target *target = bank->target;
1908
1909         if ((retval = cfi_send_command(bank, 0xaa,
1910                         flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1911         {
1912                 return retval;
1913         }
1914
1915         if ((retval = cfi_send_command(bank, 0x55,
1916                         flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1917         {
1918                 return retval;
1919         }
1920
1921         if ((retval = cfi_send_command(bank, 0xa0,
1922                         flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1923         {
1924                 return retval;
1925         }
1926
1927         if ((retval = target_write_memory(target,
1928                         address, bank->bus_width, 1, word)) != ERROR_OK)
1929         {
1930                 return retval;
1931         }
1932
1933         if (cfi_spansion_wait_status_busy(bank,
1934                         1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1935         {
1936                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1937                 {
1938                         return retval;
1939                 }
1940
1941                 LOG_ERROR("couldn't write word at base 0x%" PRIx32
1942                                 ", address %" PRIx32 , bank->base, address);
1943                 return ERROR_FLASH_OPERATION_FAILED;
1944         }
1945
1946         return ERROR_OK;
1947 }
1948
1949 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word,
1950                 uint32_t wordcount, uint32_t address)
1951 {
1952         int retval;
1953         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1954         struct target *target = bank->target;
1955         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1956
1957         /* Calculate buffer size and boundary mask */
1958         /* buffersize is (buffer size per chip) * (number of chips) */
1959         /* bufferwsize is buffersize in words */
1960         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1961         uint32_t buffermask = buffersize-1;
1962         uint32_t bufferwsize = buffersize / bank->bus_width;
1963
1964         /* Check for valid range */
1965         if (address & buffermask)
1966         {
1967                 LOG_ERROR("Write address at base 0x%" PRIx32
1968                                 ", address %" PRIx32 " not aligned to 2^%d boundary",
1969                                 bank->base, address, cfi_info->max_buf_write_size);
1970                 return ERROR_FLASH_OPERATION_FAILED;
1971         }
1972
1973         /* Check for valid size */
1974         if (wordcount > bufferwsize)
1975         {
1976                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %"
1977                                 PRId32, wordcount, buffersize);
1978                 return ERROR_FLASH_OPERATION_FAILED;
1979         }
1980
1981         // Unlock
1982         if ((retval = cfi_send_command(bank, 0xaa,
1983                         flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1984         {
1985                 return retval;
1986         }
1987
1988         if ((retval = cfi_send_command(bank, 0x55,
1989                         flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1990         {
1991                 return retval;
1992         }
1993
1994         // Buffer load command
1995         if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1996         {
1997                 return retval;
1998         }
1999
2000         /* Write buffer wordcount-1 and data words */
2001         if ((retval = cfi_send_command(bank,
2002                         bufferwsize-1, address)) != ERROR_OK)
2003         {
2004                 return retval;
2005         }
2006
2007         if ((retval = target_write_memory(target,
2008                         address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
2009         {
2010                 return retval;
2011         }
2012
2013         /* Commit write operation */
2014         if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
2015         {
2016                 return retval;
2017         }
2018
2019         if (cfi_spansion_wait_status_busy(bank,
2020                         1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
2021         {
2022                 if ((retval = cfi_send_command(bank, 0xf0,
2023                                 flash_address(bank, 0, 0x0))) != ERROR_OK)
2024                 {
2025                         return retval;
2026                 }
2027
2028                 LOG_ERROR("couldn't write block at base 0x%" PRIx32
2029                                 ", address %" PRIx32 ", size %" PRIx32, bank->base, address, bufferwsize);
2030                 return ERROR_FLASH_OPERATION_FAILED;
2031         }
2032
2033         return ERROR_OK;
2034 }
2035
2036 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
2037 {
2038         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2039
2040         switch (cfi_info->pri_id)
2041         {
2042                 case 1:
2043                 case 3:
2044                         return cfi_intel_write_word(bank, word, address);
2045                         break;
2046                 case 2:
2047                         return cfi_spansion_write_word(bank, word, address);
2048                         break;
2049                 default:
2050                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2051                         break;
2052         }
2053
2054         return ERROR_FLASH_OPERATION_FAILED;
2055 }
2056
2057 static int cfi_write_words(struct flash_bank *bank, uint8_t *word,
2058                 uint32_t wordcount, uint32_t address)
2059 {
2060         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2061
2062         switch (cfi_info->pri_id)
2063         {
2064                 case 1:
2065                 case 3:
2066                         return cfi_intel_write_words(bank, word, wordcount, address);
2067                         break;
2068                 case 2:
2069                         return cfi_spansion_write_words(bank, word, wordcount, address);
2070                         break;
2071                 default:
2072                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2073                         break;
2074         }
2075
2076         return ERROR_FLASH_OPERATION_FAILED;
2077 }
2078
2079 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2080 {
2081         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2082         struct target *target = bank->target;
2083         uint32_t address = bank->base + offset;
2084         uint32_t read_p;
2085         int align;      /* number of unaligned bytes */
2086         uint8_t current_word[CFI_MAX_BUS_WIDTH];
2087         int i;
2088         int retval;
2089
2090         LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2091                 (int)count, (unsigned)offset);
2092
2093         if (bank->target->state != TARGET_HALTED)
2094         {
2095                 LOG_ERROR("Target not halted");
2096                 return ERROR_TARGET_NOT_HALTED;
2097         }
2098
2099         if (offset + count > bank->size)
2100                 return ERROR_FLASH_DST_OUT_OF_BANK;
2101
2102         if (cfi_info->qry[0] != 'Q')
2103                 return ERROR_FLASH_BANK_NOT_PROBED;
2104
2105         /* start at the first byte of the first word (bus_width size) */
2106         read_p = address & ~(bank->bus_width - 1);
2107         if ((align = address - read_p) != 0)
2108         {
2109                 LOG_INFO("Fixup %d unaligned read head bytes", align);
2110
2111                 /* read a complete word from flash */
2112                 if ((retval = target_read_memory(target, read_p,
2113                                 bank->bus_width, 1, current_word)) != ERROR_OK)
2114                         return retval;
2115
2116                 /* take only bytes we need */
2117                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2118                         *buffer++ = current_word[i];
2119
2120                 read_p += bank->bus_width;
2121         }
2122
2123         align = count / bank->bus_width;
2124         if (align)
2125         {
2126                 if ((retval = target_read_memory(target, read_p,
2127                                 bank->bus_width, align, buffer)) != ERROR_OK)
2128                         return retval;
2129
2130                 read_p += align * bank->bus_width;
2131                 buffer += align * bank->bus_width;
2132                 count -= align * bank->bus_width;
2133         }
2134
2135         if (count)
2136         {
2137                 LOG_INFO("Fixup %d unaligned read tail bytes", count);
2138
2139                 /* read a complete word from flash */
2140                 if ((retval = target_read_memory(target, read_p,
2141                                 bank->bus_width, 1, current_word)) != ERROR_OK)
2142                         return retval;
2143
2144                 /* take only bytes we need */
2145                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2146                         *buffer++ = current_word[i];
2147         }
2148
2149         return ERROR_OK;
2150 }
2151
2152 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2153 {
2154         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2155         struct target *target = bank->target;
2156         uint32_t address = bank->base + offset; /* address of first byte to be programmed */
2157         uint32_t write_p;
2158         int align;      /* number of unaligned bytes */
2159         int blk_count; /* number of bus_width bytes for block copy */
2160         uint8_t current_word[CFI_MAX_BUS_WIDTH * 4];    /* word (bus_width size) currently being programmed */
2161         int i;
2162         int retval;
2163
2164         if (bank->target->state != TARGET_HALTED)
2165         {
2166                 LOG_ERROR("Target not halted");
2167                 return ERROR_TARGET_NOT_HALTED;
2168         }
2169
2170         if (offset + count > bank->size)
2171                 return ERROR_FLASH_DST_OUT_OF_BANK;
2172
2173         if (cfi_info->qry[0] != 'Q')
2174                 return ERROR_FLASH_BANK_NOT_PROBED;
2175
2176         /* start at the first byte of the first word (bus_width size) */
2177         write_p = address & ~(bank->bus_width - 1);
2178         if ((align = address - write_p) != 0)
2179         {
2180                 LOG_INFO("Fixup %d unaligned head bytes", align);
2181
2182                 /* read a complete word from flash */
2183                 if ((retval = target_read_memory(target, write_p,
2184                                 bank->bus_width, 1, current_word)) != ERROR_OK)
2185                         return retval;
2186
2187                 /* replace only bytes that must be written */
2188                 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2189                         current_word[i] = *buffer++;
2190
2191                 retval = cfi_write_word(bank, current_word, write_p);
2192                 if (retval != ERROR_OK)
2193                         return retval;
2194                 write_p += bank->bus_width;
2195         }
2196
2197         /* handle blocks of bus_size aligned bytes */
2198         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
2199         switch (cfi_info->pri_id)
2200         {
2201                 /* try block writes (fails without working area) */
2202                 case 1:
2203                 case 3:
2204                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
2205                         break;
2206                 case 2:
2207                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
2208                         break;
2209                 default:
2210                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2211                         retval = ERROR_FLASH_OPERATION_FAILED;
2212                         break;
2213         }
2214         if (retval == ERROR_OK)
2215         {
2216                 /* Increment pointers and decrease count on succesful block write */
2217                 buffer += blk_count;
2218                 write_p += blk_count;
2219                 count -= blk_count;
2220         }
2221         else
2222         {
2223                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
2224                 {
2225                         /* Calculate buffer size and boundary mask */
2226                         /* buffersize is (buffer size per chip) * (number of chips) */
2227                         /* bufferwsize is buffersize in words */
2228                         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2229                         uint32_t buffermask = buffersize-1;
2230                         uint32_t bufferwsize = buffersize / bank->bus_width;
2231
2232                         /* fall back to memory writes */
2233                         while (count >= (uint32_t)bank->bus_width)
2234                         {
2235                                 int fallback;
2236                                 if ((write_p & 0xff) == 0)
2237                                 {
2238                                         LOG_INFO("Programming at %08" PRIx32 ", count %08"
2239                                                         PRIx32 " bytes remaining", write_p, count);
2240                                 }
2241                                 fallback = 1;
2242                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
2243                                 {
2244                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2245                                         if (retval == ERROR_OK)
2246                                         {
2247                                                 buffer += buffersize;
2248                                                 write_p += buffersize;
2249                                                 count -= buffersize;
2250                                                 fallback = 0;
2251                                         }
2252                                 }
2253                                 /* try the slow way? */
2254                                 if (fallback)
2255                                 {
2256                                         for (i = 0; i < bank->bus_width; i++)
2257                                                 current_word[i] = *buffer++;
2258
2259                                         retval = cfi_write_word(bank, current_word, write_p);
2260                                         if (retval != ERROR_OK)
2261                                                 return retval;
2262
2263                                         write_p += bank->bus_width;
2264                                         count -= bank->bus_width;
2265                                 }
2266                         }
2267                 }
2268                 else
2269                         return retval;
2270         }
2271
2272         /* return to read array mode, so we can read from flash again for padding */
2273         if ((retval = cfi_reset(bank)) != ERROR_OK)
2274         {
2275                 return retval;
2276         }
2277
2278         /* handle unaligned tail bytes */
2279         if (count > 0)
2280         {
2281                 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2282
2283                 /* read a complete word from flash */
2284                 if ((retval = target_read_memory(target, write_p,
2285                                 bank->bus_width, 1, current_word)) != ERROR_OK)
2286                         return retval;
2287
2288                 /* replace only bytes that must be written */
2289                 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2290                         current_word[i] = *buffer++;
2291
2292                 retval = cfi_write_word(bank, current_word, write_p);
2293                 if (retval != ERROR_OK)
2294                         return retval;
2295         }
2296
2297         /* return to read array mode */
2298         return cfi_reset(bank);
2299 }
2300
2301 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param)
2302 {
2303         (void) param;
2304         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2305         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2306
2307         pri_ext->_reversed_geometry = 1;
2308 }
2309
2310 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2311 {
2312         int i;
2313         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2314         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2315         (void) param;
2316
2317         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2318         {
2319                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2320
2321                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2322                 {
2323                         int j = (cfi_info->num_erase_regions - 1) - i;
2324                         uint32_t swap;
2325
2326                         swap = cfi_info->erase_region_info[i];
2327                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2328                         cfi_info->erase_region_info[j] = swap;
2329                 }
2330         }
2331 }
2332
2333 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2334 {
2335         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2336         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2337         struct cfi_unlock_addresses *unlock_addresses = param;
2338
2339         pri_ext->_unlock1 = unlock_addresses->unlock1;
2340         pri_ext->_unlock2 = unlock_addresses->unlock2;
2341 }
2342
2343
2344 static int cfi_query_string(struct flash_bank *bank, int address)
2345 {
2346         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2347         int retval;
2348
2349         if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2350         {
2351                 return retval;
2352         }
2353
2354         retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
2355         if (retval != ERROR_OK)
2356                 return retval;
2357         retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
2358         if (retval != ERROR_OK)
2359                 return retval;
2360         retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
2361         if (retval != ERROR_OK)
2362                 return retval;
2363
2364         LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
2365                         cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2366
2367         if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2368         {
2369                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2370                 {
2371                         return retval;
2372                 }
2373                 LOG_ERROR("Could not probe bank: no QRY");
2374                 return ERROR_FLASH_BANK_INVALID;
2375         }
2376
2377         return ERROR_OK;
2378 }
2379
2380 static int cfi_probe(struct flash_bank *bank)
2381 {
2382         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2383         struct target *target = bank->target;
2384         int num_sectors = 0;
2385         int i;
2386         int sector = 0;
2387         uint32_t unlock1 = 0x555;
2388         uint32_t unlock2 = 0x2aa;
2389         int retval;
2390         uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2391
2392         if (bank->target->state != TARGET_HALTED)
2393         {
2394                 LOG_ERROR("Target not halted");
2395                 return ERROR_TARGET_NOT_HALTED;
2396         }
2397
2398         cfi_info->probed = 0;
2399         if (bank->sectors)
2400         {
2401                 free(bank->sectors);
2402                 bank->sectors = NULL;
2403         }
2404         if(cfi_info->erase_region_info)
2405         {
2406                 free(cfi_info->erase_region_info);
2407                 cfi_info->erase_region_info = NULL;
2408         }
2409
2410         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2411          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2412          */
2413         if (cfi_info->jedec_probe)
2414         {
2415                 unlock1 = 0x5555;
2416                 unlock2 = 0x2aaa;
2417         }
2418
2419         /* switch to read identifier codes mode ("AUTOSELECT") */
2420         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2421         {
2422                 return retval;
2423         }
2424         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2425         {
2426                 return retval;
2427         }
2428         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2429         {
2430                 return retval;
2431         }
2432
2433         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00),
2434                         bank->bus_width, 1, value_buf0)) != ERROR_OK)
2435         {
2436                 return retval;
2437         }
2438         if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01),
2439                         bank->bus_width, 1, value_buf1)) != ERROR_OK)
2440         {
2441                 return retval;
2442         }
2443         switch (bank->chip_width) {
2444                 case 1:
2445                         cfi_info->manufacturer = *value_buf0;
2446                         cfi_info->device_id = *value_buf1;
2447                         break;
2448                 case 2:
2449                         cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2450                         cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2451                         break;
2452                 case 4:
2453                         cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2454                         cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2455                         break;
2456                 default:
2457                         LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
2458                         return ERROR_FLASH_OPERATION_FAILED;
2459         }
2460
2461         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x",
2462                         cfi_info->manufacturer, cfi_info->device_id);
2463         /* switch back to read array mode */
2464         if ((retval = cfi_reset(bank)) != ERROR_OK)
2465         {
2466                 return retval;
2467         }
2468
2469         /* check device/manufacturer ID for known non-CFI flashes. */
2470         cfi_fixup_non_cfi(bank);
2471
2472         /* query only if this is a CFI compatible flash,
2473          * otherwise the relevant info has already been filled in
2474          */
2475         if (cfi_info->not_cfi == 0)
2476         {
2477                 /* enter CFI query mode
2478                  * according to JEDEC Standard No. 68.01,
2479                  * a single bus sequence with address = 0x55, data = 0x98 should put
2480                  * the device into CFI query mode.
2481                  *
2482                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2483                  */
2484
2485                 retval = cfi_query_string(bank, 0x55);
2486                 if (retval != ERROR_OK)
2487                 {
2488                         /*
2489                          * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2490                          * be harmless enough:
2491                          *
2492                          * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2493                          */
2494                         LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2495                         retval = cfi_query_string(bank, 0x555);
2496                 }
2497                 if (retval != ERROR_OK)
2498                         return retval;
2499
2500                 retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
2501                 if (retval != ERROR_OK)
2502                         return retval;
2503                 retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
2504                 if (retval != ERROR_OK)
2505                         return retval;
2506                 retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
2507                 if (retval != ERROR_OK)
2508                         return retval;
2509                 retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
2510                 if (retval != ERROR_OK)
2511                         return retval;
2512
2513                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
2514                                 "0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1],
2515                                 cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr,
2516                                 cfi_info->alt_id, cfi_info->alt_addr);
2517
2518                 retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
2519                 if (retval != ERROR_OK)
2520                         return retval;
2521                 retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
2522                 if (retval != ERROR_OK)
2523                         return retval;
2524                 retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
2525                 if (retval != ERROR_OK)
2526                         return retval;
2527                 retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
2528                 if (retval != ERROR_OK)
2529                         return retval;
2530                 retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
2531                 if (retval != ERROR_OK)
2532                         return retval;
2533                 retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
2534                 if (retval != ERROR_OK)
2535                         return retval;
2536                 retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
2537                 if (retval != ERROR_OK)
2538                         return retval;
2539                 retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
2540                 if (retval != ERROR_OK)
2541                         return retval;
2542                 retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
2543                 if (retval != ERROR_OK)
2544                         return retval;
2545                 retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
2546                 if (retval != ERROR_OK)
2547                         return retval;
2548                 retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
2549                 if (retval != ERROR_OK)
2550                         return retval;
2551                 retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
2552                 if (retval != ERROR_OK)
2553                         return retval;
2554
2555                 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2556                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2557                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2558                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2559                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2560
2561                 LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
2562                                 "typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms",
2563                                 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2564                                 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2565
2566                 LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
2567                                 "max. block erase timeout: %u ms, max. chip erase timeout: %u ms",
2568                                 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2569                                 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2570                                 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2571                                 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2572
2573                 uint8_t data;
2574                 retval = cfi_query_u8(bank, 0, 0x27, &data);
2575                 if (retval != ERROR_OK)
2576                         return retval;
2577                 cfi_info->dev_size = 1 << data;
2578
2579                 retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
2580                 if (retval != ERROR_OK)
2581                         return retval;
2582                 retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
2583                 if (retval != ERROR_OK)
2584                         return retval;
2585                 retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
2586                 if (retval != ERROR_OK)
2587                         return retval;
2588
2589                 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x",
2590                                 cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2591
2592                 if (cfi_info->num_erase_regions)
2593                 {
2594                         cfi_info->erase_region_info = malloc(sizeof(*cfi_info->erase_region_info)
2595                                         * cfi_info->num_erase_regions);
2596                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2597                         {
2598                                 retval = cfi_query_u32(bank, 0, 0x2d + (4 * i), &cfi_info->erase_region_info[i]);
2599                                 if (retval != ERROR_OK)
2600                                         return retval;
2601                                 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "", i,
2602                                                 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2603                                                 (cfi_info->erase_region_info[i] >> 16) * 256);
2604                         }
2605                 }
2606                 else
2607                 {
2608                         cfi_info->erase_region_info = NULL;
2609                 }
2610
2611                 /* We need to read the primary algorithm extended query table before calculating
2612                  * the sector layout to be able to apply fixups
2613                  */
2614                 switch (cfi_info->pri_id)
2615                 {
2616                         /* Intel command set (standard and extended) */
2617                         case 0x0001:
2618                         case 0x0003:
2619                                 cfi_read_intel_pri_ext(bank);
2620                                 break;
2621                         /* AMD/Spansion, Atmel, ... command set */
2622                         case 0x0002:
2623                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2624                                 cfi_read_0002_pri_ext(bank);
2625                                 break;
2626                         default:
2627                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2628                                 break;
2629                 }
2630
2631                 /* return to read array mode
2632                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2633                  */
2634                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2635                 {
2636                         return retval;
2637                 }
2638         } /* end CFI case */
2639
2640         /* apply fixups depending on the primary command set */
2641         switch (cfi_info->pri_id)
2642         {
2643                 /* Intel command set (standard and extended) */
2644                 case 0x0001:
2645                 case 0x0003:
2646                         cfi_fixup(bank, cfi_0001_fixups);
2647                         break;
2648                 /* AMD/Spansion, Atmel, ... command set */
2649                 case 0x0002:
2650                         cfi_fixup(bank, cfi_0002_fixups);
2651                         break;
2652                 default:
2653                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2654                         break;
2655         }
2656
2657         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2658         {
2659                 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32
2660                                 " size flash was found", bank->size, cfi_info->dev_size);
2661         }
2662
2663         if (cfi_info->num_erase_regions == 0)
2664         {
2665                 /* a device might have only one erase block, spanning the whole device */
2666                 bank->num_sectors = 1;
2667                 bank->sectors = malloc(sizeof(struct flash_sector));
2668
2669                 bank->sectors[sector].offset = 0x0;
2670                 bank->sectors[sector].size = bank->size;
2671                 bank->sectors[sector].is_erased = -1;
2672                 bank->sectors[sector].is_protected = -1;
2673         }
2674         else
2675         {
2676                 uint32_t offset = 0;
2677
2678                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2679                 {
2680                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2681                 }
2682
2683                 bank->num_sectors = num_sectors;
2684                 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2685
2686                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2687                 {
2688                         uint32_t j;
2689                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2690                         {
2691                                 bank->sectors[sector].offset = offset;
2692                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256)
2693                                                 * bank->bus_width / bank->chip_width;
2694                                 offset += bank->sectors[sector].size;
2695                                 bank->sectors[sector].is_erased = -1;
2696                                 bank->sectors[sector].is_protected = -1;
2697                                 sector++;
2698                         }
2699                 }
2700                 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2701                 {
2702                         LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2703                                 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2704                 }
2705         }
2706
2707         cfi_info->probed = 1;
2708
2709         return ERROR_OK;
2710 }
2711
2712 static int cfi_auto_probe(struct flash_bank *bank)
2713 {
2714         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2715         if (cfi_info->probed)
2716                 return ERROR_OK;
2717         return cfi_probe(bank);
2718 }
2719
2720 static int cfi_intel_protect_check(struct flash_bank *bank)
2721 {
2722         int retval;
2723         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2724         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2725         int i;
2726
2727         /* check if block lock bits are supported on this device */
2728         if (!(pri_ext->blk_status_reg_mask & 0x1))
2729                 return ERROR_FLASH_OPERATION_FAILED;
2730
2731         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2732         {
2733                 return retval;
2734         }
2735
2736         for (i = 0; i < bank->num_sectors; i++)
2737         {
2738                 uint8_t block_status;
2739                 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2740                 if (retval != ERROR_OK)
2741                         return retval;
2742
2743                 if (block_status & 1)
2744                         bank->sectors[i].is_protected = 1;
2745                 else
2746                         bank->sectors[i].is_protected = 0;
2747         }
2748
2749         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2750 }
2751
2752 static int cfi_spansion_protect_check(struct flash_bank *bank)
2753 {
2754         int retval;
2755         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2756         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2757         int i;
2758
2759         if ((retval = cfi_send_command(bank, 0xaa,
2760                         flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2761         {
2762                 return retval;
2763         }
2764
2765         if ((retval = cfi_send_command(bank, 0x55,
2766                         flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2767         {
2768                 return retval;
2769         }
2770
2771         if ((retval = cfi_send_command(bank, 0x90,
2772                         flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2773         {
2774                 return retval;
2775         }
2776
2777         for (i = 0; i < bank->num_sectors; i++)
2778         {
2779                 uint8_t block_status;
2780                 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2781                 if (retval != ERROR_OK)
2782                         return retval;
2783
2784                 if (block_status & 1)
2785                         bank->sectors[i].is_protected = 1;
2786                 else
2787                         bank->sectors[i].is_protected = 0;
2788         }
2789
2790         return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2791 }
2792
2793 static int cfi_protect_check(struct flash_bank *bank)
2794 {
2795         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2796
2797         if (bank->target->state != TARGET_HALTED)
2798         {
2799                 LOG_ERROR("Target not halted");
2800                 return ERROR_TARGET_NOT_HALTED;
2801         }
2802
2803         if (cfi_info->qry[0] != 'Q')
2804                 return ERROR_FLASH_BANK_NOT_PROBED;
2805
2806         switch (cfi_info->pri_id)
2807         {
2808                 case 1:
2809                 case 3:
2810                         return cfi_intel_protect_check(bank);
2811                         break;
2812                 case 2:
2813                         return cfi_spansion_protect_check(bank);
2814                         break;
2815                 default:
2816                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2817                         break;
2818         }
2819
2820         return ERROR_OK;
2821 }
2822
2823 static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2824 {
2825         int printed;
2826         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2827
2828         if (cfi_info->qry[0] == 0xff)
2829         {
2830                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2831                 return ERROR_OK;
2832         }
2833
2834         if (cfi_info->not_cfi == 0)
2835                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2836         else
2837                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2838         buf += printed;
2839         buf_size -= printed;
2840
2841         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2842                 cfi_info->manufacturer, cfi_info->device_id);
2843         buf += printed;
2844         buf_size -= printed;
2845
2846         if (cfi_info->not_cfi == 0)
2847         {
2848                 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
2849                                 "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
2850                                 cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2],
2851                                 cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2852                 buf += printed;
2853                 buf_size -= printed;
2854
2855                 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, "
2856                                 "Vpp min: %u.%x, Vpp max: %u.%x\n",
2857                                 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2858                                 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2859                                 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2860                                 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2861                 buf += printed;
2862                 buf_size -= printed;
2863
2864                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u us, "
2865                                 "typ. buf write timeout: %u us, "
2866                                 "typ. block erase timeout: %u ms, "
2867                                 "typ. chip erase timeout: %u ms\n",
2868                                 1 << cfi_info->word_write_timeout_typ,
2869                                 1 << cfi_info->buf_write_timeout_typ,
2870                                 1 << cfi_info->block_erase_timeout_typ,
2871                                 1 << cfi_info->chip_erase_timeout_typ);
2872                 buf += printed;
2873                 buf_size -= printed;
2874
2875                 printed = snprintf(buf, buf_size, "max. word write timeout: %u us, "
2876                                 "max. buf write timeout: %u us, max. "
2877                                 "block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
2878                                 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2879                                 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2880                                 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2881                                 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2882                 buf += printed;
2883                 buf_size -= printed;
2884
2885                 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, "
2886                                 "max buffer write size: %x\n",
2887                                 cfi_info->dev_size,
2888                                 cfi_info->interface_desc,
2889                                 1 << cfi_info->max_buf_write_size);
2890                 buf += printed;
2891                 buf_size -= printed;
2892
2893                 switch (cfi_info->pri_id)
2894                 {
2895                         case 1:
2896                         case 3:
2897                                 cfi_intel_info(bank, buf, buf_size);
2898                                 break;
2899                         case 2:
2900                                 cfi_spansion_info(bank, buf, buf_size);
2901                                 break;
2902                         default:
2903                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2904                                 break;
2905                 }
2906         }
2907
2908         return ERROR_OK;
2909 }
2910
2911 struct flash_driver cfi_flash = {
2912         .name = "cfi",
2913         .flash_bank_command = cfi_flash_bank_command,
2914         .erase = cfi_erase,
2915         .protect = cfi_protect,
2916         .write = cfi_write,
2917         .read = cfi_read,
2918         .probe = cfi_probe,
2919         .auto_probe = cfi_auto_probe,
2920         /* FIXME: access flash at bus_width size */
2921         .erase_check = default_flash_blank_check,
2922         .protect_check = cfi_protect_check,
2923         .info = get_cfi_info,
2924 };