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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *   Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com>            *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "imp.h"
  28 #include "cfi.h"
  29 #include "non_cfi.h"
  30 #include <target/arm.h>
  31 #include <helper/binarybuffer.h>
  32 #include <target/algorithm.h>
  33
  34
  35 #define CFI_MAX_BUS_WIDTH       4
  36 #define CFI_MAX_CHIP_WIDTH      4
  37
  38 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  39 #define CFI_MAX_INTEL_CODESIZE 256
  40
  41 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
  42 {
  43         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  44         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  45 };
  46
  47 /* CFI fixups foward declarations */
  48 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
  49 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
  50 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
  51
  52 /* fixup after reading cmdset 0002 primary query table */
  53 static const struct cfi_fixup cfi_0002_fixups[] = {
  54         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  55         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  56         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  57         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  58         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  59         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  60    {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  61         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  62         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  63         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  64         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  65         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  66         {0, 0, NULL, NULL}
  67 };
  68
  69 /* fixup after reading cmdset 0001 primary query table */
  70 static const struct cfi_fixup cfi_0001_fixups[] = {
  71         {0, 0, NULL, NULL}
  72 };
  73
  74 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
  75 {
  76         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  77         const struct cfi_fixup *f;
  78
  79         for (f = fixups; f->fixup; f++)
  80         {
  81                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
  82                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
  83                 {
  84                         f->fixup(bank, f->param);
  85                 }
  86         }
  87 }
  88
  89 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
  90 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
  91 {
  92         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  93
  94         if (cfi_info->x16_as_x8) offset *= 2;
  95
  96         /* while the sector list isn't built, only accesses to sector 0 work */
  97         if (sector == 0)
  98                 return bank->base + offset * bank->bus_width;
  99         else
 100         {
 101                 if (!bank->sectors)
 102                 {
 103                         LOG_ERROR("BUG: sector list not yet built");
 104                         exit(-1);
 105                 }
 106                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 107         }
 108 }
 109
 110 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
 111 {
 112         int i;
 113
 114         /* clear whole buffer, to ensure bits that exceed the bus_width
 115          * are set to zero
 116          */
 117         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 118                 cmd_buf[i] = 0;
 119
 120         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 121         {
 122                 for (i = bank->bus_width; i > 0; i--)
 123                 {
 124                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 125                 }
 126         }
 127         else
 128         {
 129                 for (i = 1; i <= bank->bus_width; i++)
 130                 {
 131                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 132                 }
 133         }
 134 }
 135
 136 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
 137 {
 138     uint8_t command[CFI_MAX_BUS_WIDTH];
 139
 140     cfi_command(bank, cmd, command);
 141     return target_write_memory(bank->target, address, bank->bus_width, 1, command);
 142 }
 143
 144 /* read unsigned 8-bit value from the bank
 145  * flash banks are expected to be made of similar chips
 146  * the query result should be the same for all
 147  */
 148 static uint8_t cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset)
 149 {
 150         struct target *target = bank->target;
 151         uint8_t data[CFI_MAX_BUS_WIDTH];
 152
 153         target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 154
 155         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 156                 return data[0];
 157         else
 158                 return data[bank->bus_width - 1];
 159 }
 160
 161 /* read unsigned 8-bit value from the bank
 162  * in case of a bank made of multiple chips,
 163  * the individual values are ORed
 164  */
 165 static uint8_t cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset)
 166 {
 167         struct target *target = bank->target;
 168         uint8_t data[CFI_MAX_BUS_WIDTH];
 169         int i;
 170
 171         target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 172
 173         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 174         {
 175                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 176                         data[0] |= data[i];
 177
 178                 return data[0];
 179         }
 180         else
 181         {
 182                 uint8_t value = 0;
 183                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 184                         value |= data[bank->bus_width - 1 - i];
 185
 186                 return value;
 187         }
 188 }
 189
 190 static uint16_t cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset)
 191 {
 192         struct target *target = bank->target;
 193         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 194         uint8_t data[CFI_MAX_BUS_WIDTH * 2];
 195
 196         if (cfi_info->x16_as_x8)
 197         {
 198                 uint8_t i;
 199                 for (i = 0;i < 2;i++)
 200                         target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 201                                 &data[i*bank->bus_width]);
 202         }
 203         else
 204                 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 205
 206         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 207                 return data[0] | data[bank->bus_width] << 8;
 208         else
 209                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 210 }
 211
 212 static uint32_t cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset)
 213 {
 214         struct target *target = bank->target;
 215         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 216         uint8_t data[CFI_MAX_BUS_WIDTH * 4];
 217
 218         if (cfi_info->x16_as_x8)
 219         {
 220                 uint8_t i;
 221                 for (i = 0;i < 4;i++)
 222                         target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 223                                 &data[i*bank->bus_width]);
 224         }
 225         else
 226                 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 227
 228         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 229                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 230         else
 231                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 232                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 233 }
 234
 235 static int cfi_reset(struct flash_bank *bank)
 236 {
 237         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 238         int retval = ERROR_OK;
 239
 240         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 241         {
 242                 return retval;
 243         }
 244
 245         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 246         {
 247                 return retval;
 248         }
 249
 250         if (cfi_info->manufacturer == 0x20 &&
 251                         (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
 252         {
 253                 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
 254                  * so we send an extra 0xF0 reset to fix the bug */
 255                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
 256                 {
 257                         return retval;
 258                 }
 259         }
 260
 261         return retval;
 262 }
 263
 264 static void cfi_intel_clear_status_register(struct flash_bank *bank)
 265 {
 266         struct target *target = bank->target;
 267
 268         if (target->state != TARGET_HALTED)
 269         {
 270                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 271                 exit(-1);
 272         }
 273
 274         cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
 275 }
 276
 277 static uint8_t cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout)
 278 {
 279         uint8_t status;
 280
 281         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 282         {
 283                 LOG_DEBUG("status: 0x%x", status);
 284                 alive_sleep(1);
 285         }
 286
 287         /* mask out bit 0 (reserved) */
 288         status = status & 0xfe;
 289
 290         LOG_DEBUG("status: 0x%x", status);
 291
 292         if ((status & 0x80) != 0x80)
 293         {
 294                 LOG_ERROR("timeout while waiting for WSM to become ready");
 295         }
 296         else if (status != 0x80)
 297         {
 298                 LOG_ERROR("status register: 0x%x", status);
 299                 if (status & 0x2)
 300                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 301                 if (status & 0x4)
 302                         LOG_ERROR("Program suspended");
 303                 if (status & 0x8)
 304                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 305                 if (status & 0x10)
 306                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 307                 if (status & 0x20)
 308                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 309                 if (status & 0x40)
 310                         LOG_ERROR("Block Erase Suspended");
 311
 312                 cfi_intel_clear_status_register(bank);
 313         }
 314
 315         return status;
 316 }
 317
 318 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
 319 {
 320         uint8_t status, oldstatus;
 321         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 322
 323         oldstatus = cfi_get_u8(bank, 0, 0x0);
 324
 325         do {
 326                 status = cfi_get_u8(bank, 0, 0x0);
 327                 if ((status ^ oldstatus) & 0x40) {
 328                         if (status & cfi_info->status_poll_mask & 0x20) {
 329                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 330                                 status = cfi_get_u8(bank, 0, 0x0);
 331                                 if ((status ^ oldstatus) & 0x40) {
 332                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 333                                         return(ERROR_FLASH_OPERATION_FAILED);
 334                                 } else {
 335                                         LOG_DEBUG("status: 0x%x", status);
 336                                         return(ERROR_OK);
 337                                 }
 338                         }
 339                 } else { /* no toggle: finished, OK */
 340                         LOG_DEBUG("status: 0x%x", status);
 341                         return(ERROR_OK);
 342                 }
 343
 344                 oldstatus = status;
 345                 alive_sleep(1);
 346         } while (timeout-- > 0);
 347
 348         LOG_ERROR("timeout, status: 0x%x", status);
 349
 350         return(ERROR_FLASH_BUSY);
 351 }
 352
 353 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
 354 {
 355         int retval;
 356         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 357         struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
 358
 359         cfi_info->pri_ext = pri_ext;
 360
 361         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 362         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 363         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 364
 365         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 366         {
 367                 if ((retval = cfi_reset(bank)) != ERROR_OK)
 368                 {
 369                         return retval;
 370                 }
 371                 LOG_ERROR("Could not read bank flash bank information");
 372                 return ERROR_FLASH_BANK_INVALID;
 373         }
 374
 375         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 376         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 377
 378         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 379
 380         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 381         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 382         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 383
 384         LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
 385                   pri_ext->feature_support,
 386                   pri_ext->suspend_cmd_support,
 387                   pri_ext->blk_status_reg_mask);
 388
 389         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 390         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 391
 392         LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
 393                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 394                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 395
 396         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 397         if (pri_ext->num_protection_fields != 1)
 398         {
 399                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 400         }
 401
 402         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 403         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 404         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 405
 406         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 407
 408         return ERROR_OK;
 409 }
 410
 411 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
 412 {
 413         int retval;
 414         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 415         struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 416
 417         cfi_info->pri_ext = pri_ext;
 418
 419         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 420         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 421         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 422
 423         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 424         {
 425                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 426                 {
 427                         return retval;
 428                 }
 429                 LOG_ERROR("Could not read spansion bank information");
 430                 return ERROR_FLASH_BANK_INVALID;
 431         }
 432
 433         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 434         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 435
 436         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 437
 438         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 439         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 440         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 441         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 442         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 443         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 444         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 445         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 446         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 447         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 448         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 449
 450         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 451               pri_ext->EraseSuspend, pri_ext->BlkProt);
 452
 453         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 454               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 455
 456         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 457
 458
 459         LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
 460                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 461                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 462
 463         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 464
 465         /* default values for implementation specific workarounds */
 466         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 467         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 468         pri_ext->_reversed_geometry = 0;
 469
 470         return ERROR_OK;
 471 }
 472
 473 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
 474 {
 475         int retval;
 476         struct cfi_atmel_pri_ext atmel_pri_ext;
 477         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 478         struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 479
 480         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 481          * but a different primary extended query table.
 482          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 483          */
 484
 485         memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
 486
 487         cfi_info->pri_ext = pri_ext;
 488
 489         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 490         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 491         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 492
 493         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 494         {
 495                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 496                 {
 497                         return retval;
 498                 }
 499                 LOG_ERROR("Could not read atmel bank information");
 500                 return ERROR_FLASH_BANK_INVALID;
 501         }
 502
 503         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 504         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 505         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 506
 507         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 508         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 509
 510         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 511
 512         pri_ext->major_version = atmel_pri_ext.major_version;
 513         pri_ext->minor_version = atmel_pri_ext.minor_version;
 514
 515         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 516         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 517         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 518         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 519
 520         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 521                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 522
 523         if (atmel_pri_ext.features & 0x02)
 524                 pri_ext->EraseSuspend = 2;
 525
 526         if (atmel_pri_ext.bottom_boot)
 527                 pri_ext->TopBottom = 2;
 528         else
 529                 pri_ext->TopBottom = 3;
 530
 531         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 532         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 533
 534         return ERROR_OK;
 535 }
 536
 537 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
 538 {
 539         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 540
 541         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 542         {
 543                 return cfi_read_atmel_pri_ext(bank);
 544         }
 545         else
 546         {
 547                 return cfi_read_spansion_pri_ext(bank);
 548         }
 549 }
 550
 551 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
 552 {
 553         int printed;
 554         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 555         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 556
 557         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 558         buf += printed;
 559         buf_size -= printed;
 560
 561         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 562                            pri_ext->pri[1], pri_ext->pri[2],
 563                            pri_ext->major_version, pri_ext->minor_version);
 564         buf += printed;
 565         buf_size -= printed;
 566
 567         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 568                            (pri_ext->SiliconRevision) >> 2,
 569                            (pri_ext->SiliconRevision) & 0x03);
 570         buf += printed;
 571         buf_size -= printed;
 572
 573         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 574                            pri_ext->EraseSuspend,
 575                            pri_ext->BlkProt);
 576         buf += printed;
 577         buf_size -= printed;
 578
 579         printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
 580                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 581                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 582
 583         return ERROR_OK;
 584 }
 585
 586 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
 587 {
 588         int printed;
 589         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 590         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 591
 592         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 593         buf += printed;
 594         buf_size -= printed;
 595
 596         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 597         buf += printed;
 598         buf_size -= printed;
 599
 600         printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 601         buf += printed;
 602         buf_size -= printed;
 603
 604         printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
 605                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 606                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 607         buf += printed;
 608         buf_size -= printed;
 609
 610         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 611
 612         return ERROR_OK;
 613 }
 614
 615 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 616  */
 617 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
 618 {
 619         struct cfi_flash_bank *cfi_info;
 620
 621         if (CMD_ARGC < 6)
 622         {
 623                 LOG_WARNING("incomplete flash_bank cfi configuration");
 624                 return ERROR_FLASH_BANK_INVALID;
 625         }
 626
 627         if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
 628                         || (bank->bus_width > CFI_MAX_BUS_WIDTH))
 629         {
 630                 LOG_ERROR("chip and bus width have to specified in bytes");
 631                 return ERROR_FLASH_BANK_INVALID;
 632         }
 633
 634         cfi_info = malloc(sizeof(struct cfi_flash_bank));
 635         cfi_info->probed = 0;
 636         bank->driver_priv = cfi_info;
 637
 638         cfi_info->write_algorithm = NULL;
 639
 640         cfi_info->x16_as_x8 = 0;
 641         cfi_info->jedec_probe = 0;
 642         cfi_info->not_cfi = 0;
 643
 644         for (unsigned i = 6; i < CMD_ARGC; i++)
 645         {
 646                 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
 647                 {
 648                         cfi_info->x16_as_x8 = 1;
 649                 }
 650                 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
 651                 {
 652                         cfi_info->jedec_probe = 1;
 653                 }
 654         }
 655
 656         cfi_info->write_algorithm = NULL;
 657
 658         /* bank wasn't probed yet */
 659         cfi_info->qry[0] = -1;
 660
 661         return ERROR_OK;
 662 }
 663
 664 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
 665 {
 666         int retval;
 667         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 668         int i;
 669
 670         cfi_intel_clear_status_register(bank);
 671
 672         for (i = first; i <= last; i++)
 673         {
 674                 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
 675                 {
 676                         return retval;
 677                 }
 678
 679                 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
 680                 {
 681                         return retval;
 682                 }
 683
 684                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 685                         bank->sectors[i].is_erased = 1;
 686                 else
 687                 {
 688                         if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
 689                         {
 690                                 return retval;
 691                         }
 692
 693                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
 694                         return ERROR_FLASH_OPERATION_FAILED;
 695                 }
 696         }
 697
 698         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
 699 }
 700
 701 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
 702 {
 703         int retval;
 704         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 705         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 706         int i;
 707
 708         for (i = first; i <= last; i++)
 709         {
 710                 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 711                 {
 712                         return retval;
 713                 }
 714
 715                 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 716                 {
 717                         return retval;
 718                 }
 719
 720                 if ((retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 721                 {
 722                         return retval;
 723                 }
 724
 725                 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
 726                 {
 727                         return retval;
 728                 }
 729
 730                 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
 731                 {
 732                         return retval;
 733                 }
 734
 735                 if ((retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0))) != ERROR_OK)
 736                 {
 737                         return retval;
 738                 }
 739
 740                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 741                         bank->sectors[i].is_erased = 1;
 742                 else
 743                 {
 744                         if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
 745                         {
 746                                 return retval;
 747                         }
 748
 749                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
 750                         return ERROR_FLASH_OPERATION_FAILED;
 751                 }
 752         }
 753
 754         return  cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
 755 }
 756
 757 static int cfi_erase(struct flash_bank *bank, int first, int last)
 758 {
 759         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 760
 761         if (bank->target->state != TARGET_HALTED)
 762         {
 763                 LOG_ERROR("Target not halted");
 764                 return ERROR_TARGET_NOT_HALTED;
 765         }
 766
 767         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 768         {
 769                 return ERROR_FLASH_SECTOR_INVALID;
 770         }
 771
 772         if (cfi_info->qry[0] != 'Q')
 773                 return ERROR_FLASH_BANK_NOT_PROBED;
 774
 775         switch (cfi_info->pri_id)
 776         {
 777                 case 1:
 778                 case 3:
 779                         return cfi_intel_erase(bank, first, last);
 780                         break;
 781                 case 2:
 782                         return cfi_spansion_erase(bank, first, last);
 783                         break;
 784                 default:
 785                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 786                         break;
 787         }
 788
 789         return ERROR_OK;
 790 }
 791
 792 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
 793 {
 794         int retval;
 795         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 796         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 797         struct target *target = bank->target; /* FIXME: to be removed */
 798         uint8_t command[CFI_MAX_BUS_WIDTH]; /* FIXME: to be removed */
 799         int retry = 0;
 800         int i;
 801
 802         /* if the device supports neither legacy lock/unlock (bit 3) nor
 803          * instant individual block locking (bit 5).
 804          */
 805         if (!(pri_ext->feature_support & 0x28))
 806                 return ERROR_FLASH_OPERATION_FAILED;
 807
 808         cfi_intel_clear_status_register(bank);
 809
 810         for (i = first; i <= last; i++)
 811         {
 812                 cfi_command(bank, 0x60, command); /* FIXME: to be removed */
 813                 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 814                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
 815                 {
 816                         return retval;
 817                 }
 818                 if (set)
 819                 {
 820                         cfi_command(bank, 0x01, command); /* FIXME: to be removed */
 821                         LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32 , flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 822                         if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
 823                         {
 824                                 return retval;
 825                         }
 826                         bank->sectors[i].is_protected = 1;
 827                 }
 828                 else
 829                 {
 830                         cfi_command(bank, 0xd0, command); /* FIXME: to be removed */
 831                         LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 832                         if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
 833                         {
 834                                 return retval;
 835                         }
 836                         bank->sectors[i].is_protected = 0;
 837                 }
 838
 839                 /* instant individual block locking doesn't require reading of the status register */
 840                 if (!(pri_ext->feature_support & 0x20))
 841                 {
 842                         /* Clear lock bits operation may take up to 1.4s */
 843                         cfi_intel_wait_status_busy(bank, 1400);
 844                 }
 845                 else
 846                 {
 847                         uint8_t block_status;
 848                         /* read block lock bit, to verify status */
 849                         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
 850                         {
 851                                 return retval;
 852                         }
 853                         block_status = cfi_get_u8(bank, i, 0x2);
 854
 855                         if ((block_status & 0x1) != set)
 856                         {
 857                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 858                                 if ((retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55))) != ERROR_OK)
 859                                 {
 860                                         return retval;
 861                                 }
 862                                 cfi_intel_wait_status_busy(bank, 10);
 863
 864                                 if (retry > 10)
 865                                         return ERROR_FLASH_OPERATION_FAILED;
 866                                 else
 867                                 {
 868                                         i--;
 869                                         retry++;
 870                                 }
 871                         }
 872                 }
 873         }
 874
 875         /* if the device doesn't support individual block lock bits set/clear,
 876          * all blocks have been unlocked in parallel, so we set those that should be protected
 877          */
 878         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 879         {
 880                 /* FIX!!! this code path is broken!!!
 881                  *
 882                  * The correct approach is:
 883                  *
 884                  * 1. read out current protection status
 885                  *
 886                  * 2. override read out protection status w/unprotected.
 887                  *
 888                  * 3. re-protect what should be protected.
 889                  *
 890                  */
 891                 for (i = 0; i < bank->num_sectors; i++)
 892                 {
 893                         if (bank->sectors[i].is_protected == 1)
 894                         {
 895                                 cfi_intel_clear_status_register(bank);
 896
 897                                 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
 898                                 {
 899                                         return retval;
 900                                 }
 901
 902                                 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
 903                                 {
 904                                         return retval;
 905                                 }
 906
 907                                 cfi_intel_wait_status_busy(bank, 100);
 908                         }
 909                 }
 910         }
 911
 912         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
 913 }
 914
 915 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
 916 {
 917         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 918
 919         if (bank->target->state != TARGET_HALTED)
 920         {
 921                 LOG_ERROR("Target not halted");
 922                 return ERROR_TARGET_NOT_HALTED;
 923         }
 924
 925         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 926         {
 927                 LOG_ERROR("Invalid sector range");
 928                 return ERROR_FLASH_SECTOR_INVALID;
 929         }
 930
 931         if (cfi_info->qry[0] != 'Q')
 932                 return ERROR_FLASH_BANK_NOT_PROBED;
 933
 934         switch (cfi_info->pri_id)
 935         {
 936                 case 1:
 937                 case 3:
 938                         return cfi_intel_protect(bank, set, first, last);
 939                         break;
 940                 default:
 941                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
 942                         return ERROR_FAIL;
 943         }
 944 }
 945
 946 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 947 static void cfi_add_byte(struct flash_bank *bank, uint8_t *word, uint8_t byte)
 948 {
 949         /* struct target *target = bank->target; */
 950
 951         int i;
 952
 953         /* NOTE:
 954          * The data to flash must not be changed in endian! We write a bytestrem in
 955          * target byte order already. Only the control and status byte lane of the flash
 956          * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
 957          * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
 958          */
 959
 960 #if 0
 961         if (target->endianness == TARGET_LITTLE_ENDIAN)
 962         {
 963 #endif
 964                 /* shift bytes */
 965                 for (i = 0; i < bank->bus_width - 1; i++)
 966                         word[i] = word[i + 1];
 967                 word[bank->bus_width - 1] = byte;
 968 #if 0
 969         }
 970         else
 971         {
 972                 /* shift bytes */
 973                 for (i = bank->bus_width - 1; i > 0; i--)
 974                         word[i] = word[i - 1];
 975                 word[0] = byte;
 976         }
 977 #endif
 978 }
 979
 980 /* Convert code image to target endian */
 981 /* FIXME create general block conversion fcts in target.c?) */
 982 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
 983 {
 984         uint32_t i;
 985         for (i = 0; i< count; i++)
 986         {
 987                 target_buffer_set_u32(target, dest, *src);
 988                 dest += 4;
 989                 src++;
 990         }
 991 }
 992
 993 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
 994 {
 995         struct target *target = bank->target;
 996
 997         uint8_t buf[CFI_MAX_BUS_WIDTH];
 998         cfi_command(bank, cmd, buf);
 999         switch (bank->bus_width)
1000         {
1001         case 1 :
1002                 return buf[0];
1003                 break;
1004         case 2 :
1005                 return target_buffer_get_u16(target, buf);
1006                 break;
1007         case 4 :
1008                 return target_buffer_get_u32(target, buf);
1009                 break;
1010         default :
1011                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1012                 return 0;
1013         }
1014 }
1015
1016 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1017 {
1018         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1019         struct target *target = bank->target;
1020         struct reg_param reg_params[7];
1021         struct arm_algorithm armv4_5_info;
1022         struct working_area *source;
1023         uint32_t buffer_size = 32768;
1024         uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1025
1026         /* algorithm register usage:
1027          * r0: source address (in RAM)
1028          * r1: target address (in Flash)
1029          * r2: count
1030          * r3: flash write command
1031          * r4: status byte (returned to host)
1032          * r5: busy test pattern
1033          * r6: error test pattern
1034          */
1035
1036         static const uint32_t word_32_code[] = {
1037                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1038                 0xe5813000,   /*                str r3, [r1] */
1039                 0xe5814000,   /*                str r4, [r1] */
1040                 0xe5914000,   /* busy:  ldr r4, [r1] */
1041                 0xe0047005,   /*                and r7, r4, r5 */
1042                 0xe1570005,   /*                cmp r7, r5 */
1043                 0x1afffffb,   /*                bne busy */
1044                 0xe1140006,   /*                tst r4, r6 */
1045                 0x1a000003,   /*                bne done */
1046                 0xe2522001,   /*                subs r2, r2, #1 */
1047                 0x0a000001,   /*                beq done */
1048                 0xe2811004,   /*                add r1, r1 #4 */
1049                 0xeafffff2,   /*                b loop */
1050                 0xeafffffe    /* done:  b -2 */
1051         };
1052
1053         static const uint32_t word_16_code[] = {
1054                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1055                 0xe1c130b0,   /*                strh r3, [r1] */
1056                 0xe1c140b0,   /*                strh r4, [r1] */
1057                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1058                 0xe0047005,   /*                and r7, r4, r5 */
1059                 0xe1570005,   /*                cmp r7, r5 */
1060                 0x1afffffb,   /*                bne busy */
1061                 0xe1140006,   /*                tst r4, r6 */
1062                 0x1a000003,   /*                bne done */
1063                 0xe2522001,   /*                subs r2, r2, #1 */
1064                 0x0a000001,   /*                beq done */
1065                 0xe2811002,   /*                add r1, r1 #2 */
1066                 0xeafffff2,   /*                b loop */
1067                 0xeafffffe    /* done:  b -2 */
1068         };
1069
1070         static const uint32_t word_8_code[] = {
1071                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1072                 0xe5c13000,   /*                strb r3, [r1] */
1073                 0xe5c14000,   /*                strb r4, [r1] */
1074                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1075                 0xe0047005,   /*                and r7, r4, r5 */
1076                 0xe1570005,   /*                cmp r7, r5 */
1077                 0x1afffffb,   /*                bne busy */
1078                 0xe1140006,   /*                tst r4, r6 */
1079                 0x1a000003,   /*                bne done */
1080                 0xe2522001,   /*                subs r2, r2, #1 */
1081                 0x0a000001,   /*                beq done */
1082                 0xe2811001,   /*                add r1, r1 #1 */
1083                 0xeafffff2,   /*                b loop */
1084                 0xeafffffe    /* done:  b -2 */
1085         };
1086         uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1087         const uint32_t *target_code_src;
1088         uint32_t target_code_size;
1089         int retval = ERROR_OK;
1090
1091
1092         cfi_intel_clear_status_register(bank);
1093
1094         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1095         armv4_5_info.core_mode = ARM_MODE_SVC;
1096         armv4_5_info.core_state = ARM_STATE_ARM;
1097
1098         /* If we are setting up the write_algorith, we need target_code_src */
1099         /* if not we only need target_code_size. */
1100
1101         /* However, we don't want to create multiple code paths, so we */
1102         /* do the unecessary evaluation of target_code_src, which the */
1103         /* compiler will probably nicely optimize away if not needed */
1104
1105         /* prepare algorithm code for target endian */
1106         switch (bank->bus_width)
1107         {
1108         case 1 :
1109                 target_code_src = word_8_code;
1110                 target_code_size = sizeof(word_8_code);
1111                 break;
1112         case 2 :
1113                 target_code_src = word_16_code;
1114                 target_code_size = sizeof(word_16_code);
1115                 break;
1116         case 4 :
1117                 target_code_src = word_32_code;
1118                 target_code_size = sizeof(word_32_code);
1119                 break;
1120         default:
1121                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1122                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1123         }
1124
1125         /* flash write code */
1126         if (!cfi_info->write_algorithm)
1127         {
1128                 if (target_code_size > sizeof(target_code))
1129                 {
1130                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1131                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1132                 }
1133                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1134
1135                 /* Get memory for block write handler */
1136                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1137                 if (retval != ERROR_OK)
1138                 {
1139                         LOG_WARNING("No working area available, can't do block memory writes");
1140                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1141                 };
1142
1143                 /* write algorithm code to working area */
1144                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1145                 if (retval != ERROR_OK)
1146                 {
1147                         LOG_ERROR("Unable to write block write code to target");
1148                         goto cleanup;
1149                 }
1150         }
1151
1152         /* Get a workspace buffer for the data to flash starting with 32k size.
1153            Half size until buffer would be smaller 256 Bytem then fail back */
1154         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1155         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1156         {
1157                 buffer_size /= 2;
1158                 if (buffer_size <= 256)
1159                 {
1160                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1161                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1162                         goto cleanup;
1163                 }
1164         };
1165
1166         /* setup algo registers */
1167         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1168         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1169         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1170         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1171         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1172         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1173         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1174
1175         /* prepare command and status register patterns */
1176         write_command_val = cfi_command_val(bank, 0x40);
1177         busy_pattern_val  = cfi_command_val(bank, 0x80);
1178         error_pattern_val = cfi_command_val(bank, 0x7e);
1179
1180         LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1181
1182         /* Programming main loop */
1183         while (count > 0)
1184         {
1185                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1186                 uint32_t wsm_error;
1187
1188                 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1189                 {
1190                         goto cleanup;
1191                 }
1192
1193                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1194                 buf_set_u32(reg_params[1].value, 0, 32, address);
1195                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1196
1197                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1198                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1199                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1200
1201                 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1202
1203                 /* Execute algorithm, assume breakpoint for last instruction */
1204                 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1205                         cfi_info->write_algorithm->address,
1206                         cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1207                         10000, /* 10s should be enough for max. 32k of data */
1208                         &armv4_5_info);
1209
1210                 /* On failure try a fall back to direct word writes */
1211                 if (retval != ERROR_OK)
1212                 {
1213                         cfi_intel_clear_status_register(bank);
1214                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1215                         retval = ERROR_FLASH_OPERATION_FAILED;
1216                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1217                         /* FIXME To allow fall back or recovery, we must save the actual status
1218                            somewhere, so that a higher level code can start recovery. */
1219                         goto cleanup;
1220                 }
1221
1222                 /* Check return value from algo code */
1223                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1224                 if (wsm_error)
1225                 {
1226                         /* read status register (outputs debug inforation) */
1227                         cfi_intel_wait_status_busy(bank, 100);
1228                         cfi_intel_clear_status_register(bank);
1229                         retval = ERROR_FLASH_OPERATION_FAILED;
1230                         goto cleanup;
1231                 }
1232
1233                 buffer += thisrun_count;
1234                 address += thisrun_count;
1235                 count -= thisrun_count;
1236         }
1237
1238         /* free up resources */
1239 cleanup:
1240         if (source)
1241                 target_free_working_area(target, source);
1242
1243         if (cfi_info->write_algorithm)
1244         {
1245                 target_free_working_area(target, cfi_info->write_algorithm);
1246                 cfi_info->write_algorithm = NULL;
1247         }
1248
1249         destroy_reg_param(&reg_params[0]);
1250         destroy_reg_param(&reg_params[1]);
1251         destroy_reg_param(&reg_params[2]);
1252         destroy_reg_param(&reg_params[3]);
1253         destroy_reg_param(&reg_params[4]);
1254         destroy_reg_param(&reg_params[5]);
1255         destroy_reg_param(&reg_params[6]);
1256
1257         return retval;
1258 }
1259
1260 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1261 {
1262         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1263         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1264         struct target *target = bank->target;
1265         struct reg_param reg_params[10];
1266         struct arm_algorithm armv4_5_info;
1267         struct working_area *source;
1268         uint32_t buffer_size = 32768;
1269         uint32_t status;
1270         int retval, retvaltemp;
1271         int exit_code = ERROR_OK;
1272
1273         /* input parameters - */
1274         /*      R0 = source address */
1275         /*      R1 = destination address */
1276         /*      R2 = number of writes */
1277         /*      R3 = flash write command */
1278         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1279         /* output parameters - */
1280         /*      R5 = 0x80 ok 0x00 bad */
1281         /* temp registers - */
1282         /*      R6 = value read from flash to test status */
1283         /*      R7 = holding register */
1284         /* unlock registers - */
1285         /*  R8 = unlock1_addr */
1286         /*  R9 = unlock1_cmd */
1287         /*  R10 = unlock2_addr */
1288         /*  R11 = unlock2_cmd */
1289
1290         static const uint32_t word_32_code[] = {
1291                                                 /* 00008100 <sp_32_code>:               */
1292                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1293                 0xe5889000,     /* str  r9, [r8]                                */
1294                 0xe58ab000,     /* str  r11, [r10]                              */
1295                 0xe5883000,     /* str  r3, [r8]                                */
1296                 0xe5815000,     /* str  r5, [r1]                                */
1297                 0xe1a00000,     /* nop                                                  */
1298                                                 /*                                                              */
1299                                                 /* 00008110 <sp_32_busy>:               */
1300                 0xe5916000,     /* ldr  r6, [r1]                                */
1301                 0xe0257006,     /* eor  r7, r5, r6                              */
1302                 0xe0147007,     /* ands r7, r4, r7                              */
1303                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1304                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1305                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1306                 0xe5916000,     /* ldr  r6, [r1]                                */
1307                 0xe0257006,     /* eor  r7, r5, r6                              */
1308                 0xe0147007,     /* ands r7, r4, r7                              */
1309                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1310                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1311                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1312                                                 /*                                                              */
1313                                 /* 00008140 <sp_32_cont>:                               */
1314                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1315                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1316                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1317                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1318                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1319                                                 /*                                                              */
1320                                                 /* 00008154 <sp_32_done>:               */
1321                 0xeafffffe              /* b    8154 <sp_32_done>               */
1322                 };
1323
1324                 static const uint32_t word_16_code[] = {
1325                                 /* 00008158 <sp_16_code>:              */
1326                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1327                 0xe1c890b0,     /* strh r9, [r8]                                */
1328                 0xe1cab0b0,     /* strh r11, [r10]                              */
1329                 0xe1c830b0,     /* strh r3, [r8]                                */
1330                 0xe1c150b0,     /* strh r5, [r1]                       */
1331                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1332                                 /*                                     */
1333                                 /* 00008168 <sp_16_busy>:              */
1334                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1335                 0xe0257006,     /* eor  r7, r5, r6                     */
1336                 0xe0147007,     /* ands r7, r4, r7                     */
1337                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1338                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1339                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1340                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1341                 0xe0257006,     /* eor  r7, r5, r6                     */
1342                 0xe0147007,     /* ands r7, r4, r7                     */
1343                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1344                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1345                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1346                                 /*                                     */
1347                                 /* 00008198 <sp_16_cont>:              */
1348                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1349                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1350                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1351                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1352                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1353                                 /*                                     */
1354                                 /* 000081ac <sp_16_done>:              */
1355                 0xeafffffe      /* b    81ac <sp_16_done>              */
1356                 };
1357
1358                 static const uint32_t word_16_code_dq7only[] = {
1359                                 /* <sp_16_code>:                       */
1360                 0xe0d050b2,     /* ldrh r5, [r0], #2                   */
1361                 0xe1c890b0,     /* strh r9, [r8]                       */
1362                 0xe1cab0b0,     /* strh r11, [r10]                              */
1363                 0xe1c830b0,     /* strh r3, [r8]                                */
1364                 0xe1c150b0,     /* strh r5, [r1]                       */
1365                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1366                                 /*                                     */
1367                                 /* <sp_16_busy>:                       */
1368                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1369                 0xe0257006,     /* eor  r7, r5, r6                     */
1370                 0xe2177080,     /* ands r7, #0x80                      */
1371                 0x1afffffb,     /* bne  8168 <sp_16_busy>              */
1372                                 /*                                     */
1373                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1374                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1375                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1376                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1377                 0xeafffff0,     /* b    8158 <sp_16_code>              */
1378                                 /*                                     */
1379                                 /* 000081ac <sp_16_done>:              */
1380                 0xeafffffe      /* b    81ac <sp_16_done>              */
1381                 };
1382
1383                 static const uint32_t word_8_code[] = {
1384                                 /* 000081b0 <sp_16_code_end>:          */
1385                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1386                 0xe5c89000,     /* strb r9, [r8]                                */
1387                 0xe5cab000,     /* strb r11, [r10]                              */
1388                 0xe5c83000,     /* strb r3, [r8]                                */
1389                 0xe5c15000,     /* strb r5, [r1]                       */
1390                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1391                                 /*                                     */
1392                                 /* 000081c0 <sp_8_busy>:               */
1393                 0xe5d16000,     /* ldrb r6, [r1]                       */
1394                 0xe0257006,     /* eor  r7, r5, r6                     */
1395                 0xe0147007,     /* ands r7, r4, r7                     */
1396                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1397                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1398                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1399                 0xe5d16000,     /* ldrb r6, [r1]                       */
1400                 0xe0257006,     /* eor  r7, r5, r6                     */
1401                 0xe0147007,     /* ands r7, r4, r7                     */
1402                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1403                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1404                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1405                                 /*                                     */
1406                                 /* 000081f0 <sp_8_cont>:               */
1407                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1408                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1409                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1410                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1411                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1412                                 /*                                     */
1413                                 /* 00008204 <sp_8_done>:               */
1414                 0xeafffffe      /* b    8204 <sp_8_done>               */
1415         };
1416
1417         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1418         armv4_5_info.core_mode = ARM_MODE_SVC;
1419         armv4_5_info.core_state = ARM_STATE_ARM;
1420
1421         int target_code_size;
1422         const uint32_t *target_code_src;
1423
1424         switch (bank->bus_width)
1425         {
1426         case 1 :
1427                 target_code_src = word_8_code;
1428                 target_code_size = sizeof(word_8_code);
1429                 break;
1430         case 2 :
1431                 /* Check for DQ5 support */
1432                 if( cfi_info->status_poll_mask & (1 << 5) )
1433                 {
1434                         target_code_src = word_16_code;
1435                         target_code_size = sizeof(word_16_code);
1436                 }
1437                 else
1438                 {
1439                         /* No DQ5 support. Use DQ7 DATA# polling only. */
1440                         target_code_src = word_16_code_dq7only;
1441                         target_code_size = sizeof(word_16_code_dq7only);
1442                 }
1443                 break;
1444         case 4 :
1445                 target_code_src = word_32_code;
1446                 target_code_size = sizeof(word_32_code);
1447                 break;
1448         default:
1449                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1450                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1451         }
1452
1453         /* flash write code */
1454         if (!cfi_info->write_algorithm)
1455         {
1456                 uint8_t *target_code;
1457
1458                 /* convert bus-width dependent algorithm code to correct endiannes */
1459                 target_code = malloc(target_code_size);
1460                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1461
1462                 /* allocate working area */
1463                 retval = target_alloc_working_area(target, target_code_size,
1464                                 &cfi_info->write_algorithm);
1465                 if (retval != ERROR_OK)
1466                 {
1467                         free(target_code);
1468                         return retval;
1469                 }
1470
1471                 /* write algorithm code to working area */
1472                 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1473                                     target_code_size, target_code)) != ERROR_OK)
1474                 {
1475                         free(target_code);
1476                         return retval;
1477                 }
1478
1479                 free(target_code);
1480         }
1481         /* the following code still assumes target code is fixed 24*4 bytes */
1482
1483         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1484         {
1485                 buffer_size /= 2;
1486                 if (buffer_size <= 256)
1487                 {
1488                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1489                         if (cfi_info->write_algorithm)
1490                                 target_free_working_area(target, cfi_info->write_algorithm);
1491
1492                         LOG_WARNING("not enough working area available, can't do block memory writes");
1493                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1494                 }
1495         };
1496
1497         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1498         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1499         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1500         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1501         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1502         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1503         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1504         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1505         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1506         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1507
1508         while (count > 0)
1509         {
1510                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1511
1512                 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1513
1514                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1515                 buf_set_u32(reg_params[1].value, 0, 32, address);
1516                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1517                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1518                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1519                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1520                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1521                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1522                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1523
1524                 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1525                                                      cfi_info->write_algorithm->address,
1526                                                      cfi_info->write_algorithm->address + ((target_code_size) - 4),
1527                                                      10000, &armv4_5_info);
1528
1529                 status = buf_get_u32(reg_params[5].value, 0, 32);
1530
1531                 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1532                 {
1533                         LOG_DEBUG("status: 0x%" PRIx32 , status);
1534                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1535                         break;
1536                 }
1537
1538                 buffer += thisrun_count;
1539                 address += thisrun_count;
1540                 count -= thisrun_count;
1541         }
1542
1543         target_free_all_working_areas(target);
1544
1545         destroy_reg_param(&reg_params[0]);
1546         destroy_reg_param(&reg_params[1]);
1547         destroy_reg_param(&reg_params[2]);
1548         destroy_reg_param(&reg_params[3]);
1549         destroy_reg_param(&reg_params[4]);
1550         destroy_reg_param(&reg_params[5]);
1551         destroy_reg_param(&reg_params[6]);
1552         destroy_reg_param(&reg_params[7]);
1553         destroy_reg_param(&reg_params[8]);
1554         destroy_reg_param(&reg_params[9]);
1555
1556         return exit_code;
1557 }
1558
1559 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1560 {
1561         int retval;
1562         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1563         struct target *target = bank->target;
1564
1565         cfi_intel_clear_status_register(bank);
1566         if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1567         {
1568                 return retval;
1569         }
1570
1571         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1572         {
1573                 return retval;
1574         }
1575
1576         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1577         {
1578                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1579                 {
1580                         return retval;
1581                 }
1582
1583                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1584                 return ERROR_FLASH_OPERATION_FAILED;
1585         }
1586
1587         return ERROR_OK;
1588 }
1589
1590 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1591 {
1592         int retval;
1593         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1594         struct target *target = bank->target;
1595
1596         /* Calculate buffer size and boundary mask */
1597         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1598         uint32_t buffermask = buffersize-1;
1599         uint32_t bufferwsize;
1600
1601         /* Check for valid range */
1602         if (address & buffermask)
1603         {
1604                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1605                           bank->base, address, cfi_info->max_buf_write_size);
1606                 return ERROR_FLASH_OPERATION_FAILED;
1607         }
1608         switch (bank->chip_width)
1609         {
1610         case 4 : bufferwsize = buffersize / 4; break;
1611         case 2 : bufferwsize = buffersize / 2; break;
1612         case 1 : bufferwsize = buffersize; break;
1613         default:
1614                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1615                 return ERROR_FLASH_OPERATION_FAILED;
1616         }
1617
1618         bufferwsize/=(bank->bus_width / bank->chip_width);
1619
1620
1621         /* Check for valid size */
1622         if (wordcount > bufferwsize)
1623         {
1624                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1625                 return ERROR_FLASH_OPERATION_FAILED;
1626         }
1627
1628         /* Write to flash buffer */
1629         cfi_intel_clear_status_register(bank);
1630
1631         /* Initiate buffer operation _*/
1632         if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1633         {
1634                 return retval;
1635         }
1636         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1637         {
1638                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1639                 {
1640                         return retval;
1641                 }
1642
1643                 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1644                 return ERROR_FLASH_OPERATION_FAILED;
1645         }
1646
1647         /* Write buffer wordcount-1 and data words */
1648         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1649         {
1650                 return retval;
1651         }
1652
1653         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1654         {
1655                 return retval;
1656         }
1657
1658         /* Commit write operation */
1659         if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1660         {
1661                 return retval;
1662         }
1663         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1664         {
1665                 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1666                 {
1667                         return retval;
1668                 }
1669
1670                 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1671                 return ERROR_FLASH_OPERATION_FAILED;
1672         }
1673
1674         return ERROR_OK;
1675 }
1676
1677 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1678 {
1679         int retval;
1680         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1681         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1682         struct target *target = bank->target;
1683
1684         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1685         {
1686                 return retval;
1687         }
1688
1689         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1690         {
1691                 return retval;
1692         }
1693
1694         if ((retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1695         {
1696                 return retval;
1697         }
1698
1699         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1700         {
1701                 return retval;
1702         }
1703
1704         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1705         {
1706                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1707                 {
1708                         return retval;
1709                 }
1710
1711                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1712                 return ERROR_FLASH_OPERATION_FAILED;
1713         }
1714
1715         return ERROR_OK;
1716 }
1717
1718 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1719 {
1720         int retval;
1721         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1722         struct target *target = bank->target;
1723         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1724
1725         /* Calculate buffer size and boundary mask */
1726         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1727         uint32_t buffermask = buffersize-1;
1728         uint32_t bufferwsize;
1729
1730         /* Check for valid range */
1731         if (address & buffermask)
1732         {
1733                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1734                 return ERROR_FLASH_OPERATION_FAILED;
1735         }
1736         switch (bank->chip_width)
1737         {
1738         case 4 : bufferwsize = buffersize / 4; break;
1739         case 2 : bufferwsize = buffersize / 2; break;
1740         case 1 : bufferwsize = buffersize; break;
1741         default:
1742                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1743                 return ERROR_FLASH_OPERATION_FAILED;
1744         }
1745
1746         bufferwsize/=(bank->bus_width / bank->chip_width);
1747
1748         /* Check for valid size */
1749         if (wordcount > bufferwsize)
1750         {
1751                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1752                 return ERROR_FLASH_OPERATION_FAILED;
1753         }
1754
1755         // Unlock
1756         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1757         {
1758                 return retval;
1759         }
1760
1761         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1762         {
1763                 return retval;
1764         }
1765
1766         // Buffer load command
1767         if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1768         {
1769                 return retval;
1770         }
1771
1772         /* Write buffer wordcount-1 and data words */
1773         if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1774         {
1775                 return retval;
1776         }
1777
1778         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1779         {
1780                 return retval;
1781         }
1782
1783         /* Commit write operation */
1784         if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
1785         {
1786                 return retval;
1787         }
1788
1789         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1790         {
1791                 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1792                 {
1793                         return retval;
1794                 }
1795
1796                 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1797                 return ERROR_FLASH_OPERATION_FAILED;
1798         }
1799
1800         return ERROR_OK;
1801 }
1802
1803 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1804 {
1805         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1806
1807         switch (cfi_info->pri_id)
1808         {
1809                 case 1:
1810                 case 3:
1811                         return cfi_intel_write_word(bank, word, address);
1812                         break;
1813                 case 2:
1814                         return cfi_spansion_write_word(bank, word, address);
1815                         break;
1816                 default:
1817                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1818                         break;
1819         }
1820
1821         return ERROR_FLASH_OPERATION_FAILED;
1822 }
1823
1824 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1825 {
1826         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1827
1828         switch (cfi_info->pri_id)
1829         {
1830                 case 1:
1831                 case 3:
1832                         return cfi_intel_write_words(bank, word, wordcount, address);
1833                         break;
1834                 case 2:
1835                         return cfi_spansion_write_words(bank, word, wordcount, address);
1836                         break;
1837                 default:
1838                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1839                         break;
1840         }
1841
1842         return ERROR_FLASH_OPERATION_FAILED;
1843 }
1844
1845 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1846 {
1847         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1848         struct target *target = bank->target;
1849         uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1850         uint32_t write_p, copy_p;
1851         int align;      /* number of unaligned bytes */
1852         int blk_count; /* number of bus_width bytes for block copy */
1853         uint8_t current_word[CFI_MAX_BUS_WIDTH * 4];    /* word (bus_width size) currently being programmed */
1854         int i;
1855         int retval;
1856
1857         if (bank->target->state != TARGET_HALTED)
1858         {
1859                 LOG_ERROR("Target not halted");
1860                 return ERROR_TARGET_NOT_HALTED;
1861         }
1862
1863         if (offset + count > bank->size)
1864                 return ERROR_FLASH_DST_OUT_OF_BANK;
1865
1866         if (cfi_info->qry[0] != 'Q')
1867                 return ERROR_FLASH_BANK_NOT_PROBED;
1868
1869         /* start at the first byte of the first word (bus_width size) */
1870         write_p = address & ~(bank->bus_width - 1);
1871         if ((align = address - write_p) != 0)
1872         {
1873                 LOG_INFO("Fixup %d unaligned head bytes", align);
1874
1875                 for (i = 0; i < bank->bus_width; i++)
1876                         current_word[i] = 0;
1877                 copy_p = write_p;
1878
1879                 /* copy bytes before the first write address */
1880                 for (i = 0; i < align; ++i, ++copy_p)
1881                 {
1882                         uint8_t byte;
1883                         if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1884                         {
1885                                 return retval;
1886                         }
1887                         cfi_add_byte(bank, current_word, byte);
1888                 }
1889
1890                 /* add bytes from the buffer */
1891                 for (; (i < bank->bus_width) && (count > 0); i++)
1892                 {
1893                         cfi_add_byte(bank, current_word, *buffer++);
1894                         count--;
1895                         copy_p++;
1896                 }
1897
1898                 /* if the buffer is already finished, copy bytes after the last write address */
1899                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1900                 {
1901                         uint8_t byte;
1902                         if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1903                         {
1904                                 return retval;
1905                         }
1906                         cfi_add_byte(bank, current_word, byte);
1907                 }
1908
1909                 retval = cfi_write_word(bank, current_word, write_p);
1910                 if (retval != ERROR_OK)
1911                         return retval;
1912                 write_p = copy_p;
1913         }
1914
1915         /* handle blocks of bus_size aligned bytes */
1916         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1917         switch (cfi_info->pri_id)
1918         {
1919                 /* try block writes (fails without working area) */
1920                 case 1:
1921                 case 3:
1922                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1923                         break;
1924                 case 2:
1925                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1926                         break;
1927                 default:
1928                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1929                         retval = ERROR_FLASH_OPERATION_FAILED;
1930                         break;
1931         }
1932         if (retval == ERROR_OK)
1933         {
1934                 /* Increment pointers and decrease count on succesful block write */
1935                 buffer += blk_count;
1936                 write_p += blk_count;
1937                 count -= blk_count;
1938         }
1939         else
1940         {
1941                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1942                 {
1943                         //adjust buffersize for chip width
1944                         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1945                         uint32_t buffermask = buffersize-1;
1946                         uint32_t bufferwsize;
1947
1948                         switch (bank->chip_width)
1949                         {
1950                         case 4 : bufferwsize = buffersize / 4; break;
1951                         case 2 : bufferwsize = buffersize / 2; break;
1952                         case 1 : bufferwsize = buffersize; break;
1953                         default:
1954                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1955                                 return ERROR_FLASH_OPERATION_FAILED;
1956                         }
1957
1958                         bufferwsize/=(bank->bus_width / bank->chip_width);
1959
1960                         /* fall back to memory writes */
1961                         while (count >= (uint32_t)bank->bus_width)
1962                         {
1963                                 int fallback;
1964                                 if ((write_p & 0xff) == 0)
1965                                 {
1966                                         LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
1967                                 }
1968                                 fallback = 1;
1969                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1970                                 {
1971                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1972                                         if (retval == ERROR_OK)
1973                                         {
1974                                                 buffer += buffersize;
1975                                                 write_p += buffersize;
1976                                                 count -= buffersize;
1977                                                 fallback = 0;
1978                                         }
1979                                 }
1980                                 /* try the slow way? */
1981                                 if (fallback)
1982                                 {
1983                                         for (i = 0; i < bank->bus_width; i++)
1984                                                 current_word[i] = 0;
1985
1986                                         for (i = 0; i < bank->bus_width; i++)
1987                                         {
1988                                                 cfi_add_byte(bank, current_word, *buffer++);
1989                                         }
1990
1991                                         retval = cfi_write_word(bank, current_word, write_p);
1992                                         if (retval != ERROR_OK)
1993                                                 return retval;
1994
1995                                         write_p += bank->bus_width;
1996                                         count -= bank->bus_width;
1997                                 }
1998                         }
1999                 }
2000                 else
2001                         return retval;
2002         }
2003
2004         /* return to read array mode, so we can read from flash again for padding */
2005         if ((retval = cfi_reset(bank)) != ERROR_OK)
2006         {
2007                 return retval;
2008         }
2009
2010         /* handle unaligned tail bytes */
2011         if (count > 0)
2012         {
2013                 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2014
2015                 copy_p = write_p;
2016                 for (i = 0; i < bank->bus_width; i++)
2017                         current_word[i] = 0;
2018
2019                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2020                 {
2021                         cfi_add_byte(bank, current_word, *buffer++);
2022                         count--;
2023                 }
2024                 for (; i < bank->bus_width; ++i, ++copy_p)
2025                 {
2026                         uint8_t byte;
2027                         if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2028                         {
2029                                 return retval;
2030                         }
2031                         cfi_add_byte(bank, current_word, byte);
2032                 }
2033                 retval = cfi_write_word(bank, current_word, write_p);
2034                 if (retval != ERROR_OK)
2035                         return retval;
2036         }
2037
2038         /* return to read array mode */
2039         return cfi_reset(bank);
2040 }
2041
2042 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
2043 {
2044         (void) param;
2045         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2046         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2047
2048         pri_ext->_reversed_geometry = 1;
2049 }
2050
2051 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2052 {
2053         int i;
2054         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2055         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2056         (void) param;
2057
2058         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2059         {
2060                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2061
2062                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2063                 {
2064                         int j = (cfi_info->num_erase_regions - 1) - i;
2065                         uint32_t swap;
2066
2067                         swap = cfi_info->erase_region_info[i];
2068                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2069                         cfi_info->erase_region_info[j] = swap;
2070                 }
2071         }
2072 }
2073
2074 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2075 {
2076         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2077         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2078         struct cfi_unlock_addresses *unlock_addresses = param;
2079
2080         pri_ext->_unlock1 = unlock_addresses->unlock1;
2081         pri_ext->_unlock2 = unlock_addresses->unlock2;
2082 }
2083
2084
2085 static int cfi_query_string(struct flash_bank *bank, int address)
2086 {
2087         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2088         int retval;
2089
2090         if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2091         {
2092                 return retval;
2093         }
2094
2095         cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2096         cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2097         cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2098
2099         LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2100
2101         if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2102         {
2103                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2104                 {
2105                         return retval;
2106                 }
2107                 LOG_ERROR("Could not probe bank: no QRY");
2108                 return ERROR_FLASH_BANK_INVALID;
2109         }
2110
2111         return ERROR_OK;
2112 }
2113
2114 static int cfi_probe(struct flash_bank *bank)
2115 {
2116         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2117         struct target *target = bank->target;
2118         int num_sectors = 0;
2119         int i;
2120         int sector = 0;
2121         uint32_t unlock1 = 0x555;
2122         uint32_t unlock2 = 0x2aa;
2123         int retval;
2124
2125         if (bank->target->state != TARGET_HALTED)
2126         {
2127                 LOG_ERROR("Target not halted");
2128                 return ERROR_TARGET_NOT_HALTED;
2129         }
2130
2131         cfi_info->probed = 0;
2132
2133         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2134          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2135          */
2136         if (cfi_info->jedec_probe)
2137         {
2138                 unlock1 = 0x5555;
2139                 unlock2 = 0x2aaa;
2140         }
2141
2142         /* switch to read identifier codes mode ("AUTOSELECT") */
2143         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2144         {
2145                 return retval;
2146         }
2147         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2148         {
2149                 return retval;
2150         }
2151         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2152         {
2153                 return retval;
2154         }
2155
2156         if (bank->chip_width == 1)
2157         {
2158                 uint8_t manufacturer, device_id;
2159                 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2160                 {
2161                         return retval;
2162                 }
2163                 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2164                 {
2165                         return retval;
2166                 }
2167                 cfi_info->manufacturer = manufacturer;
2168                 cfi_info->device_id = device_id;
2169         }
2170         else if (bank->chip_width == 2)
2171         {
2172                 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2173                 {
2174                         return retval;
2175                 }
2176                 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK)
2177                 {
2178                         return retval;
2179                 }
2180         }
2181
2182         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2183         /* switch back to read array mode */
2184         if ((retval = cfi_reset(bank)) != ERROR_OK)
2185         {
2186                 return retval;
2187         }
2188
2189         /* check device/manufacturer ID for known non-CFI flashes. */
2190         cfi_fixup_non_cfi(bank);
2191
2192         /* query only if this is a CFI compatible flash,
2193          * otherwise the relevant info has already been filled in
2194          */
2195         if (cfi_info->not_cfi == 0)
2196         {
2197                 int retval;
2198
2199                 /* enter CFI query mode
2200                  * according to JEDEC Standard No. 68.01,
2201                  * a single bus sequence with address = 0x55, data = 0x98 should put
2202                  * the device into CFI query mode.
2203                  *
2204                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2205                  */
2206
2207                 retval = cfi_query_string(bank, 0x55);
2208                 if (retval != ERROR_OK)
2209                 {
2210                         /*
2211                          * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2212                          * be harmless enough:
2213                          *
2214                          * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2215                          */
2216                         LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2217                         retval = cfi_query_string(bank, 0x555);
2218                 }
2219                 if (retval != ERROR_OK)
2220                         return retval;
2221
2222                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2223                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2224                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2225                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2226
2227                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2228
2229                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2230                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2231                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2232                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2233                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2234                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2235                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2236                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2237                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2238                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2239                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2240                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2241
2242                 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2243                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2244                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2245                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2246                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2247                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2248                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2249                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2250                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2251                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2252                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2253
2254                 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2255                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2256                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2257                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2258
2259                 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2260
2261                 if (cfi_info->num_erase_regions)
2262                 {
2263                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2264                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2265                         {
2266                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2267                                 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2268                                           i,
2269                                           (cfi_info->erase_region_info[i] & 0xffff) + 1,
2270                                           (cfi_info->erase_region_info[i] >> 16) * 256);
2271                         }
2272                 }
2273                 else
2274                 {
2275                         cfi_info->erase_region_info = NULL;
2276                 }
2277
2278                 /* We need to read the primary algorithm extended query table before calculating
2279                  * the sector layout to be able to apply fixups
2280                  */
2281                 switch (cfi_info->pri_id)
2282                 {
2283                         /* Intel command set (standard and extended) */
2284                         case 0x0001:
2285                         case 0x0003:
2286                                 cfi_read_intel_pri_ext(bank);
2287                                 break;
2288                         /* AMD/Spansion, Atmel, ... command set */
2289                         case 0x0002:
2290                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2291                                 cfi_read_0002_pri_ext(bank);
2292                                 break;
2293                         default:
2294                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2295                                 break;
2296                 }
2297
2298                 /* return to read array mode
2299                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2300                  */
2301                 if ((retval = cfi_reset(bank)) != ERROR_OK)
2302                 {
2303                         return retval;
2304                 }
2305         } /* end CFI case */
2306
2307         /* apply fixups depending on the primary command set */
2308         switch (cfi_info->pri_id)
2309         {
2310                 /* Intel command set (standard and extended) */
2311                 case 0x0001:
2312                 case 0x0003:
2313                         cfi_fixup(bank, cfi_0001_fixups);
2314                         break;
2315                 /* AMD/Spansion, Atmel, ... command set */
2316                 case 0x0002:
2317                         cfi_fixup(bank, cfi_0002_fixups);
2318                         break;
2319                 default:
2320                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2321                         break;
2322         }
2323
2324         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2325         {
2326                 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2327         }
2328
2329         if (cfi_info->num_erase_regions == 0)
2330         {
2331                 /* a device might have only one erase block, spanning the whole device */
2332                 bank->num_sectors = 1;
2333                 bank->sectors = malloc(sizeof(struct flash_sector));
2334
2335                 bank->sectors[sector].offset = 0x0;
2336                 bank->sectors[sector].size = bank->size;
2337                 bank->sectors[sector].is_erased = -1;
2338                 bank->sectors[sector].is_protected = -1;
2339         }
2340         else
2341         {
2342                 uint32_t offset = 0;
2343
2344                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2345                 {
2346                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2347                 }
2348
2349                 bank->num_sectors = num_sectors;
2350                 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2351
2352                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2353                 {
2354                         uint32_t j;
2355                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2356                         {
2357                                 bank->sectors[sector].offset = offset;
2358                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2359                                 offset += bank->sectors[sector].size;
2360                                 bank->sectors[sector].is_erased = -1;
2361                                 bank->sectors[sector].is_protected = -1;
2362                                 sector++;
2363                         }
2364                 }
2365                 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2366                 {
2367                         LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2368                                 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2369                 }
2370         }
2371
2372         cfi_info->probed = 1;
2373
2374         return ERROR_OK;
2375 }
2376
2377 static int cfi_auto_probe(struct flash_bank *bank)
2378 {
2379         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2380         if (cfi_info->probed)
2381                 return ERROR_OK;
2382         return cfi_probe(bank);
2383 }
2384
2385 static int cfi_intel_protect_check(struct flash_bank *bank)
2386 {
2387         int retval;
2388         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2389         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2390         int i;
2391
2392         /* check if block lock bits are supported on this device */
2393         if (!(pri_ext->blk_status_reg_mask & 0x1))
2394                 return ERROR_FLASH_OPERATION_FAILED;
2395
2396         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2397         {
2398                 return retval;
2399         }
2400
2401         for (i = 0; i < bank->num_sectors; i++)
2402         {
2403                 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2404
2405                 if (block_status & 1)
2406                         bank->sectors[i].is_protected = 1;
2407                 else
2408                         bank->sectors[i].is_protected = 0;
2409         }
2410
2411         return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2412 }
2413
2414 static int cfi_spansion_protect_check(struct flash_bank *bank)
2415 {
2416         int retval;
2417         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2418         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2419         int i;
2420
2421         if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2422         {
2423                 return retval;
2424         }
2425
2426         if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2427         {
2428                 return retval;
2429         }
2430
2431         if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2432         {
2433                 return retval;
2434         }
2435
2436         for (i = 0; i < bank->num_sectors; i++)
2437         {
2438                 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2439
2440                 if (block_status & 1)
2441                         bank->sectors[i].is_protected = 1;
2442                 else
2443                         bank->sectors[i].is_protected = 0;
2444         }
2445
2446         return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2447 }
2448
2449 static int cfi_protect_check(struct flash_bank *bank)
2450 {
2451         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2452
2453         if (bank->target->state != TARGET_HALTED)
2454         {
2455                 LOG_ERROR("Target not halted");
2456                 return ERROR_TARGET_NOT_HALTED;
2457         }
2458
2459         if (cfi_info->qry[0] != 'Q')
2460                 return ERROR_FLASH_BANK_NOT_PROBED;
2461
2462         switch (cfi_info->pri_id)
2463         {
2464                 case 1:
2465                 case 3:
2466                         return cfi_intel_protect_check(bank);
2467                         break;
2468                 case 2:
2469                         return cfi_spansion_protect_check(bank);
2470                         break;
2471                 default:
2472                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2473                         break;
2474         }
2475
2476         return ERROR_OK;
2477 }
2478
2479 static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2480 {
2481         int printed;
2482         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2483
2484         if (cfi_info->qry[0] == (char)-1)
2485         {
2486                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2487                 return ERROR_OK;
2488         }
2489
2490         if (cfi_info->not_cfi == 0)
2491                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2492         else
2493                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2494         buf += printed;
2495         buf_size -= printed;
2496
2497         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2498                 cfi_info->manufacturer, cfi_info->device_id);
2499         buf += printed;
2500         buf_size -= printed;
2501
2502         if (cfi_info->not_cfi == 0)
2503         {
2504         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2505         buf += printed;
2506         buf_size -= printed;
2507
2508                 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2509                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2510         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2511         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2512         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2513         buf += printed;
2514         buf_size -= printed;
2515
2516                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2517                                    1 << cfi_info->word_write_timeout_typ,
2518                                    1 << cfi_info->buf_write_timeout_typ,
2519                                    1 << cfi_info->block_erase_timeout_typ,
2520                                    1 << cfi_info->chip_erase_timeout_typ);
2521         buf += printed;
2522         buf_size -= printed;
2523
2524                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2525                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2526                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2527                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2528                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2529         buf += printed;
2530         buf_size -= printed;
2531
2532                 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2533                                    cfi_info->dev_size,
2534                                    cfi_info->interface_desc,
2535                                    1 << cfi_info->max_buf_write_size);
2536         buf += printed;
2537         buf_size -= printed;
2538
2539         switch (cfi_info->pri_id)
2540         {
2541                 case 1:
2542                 case 3:
2543                         cfi_intel_info(bank, buf, buf_size);
2544                         break;
2545                 case 2:
2546                         cfi_spansion_info(bank, buf, buf_size);
2547                         break;
2548                 default:
2549                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2550                         break;
2551         }
2552         }
2553
2554         return ERROR_OK;
2555 }
2556
2557 struct flash_driver cfi_flash = {
2558         .name = "cfi",
2559         .flash_bank_command = cfi_flash_bank_command,
2560         .erase = cfi_erase,
2561         .protect = cfi_protect,
2562         .write = cfi_write,
2563         .probe = cfi_probe,
2564         .auto_probe = cfi_auto_probe,
2565         .erase_check = default_flash_blank_check,
2566         .protect_check = cfi_protect_check,
2567         .info = cfi_info,
2568 };