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   1 /***************************************************************************
   2  *   Copyright (C) 2013 by Andrey Yurovsky                                 *
   3  *   Andrey Yurovsky <yurovsky@gmail.com>                                  *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "imp.h"
  26
  27 #define SAMD_NUM_SECTORS        16
  28
  29 #define SAMD_FLASH                      ((uint32_t)0x00000000)  /* physical Flash memory */
  30 #define SAMD_DSU                        0x41002000      /* Device Service Unit */
  31 #define SAMD_NVMCTRL            0x41004000      /* Non-volatile memory controller */
  32
  33 #define SAMD_DSU_DID            0x18            /* Device ID register */
  34
  35 #define SAMD_NVMCTRL_CTRLA              0x00    /* NVM control A register */
  36 #define SAMD_NVMCTRL_CTRLB              0x04    /* NVM control B register */
  37 #define SAMD_NVMCTRL_PARAM              0x08    /* NVM parameters register */
  38 #define SAMD_NVMCTRL_INTFLAG    0x18    /* NVM Interupt Flag Status & Clear */
  39 #define SAMD_NVMCTRL_STATUS             0x18    /* NVM status register */
  40 #define SAMD_NVMCTRL_ADDR               0x1C    /* NVM address register */
  41 #define SAMD_NVMCTRL_LOCK               0x20    /* NVM Lock section register */
  42
  43 #define SAMD_CMDEX_KEY          0xA5UL
  44 #define SAMD_NVM_CMD(n)         ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
  45
  46 /* NVMCTRL commands.  See Table 20-4 in 42129F–SAM–10/2013 */
  47 #define SAMD_NVM_CMD_ER         0x02            /* Erase Row */
  48 #define SAMD_NVM_CMD_WP         0x04            /* Write Page */
  49 #define SAMD_NVM_CMD_EAR        0x05            /* Erase Auxilary Row */
  50 #define SAMD_NVM_CMD_WAP        0x06            /* Write Auxilary Page */
  51 #define SAMD_NVM_CMD_LR         0x40            /* Lock Region */
  52 #define SAMD_NVM_CMD_UR         0x41            /* Unlock Region */
  53 #define SAMD_NVM_CMD_SPRM       0x42            /* Set Power Reduction Mode */
  54 #define SAMD_NVM_CMD_CPRM       0x43            /* Clear Power Reduction Mode */
  55 #define SAMD_NVM_CMD_PBC        0x44            /* Page Buffer Clear */
  56 #define SAMD_NVM_CMD_SSB        0x45            /* Set Security Bit */
  57 #define SAMD_NVM_CMD_INVALL     0x46            /* Invalidate all caches */
  58
  59 /* Known identifiers */
  60 #define SAMD_PROCESSOR_M0       0x01
  61 #define SAMD_FAMILY_D           0x00
  62 #define SAMD_SERIES_20          0x00
  63 #define SAMD_SERIES_21          0x01
  64 #define SAMD_SERIES_10          0x02
  65 #define SAMD_SERIES_11          0x03
  66
  67 struct samd_part {
  68         uint8_t id;
  69         const char *name;
  70         uint32_t flash_kb;
  71         uint32_t ram_kb;
  72 };
  73
  74 /* Known SAMD10 parts */
  75 static const struct samd_part samd10_parts[] = {
  76         { 0x0, "SAMD10D14AMU", 16, 4 },
  77         { 0x1, "SAMD10D13AMU", 8, 4 },
  78         { 0x2, "SAMD10D12AMU", 4, 4 },
  79         { 0x3, "SAMD10D14ASU", 16, 4 },
  80         { 0x4, "SAMD10D13ASU", 8, 4 },
  81         { 0x5, "SAMD10D12ASU", 4, 4 },
  82         { 0x6, "SAMD10C14A", 16, 4 },
  83         { 0x7, "SAMD10C13A", 8, 4 },
  84         { 0x8, "SAMD10C12A", 4, 4 },
  85 };
  86
  87 /* Known SAMD11 parts */
  88 static const struct samd_part samd11_parts[] = {
  89         { 0x0, "SAMD11D14AMU", 16, 4 },
  90         { 0x1, "SAMD11D13AMU", 8, 4 },
  91         { 0x2, "SAMD11D12AMU", 4, 4 },
  92         { 0x3, "SAMD11D14ASU", 16, 4 },
  93         { 0x4, "SAMD11D13ASU", 8, 4 },
  94         { 0x5, "SAMD11D12ASU", 4, 4 },
  95         { 0x6, "SAMD11C14A", 16, 4 },
  96         { 0x7, "SAMD11C13A", 8, 4 },
  97         { 0x8, "SAMD11C12A", 4, 4 },
  98 };
  99
 100 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
 101 static const struct samd_part samd20_parts[] = {
 102         { 0x0, "SAMD20J18A", 256, 32 },
 103         { 0x1, "SAMD20J17A", 128, 16 },
 104         { 0x2, "SAMD20J16A", 64, 8 },
 105         { 0x3, "SAMD20J15A", 32, 4 },
 106         { 0x4, "SAMD20J14A", 16, 2 },
 107         { 0x5, "SAMD20G18A", 256, 32 },
 108         { 0x6, "SAMD20G17A", 128, 16 },
 109         { 0x7, "SAMD20G16A", 64, 8 },
 110         { 0x8, "SAMD20G15A", 32, 4 },
 111         { 0x9, "SAMD20G14A", 16, 2 },
 112         { 0xB, "SAMD20E17A", 128, 16 },
 113         { 0xC, "SAMD20E16A", 64, 8 },
 114         { 0xD, "SAMD20E15A", 32, 4 },
 115         { 0xE, "SAMD20E14A", 16, 2 },
 116 };
 117
 118 /* Known SAMD21 parts. */
 119 static const struct samd_part samd21_parts[] = {
 120         { 0x0, "SAMD21J18A", 256, 32 },
 121         { 0x1, "SAMD21J17A", 128, 16 },
 122         { 0x2, "SAMD21J16A", 64, 8 },
 123         { 0x3, "SAMD21J15A", 32, 4 },
 124         { 0x4, "SAMD21J14A", 16, 2 },
 125         { 0x5, "SAMD21G18A", 256, 32 },
 126         { 0x6, "SAMD21G17A", 128, 16 },
 127         { 0x7, "SAMD21G16A", 64, 8 },
 128         { 0x8, "SAMD21G15A", 32, 4 },
 129         { 0x9, "SAMD21G14A", 16, 2 },
 130         { 0xA, "SAMD21E18A", 256, 32 },
 131         { 0xB, "SAMD21E17A", 128, 16 },
 132         { 0xC, "SAMD21E16A", 64, 8 },
 133         { 0xD, "SAMD21E15A", 32, 4 },
 134         { 0xE, "SAMD21E14A", 16, 2 },
 135 };
 136
 137 /* Known SAMR21 parts. */
 138 static const struct samd_part samr21_parts[] = {
 139         { 0x19, "SAMR21G18A", 256, 32 },
 140         { 0x1A, "SAMR21G17A", 128, 32 },
 141         { 0x1B, "SAMR21G16A",  64, 32 },
 142         { 0x1C, "SAMR21E18A", 256, 32 },
 143         { 0x1D, "SAMR21E17A", 128, 32 },
 144         { 0x1E, "SAMR21E16A",  64, 32 },
 145 };
 146
 147
 148 /* Each family of parts contains a parts table in the DEVSEL field of DID.  The
 149  * processor ID, family ID, and series ID are used to determine which exact
 150  * family this is and then we can use the corresponding table. */
 151 struct samd_family {
 152         uint8_t processor;
 153         uint8_t family;
 154         uint8_t series;
 155         const struct samd_part *parts;
 156         size_t num_parts;
 157 };
 158
 159 /* Known SAMD families */
 160 static const struct samd_family samd_families[] = {
 161         { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
 162                 samd20_parts, ARRAY_SIZE(samd20_parts) },
 163         { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
 164                 samd21_parts, ARRAY_SIZE(samd21_parts) },
 165         { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
 166                 samr21_parts, ARRAY_SIZE(samr21_parts) },
 167         { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
 168                 samd10_parts, ARRAY_SIZE(samd10_parts) },
 169         { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
 170                 samd11_parts, ARRAY_SIZE(samd11_parts) },
 171 };
 172
 173 struct samd_info {
 174         uint32_t page_size;
 175         int num_pages;
 176         int sector_size;
 177
 178         bool probed;
 179         struct target *target;
 180         struct samd_info *next;
 181 };
 182
 183 static struct samd_info *samd_chips;
 184
 185 static const struct samd_part *samd_find_part(uint32_t id)
 186 {
 187         uint8_t processor = (id >> 28);
 188         uint8_t family = (id >> 24) & 0x0F;
 189         uint8_t series = (id >> 16) & 0xFF;
 190         uint8_t devsel = id & 0xFF;
 191
 192         for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
 193                 if (samd_families[i].processor == processor &&
 194                         samd_families[i].series == series &&
 195                         samd_families[i].family == family) {
 196                         for (unsigned j = 0; j < samd_families[i].num_parts; j++) {
 197                                 if (samd_families[i].parts[j].id == devsel)
 198                                         return &samd_families[i].parts[j];
 199                         }
 200                 }
 201         }
 202
 203         return NULL;
 204 }
 205
 206 static int samd_protect_check(struct flash_bank *bank)
 207 {
 208         int res;
 209         uint16_t lock;
 210
 211         res = target_read_u16(bank->target,
 212                         SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
 213         if (res != ERROR_OK)
 214                 return res;
 215
 216         /* Lock bits are active-low */
 217         for (int i = 0; i < bank->num_sectors; i++)
 218                 bank->sectors[i].is_protected = !(lock & (1<<i));
 219
 220         return ERROR_OK;
 221 }
 222
 223 static int samd_probe(struct flash_bank *bank)
 224 {
 225         uint32_t id, param;
 226         int res;
 227         struct samd_info *chip = (struct samd_info *)bank->driver_priv;
 228         const struct samd_part *part;
 229
 230         if (chip->probed)
 231                 return ERROR_OK;
 232
 233         res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
 234         if (res != ERROR_OK) {
 235                 LOG_ERROR("Couldn't read Device ID register");
 236                 return res;
 237         }
 238
 239         part = samd_find_part(id);
 240         if (part == NULL) {
 241                 LOG_ERROR("Couldn't find part correspoding to DID %08" PRIx32, id);
 242                 return ERROR_FAIL;
 243         }
 244
 245         res = target_read_u32(bank->target,
 246                         SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
 247         if (res != ERROR_OK) {
 248                 LOG_ERROR("Couldn't read NVM Parameters register");
 249                 return res;
 250         }
 251
 252         bank->size = part->flash_kb * 1024;
 253
 254         chip->sector_size = bank->size / SAMD_NUM_SECTORS;
 255
 256         /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n) so
 257          * 0 is 8KB and 7 is 1024KB. */
 258         chip->page_size = (8 << ((param >> 16) & 0x7));
 259         /* The NVMP field (bits 15:0) indicates the total number of pages */
 260         chip->num_pages = param & 0xFFFF;
 261
 262         /* Sanity check: the total flash size in the DSU should match the page size
 263          * multiplied by the number of pages. */
 264         if (bank->size != chip->num_pages * chip->page_size) {
 265                 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
 266                                 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
 267                                 part->flash_kb, chip->num_pages, chip->page_size);
 268         }
 269
 270         /* Allocate the sector table */
 271         bank->num_sectors = SAMD_NUM_SECTORS;
 272         bank->sectors = calloc(bank->num_sectors, sizeof((bank->sectors)[0]));
 273         if (!bank->sectors)
 274                 return ERROR_FAIL;
 275
 276         /* Fill out the sector information: all SAMD sectors are the same size and
 277          * there is always a fixed number of them. */
 278         for (int i = 0; i < bank->num_sectors; i++) {
 279                 bank->sectors[i].size = chip->sector_size;
 280                 bank->sectors[i].offset = i * chip->sector_size;
 281                 /* mark as unknown */
 282                 bank->sectors[i].is_erased = -1;
 283                 bank->sectors[i].is_protected = -1;
 284         }
 285
 286         samd_protect_check(bank);
 287
 288         /* Done */
 289         chip->probed = true;
 290
 291         LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
 292                         part->flash_kb, part->ram_kb);
 293
 294         return ERROR_OK;
 295 }
 296
 297 static int samd_protect(struct flash_bank *bank, int set, int first, int last)
 298 {
 299         int res;
 300         struct samd_info *chip = (struct samd_info *)bank->driver_priv;
 301
 302         res = ERROR_OK;
 303
 304         for (int s = first; s <= last; s++) {
 305                 if (set != bank->sectors[s].is_protected) {
 306                         /* Load an address that is within this sector (we use offset 0) */
 307                         res = target_write_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
 308                                                s * chip->sector_size);
 309                         if (res != ERROR_OK)
 310                                 goto exit;
 311
 312                         /* Tell the controller to lock that sector */
 313
 314                         uint16_t cmd = (set) ?
 315                                 SAMD_NVM_CMD(SAMD_NVM_CMD_LR) :
 316                                 SAMD_NVM_CMD(SAMD_NVM_CMD_UR);
 317
 318                         res = target_write_u16(bank->target,
 319                                                SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA,
 320                                                cmd);
 321                         if (res != ERROR_OK)
 322                                 goto exit;
 323                 }
 324         }
 325 exit:
 326         samd_protect_check(bank);
 327
 328         return res;
 329 }
 330
 331 static bool samd_check_error(struct flash_bank *bank)
 332 {
 333         int ret;
 334         bool error;
 335         uint16_t status;
 336
 337         ret = target_read_u16(bank->target,
 338                         SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
 339         if (ret != ERROR_OK) {
 340                 LOG_ERROR("Can't read NVM status");
 341                 return true;
 342         }
 343
 344         if (status & 0x001C) {
 345                 if (status & (1 << 4)) /* NVME */
 346                         LOG_ERROR("SAMD: NVM Error");
 347                 if (status & (1 << 3)) /* LOCKE */
 348                         LOG_ERROR("SAMD: NVM lock error");
 349                 if (status & (1 << 2)) /* PROGE */
 350                         LOG_ERROR("SAMD: NVM programming error");
 351
 352                 error = true;
 353         } else {
 354                 error = false;
 355         }
 356
 357         /* Clear the error conditions by writing a one to them */
 358         ret = target_write_u16(bank->target,
 359                         SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
 360         if (ret != ERROR_OK)
 361                 LOG_ERROR("Can't clear NVM error conditions");
 362
 363         return error;
 364 }
 365
 366 static int samd_erase_row(struct flash_bank *bank, uint32_t address)
 367 {
 368         int res;
 369         bool error = false;
 370
 371         /* Set an address contained in the row to be erased */
 372         res = target_write_u32(bank->target,
 373                         SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
 374         if (res == ERROR_OK) {
 375                 /* Issue the Erase Row command to erase that row */
 376                 res = target_write_u16(bank->target,
 377                                 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA,
 378                                 SAMD_NVM_CMD(SAMD_NVM_CMD_ER));
 379
 380                 /* Check (and clear) error conditions */
 381                 error = samd_check_error(bank);
 382         }
 383
 384         if (res != ERROR_OK || error)  {
 385                 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
 386                 return ERROR_FAIL;
 387         }
 388
 389         return ERROR_OK;
 390 }
 391
 392 static int samd_erase(struct flash_bank *bank, int first, int last)
 393 {
 394         int res;
 395         int rows_in_sector;
 396         struct samd_info *chip = (struct samd_info *)bank->driver_priv;
 397
 398         if (bank->target->state != TARGET_HALTED) {
 399                 LOG_ERROR("Target not halted");
 400
 401                 return ERROR_TARGET_NOT_HALTED;
 402         }
 403
 404         if (!chip->probed) {
 405                 if (samd_probe(bank) != ERROR_OK)
 406                         return ERROR_FLASH_BANK_NOT_PROBED;
 407         }
 408
 409         /* The SAMD NVM has row erase granularity.  There are four pages in a row
 410          * and the number of rows in a sector depends on the sector size, which in
 411          * turn depends on the Flash capacity as there is a fixed number of
 412          * sectors. */
 413         rows_in_sector = chip->sector_size / (chip->page_size * 4);
 414
 415         /* For each sector to be erased */
 416         for (int s = first; s <= last; s++) {
 417                 if (bank->sectors[s].is_protected) {
 418                         LOG_ERROR("SAMD: failed to erase sector %d. That sector is write-protected", s);
 419                         return ERROR_FLASH_OPERATION_FAILED;
 420                 }
 421
 422                 if (!bank->sectors[s].is_erased) {
 423                         /* For each row in that sector */
 424                         for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
 425                                 res = samd_erase_row(bank, r * chip->page_size * 4);
 426                                 if (res != ERROR_OK) {
 427                                         LOG_ERROR("SAMD: failed to erase sector %d", s);
 428                                         return res;
 429                                 }
 430                         }
 431
 432                         bank->sectors[s].is_erased = 1;
 433                 }
 434         }
 435
 436         return ERROR_OK;
 437 }
 438
 439 static struct flash_sector *samd_find_sector_by_address(struct flash_bank *bank, uint32_t address)
 440 {
 441         struct samd_info *chip = (struct samd_info *)bank->driver_priv;
 442
 443         for (int i = 0; i < bank->num_sectors; i++) {
 444                 if (bank->sectors[i].offset <= address &&
 445                     address < bank->sectors[i].offset + chip->sector_size)
 446                         return &bank->sectors[i];
 447         }
 448         return NULL;
 449 }
 450
 451 /* Write an entire row (four pages) from host buffer 'buf' to row-aligned
 452  * 'address' in the Flash. */
 453 static int samd_write_row(struct flash_bank *bank, uint32_t address,
 454                 const uint8_t *buf)
 455 {
 456         int res;
 457         struct samd_info *chip = (struct samd_info *)bank->driver_priv;
 458
 459         struct flash_sector *sector = samd_find_sector_by_address(bank, address);
 460
 461         if (!sector) {
 462                 LOG_ERROR("Can't find sector corresponding to address 0x%08" PRIx32, address);
 463                 return ERROR_FLASH_OPERATION_FAILED;
 464         }
 465
 466         if (sector->is_protected) {
 467                 LOG_ERROR("Trying to write to a protected sector at 0x%08" PRIx32, address);
 468                 return ERROR_FLASH_OPERATION_FAILED;
 469         }
 470
 471         /* Erase the row that we'll be writing to */
 472         res = samd_erase_row(bank, address);
 473         if (res != ERROR_OK)
 474                 return res;
 475
 476         /* Now write the pages in this row. */
 477         for (unsigned int i = 0; i < 4; i++) {
 478                 bool error;
 479
 480                 /* Write the page contents to the target's page buffer.  A page write
 481                  * is issued automatically once the last location is written in the
 482                  * page buffer (ie: a complete page has been written out). */
 483                 res = target_write_memory(bank->target, address, 4,
 484                                 chip->page_size / 4, buf);
 485                 if (res != ERROR_OK) {
 486                         LOG_ERROR("%s: %d", __func__, __LINE__);
 487                         return res;
 488                 }
 489
 490                 error = samd_check_error(bank);
 491                 if (error)
 492                         return ERROR_FAIL;
 493
 494                 /* Next page */
 495                 address += chip->page_size;
 496                 buf += chip->page_size;
 497         }
 498
 499         sector->is_erased = 0;
 500
 501         return res;
 502 }
 503
 504 /* Write partial contents into row-aligned 'address' on the Flash from host
 505  * buffer 'buf' by writing 'nb' of 'buf' at 'row_offset' into the Flash row. */
 506 static int samd_write_row_partial(struct flash_bank *bank, uint32_t address,
 507                 const uint8_t *buf, uint32_t row_offset, uint32_t nb)
 508 {
 509         int res;
 510         struct samd_info *chip = (struct samd_info *)bank->driver_priv;
 511         uint32_t row_size = chip->page_size * 4;
 512         uint8_t *rb = malloc(row_size);
 513         if (!rb)
 514                 return ERROR_FAIL;
 515
 516         assert(row_offset + nb < row_size);
 517         assert((address % row_size) == 0);
 518
 519         /* Retrieve the full row contents from Flash */
 520         res = target_read_memory(bank->target, address, 4, row_size / 4, rb);
 521         if (res != ERROR_OK) {
 522                 free(rb);
 523                 return res;
 524         }
 525
 526         /* Insert our partial row over the data from Flash */
 527         memcpy(rb + (row_offset % row_size), buf, nb);
 528
 529         /* Write the row back out */
 530         res = samd_write_row(bank, address, rb);
 531         free(rb);
 532
 533         return res;
 534 }
 535
 536 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
 537                 uint32_t offset, uint32_t count)
 538 {
 539         int res;
 540         uint32_t address;
 541         uint32_t nb = 0;
 542         struct samd_info *chip = (struct samd_info *)bank->driver_priv;
 543         uint32_t row_size = chip->page_size * 4;
 544
 545         if (bank->target->state != TARGET_HALTED) {
 546                 LOG_ERROR("Target not halted");
 547
 548                 return ERROR_TARGET_NOT_HALTED;
 549         }
 550
 551         if (!chip->probed) {
 552                 if (samd_probe(bank) != ERROR_OK)
 553                         return ERROR_FLASH_BANK_NOT_PROBED;
 554         }
 555
 556         if (offset % row_size) {
 557                 /* We're starting at an unaligned offset so we'll write a partial row
 558                  * comprising that offset and up to the end of that row. */
 559                 nb = row_size - (offset % row_size);
 560                 if (nb > count)
 561                         nb = count;
 562         } else if (count < row_size) {
 563                 /* We're writing an aligned but partial row. */
 564                 nb = count;
 565         }
 566
 567         address = (offset / row_size) * row_size + bank->base;
 568
 569         if (nb > 0) {
 570                 res = samd_write_row_partial(bank, address, buffer,
 571                                 offset % row_size, nb);
 572                 if (res != ERROR_OK)
 573                         return res;
 574
 575                 /* We're done with the row contents */
 576                 count -= nb;
 577                 offset += nb;
 578                 buffer += row_size;
 579         }
 580
 581         /* There's at least one aligned row to write out. */
 582         if (count >= row_size) {
 583                 int nr = count / row_size + ((count % row_size) ? 1 : 0);
 584                 unsigned int r = 0;
 585
 586                 for (unsigned int i = address / row_size;
 587                                 (i < (address / row_size) + nr) && count > 0; i++) {
 588                         address = (i * row_size) + bank->base;
 589
 590                         if (count >= row_size) {
 591                                 res = samd_write_row(bank, address, buffer + (r * row_size));
 592                                 /* Advance one row */
 593                                 offset += row_size;
 594                                 count -= row_size;
 595                         } else {
 596                                 res = samd_write_row_partial(bank, address,
 597                                                 buffer + (r * row_size), 0, count);
 598                                 /* We're done after this. */
 599                                 offset += count;
 600                                 count = 0;
 601                         }
 602
 603                         r++;
 604
 605                         if (res != ERROR_OK)
 606                                 return res;
 607                 }
 608         }
 609
 610         return ERROR_OK;
 611 }
 612
 613 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
 614 {
 615         struct samd_info *chip = samd_chips;
 616
 617         while (chip) {
 618                 if (chip->target == bank->target)
 619                         break;
 620                 chip = chip->next;
 621         }
 622
 623         if (!chip) {
 624                 /* Create a new chip */
 625                 chip = calloc(1, sizeof(*chip));
 626                 if (!chip)
 627                         return ERROR_FAIL;
 628
 629                 chip->target = bank->target;
 630                 chip->probed = false;
 631
 632                 bank->driver_priv = chip;
 633
 634                 /* Insert it into the chips list (at head) */
 635                 chip->next = samd_chips;
 636                 samd_chips = chip;
 637         }
 638
 639         if (bank->base != SAMD_FLASH) {
 640                 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
 641                                 "[at91samd series] )",
 642                                 bank->base, SAMD_FLASH);
 643                 return ERROR_FAIL;
 644         }
 645
 646         return ERROR_OK;
 647 }
 648
 649 COMMAND_HANDLER(samd_handle_info_command)
 650 {
 651         return ERROR_OK;
 652 }
 653
 654 static const struct command_registration at91samd_exec_command_handlers[] = {
 655         {
 656                 .name = "info",
 657                 .handler = samd_handle_info_command,
 658                 .mode = COMMAND_EXEC,
 659                 .help = "Print information about the current at91samd chip"
 660                         "and its flash configuration.",
 661         },
 662         COMMAND_REGISTRATION_DONE
 663 };
 664
 665 static const struct command_registration at91samd_command_handlers[] = {
 666         {
 667                 .name = "at91samd",
 668                 .mode = COMMAND_ANY,
 669                 .help = "at91samd flash command group",
 670                 .usage = "",
 671                 .chain = at91samd_exec_command_handlers,
 672         },
 673         COMMAND_REGISTRATION_DONE
 674 };
 675
 676 struct flash_driver at91samd_flash = {
 677         .name = "at91samd",
 678         .commands = at91samd_command_handlers,
 679         .flash_bank_command = samd_flash_bank_command,
 680         .erase = samd_erase,
 681         .protect = samd_protect,
 682         .write = samd_write,
 683         .read = default_flash_read,
 684         .probe = samd_probe,
 685         .auto_probe = samd_probe,
 686         .erase_check = default_flash_blank_check,
 687         .protect_check = samd_protect_check,
 688 };