1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code)
4 * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com>
7 * Copyright (C) 2010 by Olaf Lüke <olaf@uni-paderborn.de>
9 * at91sam3x* & at91sam4 support
10 * Copyright (C) 2011 by Olivier Schonken, Jim Norris
12 * Some of the lower level code was based on code supplied by
13 * ATMEL under BSD-Source-Code License and this copyright.
14 * ATMEL Microcontroller Software Support
15 * Copyright (c) 2009, Atmel Corporation. All rights reserved.
23 #include <helper/time_support.h>
25 #define REG_NAME_WIDTH (12)
27 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
28 #define FLASH_BANK_BASE_S 0x00400000
29 #define FLASH_BANK_BASE_C 0x01000000
31 /* at91sam4sd series (two one flash banks), first bank address */
32 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
33 /* at91sam4sd16x, second bank address */
34 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
35 /* at91sam4sd32x, second bank address */
36 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
38 /* at91sam4c32x, first and second bank address */
39 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
40 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
42 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
43 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
44 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
45 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
46 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
47 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
48 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
49 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
50 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
51 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
52 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
53 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
54 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
55 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
56 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
57 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
58 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
60 #define OFFSET_EFC_FMR 0
61 #define OFFSET_EFC_FCR 4
62 #define OFFSET_EFC_FSR 8
63 #define OFFSET_EFC_FRR 12
65 extern const struct flash_driver at91sam4_flash;
67 static float _tomhz(uint32_t freq_hz)
71 f = ((float)(freq_hz)) / 1000000.0;
75 /* How the chip is configured. */
77 uint32_t unique_id[4];
81 uint32_t mainosc_freq;
91 #define SAM4_CHIPID_CIDR (0x400E0740)
93 #define SAM4_CHIPID_EXID (0x400E0744)
96 #define SAM4_PMC_BASE (0x400E0400)
97 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
99 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
101 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
103 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
105 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
107 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
109 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
111 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
113 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
115 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
117 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
119 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
121 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
123 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
127 struct sam4_bank_private {
129 /* DANGER: THERE ARE DRAGONS HERE.. */
130 /* NOTE: If you add more 'ghost' pointers */
131 /* be aware that you must *manually* update */
132 /* these pointers in the function sam4_get_details() */
133 /* See the comment "Here there be dragons" */
135 /* so we can find the chip we belong to */
136 struct sam4_chip *chip;
137 /* so we can find the original bank pointer */
138 struct flash_bank *bank;
139 unsigned bank_number;
140 uint32_t controller_address;
141 uint32_t base_address;
142 uint32_t flash_wait_states;
146 unsigned sector_size;
150 struct sam4_chip_details {
151 /* THERE ARE DRAGONS HERE.. */
152 /* note: If you add pointers here */
153 /* be careful about them as they */
154 /* may need to be updated inside */
155 /* the function: "sam4_get_details() */
156 /* which copy/overwrites the */
157 /* 'runtime' copy of this structure */
158 uint32_t chipid_cidr;
162 #define SAM4_N_NVM_BITS 3
163 unsigned gpnvm[SAM4_N_NVM_BITS];
164 unsigned total_flash_size;
165 unsigned total_sram_size;
167 #define SAM4_MAX_FLASH_BANKS 2
168 /* these are "initialized" from the global const data */
169 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
173 struct sam4_chip *next;
176 /* this is "initialized" from the global const structure */
177 struct sam4_chip_details details;
178 struct target *target;
183 struct sam4_reg_list {
184 uint32_t address; size_t struct_offset; const char *name;
185 void (*explain_func)(struct sam4_chip *chip);
188 static struct sam4_chip *all_sam4_chips;
190 static struct sam4_chip *get_current_sam4(struct command_invocation *cmd)
193 static struct sam4_chip *p;
195 t = get_current_target(cmd->ctx);
197 command_print_sameline(cmd, "No current target?\n");
203 /* this should not happen */
204 /* the command is not registered until the chip is created? */
205 command_print_sameline(cmd, "No SAM4 chips exist?\n");
214 command_print_sameline(cmd, "Cannot find SAM4 chip?\n");
218 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
219 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
220 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
221 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
223 /* these are used to *initialize* the "chip->details" structure. */
224 static const struct sam4_chip_details all_sam4_details[] = {
225 /* Start at91sam4c* series */
226 /* at91sam4c32e - LQFP144 */
228 .chipid_cidr = 0xA66D0EE0,
229 .name = "at91sam4c32e",
230 .total_flash_size = 2024 * 1024,
231 .total_sram_size = 256 * 1024,
241 .base_address = FLASH_BANK0_BASE_C32,
242 .controller_address = 0x400e0a00,
243 .flash_wait_states = 5,
245 .size_bytes = 1024 * 1024,
256 .base_address = FLASH_BANK1_BASE_C32,
257 .controller_address = 0x400e0c00,
258 .flash_wait_states = 5,
260 .size_bytes = 1024 * 1024,
267 /* at91sam4c32c - LQFP100 */
269 .chipid_cidr = 0xA64D0EE0,
270 .name = "at91sam4c32c",
271 .total_flash_size = 2024 * 1024,
272 .total_sram_size = 256 * 1024,
282 .base_address = FLASH_BANK0_BASE_C32,
283 .controller_address = 0x400e0a00,
284 .flash_wait_states = 5,
286 .size_bytes = 1024 * 1024,
297 .base_address = FLASH_BANK1_BASE_C32,
298 .controller_address = 0x400e0c00,
299 .flash_wait_states = 5,
301 .size_bytes = 1024 * 1024,
308 /* at91sam4c16c - LQFP100 */
310 .chipid_cidr = 0xA64C0CE0,
311 .name = "at91sam4c16c",
312 .total_flash_size = 1024 * 1024,
313 .total_sram_size = 128 * 1024,
323 .base_address = FLASH_BANK_BASE_C,
324 .controller_address = 0x400e0a00,
325 .flash_wait_states = 5,
327 .size_bytes = 1024 * 1024,
341 /* at91sam4c8c - LQFP100 */
343 .chipid_cidr = 0xA64C0AE0,
344 .name = "at91sam4c8c",
345 .total_flash_size = 512 * 1024,
346 .total_sram_size = 128 * 1024,
356 .base_address = FLASH_BANK_BASE_C,
357 .controller_address = 0x400e0a00,
358 .flash_wait_states = 5,
360 .size_bytes = 512 * 1024,
374 /* at91sam4c4c (rev B) - LQFP100 */
376 .chipid_cidr = 0xA64C0CE5,
377 .name = "at91sam4c4c",
378 .total_flash_size = 256 * 1024,
379 .total_sram_size = 128 * 1024,
389 .base_address = FLASH_BANK_BASE_C,
390 .controller_address = 0x400e0a00,
391 .flash_wait_states = 5,
393 .size_bytes = 256 * 1024,
408 /* Start at91sam4e* series */
409 /*atsam4e16e - LQFP144/LFBGA144*/
411 .chipid_cidr = 0xA3CC0CE0,
412 .name = "at91sam4e16e",
413 .total_flash_size = 1024 * 1024,
414 .total_sram_size = 128 * 1024,
424 .base_address = FLASH_BANK_BASE_S,
425 .controller_address = 0x400e0a00,
426 .flash_wait_states = 5,
428 .size_bytes = 1024 * 1024,
443 /* Start at91sam4n* series */
444 /*atsam4n8a - LQFP48/QFN48*/
446 .chipid_cidr = 0x293B0AE0,
447 .name = "at91sam4n8a",
448 .total_flash_size = 512 * 1024,
449 .total_sram_size = 64 * 1024,
459 .base_address = FLASH_BANK_BASE_S,
460 .controller_address = 0x400e0a00,
461 .flash_wait_states = 5,
463 .size_bytes = 512 * 1024,
477 /*atsam4n8b - LQFP64/QFN64*/
479 .chipid_cidr = 0x294B0AE0,
480 .name = "at91sam4n8b",
481 .total_flash_size = 512 * 1024,
482 .total_sram_size = 64 * 1024,
492 .base_address = FLASH_BANK_BASE_S,
493 .controller_address = 0x400e0a00,
494 .flash_wait_states = 5,
496 .size_bytes = 512 * 1024,
510 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
512 .chipid_cidr = 0x295B0AE0,
513 .name = "at91sam4n8c",
514 .total_flash_size = 512 * 1024,
515 .total_sram_size = 64 * 1024,
525 .base_address = FLASH_BANK_BASE_S,
526 .controller_address = 0x400e0a00,
527 .flash_wait_states = 5,
529 .size_bytes = 512 * 1024,
543 /*atsam4n16b - LQFP64/QFN64*/
545 .chipid_cidr = 0x29460CE0,
546 .name = "at91sam4n16b",
547 .total_flash_size = 1024 * 1024,
548 .total_sram_size = 80 * 1024,
558 .base_address = FLASH_BANK_BASE_S,
559 .controller_address = 0x400e0a00,
560 .flash_wait_states = 5,
562 .size_bytes = 1024 * 1024,
576 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
578 .chipid_cidr = 0x29560CE0,
579 .name = "at91sam4n16c",
580 .total_flash_size = 1024 * 1024,
581 .total_sram_size = 80 * 1024,
591 .base_address = FLASH_BANK_BASE_S,
592 .controller_address = 0x400e0a00,
593 .flash_wait_states = 5,
595 .size_bytes = 1024 * 1024,
610 /* Start at91sam4s* series */
611 /*atsam4s16c - LQFP100/BGA100*/
613 .chipid_cidr = 0x28AC0CE0,
614 .name = "at91sam4s16c",
615 .total_flash_size = 1024 * 1024,
616 .total_sram_size = 128 * 1024,
626 .base_address = FLASH_BANK_BASE_S,
627 .controller_address = 0x400e0a00,
628 .flash_wait_states = 5,
630 .size_bytes = 1024 * 1024,
644 /*at91sam4sa16c - TFBGA100/VFBGA100/LQFP100*/
646 .chipid_cidr = 0x28a70ce0,
647 .name = "at91sam4sa16c",
648 .total_flash_size = 1024 * 1024,
649 .total_sram_size = 160 * 1024,
660 .base_address = FLASH_BANK_BASE_S,
661 .controller_address = 0x400e0a00,
662 .flash_wait_states = 5,
664 .size_bytes = 1024 * 1024,
678 /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
680 .chipid_cidr = 0x289C0CE0,
681 .name = "at91sam4s16b",
682 .total_flash_size = 1024 * 1024,
683 .total_sram_size = 128 * 1024,
693 .base_address = FLASH_BANK_BASE_S,
694 .controller_address = 0x400e0a00,
695 .flash_wait_states = 5,
697 .size_bytes = 1024 * 1024,
711 /*atsam4sa16b - LQFP64/QFN64*/
713 .chipid_cidr = 0x28970CE0,
714 .name = "at91sam4sa16b",
715 .total_flash_size = 1024 * 1024,
716 .total_sram_size = 160 * 1024,
726 .base_address = FLASH_BANK_BASE_S,
727 .controller_address = 0x400e0a00,
728 .flash_wait_states = 5,
730 .size_bytes = 1024 * 1024,
744 /*atsam4s16a - LQFP48/QFN48*/
746 .chipid_cidr = 0x288C0CE0,
747 .name = "at91sam4s16a",
748 .total_flash_size = 1024 * 1024,
749 .total_sram_size = 128 * 1024,
759 .base_address = FLASH_BANK_BASE_S,
760 .controller_address = 0x400e0a00,
761 .flash_wait_states = 5,
763 .size_bytes = 1024 * 1024,
777 /*atsam4s8c - LQFP100/BGA100*/
779 .chipid_cidr = 0x28AC0AE0,
780 .name = "at91sam4s8c",
781 .total_flash_size = 512 * 1024,
782 .total_sram_size = 128 * 1024,
792 .base_address = FLASH_BANK_BASE_S,
793 .controller_address = 0x400e0a00,
794 .flash_wait_states = 5,
796 .size_bytes = 512 * 1024,
810 /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
812 .chipid_cidr = 0x289C0AE0,
813 .name = "at91sam4s8b",
814 .total_flash_size = 512 * 1024,
815 .total_sram_size = 128 * 1024,
825 .base_address = FLASH_BANK_BASE_S,
826 .controller_address = 0x400e0a00,
827 .flash_wait_states = 5,
829 .size_bytes = 512 * 1024,
843 /*atsam4s8a - LQFP48/BGA48*/
845 .chipid_cidr = 0x288C0AE0,
846 .name = "at91sam4s8a",
847 .total_flash_size = 512 * 1024,
848 .total_sram_size = 128 * 1024,
858 .base_address = FLASH_BANK_BASE_S,
859 .controller_address = 0x400e0a00,
860 .flash_wait_states = 5,
862 .size_bytes = 512 * 1024,
877 /*atsam4s4c - LQFP100/BGA100*/
879 .chipid_cidr = 0x28ab09e0,
880 .name = "at91sam4s4c",
881 .total_flash_size = 256 * 1024,
882 .total_sram_size = 64 * 1024,
892 .base_address = FLASH_BANK_BASE_S,
893 .controller_address = 0x400e0a00,
894 .flash_wait_states = 5,
896 .size_bytes = 256 * 1024,
911 /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
913 .chipid_cidr = 0x289b09e0,
914 .name = "at91sam4s4b",
915 .total_flash_size = 256 * 1024,
916 .total_sram_size = 64 * 1024,
926 .base_address = FLASH_BANK_BASE_S,
927 .controller_address = 0x400e0a00,
928 .flash_wait_states = 5,
930 .size_bytes = 256 * 1024,
945 /*atsam4s4a - LQFP48/QFN48*/
947 .chipid_cidr = 0x288b09e0,
948 .name = "at91sam4s4a",
949 .total_flash_size = 256 * 1024,
950 .total_sram_size = 64 * 1024,
960 .base_address = FLASH_BANK_BASE_S,
961 .controller_address = 0x400e0a00,
962 .flash_wait_states = 5,
964 .size_bytes = 256 * 1024,
979 /*atsam4s2c - LQFP100/BGA100*/
981 .chipid_cidr = 0x28ab07e0,
982 .name = "at91sam4s2c",
983 .total_flash_size = 128 * 1024,
984 .total_sram_size = 64 * 1024,
994 .base_address = FLASH_BANK_BASE_S,
995 .controller_address = 0x400e0a00,
996 .flash_wait_states = 5,
998 .size_bytes = 128 * 1024,
1000 .sector_size = 8192,
1013 /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1015 .chipid_cidr = 0x289b07e0,
1016 .name = "at91sam4s2b",
1017 .total_flash_size = 128 * 1024,
1018 .total_sram_size = 64 * 1024,
1028 .base_address = FLASH_BANK_BASE_S,
1029 .controller_address = 0x400e0a00,
1030 .flash_wait_states = 5,
1032 .size_bytes = 128 * 1024,
1034 .sector_size = 8192,
1047 /*atsam4s2a - LQFP48/QFN48*/
1049 .chipid_cidr = 0x288b07e0,
1050 .name = "at91sam4s2a",
1051 .total_flash_size = 128 * 1024,
1052 .total_sram_size = 64 * 1024,
1062 .base_address = FLASH_BANK_BASE_S,
1063 .controller_address = 0x400e0a00,
1064 .flash_wait_states = 5,
1066 .size_bytes = 128 * 1024,
1068 .sector_size = 8192,
1081 /*at91sam4sd32c - LQFP100/BGA100*/
1083 .chipid_cidr = 0x29a70ee0,
1084 .name = "at91sam4sd32c",
1085 .total_flash_size = 2048 * 1024,
1086 .total_sram_size = 160 * 1024,
1097 .base_address = FLASH_BANK0_BASE_SD,
1098 .controller_address = 0x400e0a00,
1099 .flash_wait_states = 5,
1101 .size_bytes = 1024 * 1024,
1103 .sector_size = 8192,
1113 .base_address = FLASH_BANK1_BASE_2048K_SD,
1114 .controller_address = 0x400e0c00,
1115 .flash_wait_states = 5,
1117 .size_bytes = 1024 * 1024,
1119 .sector_size = 8192,
1125 /*at91sam4sd32b - LQFP64/BGA64*/
1127 .chipid_cidr = 0x29970ee0,
1128 .name = "at91sam4sd32b",
1129 .total_flash_size = 2048 * 1024,
1130 .total_sram_size = 160 * 1024,
1141 .base_address = FLASH_BANK0_BASE_SD,
1142 .controller_address = 0x400e0a00,
1143 .flash_wait_states = 5,
1145 .size_bytes = 1024 * 1024,
1147 .sector_size = 8192,
1157 .base_address = FLASH_BANK1_BASE_2048K_SD,
1158 .controller_address = 0x400e0c00,
1159 .flash_wait_states = 5,
1161 .size_bytes = 1024 * 1024,
1163 .sector_size = 8192,
1169 /*at91sam4sd16c - LQFP100/BGA100*/
1171 .chipid_cidr = 0x29a70ce0,
1172 .name = "at91sam4sd16c",
1173 .total_flash_size = 1024 * 1024,
1174 .total_sram_size = 160 * 1024,
1185 .base_address = FLASH_BANK0_BASE_SD,
1186 .controller_address = 0x400e0a00,
1187 .flash_wait_states = 5,
1189 .size_bytes = 512 * 1024,
1191 .sector_size = 8192,
1201 .base_address = FLASH_BANK1_BASE_1024K_SD,
1202 .controller_address = 0x400e0c00,
1203 .flash_wait_states = 5,
1205 .size_bytes = 512 * 1024,
1207 .sector_size = 8192,
1213 /*at91sam4sd16b - LQFP64/BGA64*/
1215 .chipid_cidr = 0x29970ce0,
1216 .name = "at91sam4sd16b",
1217 .total_flash_size = 1024 * 1024,
1218 .total_sram_size = 160 * 1024,
1229 .base_address = FLASH_BANK0_BASE_SD,
1230 .controller_address = 0x400e0a00,
1231 .flash_wait_states = 5,
1233 .size_bytes = 512 * 1024,
1235 .sector_size = 8192,
1245 .base_address = FLASH_BANK1_BASE_1024K_SD,
1246 .controller_address = 0x400e0c00,
1247 .flash_wait_states = 5,
1249 .size_bytes = 512 * 1024,
1251 .sector_size = 8192,
1259 .chipid_cidr = 0x247e0ae0,
1260 .name = "atsamg53n19",
1261 .total_flash_size = 512 * 1024,
1262 .total_sram_size = 96 * 1024,
1273 .base_address = FLASH_BANK_BASE_S,
1274 .controller_address = 0x400e0a00,
1275 .flash_wait_states = 5,
1277 .size_bytes = 512 * 1024,
1279 .sector_size = 8192,
1292 /* atsamg55g19 Rev.A */
1294 .chipid_cidr = 0x24470ae0,
1295 .name = "atsamg55g19",
1296 .total_flash_size = 512 * 1024,
1297 .total_sram_size = 160 * 1024,
1308 .base_address = FLASH_BANK_BASE_S,
1309 .controller_address = 0x400e0a00,
1310 .flash_wait_states = 5,
1312 .size_bytes = 512 * 1024,
1314 .sector_size = 8192,
1326 /* atsamg55g19 Rev.B */
1328 .chipid_cidr = 0x24470ae1,
1329 .name = "atsamg55g19b",
1330 .total_flash_size = 512 * 1024,
1331 .total_sram_size = 160 * 1024,
1342 .base_address = FLASH_BANK_BASE_S,
1343 .controller_address = 0x400e0a00,
1344 .flash_wait_states = 5,
1346 .size_bytes = 512 * 1024,
1348 .sector_size = 8192,
1360 /* atsamg55j19 Rev.A */
1362 .chipid_cidr = 0x24570ae0,
1363 .name = "atsamg55j19",
1364 .total_flash_size = 512 * 1024,
1365 .total_sram_size = 160 * 1024,
1376 .base_address = FLASH_BANK_BASE_S,
1377 .controller_address = 0x400e0a00,
1378 .flash_wait_states = 5,
1380 .size_bytes = 512 * 1024,
1382 .sector_size = 8192,
1394 /* atsamg55j19 Rev.B */
1396 .chipid_cidr = 0x24570ae1,
1397 .name = "atsamg55j19b",
1398 .total_flash_size = 512 * 1024,
1399 .total_sram_size = 160 * 1024,
1410 .base_address = FLASH_BANK_BASE_S,
1411 .controller_address = 0x400e0a00,
1412 .flash_wait_states = 5,
1414 .size_bytes = 512 * 1024,
1416 .sector_size = 8192,
1436 /***********************************************************************
1437 **********************************************************************
1438 **********************************************************************
1439 **********************************************************************
1440 **********************************************************************
1441 **********************************************************************/
1442 /* *ATMEL* style code - from the SAM4 driver code */
1445 * Get the current status of the EEFC and
1446 * the value of some status bits (LOCKE, PROGE).
1447 * @param private - info about the bank
1448 * @param v - result goes here
1450 static int efc_get_status(struct sam4_bank_private *private, uint32_t *v)
1453 r = target_read_u32(private->chip->target,
1454 private->controller_address + OFFSET_EFC_FSR,
1456 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1458 ((unsigned int)((*v >> 2) & 1)),
1459 ((unsigned int)((*v >> 1) & 1)),
1460 ((unsigned int)((*v >> 0) & 1)));
1466 * Get the result of the last executed command.
1467 * @param private - info about the bank
1468 * @param v - result goes here
1470 static int efc_get_result(struct sam4_bank_private *private, uint32_t *v)
1474 r = target_read_u32(private->chip->target,
1475 private->controller_address + OFFSET_EFC_FRR,
1479 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1483 static int efc_start_command(struct sam4_bank_private *private,
1484 unsigned command, unsigned argument)
1493 /* Check command & argument */
1496 case AT91C_EFC_FCMD_WP:
1497 case AT91C_EFC_FCMD_WPL:
1498 case AT91C_EFC_FCMD_EWP:
1499 case AT91C_EFC_FCMD_EWPL:
1500 /* case AT91C_EFC_FCMD_EPL: */
1501 case AT91C_EFC_FCMD_EPA:
1502 case AT91C_EFC_FCMD_SLB:
1503 case AT91C_EFC_FCMD_CLB:
1504 n = (private->size_bytes / private->page_size);
1506 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1509 case AT91C_EFC_FCMD_SFB:
1510 case AT91C_EFC_FCMD_CFB:
1511 if (argument >= private->chip->details.n_gpnvms) {
1512 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1513 private->chip->details.n_gpnvms);
1517 case AT91C_EFC_FCMD_GETD:
1518 case AT91C_EFC_FCMD_EA:
1519 case AT91C_EFC_FCMD_GLB:
1520 case AT91C_EFC_FCMD_GFB:
1521 case AT91C_EFC_FCMD_STUI:
1522 case AT91C_EFC_FCMD_SPUI:
1524 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1527 LOG_ERROR("Unknown command %d", command);
1531 if (command == AT91C_EFC_FCMD_SPUI) {
1532 /* this is a very special situation. */
1533 /* Situation (1) - error/retry - see below */
1534 /* And we are being called recursively */
1535 /* Situation (2) - normal, finished reading unique id */
1537 /* it should be "ready" */
1538 efc_get_status(private, &v);
1540 /* then it is ready */
1544 /* we have done this before */
1545 /* the controller is not responding. */
1546 LOG_ERROR("flash controller(%d) is not ready! Error",
1547 private->bank_number);
1551 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1552 private->bank_number);
1553 /* we do that by issuing the *STOP* command */
1554 efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
1555 /* above is recursive, and further recursion is blocked by */
1556 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1562 v = (0x5A << 24) | (argument << 8) | command;
1563 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1564 r = target_write_u32(private->bank->target,
1565 private->controller_address + OFFSET_EFC_FCR, v);
1567 LOG_DEBUG("Error Write failed");
1572 * Performs the given command and wait until its completion (or an error).
1573 * @param private - info about the bank
1574 * @param command - Command to perform.
1575 * @param argument - Optional command argument.
1576 * @param status - put command status bits here
1578 static int efc_perform_command(struct sam4_bank_private *private,
1586 int64_t ms_now, ms_end;
1592 r = efc_start_command(private, command, argument);
1596 ms_end = 10000 + timeval_ms();
1599 r = efc_get_status(private, &v);
1602 ms_now = timeval_ms();
1603 if (ms_now > ms_end) {
1605 LOG_ERROR("Command timeout");
1608 } while ((v & 1) == 0);
1612 *status = (v & 0x6);
1618 * Read the unique ID.
1619 * @param private - info about the bank
1620 * The unique ID is stored in the 'private' structure.
1622 static int flashd_read_uid(struct sam4_bank_private *private)
1628 private->chip->cfg.unique_id[0] = 0;
1629 private->chip->cfg.unique_id[1] = 0;
1630 private->chip->cfg.unique_id[2] = 0;
1631 private->chip->cfg.unique_id[3] = 0;
1634 r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
1638 for (x = 0; x < 4; x++) {
1639 r = target_read_u32(private->chip->target,
1640 private->bank->base + (x * 4),
1644 private->chip->cfg.unique_id[x] = v;
1647 r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
1648 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1650 (unsigned int)(private->chip->cfg.unique_id[0]),
1651 (unsigned int)(private->chip->cfg.unique_id[1]),
1652 (unsigned int)(private->chip->cfg.unique_id[2]),
1653 (unsigned int)(private->chip->cfg.unique_id[3]));
1659 * Erases the entire flash.
1660 * @param private - the info about the bank.
1662 static int flashd_erase_entire_bank(struct sam4_bank_private *private)
1665 return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
1669 * Erases the entire flash.
1670 * @param private - the info about the bank.
1675 static int flashd_erase_pages(struct sam4_bank_private *private,
1681 uint8_t erase_pages;
1682 switch (num_pages) {
1700 /* AT91C_EFC_FCMD_EPA
1701 * According to the datasheet FARG[15:2] defines the page from which
1702 * the erase will start.This page must be modulo 4, 8, 16 or 32
1703 * according to the number of pages to erase. FARG[1:0] defines the
1704 * number of pages to be erased. Previously (firstpage << 2) was used
1705 * to conform to this, seems it should not be shifted...
1707 return efc_perform_command(private,
1708 /* send Erase Page */
1710 (first_page) | erase_pages,
1715 * Gets current GPNVM state.
1716 * @param private - info about the bank.
1717 * @param gpnvm - GPNVM bit index.
1718 * @param puthere - result stored here.
1720 /* ------------------------------------------------------------------------------ */
1721 static int flashd_get_gpnvm(struct sam4_bank_private *private, unsigned gpnvm, unsigned *puthere)
1727 if (private->bank_number != 0) {
1728 LOG_ERROR("GPNVM only works with Bank0");
1732 if (gpnvm >= private->chip->details.n_gpnvms) {
1733 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1734 gpnvm, private->chip->details.n_gpnvms);
1738 /* Get GPNVMs status */
1739 r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
1740 if (r != ERROR_OK) {
1741 LOG_ERROR("Failed");
1745 r = efc_get_result(private, &v);
1748 /* Check if GPNVM is set */
1749 /* get the bit and make it a 0/1 */
1750 *puthere = (v >> gpnvm) & 1;
1757 * Clears the selected GPNVM bit.
1758 * @param private info about the bank
1759 * @param gpnvm GPNVM index.
1760 * @returns 0 if successful; otherwise returns an error code.
1762 static int flashd_clr_gpnvm(struct sam4_bank_private *private, unsigned gpnvm)
1768 if (private->bank_number != 0) {
1769 LOG_ERROR("GPNVM only works with Bank0");
1773 if (gpnvm >= private->chip->details.n_gpnvms) {
1774 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1775 gpnvm, private->chip->details.n_gpnvms);
1779 r = flashd_get_gpnvm(private, gpnvm, &v);
1780 if (r != ERROR_OK) {
1781 LOG_DEBUG("Failed: %d", r);
1784 r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1785 LOG_DEBUG("End: %d", r);
1790 * Sets the selected GPNVM bit.
1791 * @param private info about the bank
1792 * @param gpnvm GPNVM index.
1794 static int flashd_set_gpnvm(struct sam4_bank_private *private, unsigned gpnvm)
1799 if (private->bank_number != 0) {
1800 LOG_ERROR("GPNVM only works with Bank0");
1804 if (gpnvm >= private->chip->details.n_gpnvms) {
1805 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1806 gpnvm, private->chip->details.n_gpnvms);
1810 r = flashd_get_gpnvm(private, gpnvm, &v);
1818 r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1824 * Returns a bit field (at most 64) of locked regions within a page.
1825 * @param private info about the bank
1826 * @param v where to store locked bits
1828 static int flashd_get_lock_bits(struct sam4_bank_private *private, uint32_t *v)
1832 r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
1833 if (r == ERROR_OK) {
1834 efc_get_result(private, v);
1835 efc_get_result(private, v);
1836 efc_get_result(private, v);
1837 r = efc_get_result(private, v);
1839 LOG_DEBUG("End: %d", r);
1844 * Unlocks all the regions in the given address range.
1845 * @param private info about the bank
1846 * @param start_sector first sector to unlock
1847 * @param end_sector last (inclusive) to unlock
1850 static int flashd_unlock(struct sam4_bank_private *private,
1851 unsigned start_sector,
1852 unsigned end_sector)
1857 uint32_t pages_per_sector;
1859 pages_per_sector = private->sector_size / private->page_size;
1861 /* Unlock all pages */
1862 while (start_sector <= end_sector) {
1863 pg = start_sector * pages_per_sector;
1865 r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
1876 * @param private - info about the bank
1877 * @param start_sector - first sector to lock
1878 * @param end_sector - last sector (inclusive) to lock
1880 static int flashd_lock(struct sam4_bank_private *private,
1881 unsigned start_sector,
1882 unsigned end_sector)
1886 uint32_t pages_per_sector;
1889 pages_per_sector = private->sector_size / private->page_size;
1891 /* Lock all pages */
1892 while (start_sector <= end_sector) {
1893 pg = start_sector * pages_per_sector;
1895 r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
1903 /****** END SAM4 CODE ********/
1905 /* begin helpful debug code */
1906 /* print the fieldname, the field value, in dec & hex, and return field value */
1907 static uint32_t sam4_reg_fieldname(struct sam4_chip *chip,
1908 const char *regname,
1917 /* extract the field */
1919 v = v & ((1 << width)-1);
1928 /* show the basics */
1929 LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
1930 REG_NAME_WIDTH, regname,
1936 static const char _unknown[] = "unknown";
1937 static const char *const eproc_names[] = {
1938 "Cortex-M7", /* 0 */
1941 "Cortex-M3", /* 3 */
1943 "arm926ejs", /* 5 */
1944 "Cortex-A5", /* 6 */
1945 "Cortex-M4", /* 7 */
1956 #define nvpsize2 nvpsize /* these two tables are identical */
1957 static const char *const nvpsize[] = {
1960 "16K bytes", /* 2 */
1961 "32K bytes", /* 3 */
1963 "64K bytes", /* 5 */
1965 "128K bytes", /* 7 */
1966 "160K bytes", /* 8 */
1967 "256K bytes", /* 9 */
1968 "512K bytes", /* 10 */
1970 "1024K bytes", /* 12 */
1972 "2048K bytes", /* 14 */
1976 static const char *const sramsize[] = {
1977 "48K Bytes", /* 0 */
1981 "112K Bytes", /* 4 */
1983 "80K Bytes", /* 6 */
1984 "160K Bytes", /* 7 */
1986 "16K Bytes", /* 9 */
1987 "32K Bytes", /* 10 */
1988 "64K Bytes", /* 11 */
1989 "128K Bytes", /* 12 */
1990 "256K Bytes", /* 13 */
1991 "96K Bytes", /* 14 */
1992 "512K Bytes", /* 15 */
1996 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1997 { 0x19, "AT91SAM9xx Series" },
1998 { 0x29, "AT91SAM9XExx Series" },
1999 { 0x34, "AT91x34 Series" },
2000 { 0x37, "CAP7 Series" },
2001 { 0x39, "CAP9 Series" },
2002 { 0x3B, "CAP11 Series" },
2003 { 0x3C, "ATSAM4E" },
2004 { 0x40, "AT91x40 Series" },
2005 { 0x42, "AT91x42 Series" },
2006 { 0x43, "SAMG51 Series"
2008 { 0x44, "SAMG55 Series (49-pin WLCSP)" },
2009 { 0x45, "SAMG55 Series (64-pin)" },
2010 { 0x47, "SAMG53 Series"
2012 { 0x55, "AT91x55 Series" },
2013 { 0x60, "AT91SAM7Axx Series" },
2014 { 0x61, "AT91SAM7AQxx Series" },
2015 { 0x63, "AT91x63 Series" },
2016 { 0x64, "SAM4CxxC (100-pin version)" },
2017 { 0x66, "SAM4CxxE (144-pin version)" },
2018 { 0x70, "AT91SAM7Sxx Series" },
2019 { 0x71, "AT91SAM7XCxx Series" },
2020 { 0x72, "AT91SAM7SExx Series" },
2021 { 0x73, "AT91SAM7Lxx Series" },
2022 { 0x75, "AT91SAM7Xxx Series" },
2023 { 0x76, "AT91SAM7SLxx Series" },
2024 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2025 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2026 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
2027 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
2028 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
2029 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2030 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2031 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2032 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2033 { 0x92, "AT91x92 Series" },
2034 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2035 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2036 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2037 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2038 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2039 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2040 { 0xA5, "ATSAM5A" },
2041 { 0xF0, "AT75Cxx Series" },
2045 static const char *const nvptype[] = {
2047 "romless or onchip flash", /* 1 */
2048 "embedded flash memory",/* 2 */
2049 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2050 "sram emulating flash", /* 4 */
2056 static const char *_yes_or_no(uint32_t v)
2064 static const char *const _rc_freq[] = {
2065 "4 MHz", "8 MHz", "12 MHz", "reserved"
2068 static void sam4_explain_ckgr_mor(struct sam4_chip *chip)
2073 v = sam4_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
2074 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2075 v = sam4_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
2076 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2077 rcen = sam4_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
2078 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2079 v = sam4_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
2080 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2082 chip->cfg.rc_freq = 0;
2086 chip->cfg.rc_freq = 0;
2089 chip->cfg.rc_freq = 4 * 1000 * 1000;
2092 chip->cfg.rc_freq = 8 * 1000 * 1000;
2095 chip->cfg.rc_freq = 12 * 1000 * 1000;
2100 v = sam4_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
2101 LOG_USER("(startup clks, time= %f uSecs)",
2102 ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
2103 v = sam4_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
2104 LOG_USER("(mainosc source: %s)",
2105 v ? "external xtal" : "internal RC");
2107 v = sam4_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
2108 LOG_USER("(clock failure enabled: %s)",
2112 static void sam4_explain_chipid_cidr(struct sam4_chip *chip)
2118 sam4_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
2121 v = sam4_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
2122 LOG_USER("%s", eproc_names[v]);
2124 v = sam4_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
2125 LOG_USER("%s", nvpsize[v]);
2127 v = sam4_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
2128 LOG_USER("%s", nvpsize2[v]);
2130 v = sam4_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
2131 LOG_USER("%s", sramsize[v]);
2133 v = sam4_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
2135 for (x = 0; archnames[x].name; x++) {
2136 if (v == archnames[x].value) {
2137 cp = archnames[x].name;
2144 v = sam4_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
2145 LOG_USER("%s", nvptype[v]);
2147 v = sam4_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
2148 LOG_USER("(exists: %s)", _yes_or_no(v));
2151 static void sam4_explain_ckgr_mcfr(struct sam4_chip *chip)
2155 v = sam4_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
2156 LOG_USER("(main ready: %s)", _yes_or_no(v));
2158 v = sam4_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
2160 v = (v * chip->cfg.slow_freq) / 16;
2161 chip->cfg.mainosc_freq = v;
2163 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2165 (uint32_t)(chip->cfg.slow_freq / 1000),
2166 (uint32_t)(chip->cfg.slow_freq % 1000));
2169 static void sam4_explain_ckgr_plla(struct sam4_chip *chip)
2171 uint32_t mula, diva;
2173 diva = sam4_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
2175 mula = sam4_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
2177 chip->cfg.plla_freq = 0;
2179 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2181 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2182 else if (diva >= 1) {
2183 chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
2184 LOG_USER("\tPLLA Freq: %3.03f MHz",
2185 _tomhz(chip->cfg.plla_freq));
2189 static void sam4_explain_mckr(struct sam4_chip *chip)
2191 uint32_t css, pres, fin = 0;
2193 const char *cp = NULL;
2195 css = sam4_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
2198 fin = chip->cfg.slow_freq;
2202 fin = chip->cfg.mainosc_freq;
2206 fin = chip->cfg.plla_freq;
2210 if (chip->cfg.CKGR_UCKR & (1 << 16)) {
2211 fin = 480 * 1000 * 1000;
2215 cp = "upll (*ERROR* UPLL is disabled)";
2223 LOG_USER("%s (%3.03f Mhz)",
2226 pres = sam4_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
2227 switch (pres & 0x07) {
2230 cp = "selected clock";
2264 LOG_USER("(%s)", cp);
2266 /* sam4 has a *SINGLE* clock - */
2267 /* other at91 series parts have divisors for these. */
2268 chip->cfg.cpu_freq = fin;
2269 chip->cfg.mclk_freq = fin;
2270 chip->cfg.fclk_freq = fin;
2271 LOG_USER("\t\tResult CPU Freq: %3.03f",
2276 static struct sam4_chip *target2sam4(struct target *target)
2278 struct sam4_chip *chip;
2283 chip = all_sam4_chips;
2285 if (chip->target == target)
2286 break; /* return below */
2294 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *cfg, const struct sam4_reg_list *list)
2296 /* this function exists to help */
2297 /* keep funky offsetof() errors */
2298 /* and casting from causing bugs */
2300 /* By using prototypes - we can detect what would */
2301 /* be casting errors. */
2303 return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
2307 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2309 NAME), # NAME, FUNC }
2310 static const struct sam4_reg_list sam4_all_regs[] = {
2311 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
2312 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
2313 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
2314 SAM4_ENTRY(CKGR_UCKR, NULL),
2315 SAM4_ENTRY(PMC_FSMR, NULL),
2316 SAM4_ENTRY(PMC_FSPR, NULL),
2317 SAM4_ENTRY(PMC_IMR, NULL),
2318 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
2319 SAM4_ENTRY(PMC_PCK0, NULL),
2320 SAM4_ENTRY(PMC_PCK1, NULL),
2321 SAM4_ENTRY(PMC_PCK2, NULL),
2322 SAM4_ENTRY(PMC_PCSR, NULL),
2323 SAM4_ENTRY(PMC_SCSR, NULL),
2324 SAM4_ENTRY(PMC_SR, NULL),
2325 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
2326 SAM4_ENTRY(CHIPID_EXID, NULL),
2327 /* TERMINATE THE LIST */
2332 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
2334 return bank->driver_priv;
2338 * Given a pointer to where it goes in the structure,
2339 * determine the register name, address from the all registers table.
2341 static const struct sam4_reg_list *sam4_get_reg(struct sam4_chip *chip, uint32_t *goes_here)
2343 const struct sam4_reg_list *reg;
2345 reg = &(sam4_all_regs[0]);
2349 /* calculate where this one go.. */
2350 /* it is "possibly" this register. */
2352 possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
2354 /* well? Is it this register */
2355 if (possible == goes_here) {
2363 /* This is *TOTAL*PANIC* - we are totally screwed. */
2364 LOG_ERROR("INVALID SAM4 REGISTER");
2368 static int sam4_read_this_reg(struct sam4_chip *chip, uint32_t *goes_here)
2370 const struct sam4_reg_list *reg;
2373 reg = sam4_get_reg(chip, goes_here);
2377 r = target_read_u32(chip->target, reg->address, goes_here);
2378 if (r != ERROR_OK) {
2379 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2380 reg->name, (unsigned)(reg->address), r);
2385 static int sam4_read_all_regs(struct sam4_chip *chip)
2388 const struct sam4_reg_list *reg;
2390 reg = &(sam4_all_regs[0]);
2392 r = sam4_read_this_reg(chip,
2393 sam4_get_reg_ptr(&(chip->cfg), reg));
2394 if (r != ERROR_OK) {
2395 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2396 reg->name, ((unsigned)(reg->address)), r);
2405 static int sam4_get_info(struct sam4_chip *chip)
2407 const struct sam4_reg_list *reg;
2411 r = sam4_read_all_regs(chip);
2415 reg = &(sam4_all_regs[0]);
2417 /* display all regs */
2418 LOG_DEBUG("Start: %s", reg->name);
2419 regval = *sam4_get_reg_ptr(&(chip->cfg), reg);
2420 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2425 if (reg->explain_func)
2426 (*(reg->explain_func))(chip);
2427 LOG_DEBUG("End: %s", reg->name);
2430 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
2431 LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
2432 LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
2433 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
2434 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
2436 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
2437 chip->cfg.unique_id[0],
2438 chip->cfg.unique_id[1],
2439 chip->cfg.unique_id[2],
2440 chip->cfg.unique_id[3]);
2445 static int sam4_protect_check(struct flash_bank *bank)
2448 uint32_t v[4] = {0};
2450 struct sam4_bank_private *private;
2453 if (bank->target->state != TARGET_HALTED) {
2454 LOG_ERROR("Target not halted");
2455 return ERROR_TARGET_NOT_HALTED;
2458 private = get_sam4_bank_private(bank);
2460 LOG_ERROR("no private for this bank?");
2463 if (!(private->probed))
2464 return ERROR_FLASH_BANK_NOT_PROBED;
2466 r = flashd_get_lock_bits(private, v);
2467 if (r != ERROR_OK) {
2468 LOG_DEBUG("Failed: %d", r);
2472 for (x = 0; x < private->nsectors; x++)
2473 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
2478 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
2480 struct sam4_chip *chip;
2482 chip = all_sam4_chips;
2484 /* is this an existing chip? */
2486 if (chip->target == bank->target)
2492 /* this is a *NEW* chip */
2493 chip = calloc(1, sizeof(struct sam4_chip));
2495 LOG_ERROR("NO RAM!");
2498 chip->target = bank->target;
2499 /* insert at head */
2500 chip->next = all_sam4_chips;
2501 all_sam4_chips = chip;
2502 chip->target = bank->target;
2503 /* assumption is this runs at 32khz */
2504 chip->cfg.slow_freq = 32768;
2505 chip->probed = false;
2508 switch (bank->base) {
2510 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2511 "[at91sam4s series] )",
2512 ((unsigned int)(bank->base)),
2513 ((unsigned int)(FLASH_BANK_BASE_S)));
2516 /* at91sam4s series only has bank 0*/
2517 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2518 case FLASH_BANK_BASE_S:
2519 case FLASH_BANK_BASE_C:
2520 bank->driver_priv = &(chip->details.bank[0]);
2521 bank->bank_number = 0;
2522 chip->details.bank[0].chip = chip;
2523 chip->details.bank[0].bank = bank;
2526 /* Bank 1 of at91sam4sd/at91sam4c32 series */
2527 case FLASH_BANK1_BASE_1024K_SD:
2528 case FLASH_BANK1_BASE_2048K_SD:
2529 case FLASH_BANK1_BASE_C32:
2530 bank->driver_priv = &(chip->details.bank[1]);
2531 bank->bank_number = 1;
2532 chip->details.bank[1].chip = chip;
2533 chip->details.bank[1].bank = bank;
2537 /* we initialize after probing. */
2542 * Remove all chips from the internal list without distinguishing which one
2543 * is owned by this bank. This simplification works only for one shot
2544 * deallocation like current flash_free_all_banks()
2546 static void sam4_free_driver_priv(struct flash_bank *bank)
2548 struct sam4_chip *chip = all_sam4_chips;
2550 struct sam4_chip *next = chip->next;
2554 all_sam4_chips = NULL;
2557 static int sam4_get_details(struct sam4_bank_private *private)
2559 const struct sam4_chip_details *details;
2560 struct sam4_chip *chip;
2561 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2565 details = all_sam4_details;
2566 while (details->name) {
2567 /* Compare cidr without version bits */
2568 if (details->chipid_cidr == (private->chip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2573 if (!details->name) {
2574 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2575 (unsigned int)(private->chip->cfg.CHIPID_CIDR));
2576 /* Help the victim, print details about the chip */
2577 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2578 private->chip->cfg.CHIPID_CIDR);
2579 sam4_explain_chipid_cidr(private->chip);
2582 LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, details->name, details->chipid_cidr);
2585 /* DANGER: THERE ARE DRAGONS HERE */
2587 /* get our chip - it is going */
2588 /* to be over-written shortly */
2589 chip = private->chip;
2591 /* Note that, in reality: */
2593 /* private = &(chip->details.bank[0]) */
2594 /* or private = &(chip->details.bank[1]) */
2597 /* save the "bank" pointers */
2598 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2599 saved_banks[x] = chip->details.bank[x].bank;
2601 /* Overwrite the "details" structure. */
2602 memcpy(&(private->chip->details),
2604 sizeof(private->chip->details));
2606 /* now fix the ghosted pointers */
2607 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2608 chip->details.bank[x].chip = chip;
2609 chip->details.bank[x].bank = saved_banks[x];
2612 /* update the *BANK*SIZE* */
2618 static int sam4_info(struct flash_bank *bank, struct command_invocation *cmd)
2620 struct sam4_bank_private *private;
2621 int k = bank->size / 1024;
2623 private = get_sam4_bank_private(bank);
2627 command_print_sameline(cmd, "%s bank %d: %d kB at " TARGET_ADDR_FMT,
2628 private->chip->details.name,
2629 private->bank_number,
2636 static int sam4_probe(struct flash_bank *bank)
2639 struct sam4_bank_private *private;
2642 LOG_DEBUG("Begin: Bank: %u", bank->bank_number);
2643 if (bank->target->state != TARGET_HALTED) {
2644 LOG_ERROR("Target not halted");
2645 return ERROR_TARGET_NOT_HALTED;
2648 private = get_sam4_bank_private(bank);
2650 LOG_ERROR("Invalid/unknown bank number");
2654 r = sam4_read_all_regs(private->chip);
2659 if (private->chip->probed)
2660 r = sam4_get_info(private->chip);
2662 r = sam4_get_details(private);
2666 /* update the flash bank size */
2667 for (unsigned int x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2668 if (bank->base == private->chip->details.bank[x].base_address) {
2669 bank->size = private->chip->details.bank[x].size_bytes;
2670 LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
2671 TARGET_ADDR_FMT ", idx %d", bank->base,
2672 bank->base + bank->size, x);
2677 if (!bank->sectors) {
2678 bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
2679 if (!bank->sectors) {
2680 LOG_ERROR("No memory!");
2683 bank->num_sectors = private->nsectors;
2685 for (unsigned int x = 0; x < bank->num_sectors; x++) {
2686 bank->sectors[x].size = private->sector_size;
2687 bank->sectors[x].offset = x * (private->sector_size);
2688 /* mark as unknown */
2689 bank->sectors[x].is_erased = -1;
2690 bank->sectors[x].is_protected = -1;
2694 private->probed = true;
2696 r = sam4_protect_check(bank);
2700 LOG_DEBUG("Bank = %d, nbanks = %d",
2701 private->bank_number, private->chip->details.n_banks);
2702 if ((private->bank_number + 1) == private->chip->details.n_banks) {
2703 /* read unique id, */
2704 /* it appears to be associated with the *last* flash bank. */
2705 flashd_read_uid(private);
2711 static int sam4_auto_probe(struct flash_bank *bank)
2713 struct sam4_bank_private *private;
2715 private = get_sam4_bank_private(bank);
2716 if (private && private->probed)
2719 return sam4_probe(bank);
2722 static int sam4_erase(struct flash_bank *bank, unsigned int first,
2725 struct sam4_bank_private *private;
2728 /*16 pages equals 8KB - Same size as a lock region*/
2733 if (bank->target->state != TARGET_HALTED) {
2734 LOG_ERROR("Target not halted");
2735 return ERROR_TARGET_NOT_HALTED;
2738 r = sam4_auto_probe(bank);
2739 if (r != ERROR_OK) {
2740 LOG_DEBUG("Here,r=%d", r);
2744 private = get_sam4_bank_private(bank);
2745 if (!(private->probed))
2746 return ERROR_FLASH_BANK_NOT_PROBED;
2748 if ((first == 0) && ((last + 1) == private->nsectors)) {
2751 return flashd_erase_entire_bank(private);
2753 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2754 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", first, last);
2755 for (unsigned int i = first; i <= last; i++) {
2756 /*16 pages equals 8KB - Same size as a lock region*/
2757 r = flashd_erase_pages(private, (i * page_count), page_count, &status);
2758 LOG_INFO("Erasing sector: 0x%08x", i);
2760 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %u",
2762 if (status & (1 << 2)) {
2763 LOG_ERROR("SAM4: Lock Region %u is locked", i);
2766 if (status & (1 << 1)) {
2767 LOG_ERROR("SAM4: Flash Command error @lock region %u", i);
2775 static int sam4_protect(struct flash_bank *bank, int set, unsigned int first,
2778 struct sam4_bank_private *private;
2782 if (bank->target->state != TARGET_HALTED) {
2783 LOG_ERROR("Target not halted");
2784 return ERROR_TARGET_NOT_HALTED;
2787 private = get_sam4_bank_private(bank);
2788 if (!(private->probed))
2789 return ERROR_FLASH_BANK_NOT_PROBED;
2792 r = flashd_lock(private, first, last);
2794 r = flashd_unlock(private, first, last);
2795 LOG_DEBUG("End: r=%d", r);
2801 static int sam4_page_read(struct sam4_bank_private *private, unsigned pagenum, uint8_t *buf)
2806 adr = pagenum * private->page_size;
2807 adr = adr + private->base_address;
2809 r = target_read_memory(private->chip->target,
2811 4, /* THIS*MUST*BE* in 32bit values */
2812 private->page_size / 4,
2815 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2816 (unsigned int)(adr));
2820 static int sam4_set_wait(struct sam4_bank_private *private)
2822 uint32_t fmr; /* EEFC Flash Mode Register */
2825 /* Get flash mode register value */
2826 r = target_read_u32(private->chip->target, private->controller_address, &fmr);
2827 if (r != ERROR_OK) {
2828 LOG_ERROR("Error Read failed: read flash mode register");
2832 /* Clear flash wait state field */
2835 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2836 fmr |= (private->flash_wait_states << 8);
2838 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2839 r = target_write_u32(private->bank->target, private->controller_address, fmr);
2841 LOG_ERROR("Error Write failed: set flash mode register");
2846 static int sam4_page_write(struct sam4_bank_private *private, unsigned pagenum, const uint8_t *buf)
2852 adr = pagenum * private->page_size;
2853 adr = (adr + private->base_address);
2855 /* 1st sector 8kBytes - page 0 - 15*/
2856 /* 2nd sector 8kBytes - page 16 - 30*/
2857 /* 3rd sector 48kBytes - page 31 - 127*/
2858 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2859 r = target_write_memory(private->chip->target,
2861 4, /* THIS*MUST*BE* in 32bit values */
2862 private->page_size / 4,
2864 if (r != ERROR_OK) {
2865 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2866 (unsigned int)(adr));
2870 r = efc_perform_command(private,
2871 /* send Erase & Write Page */
2872 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2877 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2878 (unsigned int)(adr));
2879 if (status & (1 << 2)) {
2880 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2883 if (status & (1 << 1)) {
2884 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2890 static int sam4_write(struct flash_bank *bank,
2891 const uint8_t *buffer,
2899 unsigned page_offset;
2900 struct sam4_bank_private *private;
2901 uint8_t *pagebuffer;
2903 /* in case we bail further below, set this to null */
2906 /* ignore dumb requests */
2912 if (bank->target->state != TARGET_HALTED) {
2913 LOG_ERROR("Target not halted");
2914 r = ERROR_TARGET_NOT_HALTED;
2918 private = get_sam4_bank_private(bank);
2919 if (!(private->probed)) {
2920 r = ERROR_FLASH_BANK_NOT_PROBED;
2924 if ((offset + count) > private->size_bytes) {
2925 LOG_ERROR("Flash write error - past end of bank");
2926 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2927 (unsigned int)(offset),
2928 (unsigned int)(count),
2929 (unsigned int)(private->size_bytes));
2934 pagebuffer = malloc(private->page_size);
2936 LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
2941 r = sam4_set_wait(private);
2945 /* what page do we start & end in? */
2946 page_cur = offset / private->page_size;
2947 page_end = (offset + count - 1) / private->page_size;
2949 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2950 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2952 /* Special case: all one page */
2955 /* (1) non-aligned start */
2956 /* (2) body pages */
2957 /* (3) non-aligned end. */
2959 /* Handle special case - all one page. */
2960 if (page_cur == page_end) {
2961 LOG_DEBUG("Special case, all in one page");
2962 r = sam4_page_read(private, page_cur, pagebuffer);
2966 page_offset = (offset & (private->page_size-1));
2967 memcpy(pagebuffer + page_offset,
2971 r = sam4_page_write(private, page_cur, pagebuffer);
2978 /* non-aligned start */
2979 page_offset = offset & (private->page_size - 1);
2981 LOG_DEBUG("Not-Aligned start");
2982 /* read the partial */
2983 r = sam4_page_read(private, page_cur, pagebuffer);
2987 /* over-write with new data */
2988 n = (private->page_size - page_offset);
2989 memcpy(pagebuffer + page_offset,
2993 r = sam4_page_write(private, page_cur, pagebuffer);
3003 /* By checking that offset is correct here, we also
3004 fix a clang warning */
3005 assert(offset % private->page_size == 0);
3007 /* intermediate large pages */
3008 /* also - the final *terminal* */
3009 /* if that terminal page is a full page */
3010 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3011 (int)page_cur, (int)page_end, (unsigned int)(count));
3013 while ((page_cur < page_end) &&
3014 (count >= private->page_size)) {
3015 r = sam4_page_write(private, page_cur, buffer);
3018 count -= private->page_size;
3019 buffer += private->page_size;
3023 /* terminal partial page? */
3025 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3026 /* we have a partial page */
3027 r = sam4_page_read(private, page_cur, pagebuffer);
3030 /* data goes at start */
3031 memcpy(pagebuffer, buffer, count);
3032 r = sam4_page_write(private, page_cur, pagebuffer);
3043 COMMAND_HANDLER(sam4_handle_info_command)
3045 struct sam4_chip *chip;
3046 chip = get_current_sam4(CMD);
3053 /* bank0 must exist before we can do anything */
3054 if (!chip->details.bank[0].bank) {
3058 "Please define bank %d via command: flash bank %s ... ",
3060 at91sam4_flash.name);
3064 /* if bank 0 is not probed, then probe it */
3065 if (!(chip->details.bank[0].probed)) {
3066 r = sam4_auto_probe(chip->details.bank[0].bank);
3070 /* above guarantees the "chip details" structure is valid */
3071 /* and thus, bank private areas are valid */
3072 /* and we have a SAM4 chip, what a concept! */
3074 /* auto-probe other banks, 0 done above */
3075 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
3076 /* skip banks not present */
3077 if (!(chip->details.bank[x].present))
3080 if (!chip->details.bank[x].bank)
3083 if (chip->details.bank[x].probed)
3086 r = sam4_auto_probe(chip->details.bank[x].bank);
3091 r = sam4_get_info(chip);
3092 if (r != ERROR_OK) {
3093 LOG_DEBUG("Sam4Info, Failed %d", r);
3100 COMMAND_HANDLER(sam4_handle_gpnvm_command)
3104 struct sam4_chip *chip;
3106 chip = get_current_sam4(CMD);
3110 if (chip->target->state != TARGET_HALTED) {
3111 LOG_ERROR("sam4 - target not halted");
3112 return ERROR_TARGET_NOT_HALTED;
3115 if (!chip->details.bank[0].bank) {
3116 command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
3117 at91sam4_flash.name);
3120 if (!chip->details.bank[0].probed) {
3121 r = sam4_auto_probe(chip->details.bank[0].bank);
3128 return ERROR_COMMAND_SYNTAX_ERROR;
3135 if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0))
3139 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3145 if (strcmp("show", CMD_ARGV[0]) == 0) {
3149 for (x = 0; x < chip->details.n_gpnvms; x++) {
3150 r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
3153 command_print(CMD, "sam4-gpnvm%u: %u", x, v);
3157 if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
3158 r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
3160 command_print(CMD, "sam4-gpnvm%u: %u", who, v);
3163 command_print(CMD, "sam4-gpnvm invalid GPNVM: %u", who);
3164 return ERROR_COMMAND_SYNTAX_ERROR;
3169 command_print(CMD, "Missing GPNVM number");
3170 return ERROR_COMMAND_SYNTAX_ERROR;
3173 if (strcmp("set", CMD_ARGV[0]) == 0)
3174 r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
3175 else if ((strcmp("clr", CMD_ARGV[0]) == 0) ||
3176 (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */
3177 r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
3179 command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
3180 r = ERROR_COMMAND_SYNTAX_ERROR;
3185 COMMAND_HANDLER(sam4_handle_slowclk_command)
3187 struct sam4_chip *chip;
3189 chip = get_current_sam4(CMD);
3201 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3203 /* absurd slow clock of 200Khz? */
3204 command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3205 return ERROR_COMMAND_SYNTAX_ERROR;
3207 chip->cfg.slow_freq = v;
3212 command_print(CMD, "Too many parameters");
3213 return ERROR_COMMAND_SYNTAX_ERROR;
3215 command_print(CMD, "Slowclk freq: %d.%03dkhz",
3216 (int)(chip->cfg.slow_freq / 1000),
3217 (int)(chip->cfg.slow_freq % 1000));
3221 static const struct command_registration at91sam4_exec_command_handlers[] = {
3224 .handler = sam4_handle_gpnvm_command,
3225 .mode = COMMAND_EXEC,
3226 .usage = "[('clr'|'set'|'show') bitnum]",
3227 .help = "Without arguments, shows all bits in the gpnvm "
3228 "register. Otherwise, clears, sets, or shows one "
3229 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3233 .handler = sam4_handle_info_command,
3234 .mode = COMMAND_EXEC,
3235 .help = "Print information about the current at91sam4 chip "
3236 "and its flash configuration.",
3241 .handler = sam4_handle_slowclk_command,
3242 .mode = COMMAND_EXEC,
3243 .usage = "[clock_hz]",
3244 .help = "Display or set the slowclock frequency "
3245 "(default 32768 Hz).",
3247 COMMAND_REGISTRATION_DONE
3249 static const struct command_registration at91sam4_command_handlers[] = {
3252 .mode = COMMAND_ANY,
3253 .help = "at91sam4 flash command group",
3255 .chain = at91sam4_exec_command_handlers,
3257 COMMAND_REGISTRATION_DONE
3260 const struct flash_driver at91sam4_flash = {
3262 .commands = at91sam4_command_handlers,
3263 .flash_bank_command = sam4_flash_bank_command,
3264 .erase = sam4_erase,
3265 .protect = sam4_protect,
3266 .write = sam4_write,
3267 .read = default_flash_read,
3268 .probe = sam4_probe,
3269 .auto_probe = sam4_auto_probe,
3270 .erase_check = default_flash_blank_check,
3271 .protect_check = sam4_protect_check,
3273 .free_driver_priv = sam4_free_driver_priv,