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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Duane Ellis                                     *
   3  *   openocd@duaneellis.com                                                *
   4  *                                                                         *
   5  *   Copyright (C) 2010 by Olaf Lüke (at91sam3s* support)                  *
   6  *   olaf@uni-paderborn.de                                                 *
   7  *                                                                                                                                                 *
   8  *   Copyright (C) 2011 by Olivier Schonken (at91sam3x* support)           *                                          *
   9  *                     and Jim Norris                                      *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24 ****************************************************************************/
  25
  26 /* Some of the the lower level code was based on code supplied by
  27  * ATMEL under this copyright. */
  28
  29 /* BEGIN ATMEL COPYRIGHT */
  30 /* ----------------------------------------------------------------------------
  31  *         ATMEL Microcontroller Software Support
  32  * ----------------------------------------------------------------------------
  33  * Copyright (c) 2009, Atmel Corporation
  34  *
  35  * All rights reserved.
  36  *
  37  * Redistribution and use in source and binary forms, with or without
  38  * modification, are permitted provided that the following conditions are met:
  39  *
  40  * - Redistributions of source code must retain the above copyright notice,
  41  * this list of conditions and the disclaimer below.
  42  *
  43  * Atmel's name may not be used to endorse or promote products derived from
  44  * this software without specific prior written permission.
  45  *
  46  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  47  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  48  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  49  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  50  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  51  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  52  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  53  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  54  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  55  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  56  * ----------------------------------------------------------------------------
  57  */
  58 /* END ATMEL COPYRIGHT */
  59
  60 #ifdef HAVE_CONFIG_H
  61 #include "config.h"
  62 #endif
  63
  64 #include "imp.h"
  65 #include <helper/time_support.h>
  66
  67 #define REG_NAME_WIDTH  (12)
  68
  69 /* at91sam3u series (has one or two flash banks) */
  70 #define FLASH_BANK0_BASE_U   0x00080000
  71 #define FLASH_BANK1_BASE_U   0x00100000
  72
  73 /* at91sam3s series (has always one flash bank) */
  74 #define FLASH_BANK_BASE_S   0x00400000
  75
  76 /* at91sam3n series (has always one flash bank) */
  77 #define FLASH_BANK_BASE_N   0x00400000
  78
  79 /* at91sam3a/x series has two flash banks*/
  80 #define FLASH_BANK0_BASE_AX                     0x00080000
  81 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
  82 #define FLASH_BANK1_BASE_256K_AX        0x000A0000
  83 #define FLASH_BANK1_BASE_512K_AX        0x000C0000
  84
  85 #define         AT91C_EFC_FCMD_GETD                 (0x0)       /* (EFC) Get Flash Descriptor */
  86 #define         AT91C_EFC_FCMD_WP                   (0x1)       /* (EFC) Write Page */
  87 #define         AT91C_EFC_FCMD_WPL                  (0x2)       /* (EFC) Write Page and Lock */
  88 #define         AT91C_EFC_FCMD_EWP                  (0x3)       /* (EFC) Erase Page and Write Page */
  89 #define         AT91C_EFC_FCMD_EWPL                 (0x4)       /* (EFC) Erase Page and Write Page
  90                                                                  * then Lock */
  91 #define         AT91C_EFC_FCMD_EA                   (0x5)       /* (EFC) Erase All */
  92 /* cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
  93 /* #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane? */
  94 /* cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
  95 /* #define      AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages? */
  96 #define         AT91C_EFC_FCMD_SLB                  (0x8)       /* (EFC) Set Lock Bit */
  97 #define         AT91C_EFC_FCMD_CLB                  (0x9)       /* (EFC) Clear Lock Bit */
  98 #define         AT91C_EFC_FCMD_GLB                  (0xA)       /* (EFC) Get Lock Bit */
  99 #define         AT91C_EFC_FCMD_SFB                  (0xB)       /* (EFC) Set Fuse Bit */
 100 #define         AT91C_EFC_FCMD_CFB                  (0xC)       /* (EFC) Clear Fuse Bit */
 101 #define         AT91C_EFC_FCMD_GFB                  (0xD)       /* (EFC) Get Fuse Bit */
 102 #define         AT91C_EFC_FCMD_STUI                 (0xE)       /* (EFC) Start Read Unique ID */
 103 #define         AT91C_EFC_FCMD_SPUI                 (0xF)       /* (EFC) Stop Read Unique ID */
 104
 105 #define  offset_EFC_FMR   0
 106 #define  offset_EFC_FCR   4
 107 #define  offset_EFC_FSR   8
 108 #define  offset_EFC_FRR   12
 109
 110 extern struct flash_driver at91sam3_flash;
 111
 112 static float _tomhz(uint32_t freq_hz)
 113 {
 114         float f;
 115
 116         f = ((float)(freq_hz)) / 1000000.0;
 117         return f;
 118 }
 119
 120 /* How the chip is configured. */
 121 struct sam3_cfg {
 122         uint32_t unique_id[4];
 123
 124         uint32_t slow_freq;
 125         uint32_t rc_freq;
 126         uint32_t mainosc_freq;
 127         uint32_t plla_freq;
 128         uint32_t mclk_freq;
 129         uint32_t cpu_freq;
 130         uint32_t fclk_freq;
 131         uint32_t pclk0_freq;
 132         uint32_t pclk1_freq;
 133         uint32_t pclk2_freq;
 134
 135
 136 #define SAM3_CHIPID_CIDR          (0x400E0740)
 137         uint32_t CHIPID_CIDR;
 138 #define SAM3_CHIPID_CIDR2         (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
 139         uint32_t CHIPID_CIDR2;
 140 #define SAM3_CHIPID_EXID          (0x400E0744)
 141         uint32_t CHIPID_EXID;
 142 #define SAM3_CHIPID_EXID2         (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
 143         uint32_t CHIPID_EXID2;
 144
 145
 146 #define SAM3_PMC_BASE             (0x400E0400)
 147 #define SAM3_PMC_SCSR             (SAM3_PMC_BASE + 0x0008)
 148         uint32_t PMC_SCSR;
 149 #define SAM3_PMC_PCSR             (SAM3_PMC_BASE + 0x0018)
 150         uint32_t PMC_PCSR;
 151 #define SAM3_CKGR_UCKR            (SAM3_PMC_BASE + 0x001c)
 152         uint32_t CKGR_UCKR;
 153 #define SAM3_CKGR_MOR             (SAM3_PMC_BASE + 0x0020)
 154         uint32_t CKGR_MOR;
 155 #define SAM3_CKGR_MCFR            (SAM3_PMC_BASE + 0x0024)
 156         uint32_t CKGR_MCFR;
 157 #define SAM3_CKGR_PLLAR           (SAM3_PMC_BASE + 0x0028)
 158         uint32_t CKGR_PLLAR;
 159 #define SAM3_PMC_MCKR             (SAM3_PMC_BASE + 0x0030)
 160         uint32_t PMC_MCKR;
 161 #define SAM3_PMC_PCK0             (SAM3_PMC_BASE + 0x0040)
 162         uint32_t PMC_PCK0;
 163 #define SAM3_PMC_PCK1             (SAM3_PMC_BASE + 0x0044)
 164         uint32_t PMC_PCK1;
 165 #define SAM3_PMC_PCK2             (SAM3_PMC_BASE + 0x0048)
 166         uint32_t PMC_PCK2;
 167 #define SAM3_PMC_SR               (SAM3_PMC_BASE + 0x0068)
 168         uint32_t PMC_SR;
 169 #define SAM3_PMC_IMR              (SAM3_PMC_BASE + 0x006c)
 170         uint32_t PMC_IMR;
 171 #define SAM3_PMC_FSMR             (SAM3_PMC_BASE + 0x0070)
 172         uint32_t PMC_FSMR;
 173 #define SAM3_PMC_FSPR             (SAM3_PMC_BASE + 0x0074)
 174         uint32_t PMC_FSPR;
 175 };
 176
 177 /*
 178  * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
 179  * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
 180  * the flash wait state (FWS) should be set to 6. It seems like that the
 181  * cause of the problem is not the flash itself, but the flash write
 182  * buffer. Ie the wait states have to be set before writing into the
 183  * buffer.
 184  * Tested and confirmed with SAM3N and SAM3U
 185  */
 186
 187 struct sam3_bank_private {
 188         int probed;
 189         /* DANGER: THERE ARE DRAGONS HERE.. */
 190         /* NOTE: If you add more 'ghost' pointers */
 191         /* be aware that you must *manually* update */
 192         /* these pointers in the function sam3_GetDetails() */
 193         /* See the comment "Here there be dragons" */
 194
 195         /* so we can find the chip we belong to */
 196         struct sam3_chip *pChip;
 197         /* so we can find the orginal bank pointer */
 198         struct flash_bank *pBank;
 199         unsigned bank_number;
 200         uint32_t controller_address;
 201         uint32_t base_address;
 202         uint32_t flash_wait_states;
 203         bool present;
 204         unsigned size_bytes;
 205         unsigned nsectors;
 206         unsigned sector_size;
 207         unsigned page_size;
 208 };
 209
 210 struct sam3_chip_details {
 211         /* THERE ARE DRAGONS HERE.. */
 212         /* note: If you add pointers here */
 213         /* becareful about them as they */
 214         /* may need to be updated inside */
 215         /* the function: "sam3_GetDetails() */
 216         /* which copy/overwrites the */
 217         /* 'runtime' copy of this structure */
 218         uint32_t chipid_cidr;
 219         const char *name;
 220
 221         unsigned n_gpnvms;
 222 #define SAM3_N_NVM_BITS 3
 223         unsigned gpnvm[SAM3_N_NVM_BITS];
 224         unsigned total_flash_size;
 225         unsigned total_sram_size;
 226         unsigned n_banks;
 227 #define SAM3_MAX_FLASH_BANKS 2
 228         /* these are "initialized" from the global const data */
 229         struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
 230 };
 231
 232 struct sam3_chip {
 233         struct sam3_chip *next;
 234         int probed;
 235
 236         /* this is "initialized" from the global const structure */
 237         struct sam3_chip_details details;
 238         struct target *target;
 239         struct sam3_cfg cfg;
 240 };
 241
 242
 243 struct sam3_reg_list {
 244         uint32_t address;  size_t struct_offset; const char *name;
 245         void (*explain_func)(struct sam3_chip *pInfo);
 246 };
 247
 248 static struct sam3_chip *all_sam3_chips;
 249
 250 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
 251 {
 252         struct target *t;
 253         static struct sam3_chip *p;
 254
 255         t = get_current_target(cmd_ctx);
 256         if (!t) {
 257                 command_print(cmd_ctx, "No current target?");
 258                 return NULL;
 259         }
 260
 261         p = all_sam3_chips;
 262         if (!p) {
 263                 /* this should not happen */
 264                 /* the command is not registered until the chip is created? */
 265                 command_print(cmd_ctx, "No SAM3 chips exist?");
 266                 return NULL;
 267         }
 268
 269         while (p) {
 270                 if (p->target == t)
 271                         return p;
 272                 p = p->next;
 273         }
 274         command_print(cmd_ctx, "Cannot find SAM3 chip?");
 275         return NULL;
 276 }
 277
 278 /* these are used to *initialize* the "pChip->details" structure. */
 279 static const struct sam3_chip_details all_sam3_details[] = {
 280         /* Start at91sam3u* series */
 281         {
 282                 .chipid_cidr    = 0x28100960,
 283                 .name           = "at91sam3u4e",
 284                 .total_flash_size     = 256 * 1024,
 285                 .total_sram_size      = 52 * 1024,
 286                 .n_gpnvms       = 3,
 287                 .n_banks        = 2,
 288
 289                 /* System boots at address 0x0 */
 290                 /* gpnvm[1] = selects boot code */
 291                 /*     if gpnvm[1] == 0 */
 292                 /*         boot is via "SAMBA" (rom) */
 293                 /*     else */
 294                 /*         boot is via FLASH */
 295                 /*         Selection is via gpnvm[2] */
 296                 /*     endif */
 297                 /*  */
 298                 /* NOTE: banks 0 & 1 switch places */
 299                 /*     if gpnvm[2] == 0 */
 300                 /*         Bank0 is the boot rom */
 301                 /*      else */
 302                 /*         Bank1 is the boot rom */
 303                 /*      endif */
 304 /*              .bank[0] = { */
 305                 {
 306                         {
 307                                 .probed = 0,
 308                                 .pChip  = NULL,
 309                                 .pBank  = NULL,
 310                                 .bank_number = 0,
 311                                 .base_address = FLASH_BANK0_BASE_U,
 312                                 .controller_address = 0x400e0800,
 313                                 .flash_wait_states = 6, /* workaround silicon bug */
 314                                 .present = 1,
 315                                 .size_bytes = 128 * 1024,
 316                                 .nsectors   = 16,
 317                                 .sector_size = 8192,
 318                                 .page_size   = 256,
 319                         },
 320
 321 /*              .bank[1] = { */
 322                         {
 323                                 .probed = 0,
 324                                 .pChip  = NULL,
 325                                 .pBank  = NULL,
 326                                 .bank_number = 1,
 327                                 .base_address = FLASH_BANK1_BASE_U,
 328                                 .controller_address = 0x400e0a00,
 329                                 .flash_wait_states = 6, /* workaround silicon bug */
 330                                 .present = 1,
 331                                 .size_bytes = 128 * 1024,
 332                                 .nsectors   = 16,
 333                                 .sector_size = 8192,
 334                                 .page_size   = 256,
 335                         },
 336                 },
 337         },
 338
 339         {
 340                 .chipid_cidr    = 0x281a0760,
 341                 .name           = "at91sam3u2e",
 342                 .total_flash_size     = 128 * 1024,
 343                 .total_sram_size      = 36 * 1024,
 344                 .n_gpnvms       = 2,
 345                 .n_banks        = 1,
 346
 347                 /* System boots at address 0x0 */
 348                 /* gpnvm[1] = selects boot code */
 349                 /*     if gpnvm[1] == 0 */
 350                 /*         boot is via "SAMBA" (rom) */
 351                 /*     else */
 352                 /*         boot is via FLASH */
 353                 /*         Selection is via gpnvm[2] */
 354                 /*     endif */
 355 /*              .bank[0] = { */
 356                 {
 357                         {
 358                                 .probed = 0,
 359                                 .pChip  = NULL,
 360                                 .pBank  = NULL,
 361                                 .bank_number = 0,
 362                                 .base_address = FLASH_BANK0_BASE_U,
 363                                 .controller_address = 0x400e0800,
 364                                 .flash_wait_states = 6, /* workaround silicon bug */
 365                                 .present = 1,
 366                                 .size_bytes = 128 * 1024,
 367                                 .nsectors   = 16,
 368                                 .sector_size = 8192,
 369                                 .page_size   = 256,
 370                         },
 371 /*                .bank[1] = { */
 372                         {
 373                                 .present = 0,
 374                                 .probed = 0,
 375                                 .bank_number = 1,
 376                         },
 377                 },
 378         },
 379         {
 380                 .chipid_cidr    = 0x28190560,
 381                 .name           = "at91sam3u1e",
 382                 .total_flash_size     = 64 * 1024,
 383                 .total_sram_size      = 20 * 1024,
 384                 .n_gpnvms       = 2,
 385                 .n_banks        = 1,
 386
 387                 /* System boots at address 0x0 */
 388                 /* gpnvm[1] = selects boot code */
 389                 /*     if gpnvm[1] == 0 */
 390                 /*         boot is via "SAMBA" (rom) */
 391                 /*     else */
 392                 /*         boot is via FLASH */
 393                 /*         Selection is via gpnvm[2] */
 394                 /*     endif */
 395                 /*  */
 396
 397 /*              .bank[0] = { */
 398                 {
 399                         {
 400                                 .probed = 0,
 401                                 .pChip  = NULL,
 402                                 .pBank  = NULL,
 403                                 .bank_number = 0,
 404                                 .base_address = FLASH_BANK0_BASE_U,
 405                                 .controller_address = 0x400e0800,
 406                                 .flash_wait_states = 6, /* workaround silicon bug */
 407                                 .present = 1,
 408                                 .size_bytes = 64 * 1024,
 409                                 .nsectors   = 8,
 410                                 .sector_size = 8192,
 411                                 .page_size   = 256,
 412                         },
 413
 414 /*              .bank[1] = { */
 415                         {
 416                                 .present = 0,
 417                                 .probed = 0,
 418                                 .bank_number = 1,
 419                         },
 420                 },
 421         },
 422
 423         {
 424                 .chipid_cidr    = 0x28000960,
 425                 .name           = "at91sam3u4c",
 426                 .total_flash_size     = 256 * 1024,
 427                 .total_sram_size      = 52 * 1024,
 428                 .n_gpnvms       = 3,
 429                 .n_banks        = 2,
 430
 431                 /* System boots at address 0x0 */
 432                 /* gpnvm[1] = selects boot code */
 433                 /*     if gpnvm[1] == 0 */
 434                 /*         boot is via "SAMBA" (rom) */
 435                 /*     else */
 436                 /*         boot is via FLASH */
 437                 /*         Selection is via gpnvm[2] */
 438                 /*     endif */
 439                 /*  */
 440                 /* NOTE: banks 0 & 1 switch places */
 441                 /*     if gpnvm[2] == 0 */
 442                 /*         Bank0 is the boot rom */
 443                 /*      else */
 444                 /*         Bank1 is the boot rom */
 445                 /*      endif */
 446                 {
 447                         {
 448 /*              .bank[0] = { */
 449                                 .probed = 0,
 450                                 .pChip  = NULL,
 451                                 .pBank  = NULL,
 452                                 .bank_number = 0,
 453                                 .base_address = FLASH_BANK0_BASE_U,
 454                                 .controller_address = 0x400e0800,
 455                                 .flash_wait_states = 6, /* workaround silicon bug */
 456                                 .present = 1,
 457                                 .size_bytes = 128 * 1024,
 458                                 .nsectors   = 16,
 459                                 .sector_size = 8192,
 460                                 .page_size   = 256,
 461                         },
 462 /*              .bank[1] = { */
 463                         {
 464                                 .probed = 0,
 465                                 .pChip  = NULL,
 466                                 .pBank  = NULL,
 467                                 .bank_number = 1,
 468                                 .base_address = FLASH_BANK1_BASE_U,
 469                                 .controller_address = 0x400e0a00,
 470                                 .flash_wait_states = 6, /* workaround silicon bug */
 471                                 .present = 1,
 472                                 .size_bytes = 128 * 1024,
 473                                 .nsectors   = 16,
 474                                 .sector_size = 8192,
 475                                 .page_size   = 256,
 476                         },
 477                 },
 478         },
 479
 480         {
 481                 .chipid_cidr    = 0x280a0760,
 482                 .name           = "at91sam3u2c",
 483                 .total_flash_size     = 128 * 1024,
 484                 .total_sram_size      = 36 * 1024,
 485                 .n_gpnvms       = 2,
 486                 .n_banks        = 1,
 487
 488                 /* System boots at address 0x0 */
 489                 /* gpnvm[1] = selects boot code */
 490                 /*     if gpnvm[1] == 0 */
 491                 /*         boot is via "SAMBA" (rom) */
 492                 /*     else */
 493                 /*         boot is via FLASH */
 494                 /*         Selection is via gpnvm[2] */
 495                 /*     endif */
 496                 {
 497 /*              .bank[0] = { */
 498                         {
 499                                 .probed = 0,
 500                                 .pChip  = NULL,
 501                                 .pBank  = NULL,
 502                                 .bank_number = 0,
 503                                 .base_address = FLASH_BANK0_BASE_U,
 504                                 .controller_address = 0x400e0800,
 505                                 .flash_wait_states = 6, /* workaround silicon bug */
 506                                 .present = 1,
 507                                 .size_bytes = 128 * 1024,
 508                                 .nsectors   = 16,
 509                                 .sector_size = 8192,
 510                                 .page_size   = 256,
 511                         },
 512 /*              .bank[1] = { */
 513                         {
 514                                 .present = 0,
 515                                 .probed = 0,
 516                                 .bank_number = 1,
 517                         },
 518                 },
 519         },
 520         {
 521                 .chipid_cidr    = 0x28090560,
 522                 .name           = "at91sam3u1c",
 523                 .total_flash_size     = 64 * 1024,
 524                 .total_sram_size      = 20 * 1024,
 525                 .n_gpnvms       = 2,
 526                 .n_banks        = 1,
 527
 528                 /* System boots at address 0x0 */
 529                 /* gpnvm[1] = selects boot code */
 530                 /*     if gpnvm[1] == 0 */
 531                 /*         boot is via "SAMBA" (rom) */
 532                 /*     else */
 533                 /*         boot is via FLASH */
 534                 /*         Selection is via gpnvm[2] */
 535                 /*     endif */
 536                 /*  */
 537
 538                 {
 539 /*              .bank[0] = { */
 540                         {
 541                                 .probed = 0,
 542                                 .pChip  = NULL,
 543                                 .pBank  = NULL,
 544                                 .bank_number = 0,
 545                                 .base_address = FLASH_BANK0_BASE_U,
 546                                 .controller_address = 0x400e0800,
 547                                 .flash_wait_states = 6, /* workaround silicon bug */
 548                                 .present = 1,
 549                                 .size_bytes = 64 * 1024,
 550                                 .nsectors   = 8,
 551                                 .sector_size = 8192,
 552                                 .page_size   = 256,
 553                         },
 554 /*              .bank[1] = { */
 555                         {
 556                                 .present = 0,
 557                                 .probed = 0,
 558                                 .bank_number = 1,
 559
 560                         },
 561                 },
 562         },
 563
 564         /* Start at91sam3s* series */
 565
 566         /* Note: The preliminary at91sam3s datasheet says on page 302 */
 567         /* that the flash controller is at address 0x400E0800. */
 568         /* This is _not_ the case, the controller resides at address 0x400e0a0. */
 569         {
 570                 .chipid_cidr    = 0x28A00960,
 571                 .name           = "at91sam3s4c",
 572                 .total_flash_size     = 256 * 1024,
 573                 .total_sram_size      = 48 * 1024,
 574                 .n_gpnvms       = 2,
 575                 .n_banks        = 1,
 576                 {
 577 /*              .bank[0] = { */
 578                         {
 579                                 .probed = 0,
 580                                 .pChip  = NULL,
 581                                 .pBank  = NULL,
 582                                 .bank_number = 0,
 583                                 .base_address = FLASH_BANK_BASE_S,
 584                                 .controller_address = 0x400e0a00,
 585                                 .flash_wait_states = 6, /* workaround silicon bug */
 586                                 .present = 1,
 587                                 .size_bytes = 256 * 1024,
 588                                 .nsectors   = 16,
 589                                 .sector_size = 16384,
 590                                 .page_size   = 256,
 591                         },
 592 /*              .bank[1] = { */
 593                         {
 594                                 .present = 0,
 595                                 .probed = 0,
 596                                 .bank_number = 1,
 597
 598                         },
 599                 },
 600         },
 601
 602         {
 603                 .chipid_cidr    = 0x28900960,
 604                 .name           = "at91sam3s4b",
 605                 .total_flash_size     = 256 * 1024,
 606                 .total_sram_size      = 48 * 1024,
 607                 .n_gpnvms       = 2,
 608                 .n_banks        = 1,
 609                 {
 610 /*              .bank[0] = { */
 611                         {
 612                                 .probed = 0,
 613                                 .pChip  = NULL,
 614                                 .pBank  = NULL,
 615                                 .bank_number = 0,
 616                                 .base_address = FLASH_BANK_BASE_S,
 617                                 .controller_address = 0x400e0a00,
 618                                 .flash_wait_states = 6, /* workaround silicon bug */
 619                                 .present = 1,
 620                                 .size_bytes = 256 * 1024,
 621                                 .nsectors   = 16,
 622                                 .sector_size = 16384,
 623                                 .page_size   = 256,
 624                         },
 625 /*              .bank[1] = { */
 626                         {
 627                                 .present = 0,
 628                                 .probed = 0,
 629                                 .bank_number = 1,
 630
 631                         },
 632                 },
 633         },
 634         {
 635                 .chipid_cidr    = 0x28800960,
 636                 .name           = "at91sam3s4a",
 637                 .total_flash_size     = 256 * 1024,
 638                 .total_sram_size      = 48 * 1024,
 639                 .n_gpnvms       = 2,
 640                 .n_banks        = 1,
 641                 {
 642 /*              .bank[0] = { */
 643                         {
 644                                 .probed = 0,
 645                                 .pChip  = NULL,
 646                                 .pBank  = NULL,
 647                                 .bank_number = 0,
 648                                 .base_address = FLASH_BANK_BASE_S,
 649                                 .controller_address = 0x400e0a00,
 650                                 .flash_wait_states = 6, /* workaround silicon bug */
 651                                 .present = 1,
 652                                 .size_bytes = 256 * 1024,
 653                                 .nsectors   = 16,
 654                                 .sector_size = 16384,
 655                                 .page_size   = 256,
 656                         },
 657 /*              .bank[1] = { */
 658                         {
 659                                 .present = 0,
 660                                 .probed = 0,
 661                                 .bank_number = 1,
 662
 663                         },
 664                 },
 665         },
 666         {
 667                 .chipid_cidr    = 0x28AA0760,
 668                 .name           = "at91sam3s2c",
 669                 .total_flash_size     = 128 * 1024,
 670                 .total_sram_size      = 32 * 1024,
 671                 .n_gpnvms       = 2,
 672                 .n_banks        = 1,
 673                 {
 674 /*              .bank[0] = { */
 675                         {
 676                                 .probed = 0,
 677                                 .pChip  = NULL,
 678                                 .pBank  = NULL,
 679                                 .bank_number = 0,
 680                                 .base_address = FLASH_BANK_BASE_S,
 681                                 .controller_address = 0x400e0a00,
 682                                 .flash_wait_states = 6, /* workaround silicon bug */
 683                                 .present = 1,
 684                                 .size_bytes = 128 * 1024,
 685                                 .nsectors   = 8,
 686                                 .sector_size = 16384,
 687                                 .page_size   = 256,
 688                         },
 689 /*              .bank[1] = { */
 690                         {
 691                                 .present = 0,
 692                                 .probed = 0,
 693                                 .bank_number = 1,
 694
 695                         },
 696                 },
 697         },
 698         {
 699                 .chipid_cidr    = 0x289A0760,
 700                 .name           = "at91sam3s2b",
 701                 .total_flash_size     = 128 * 1024,
 702                 .total_sram_size      = 32 * 1024,
 703                 .n_gpnvms       = 2,
 704                 .n_banks        = 1,
 705                 {
 706 /*              .bank[0] = { */
 707                         {
 708                                 .probed = 0,
 709                                 .pChip  = NULL,
 710                                 .pBank  = NULL,
 711                                 .bank_number = 0,
 712                                 .base_address = FLASH_BANK_BASE_S,
 713                                 .controller_address = 0x400e0a00,
 714                                 .flash_wait_states = 6, /* workaround silicon bug */
 715                                 .present = 1,
 716                                 .size_bytes = 128 * 1024,
 717                                 .nsectors   = 8,
 718                                 .sector_size = 16384,
 719                                 .page_size   = 256,
 720                         },
 721 /*              .bank[1] = { */
 722                         {
 723                                 .present = 0,
 724                                 .probed = 0,
 725                                 .bank_number = 1,
 726
 727                         },
 728                 },
 729         },
 730         {
 731                 .chipid_cidr    = 0x288A0760,
 732                 .name           = "at91sam3s2a",
 733                 .total_flash_size     = 128 * 1024,
 734                 .total_sram_size      = 32 * 1024,
 735                 .n_gpnvms       = 2,
 736                 .n_banks        = 1,
 737                 {
 738 /*              .bank[0] = { */
 739                         {
 740                                 .probed = 0,
 741                                 .pChip  = NULL,
 742                                 .pBank  = NULL,
 743                                 .bank_number = 0,
 744                                 .base_address = FLASH_BANK_BASE_S,
 745                                 .controller_address = 0x400e0a00,
 746                                 .flash_wait_states = 6, /* workaround silicon bug */
 747                                 .present = 1,
 748                                 .size_bytes = 128 * 1024,
 749                                 .nsectors   = 8,
 750                                 .sector_size = 16384,
 751                                 .page_size   = 256,
 752                         },
 753 /*              .bank[1] = { */
 754                         {
 755                                 .present = 0,
 756                                 .probed = 0,
 757                                 .bank_number = 1,
 758
 759                         },
 760                 },
 761         },
 762         {
 763                 .chipid_cidr    = 0x28A90560,
 764                 .name           = "at91sam3s1c",
 765                 .total_flash_size     = 64 * 1024,
 766                 .total_sram_size      = 16 * 1024,
 767                 .n_gpnvms       = 2,
 768                 .n_banks        = 1,
 769                 {
 770 /*              .bank[0] = { */
 771                         {
 772                                 .probed = 0,
 773                                 .pChip  = NULL,
 774                                 .pBank  = NULL,
 775                                 .bank_number = 0,
 776                                 .base_address = FLASH_BANK_BASE_S,
 777                                 .controller_address = 0x400e0a00,
 778                                 .flash_wait_states = 6, /* workaround silicon bug */
 779                                 .present = 1,
 780                                 .size_bytes = 64 * 1024,
 781                                 .nsectors   = 4,
 782                                 .sector_size = 16384,
 783                                 .page_size   = 256,
 784                         },
 785 /*              .bank[1] = { */
 786                         {
 787                                 .present = 0,
 788                                 .probed = 0,
 789                                 .bank_number = 1,
 790
 791                         },
 792                 },
 793         },
 794         {
 795                 .chipid_cidr    = 0x28990560,
 796                 .name           = "at91sam3s1b",
 797                 .total_flash_size     = 64 * 1024,
 798                 .total_sram_size      = 16 * 1024,
 799                 .n_gpnvms       = 2,
 800                 .n_banks        = 1,
 801                 {
 802 /*              .bank[0] = { */
 803                         {
 804                                 .probed = 0,
 805                                 .pChip  = NULL,
 806                                 .pBank  = NULL,
 807                                 .bank_number = 0,
 808                                 .base_address = FLASH_BANK_BASE_S,
 809                                 .controller_address = 0x400e0a00,
 810                                 .flash_wait_states = 6, /* workaround silicon bug */
 811                                 .present = 1,
 812                                 .size_bytes = 64 * 1024,
 813                                 .nsectors   = 4,
 814                                 .sector_size = 16384,
 815                                 .page_size   = 256,
 816                         },
 817 /*              .bank[1] = { */
 818                         {
 819                                 .present = 0,
 820                                 .probed = 0,
 821                                 .bank_number = 1,
 822
 823                         },
 824                 },
 825         },
 826         {
 827                 .chipid_cidr    = 0x28890560,
 828                 .name           = "at91sam3s1a",
 829                 .total_flash_size     = 64 * 1024,
 830                 .total_sram_size      = 16 * 1024,
 831                 .n_gpnvms       = 2,
 832                 .n_banks        = 1,
 833                 {
 834 /*              .bank[0] = { */
 835                         {
 836                                 .probed = 0,
 837                                 .pChip  = NULL,
 838                                 .pBank  = NULL,
 839                                 .bank_number = 0,
 840                                 .base_address = FLASH_BANK_BASE_S,
 841                                 .controller_address = 0x400e0a00,
 842                                 .flash_wait_states = 6, /* workaround silicon bug */
 843                                 .present = 1,
 844                                 .size_bytes = 64 * 1024,
 845                                 .nsectors   = 4,
 846                                 .sector_size = 16384,
 847                                 .page_size   = 256,
 848                         },
 849 /*              .bank[1] = { */
 850                         {
 851                                 .present = 0,
 852                                 .probed = 0,
 853                                 .bank_number = 1,
 854
 855                         },
 856                 },
 857         },
 858
 859         /* Start at91sam3n* series */
 860         {
 861                 .chipid_cidr    = 0x29540960,
 862                 .name           = "at91sam3n4c",
 863                 .total_flash_size     = 256 * 1024,
 864                 .total_sram_size      = 24 * 1024,
 865                 .n_gpnvms       = 3,
 866                 .n_banks        = 1,
 867
 868                 /* System boots at address 0x0 */
 869                 /* gpnvm[1] = selects boot code */
 870                 /*     if gpnvm[1] == 0 */
 871                 /*         boot is via "SAMBA" (rom) */
 872                 /*     else */
 873                 /*         boot is via FLASH */
 874                 /*         Selection is via gpnvm[2] */
 875                 /*     endif */
 876                 /*  */
 877                 /* NOTE: banks 0 & 1 switch places */
 878                 /*     if gpnvm[2] == 0 */
 879                 /*         Bank0 is the boot rom */
 880                 /*      else */
 881                 /*         Bank1 is the boot rom */
 882                 /*      endif */
 883 /*              .bank[0] = { */
 884                 {
 885                         {
 886                                 .probed = 0,
 887                                 .pChip  = NULL,
 888                                 .pBank  = NULL,
 889                                 .bank_number = 0,
 890                                 .base_address = FLASH_BANK_BASE_N,
 891                                 .controller_address = 0x400e0A00,
 892                                 .flash_wait_states = 6, /* workaround silicon bug */
 893                                 .present = 1,
 894                                 .size_bytes = 256 * 1024,
 895                                 .nsectors   = 16,
 896                                 .sector_size = 16384,
 897                                 .page_size   = 256,
 898                         },
 899
 900 /*              .bank[1] = { */
 901                         {
 902                                 .present = 0,
 903                                 .probed = 0,
 904                                 .bank_number = 1,
 905                         },
 906                 },
 907         },
 908
 909         {
 910                 .chipid_cidr    = 0x29440960,
 911                 .name           = "at91sam3n4b",
 912                 .total_flash_size     = 256 * 1024,
 913                 .total_sram_size      = 24 * 1024,
 914                 .n_gpnvms       = 3,
 915                 .n_banks        = 1,
 916
 917                 /* System boots at address 0x0 */
 918                 /* gpnvm[1] = selects boot code */
 919                 /*     if gpnvm[1] == 0 */
 920                 /*         boot is via "SAMBA" (rom) */
 921                 /*     else */
 922                 /*         boot is via FLASH */
 923                 /*         Selection is via gpnvm[2] */
 924                 /*     endif */
 925                 /*  */
 926                 /* NOTE: banks 0 & 1 switch places */
 927                 /*     if gpnvm[2] == 0 */
 928                 /*         Bank0 is the boot rom */
 929                 /*      else */
 930                 /*         Bank1 is the boot rom */
 931                 /*      endif */
 932 /*              .bank[0] = { */
 933                 {
 934                         {
 935                                 .probed = 0,
 936                                 .pChip  = NULL,
 937                                 .pBank  = NULL,
 938                                 .bank_number = 0,
 939                                 .base_address = FLASH_BANK_BASE_N,
 940                                 .controller_address = 0x400e0A00,
 941                                 .flash_wait_states = 6, /* workaround silicon bug */
 942                                 .present = 1,
 943                                 .size_bytes = 256 * 1024,
 944                                 .nsectors   = 16,
 945                                 .sector_size = 16384,
 946                                 .page_size   = 256,
 947                         },
 948
 949 /*              .bank[1] = { */
 950                         {
 951                                 .present = 0,
 952                                 .probed = 0,
 953                                 .bank_number = 1,
 954                         },
 955                 },
 956         },
 957
 958         {
 959                 .chipid_cidr    = 0x29340960,
 960                 .name           = "at91sam3n4a",
 961                 .total_flash_size     = 256 * 1024,
 962                 .total_sram_size      = 24 * 1024,
 963                 .n_gpnvms       = 3,
 964                 .n_banks        = 1,
 965
 966                 /* System boots at address 0x0 */
 967                 /* gpnvm[1] = selects boot code */
 968                 /*     if gpnvm[1] == 0 */
 969                 /*         boot is via "SAMBA" (rom) */
 970                 /*     else */
 971                 /*         boot is via FLASH */
 972                 /*         Selection is via gpnvm[2] */
 973                 /*     endif */
 974                 /*  */
 975                 /* NOTE: banks 0 & 1 switch places */
 976                 /*     if gpnvm[2] == 0 */
 977                 /*         Bank0 is the boot rom */
 978                 /*      else */
 979                 /*         Bank1 is the boot rom */
 980                 /*      endif */
 981 /*              .bank[0] = { */
 982                 {
 983                         {
 984                                 .probed = 0,
 985                                 .pChip  = NULL,
 986                                 .pBank  = NULL,
 987                                 .bank_number = 0,
 988                                 .base_address = FLASH_BANK_BASE_N,
 989                                 .controller_address = 0x400e0A00,
 990                                 .flash_wait_states = 6, /* workaround silicon bug */
 991                                 .present = 1,
 992                                 .size_bytes = 256 * 1024,
 993                                 .nsectors   = 16,
 994                                 .sector_size = 16384,
 995                                 .page_size   = 256,
 996                         },
 997
 998 /*              .bank[1] = { */
 999                         {
1000                                 .present = 0,
1001                                 .probed = 0,
1002                                 .bank_number = 1,
1003                         },
1004                 },
1005         },
1006
1007         {
1008                 .chipid_cidr    = 0x29590760,
1009                 .name           = "at91sam3n2c",
1010                 .total_flash_size     = 128 * 1024,
1011                 .total_sram_size      = 16 * 1024,
1012                 .n_gpnvms       = 3,
1013                 .n_banks        = 1,
1014
1015                 /* System boots at address 0x0 */
1016                 /* gpnvm[1] = selects boot code */
1017                 /*     if gpnvm[1] == 0 */
1018                 /*         boot is via "SAMBA" (rom) */
1019                 /*     else */
1020                 /*         boot is via FLASH */
1021                 /*         Selection is via gpnvm[2] */
1022                 /*     endif */
1023                 /*  */
1024                 /* NOTE: banks 0 & 1 switch places */
1025                 /*     if gpnvm[2] == 0 */
1026                 /*         Bank0 is the boot rom */
1027                 /*      else */
1028                 /*         Bank1 is the boot rom */
1029                 /*      endif */
1030 /*              .bank[0] = { */
1031                 {
1032                         {
1033                                 .probed = 0,
1034                                 .pChip  = NULL,
1035                                 .pBank  = NULL,
1036                                 .bank_number = 0,
1037                                 .base_address = FLASH_BANK_BASE_N,
1038                                 .controller_address = 0x400e0A00,
1039                                 .flash_wait_states = 6, /* workaround silicon bug */
1040                                 .present = 1,
1041                                 .size_bytes = 128 * 1024,
1042                                 .nsectors   = 8,
1043                                 .sector_size = 16384,
1044                                 .page_size   = 256,
1045                         },
1046
1047 /*              .bank[1] = { */
1048                         {
1049                                 .present = 0,
1050                                 .probed = 0,
1051                                 .bank_number = 1,
1052                         },
1053                 },
1054         },
1055
1056         {
1057                 .chipid_cidr    = 0x29490760,
1058                 .name           = "at91sam3n2b",
1059                 .total_flash_size     = 128 * 1024,
1060                 .total_sram_size      = 16 * 1024,
1061                 .n_gpnvms       = 3,
1062                 .n_banks        = 1,
1063
1064                 /* System boots at address 0x0 */
1065                 /* gpnvm[1] = selects boot code */
1066                 /*     if gpnvm[1] == 0 */
1067                 /*         boot is via "SAMBA" (rom) */
1068                 /*     else */
1069                 /*         boot is via FLASH */
1070                 /*         Selection is via gpnvm[2] */
1071                 /*     endif */
1072                 /*  */
1073                 /* NOTE: banks 0 & 1 switch places */
1074                 /*     if gpnvm[2] == 0 */
1075                 /*         Bank0 is the boot rom */
1076                 /*      else */
1077                 /*         Bank1 is the boot rom */
1078                 /*      endif */
1079 /*              .bank[0] = { */
1080                 {
1081                         {
1082                                 .probed = 0,
1083                                 .pChip  = NULL,
1084                                 .pBank  = NULL,
1085                                 .bank_number = 0,
1086                                 .base_address = FLASH_BANK_BASE_N,
1087                                 .controller_address = 0x400e0A00,
1088                                 .flash_wait_states = 6, /* workaround silicon bug */
1089                                 .present = 1,
1090                                 .size_bytes = 128 * 1024,
1091                                 .nsectors   = 8,
1092                                 .sector_size = 16384,
1093                                 .page_size   = 256,
1094                         },
1095
1096 /*              .bank[1] = { */
1097                         {
1098                                 .present = 0,
1099                                 .probed = 0,
1100                                 .bank_number = 1,
1101                         },
1102                 },
1103         },
1104
1105         {
1106                 .chipid_cidr    = 0x29390760,
1107                 .name           = "at91sam3n2a",
1108                 .total_flash_size     = 128 * 1024,
1109                 .total_sram_size      = 16 * 1024,
1110                 .n_gpnvms       = 3,
1111                 .n_banks        = 1,
1112
1113                 /* System boots at address 0x0 */
1114                 /* gpnvm[1] = selects boot code */
1115                 /*     if gpnvm[1] == 0 */
1116                 /*         boot is via "SAMBA" (rom) */
1117                 /*     else */
1118                 /*         boot is via FLASH */
1119                 /*         Selection is via gpnvm[2] */
1120                 /*     endif */
1121                 /*  */
1122                 /* NOTE: banks 0 & 1 switch places */
1123                 /*     if gpnvm[2] == 0 */
1124                 /*         Bank0 is the boot rom */
1125                 /*      else */
1126                 /*         Bank1 is the boot rom */
1127                 /*      endif */
1128 /*              .bank[0] = { */
1129                 {
1130                         {
1131                                 .probed = 0,
1132                                 .pChip  = NULL,
1133                                 .pBank  = NULL,
1134                                 .bank_number = 0,
1135                                 .base_address = FLASH_BANK_BASE_N,
1136                                 .controller_address = 0x400e0A00,
1137                                 .flash_wait_states = 6, /* workaround silicon bug */
1138                                 .present = 1,
1139                                 .size_bytes = 128 * 1024,
1140                                 .nsectors   = 8,
1141                                 .sector_size = 16384,
1142                                 .page_size   = 256,
1143                         },
1144
1145 /*              .bank[1] = { */
1146                         {
1147                                 .present = 0,
1148                                 .probed = 0,
1149                                 .bank_number = 1,
1150                         },
1151                 },
1152         },
1153
1154         {
1155                 .chipid_cidr    = 0x29580560,
1156                 .name           = "at91sam3n1c",
1157                 .total_flash_size     = 64 * 1024,
1158                 .total_sram_size      = 8 * 1024,
1159                 .n_gpnvms       = 3,
1160                 .n_banks        = 1,
1161
1162                 /* System boots at address 0x0 */
1163                 /* gpnvm[1] = selects boot code */
1164                 /*     if gpnvm[1] == 0 */
1165                 /*         boot is via "SAMBA" (rom) */
1166                 /*     else */
1167                 /*         boot is via FLASH */
1168                 /*         Selection is via gpnvm[2] */
1169                 /*     endif */
1170                 /*  */
1171                 /* NOTE: banks 0 & 1 switch places */
1172                 /*     if gpnvm[2] == 0 */
1173                 /*         Bank0 is the boot rom */
1174                 /*      else */
1175                 /*         Bank1 is the boot rom */
1176                 /*      endif */
1177 /*              .bank[0] = { */
1178                 {
1179                         {
1180                                 .probed = 0,
1181                                 .pChip  = NULL,
1182                                 .pBank  = NULL,
1183                                 .bank_number = 0,
1184                                 .base_address = FLASH_BANK_BASE_N,
1185                                 .controller_address = 0x400e0A00,
1186                                 .flash_wait_states = 6, /* workaround silicon bug */
1187                                 .present = 1,
1188                                 .size_bytes = 64 * 1024,
1189                                 .nsectors   = 4,
1190                                 .sector_size = 16384,
1191                                 .page_size   = 256,
1192                         },
1193
1194 /*              .bank[1] = { */
1195                         {
1196                                 .present = 0,
1197                                 .probed = 0,
1198                                 .bank_number = 1,
1199                         },
1200                 },
1201         },
1202
1203         {
1204                 .chipid_cidr    = 0x29480560,
1205                 .name           = "at91sam3n1b",
1206                 .total_flash_size     = 64 * 1024,
1207                 .total_sram_size      = 8 * 1024,
1208                 .n_gpnvms       = 3,
1209                 .n_banks        = 1,
1210
1211                 /* System boots at address 0x0 */
1212                 /* gpnvm[1] = selects boot code */
1213                 /*     if gpnvm[1] == 0 */
1214                 /*         boot is via "SAMBA" (rom) */
1215                 /*     else */
1216                 /*         boot is via FLASH */
1217                 /*         Selection is via gpnvm[2] */
1218                 /*     endif */
1219                 /*  */
1220                 /* NOTE: banks 0 & 1 switch places */
1221                 /*     if gpnvm[2] == 0 */
1222                 /*         Bank0 is the boot rom */
1223                 /*      else */
1224                 /*         Bank1 is the boot rom */
1225                 /*      endif */
1226 /*              .bank[0] = { */
1227                 {
1228                         {
1229                                 .probed = 0,
1230                                 .pChip  = NULL,
1231                                 .pBank  = NULL,
1232                                 .bank_number = 0,
1233                                 .base_address = FLASH_BANK_BASE_N,
1234                                 .controller_address = 0x400e0A00,
1235                                 .flash_wait_states = 6, /* workaround silicon bug */
1236                                 .present = 1,
1237                                 .size_bytes = 64 * 1024,
1238                                 .nsectors   = 4,
1239                                 .sector_size = 16384,
1240                                 .page_size   = 256,
1241                         },
1242
1243 /*              .bank[1] = { */
1244                         {
1245                                 .present = 0,
1246                                 .probed = 0,
1247                                 .bank_number = 1,
1248                         },
1249                 },
1250         },
1251
1252         {
1253                 .chipid_cidr    = 0x29380560,
1254                 .name           = "at91sam3n1a",
1255                 .total_flash_size     = 64 * 1024,
1256                 .total_sram_size      = 8 * 1024,
1257                 .n_gpnvms       = 3,
1258                 .n_banks        = 1,
1259
1260                 /* System boots at address 0x0 */
1261                 /* gpnvm[1] = selects boot code */
1262                 /*     if gpnvm[1] == 0 */
1263                 /*         boot is via "SAMBA" (rom) */
1264                 /*     else */
1265                 /*         boot is via FLASH */
1266                 /*         Selection is via gpnvm[2] */
1267                 /*     endif */
1268                 /*  */
1269                 /* NOTE: banks 0 & 1 switch places */
1270                 /*     if gpnvm[2] == 0 */
1271                 /*         Bank0 is the boot rom */
1272                 /*      else */
1273                 /*         Bank1 is the boot rom */
1274                 /*      endif */
1275 /*              .bank[0] = { */
1276                 {
1277                         {
1278                                 .probed = 0,
1279                                 .pChip  = NULL,
1280                                 .pBank  = NULL,
1281                                 .bank_number = 0,
1282                                 .base_address = FLASH_BANK_BASE_N,
1283                                 .controller_address = 0x400e0A00,
1284                                 .flash_wait_states = 6, /* workaround silicon bug */
1285                                 .present = 1,
1286                                 .size_bytes = 64 * 1024,
1287                                 .nsectors   = 4,
1288                                 .sector_size = 16384,
1289                                 .page_size   = 256,
1290                         },
1291
1292 /*              .bank[1] = { */
1293                         {
1294                                 .present = 0,
1295                                 .probed = 0,
1296                                 .bank_number = 1,
1297                         },
1298                 },
1299         },
1300
1301         /* Start at91sam3a series*/
1302         /* System boots at address 0x0 */
1303         /* gpnvm[1] = selects boot code */
1304         /*     if gpnvm[1] == 0 */
1305         /*         boot is via "SAMBA" (rom) */
1306         /*     else */
1307         /*         boot is via FLASH */
1308         /*         Selection is via gpnvm[2] */
1309         /*     endif */
1310         /*  */
1311         /* NOTE: banks 0 & 1 switch places */
1312         /*     if gpnvm[2] == 0 */
1313         /*         Bank0 is the boot rom */
1314         /*      else */
1315         /*         Bank1 is the boot rom */
1316         /*      endif */
1317
1318         {
1319                 .chipid_cidr    = 0x283E0A60,
1320                 .name           = "at91sam3a8c",
1321                 .total_flash_size     = 512 * 1024,
1322                 .total_sram_size      = 96 * 1024,
1323                 .n_gpnvms       = 3,
1324                 .n_banks        = 2,
1325                 {
1326 /*              .bank[0] = { */
1327                   {
1328                         .probed = 0,
1329                         .pChip  = NULL,
1330                         .pBank  = NULL,
1331                         .bank_number = 0,
1332                         .base_address = FLASH_BANK0_BASE_AX,
1333                         .controller_address = 0x400e0a00,
1334                         .flash_wait_states = 6, /* workaround silicon bug */
1335                         .present = 1,
1336                         .size_bytes =  256 * 1024,
1337                         .nsectors   =  16,
1338                         .sector_size = 16384,
1339                         .page_size   = 256,
1340                   },
1341 /*              .bank[1] = { */
1342                   {
1343                         .probed = 0,
1344                         .pChip  = NULL,
1345                         .pBank  = NULL,
1346                         .bank_number = 1,
1347                         .base_address = FLASH_BANK1_BASE_512K_AX,
1348                         .controller_address = 0x400e0c00,
1349                         .flash_wait_states = 6, /* workaround silicon bug */
1350                         .present = 1,
1351                         .size_bytes =  256 * 1024,
1352                         .nsectors   =  16,
1353                         .sector_size = 16384,
1354                         .page_size   = 256,
1355
1356                   },
1357                 },
1358         },
1359         {
1360                 .chipid_cidr    = 0x283B0960,
1361                 .name           = "at91sam3a4c",
1362                 .total_flash_size     = 256 * 1024,
1363                 .total_sram_size      = 64 * 1024,
1364                 .n_gpnvms       = 3,
1365                 .n_banks        = 2,
1366                 {
1367 /*              .bank[0] = { */
1368                   {
1369                         .probed = 0,
1370                         .pChip  = NULL,
1371                         .pBank  = NULL,
1372                         .bank_number = 0,
1373                         .base_address = FLASH_BANK0_BASE_AX,
1374                         .controller_address = 0x400e0a00,
1375                         .flash_wait_states = 6, /* workaround silicon bug */
1376                         .present = 1,
1377                         .size_bytes =  128 * 1024,
1378                         .nsectors   =  8,
1379                         .sector_size = 16384,
1380                         .page_size   = 256,
1381                   },
1382 /*              .bank[1] = { */
1383                   {
1384                         .probed = 0,
1385                         .pChip  = NULL,
1386                         .pBank  = NULL,
1387                         .bank_number = 1,
1388                         .base_address = FLASH_BANK1_BASE_256K_AX,
1389                         .controller_address = 0x400e0c00,
1390                         .flash_wait_states = 6, /* workaround silicon bug */
1391                         .present = 1,
1392                         .size_bytes =  128 * 1024,
1393                         .nsectors   =  8,
1394                         .sector_size = 16384,
1395                         .page_size   = 256,
1396
1397                   },
1398                 },
1399         },
1400
1401         /* Start at91sam3x* series */
1402         /* System boots at address 0x0 */
1403         /* gpnvm[1] = selects boot code */
1404         /*     if gpnvm[1] == 0 */
1405         /*         boot is via "SAMBA" (rom) */
1406         /*     else */
1407         /*         boot is via FLASH */
1408         /*         Selection is via gpnvm[2] */
1409         /*     endif */
1410         /*  */
1411         /* NOTE: banks 0 & 1 switch places */
1412         /*     if gpnvm[2] == 0 */
1413         /*         Bank0 is the boot rom */
1414         /*      else */
1415         /*         Bank1 is the boot rom */
1416         /*      endif */
1417         /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1418         {
1419                 .chipid_cidr    = 0x286E0A20,
1420                 .name           = "at91sam3x8h - ES",
1421                 .total_flash_size     = 512 * 1024,
1422                 .total_sram_size      = 96 * 1024,
1423                 .n_gpnvms       = 3,
1424                 .n_banks        = 2,
1425                 {
1426 /*              .bank[0] = { */
1427                   {
1428                         .probed = 0,
1429                         .pChip  = NULL,
1430                         .pBank  = NULL,
1431                         .bank_number = 0,
1432                         .base_address = FLASH_BANK0_BASE_AX,
1433                         .controller_address = 0x400e0a00,
1434                         .flash_wait_states = 6, /* workaround silicon bug */
1435                         .present = 1,
1436                         .size_bytes =  256 * 1024,
1437                         .nsectors   =  16,
1438                         .sector_size = 16384,
1439                         .page_size   = 256,
1440                   },
1441 /*              .bank[1] = { */
1442                   {
1443                         .probed = 0,
1444                         .pChip  = NULL,
1445                         .pBank  = NULL,
1446                         .bank_number = 1,
1447                         .base_address = FLASH_BANK1_BASE_512K_AX,
1448                         .controller_address = 0x400e0c00,
1449                         .flash_wait_states = 6, /* workaround silicon bug */
1450                         .present = 1,
1451                         .size_bytes =  256 * 1024,
1452                         .nsectors   =  16,
1453                         .sector_size = 16384,
1454                         .page_size   = 256,
1455
1456                   },
1457                 },
1458         },
1459         /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1460         {
1461                 .chipid_cidr    = 0x286E0A60,
1462                 .name           = "at91sam3x8h",
1463                 .total_flash_size     = 512 * 1024,
1464                 .total_sram_size      = 96 * 1024,
1465                 .n_gpnvms       = 3,
1466                 .n_banks        = 2,
1467                 {
1468 /*              .bank[0] = { */
1469                   {
1470                         .probed = 0,
1471                         .pChip  = NULL,
1472                         .pBank  = NULL,
1473                         .bank_number = 0,
1474                         .base_address = FLASH_BANK0_BASE_AX,
1475                         .controller_address = 0x400e0a00,
1476                         .flash_wait_states = 6, /* workaround silicon bug */
1477                         .present = 1,
1478                         .size_bytes =  256 * 1024,
1479                         .nsectors   =  16,
1480                         .sector_size = 16384,
1481                         .page_size   = 256,
1482                   },
1483 /*              .bank[1] = { */
1484                   {
1485                         .probed = 0,
1486                         .pChip  = NULL,
1487                         .pBank  = NULL,
1488                         .bank_number = 1,
1489                         .base_address = FLASH_BANK1_BASE_512K_AX,
1490                         .controller_address = 0x400e0c00,
1491                         .flash_wait_states = 6, /* workaround silicon bug */
1492                         .present = 1,
1493                         .size_bytes =  256 * 1024,
1494                         .nsectors   =  16,
1495                         .sector_size = 16384,
1496                         .page_size   = 256,
1497
1498                   },
1499                 },
1500         },
1501         {
1502                 .chipid_cidr    = 0x285E0A60,
1503                 .name           = "at91sam3x8e",
1504                 .total_flash_size     = 512 * 1024,
1505                 .total_sram_size      = 96 * 1024,
1506                 .n_gpnvms       = 3,
1507                 .n_banks        = 2,
1508                 {
1509 /*              .bank[0] = { */
1510                   {
1511                         .probed = 0,
1512                         .pChip  = NULL,
1513                         .pBank  = NULL,
1514                         .bank_number = 0,
1515                         .base_address = FLASH_BANK0_BASE_AX,
1516                         .controller_address = 0x400e0a00,
1517                         .flash_wait_states = 6, /* workaround silicon bug */
1518                         .present = 1,
1519                         .size_bytes =  256 * 1024,
1520                         .nsectors   =  16,
1521                         .sector_size = 16384,
1522                         .page_size   = 256,
1523                   },
1524 /*              .bank[1] = { */
1525                   {
1526                         .probed = 0,
1527                         .pChip  = NULL,
1528                         .pBank  = NULL,
1529                         .bank_number = 1,
1530                         .base_address = FLASH_BANK1_BASE_512K_AX,
1531                         .controller_address = 0x400e0c00,
1532                         .flash_wait_states = 6, /* workaround silicon bug */
1533                         .present = 1,
1534                         .size_bytes =  256 * 1024,
1535                         .nsectors   =  16,
1536                         .sector_size = 16384,
1537                         .page_size   = 256,
1538
1539                   },
1540                 },
1541         },
1542         {
1543                 .chipid_cidr    = 0x284E0A60,
1544                 .name           = "at91sam3x8c",
1545                 .total_flash_size     = 512 * 1024,
1546                 .total_sram_size      = 96 * 1024,
1547                 .n_gpnvms       = 3,
1548                 .n_banks        = 2,
1549                 {
1550 /*              .bank[0] = { */
1551                   {
1552                         .probed = 0,
1553                         .pChip  = NULL,
1554                         .pBank  = NULL,
1555                         .bank_number = 0,
1556                         .base_address = FLASH_BANK0_BASE_AX,
1557                         .controller_address = 0x400e0a00,
1558                         .flash_wait_states = 6, /* workaround silicon bug */
1559                         .present = 1,
1560                         .size_bytes =  256 * 1024,
1561                         .nsectors   =  16,
1562                         .sector_size = 16384,
1563                         .page_size   = 256,
1564                   },
1565 /*              .bank[1] = { */
1566                   {
1567                         .probed = 0,
1568                         .pChip  = NULL,
1569                         .pBank  = NULL,
1570                         .bank_number = 1,
1571                         .base_address = FLASH_BANK1_BASE_512K_AX ,
1572                         .controller_address = 0x400e0c00,
1573                         .flash_wait_states = 6, /* workaround silicon bug */
1574                         .present = 1,
1575                         .size_bytes =  256 * 1024,
1576                         .nsectors   =  16,
1577                         .sector_size = 16384,
1578                         .page_size   = 256,
1579
1580                   },
1581                 },
1582         },
1583         {
1584                 .chipid_cidr    = 0x285B0960,
1585                 .name           = "at91sam3x4e",
1586                 .total_flash_size     = 256 * 1024,
1587                 .total_sram_size      = 64 * 1024,
1588                 .n_gpnvms       = 3,
1589                 .n_banks        = 2,
1590                 {
1591 /*              .bank[0] = { */
1592                   {
1593                         .probed = 0,
1594                         .pChip  = NULL,
1595                         .pBank  = NULL,
1596                         .bank_number = 0,
1597                         .base_address = FLASH_BANK0_BASE_AX,
1598                         .controller_address = 0x400e0a00,
1599                         .flash_wait_states = 6, /* workaround silicon bug */
1600                         .present = 1,
1601                         .size_bytes =  128 * 1024,
1602                         .nsectors   =  8,
1603                         .sector_size = 16384,
1604                         .page_size   = 256,
1605                   },
1606 /*              .bank[1] = { */
1607                   {
1608                         .probed = 0,
1609                         .pChip  = NULL,
1610                         .pBank  = NULL,
1611                         .bank_number = 1,
1612                         .base_address = FLASH_BANK1_BASE_256K_AX,
1613                         .controller_address = 0x400e0c00,
1614                         .flash_wait_states = 6, /* workaround silicon bug */
1615                         .present = 1,
1616                         .size_bytes =  128 * 1024,
1617                         .nsectors   =  8,
1618                         .sector_size = 16384,
1619                         .page_size   = 256,
1620
1621                   },
1622                 },
1623         },
1624         {
1625                 .chipid_cidr    = 0x284B0960,
1626                 .name           = "at91sam3x4c",
1627                 .total_flash_size     = 256 * 1024,
1628                 .total_sram_size      = 64 * 1024,
1629                 .n_gpnvms       = 3,
1630                 .n_banks        = 2,
1631                 {
1632 /*              .bank[0] = { */
1633                   {
1634                         .probed = 0,
1635                         .pChip  = NULL,
1636                         .pBank  = NULL,
1637                         .bank_number = 0,
1638                         .base_address = FLASH_BANK0_BASE_AX,
1639                         .controller_address = 0x400e0a00,
1640                         .flash_wait_states = 6, /* workaround silicon bug */
1641                         .present = 1,
1642                         .size_bytes =  128 * 1024,
1643                         .nsectors   =  8,
1644                         .sector_size = 16384,
1645                         .page_size   = 256,
1646                   },
1647 /*              .bank[1] = { */
1648                   {
1649                         .probed = 0,
1650                         .pChip  = NULL,
1651                         .pBank  = NULL,
1652                         .bank_number = 1,
1653                         .base_address = FLASH_BANK1_BASE_256K_AX,
1654                         .controller_address = 0x400e0c00,
1655                         .flash_wait_states = 6, /* workaround silicon bug */
1656                         .present = 1,
1657                         .size_bytes =  128 * 1024,
1658                         .nsectors   =  8,
1659                         .sector_size = 16384,
1660                         .page_size   = 256,
1661
1662                   },
1663                 },
1664         },
1665         /* terminate */
1666         {
1667                 .chipid_cidr    = 0,
1668                 .name                   = NULL,
1669         }
1670 };
1671
1672 /* Globals above */
1673 /***********************************************************************
1674  **********************************************************************
1675  **********************************************************************
1676  **********************************************************************
1677  **********************************************************************
1678  **********************************************************************/
1679 /* *ATMEL* style code - from the SAM3 driver code */
1680
1681 /**
1682  * Get the current status of the EEFC and
1683  * the value of some status bits (LOCKE, PROGE).
1684  * @param pPrivate - info about the bank
1685  * @param v        - result goes here
1686  */
1687 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
1688 {
1689         int r;
1690         r = target_read_u32(pPrivate->pChip->target,
1691                         pPrivate->controller_address + offset_EFC_FSR,
1692                         v);
1693         LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1694                 (unsigned int)(*v),
1695                 ((unsigned int)((*v >> 2) & 1)),
1696                 ((unsigned int)((*v >> 1) & 1)),
1697                 ((unsigned int)((*v >> 0) & 1)));
1698
1699         return r;
1700 }
1701
1702 /**
1703  * Get the result of the last executed command.
1704  * @param pPrivate - info about the bank
1705  * @param v        - result goes here
1706  */
1707 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
1708 {
1709         int r;
1710         uint32_t rv;
1711         r = target_read_u32(pPrivate->pChip->target,
1712                         pPrivate->controller_address + offset_EFC_FRR,
1713                         &rv);
1714         if (v)
1715                 *v = rv;
1716         LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1717         return r;
1718 }
1719
1720 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
1721         unsigned command, unsigned argument)
1722 {
1723         uint32_t n, v;
1724         int r;
1725         int retry;
1726
1727         retry = 0;
1728 do_retry:
1729
1730         /* Check command & argument */
1731         switch (command) {
1732
1733                 case AT91C_EFC_FCMD_WP:
1734                 case AT91C_EFC_FCMD_WPL:
1735                 case AT91C_EFC_FCMD_EWP:
1736                 case AT91C_EFC_FCMD_EWPL:
1737                 /* case AT91C_EFC_FCMD_EPL: */
1738                 /* case AT91C_EFC_FCMD_EPA: */
1739                 case AT91C_EFC_FCMD_SLB:
1740                 case AT91C_EFC_FCMD_CLB:
1741                         n = (pPrivate->size_bytes / pPrivate->page_size);
1742                         if (argument >= n)
1743                                 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1744                         break;
1745
1746                 case AT91C_EFC_FCMD_SFB:
1747                 case AT91C_EFC_FCMD_CFB:
1748                         if (argument >= pPrivate->pChip->details.n_gpnvms) {
1749                                 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1750                                                 pPrivate->pChip->details.n_gpnvms);
1751                         }
1752                         break;
1753
1754                 case AT91C_EFC_FCMD_GETD:
1755                 case AT91C_EFC_FCMD_EA:
1756                 case AT91C_EFC_FCMD_GLB:
1757                 case AT91C_EFC_FCMD_GFB:
1758                 case AT91C_EFC_FCMD_STUI:
1759                 case AT91C_EFC_FCMD_SPUI:
1760                         if (argument != 0)
1761                                 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1762                         break;
1763                 default:
1764                         LOG_ERROR("Unknown command %d", command);
1765                         break;
1766         }
1767
1768         if (command == AT91C_EFC_FCMD_SPUI) {
1769                 /* this is a very special situation. */
1770                 /* Situation (1) - error/retry - see below */
1771                 /*      And we are being called recursively */
1772                 /* Situation (2) - normal, finished reading unique id */
1773         } else {
1774                 /* it should be "ready" */
1775                 EFC_GetStatus(pPrivate, &v);
1776                 if (v & 1) {
1777                         /* then it is ready */
1778                         /* we go on */
1779                 } else {
1780                         if (retry) {
1781                                 /* we have done this before */
1782                                 /* the controller is not responding. */
1783                                 LOG_ERROR("flash controller(%d) is not ready! Error",
1784                                         pPrivate->bank_number);
1785                                 return ERROR_FAIL;
1786                         } else {
1787                                 retry++;
1788                                 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1789                                         pPrivate->bank_number);
1790                                 /* we do that by issuing the *STOP* command */
1791                                 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1792                                 /* above is recursive, and further recursion is blocked by */
1793                                 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1794                                 goto do_retry;
1795                         }
1796                 }
1797         }
1798
1799         v = (0x5A << 24) | (argument << 8) | command;
1800         LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1801         r = target_write_u32(pPrivate->pBank->target,
1802                         pPrivate->controller_address + offset_EFC_FCR, v);
1803         if (r != ERROR_OK)
1804                 LOG_DEBUG("Error Write failed");
1805         return r;
1806 }
1807
1808 /**
1809  * Performs the given command and wait until its completion (or an error).
1810  * @param pPrivate - info about the bank
1811  * @param command  - Command to perform.
1812  * @param argument - Optional command argument.
1813  * @param status   - put command status bits here
1814  */
1815 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
1816         unsigned command,
1817         unsigned argument,
1818         uint32_t *status)
1819 {
1820
1821         int r;
1822         uint32_t v;
1823         long long ms_now, ms_end;
1824
1825         /* default */
1826         if (status)
1827                 *status = 0;
1828
1829         r = EFC_StartCommand(pPrivate, command, argument);
1830         if (r != ERROR_OK)
1831                 return r;
1832
1833         ms_end = 500 + timeval_ms();
1834
1835         do {
1836                 r = EFC_GetStatus(pPrivate, &v);
1837                 if (r != ERROR_OK)
1838                         return r;
1839                 ms_now = timeval_ms();
1840                 if (ms_now > ms_end) {
1841                         /* error */
1842                         LOG_ERROR("Command timeout");
1843                         return ERROR_FAIL;
1844                 }
1845         } while ((v & 1) == 0);
1846
1847         /* error bits.. */
1848         if (status)
1849                 *status = (v & 0x6);
1850         return ERROR_OK;
1851
1852 }
1853
1854 /**
1855  * Read the unique ID.
1856  * @param pPrivate - info about the bank
1857  * The unique ID is stored in the 'pPrivate' structure.
1858  */
1859 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
1860 {
1861         int r;
1862         uint32_t v;
1863         int x;
1864         /* assume 0 */
1865         pPrivate->pChip->cfg.unique_id[0] = 0;
1866         pPrivate->pChip->cfg.unique_id[1] = 0;
1867         pPrivate->pChip->cfg.unique_id[2] = 0;
1868         pPrivate->pChip->cfg.unique_id[3] = 0;
1869
1870         LOG_DEBUG("Begin");
1871         r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1872         if (r < 0)
1873                 return r;
1874
1875         for (x = 0; x < 4; x++) {
1876                 r = target_read_u32(pPrivate->pChip->target,
1877                                 pPrivate->pBank->base + (x * 4),
1878                                 &v);
1879                 if (r < 0)
1880                         return r;
1881                 pPrivate->pChip->cfg.unique_id[x] = v;
1882         }
1883
1884         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1885         LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1886                 r,
1887                 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1888                 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1889                 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1890                 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1891         return r;
1892
1893 }
1894
1895 /**
1896  * Erases the entire flash.
1897  * @param pPrivate - the info about the bank.
1898  */
1899 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
1900 {
1901         LOG_DEBUG("Here");
1902         return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1903 }
1904
1905 /**
1906  * Gets current GPNVM state.
1907  * @param pPrivate - info about the bank.
1908  * @param gpnvm    -  GPNVM bit index.
1909  * @param puthere  - result stored here.
1910  */
1911 /* ------------------------------------------------------------------------------ */
1912 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1913 {
1914         uint32_t v;
1915         int r;
1916
1917         LOG_DEBUG("Here");
1918         if (pPrivate->bank_number != 0) {
1919                 LOG_ERROR("GPNVM only works with Bank0");
1920                 return ERROR_FAIL;
1921         }
1922
1923         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1924                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1925                         gpnvm, pPrivate->pChip->details.n_gpnvms);
1926                 return ERROR_FAIL;
1927         }
1928
1929         /* Get GPNVMs status */
1930         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1931         if (r != ERROR_OK) {
1932                 LOG_ERROR("Failed");
1933                 return r;
1934         }
1935
1936         r = EFC_GetResult(pPrivate, &v);
1937
1938         if (puthere) {
1939                 /* Check if GPNVM is set */
1940                 /* get the bit and make it a 0/1 */
1941                 *puthere = (v >> gpnvm) & 1;
1942         }
1943
1944         return r;
1945 }
1946
1947 /**
1948  * Clears the selected GPNVM bit.
1949  * @param pPrivate info about the bank
1950  * @param gpnvm GPNVM index.
1951  * @returns 0 if successful; otherwise returns an error code.
1952  */
1953 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1954 {
1955         int r;
1956         unsigned v;
1957
1958         LOG_DEBUG("Here");
1959         if (pPrivate->bank_number != 0) {
1960                 LOG_ERROR("GPNVM only works with Bank0");
1961                 return ERROR_FAIL;
1962         }
1963
1964         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1965                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1966                         gpnvm, pPrivate->pChip->details.n_gpnvms);
1967                 return ERROR_FAIL;
1968         }
1969
1970         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1971         if (r != ERROR_OK) {
1972                 LOG_DEBUG("Failed: %d", r);
1973                 return r;
1974         }
1975         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1976         LOG_DEBUG("End: %d", r);
1977         return r;
1978 }
1979
1980 /**
1981  * Sets the selected GPNVM bit.
1982  * @param pPrivate info about the bank
1983  * @param gpnvm GPNVM index.
1984  */
1985 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1986 {
1987         int r;
1988         unsigned v;
1989
1990         if (pPrivate->bank_number != 0) {
1991                 LOG_ERROR("GPNVM only works with Bank0");
1992                 return ERROR_FAIL;
1993         }
1994
1995         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1996                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1997                         gpnvm, pPrivate->pChip->details.n_gpnvms);
1998                 return ERROR_FAIL;
1999         }
2000
2001         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2002         if (r != ERROR_OK)
2003                 return r;
2004         if (v) {
2005                 /* already set */
2006                 r = ERROR_OK;
2007         } else {
2008                 /* set it */
2009                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2010         }
2011         return r;
2012 }
2013
2014 /**
2015  * Returns a bit field (at most 64) of locked regions within a page.
2016  * @param pPrivate info about the bank
2017  * @param v where to store locked bits
2018  */
2019 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
2020 {
2021         int r;
2022         LOG_DEBUG("Here");
2023         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
2024         if (r == ERROR_OK)
2025                 r = EFC_GetResult(pPrivate, v);
2026         LOG_DEBUG("End: %d", r);
2027         return r;
2028 }
2029
2030 /**
2031  * Unlocks all the regions in the given address range.
2032  * @param pPrivate info about the bank
2033  * @param start_sector first sector to unlock
2034  * @param end_sector last (inclusive) to unlock
2035  */
2036
2037 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
2038         unsigned start_sector,
2039         unsigned end_sector)
2040 {
2041         int r;
2042         uint32_t status;
2043         uint32_t pg;
2044         uint32_t pages_per_sector;
2045
2046         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2047
2048         /* Unlock all pages */
2049         while (start_sector <= end_sector) {
2050                 pg = start_sector * pages_per_sector;
2051
2052                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
2053                 if (r != ERROR_OK)
2054                         return r;
2055                 start_sector++;
2056         }
2057
2058         return ERROR_OK;
2059 }
2060
2061 /**
2062  * Locks regions
2063  * @param pPrivate - info about the bank
2064  * @param start_sector - first sector to lock
2065  * @param end_sector   - last sector (inclusive) to lock
2066  */
2067 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
2068         unsigned start_sector,
2069         unsigned end_sector)
2070 {
2071         uint32_t status;
2072         uint32_t pg;
2073         uint32_t pages_per_sector;
2074         int r;
2075
2076         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2077
2078         /* Lock all pages */
2079         while (start_sector <= end_sector) {
2080                 pg = start_sector * pages_per_sector;
2081
2082                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
2083                 if (r != ERROR_OK)
2084                         return r;
2085                 start_sector++;
2086         }
2087         return ERROR_OK;
2088 }
2089
2090 /****** END SAM3 CODE ********/
2091
2092 /* begin helpful debug code */
2093 /* print the fieldname, the field value, in dec & hex, and return field value */
2094 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
2095         const char *regname,
2096         uint32_t value,
2097         unsigned shift,
2098         unsigned width)
2099 {
2100         uint32_t v;
2101         int hwidth, dwidth;
2102
2103
2104         /* extract the field */
2105         v = value >> shift;
2106         v = v & ((1 << width)-1);
2107         if (width <= 16) {
2108                 hwidth = 4;
2109                 dwidth = 5;
2110         } else {
2111                 hwidth = 8;
2112                 dwidth = 12;
2113         }
2114
2115         /* show the basics */
2116         LOG_USER_N("\t%*s: %*d [0x%0*x] ",
2117                 REG_NAME_WIDTH, regname,
2118                 dwidth, v,
2119                 hwidth, v);
2120         return v;
2121 }
2122
2123 static const char _unknown[] = "unknown";
2124 static const char *const eproc_names[] = {
2125         _unknown,                                       /* 0 */
2126         "arm946es",                                     /* 1 */
2127         "arm7tdmi",                                     /* 2 */
2128         "cortex-m3",                            /* 3 */
2129         "arm920t",                                      /* 4 */
2130         "arm926ejs",                            /* 5 */
2131         _unknown,                                       /* 6 */
2132         _unknown,                                       /* 7 */
2133         _unknown,                                       /* 8 */
2134         _unknown,                                       /* 9 */
2135         _unknown,                                       /* 10 */
2136         _unknown,                                       /* 11 */
2137         _unknown,                                       /* 12 */
2138         _unknown,                                       /* 13 */
2139         _unknown,                                       /* 14 */
2140         _unknown,                                       /* 15 */
2141 };
2142
2143 #define nvpsize2 nvpsize                /* these two tables are identical */
2144 static const char *const nvpsize[] = {
2145         "none",                                         /*  0 */
2146         "8K bytes",                                     /*  1 */
2147         "16K bytes",                            /*  2 */
2148         "32K bytes",                            /*  3 */
2149         _unknown,                                       /*  4 */
2150         "64K bytes",                            /*  5 */
2151         _unknown,                                       /*  6 */
2152         "128K bytes",                           /*  7 */
2153         _unknown,                                       /*  8 */
2154         "256K bytes",                           /*  9 */
2155         "512K bytes",                           /* 10 */
2156         _unknown,                                       /* 11 */
2157         "1024K bytes",                          /* 12 */
2158         _unknown,                                       /* 13 */
2159         "2048K bytes",                          /* 14 */
2160         _unknown,                                       /* 15 */
2161 };
2162
2163 static const char *const sramsize[] = {
2164         "48K Bytes",                            /*  0 */
2165         "1K Bytes",                                     /*  1 */
2166         "2K Bytes",                                     /*  2 */
2167         "6K Bytes",                                     /*  3 */
2168         "112K Bytes",                           /*  4 */
2169         "4K Bytes",                                     /*  5 */
2170         "80K Bytes",                            /*  6 */
2171         "160K Bytes",                           /*  7 */
2172         "8K Bytes",                                     /*  8 */
2173         "16K Bytes",                            /*  9 */
2174         "32K Bytes",                            /* 10 */
2175         "64K Bytes",                            /* 11 */
2176         "128K Bytes",                           /* 12 */
2177         "256K Bytes",                           /* 13 */
2178         "96K Bytes",                            /* 14 */
2179         "512K Bytes",                           /* 15 */
2180
2181 };
2182
2183 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2184         { 0x19,  "AT91SAM9xx Series"                                            },
2185         { 0x29,  "AT91SAM9XExx Series"                                          },
2186         { 0x34,  "AT91x34 Series"                                                       },
2187         { 0x37,  "CAP7 Series"                                                          },
2188         { 0x39,  "CAP9 Series"                                                          },
2189         { 0x3B,  "CAP11 Series"                                                         },
2190         { 0x40,  "AT91x40 Series"                                                       },
2191         { 0x42,  "AT91x42 Series"                                                       },
2192         { 0x55,  "AT91x55 Series"                                                       },
2193         { 0x60,  "AT91SAM7Axx Series"                                           },
2194         { 0x61,  "AT91SAM7AQxx Series"                                          },
2195         { 0x63,  "AT91x63 Series"                                                       },
2196         { 0x70,  "AT91SAM7Sxx Series"                                           },
2197         { 0x71,  "AT91SAM7XCxx Series"                                          },
2198         { 0x72,  "AT91SAM7SExx Series"                                          },
2199         { 0x73,  "AT91SAM7Lxx Series"                                           },
2200         { 0x75,  "AT91SAM7Xxx Series"                                           },
2201         { 0x76,  "AT91SAM7SLxx Series"                                          },
2202         { 0x80,  "ATSAM3UxC Series (100-pin version)"           },
2203         { 0x81,  "ATSAM3UxE Series (144-pin version)"           },
2204         { 0x83,  "ATSAM3AxC Series (100-pin version)"           },
2205         { 0x84,  "ATSAM3XxC Series (100-pin version)"           },
2206         { 0x85,  "ATSAM3XxE Series (144-pin version)"           },
2207         { 0x86,  "ATSAM3XxG Series (208/217-pin version)"       },
2208         { 0x88,  "ATSAM3SxA Series (48-pin version)"            },
2209         { 0x89,  "ATSAM3SxB Series (64-pin version)"            },
2210         { 0x8A,  "ATSAM3SxC Series (100-pin version)"           },
2211         { 0x92,  "AT91x92 Series"                                                       },
2212         { 0x93,  "ATSAM3NxA Series (48-pin version)"            },
2213         { 0x94,  "ATSAM3NxB Series (64-pin version)"            },
2214         { 0x95,  "ATSAM3NxC Series (100-pin version)"           },
2215         { 0x98,  "ATSAM3SDxA Series (48-pin version)"           },
2216         { 0x99,  "ATSAM3SDxB Series (64-pin version)"           },
2217         { 0x9A,  "ATSAM3SDxC Series (100-pin version)"          },
2218         { 0xA5,  "ATSAM5A"                                                              },
2219         { 0xF0,  "AT75Cxx Series"                                                       },
2220         { -1, NULL },
2221 };
2222
2223 static const char *const nvptype[] = {
2224         "rom",  /* 0 */
2225         "romless or onchip flash",      /* 1 */
2226         "embedded flash memory",/* 2 */
2227         "rom(nvpsiz) + embedded flash (nvpsiz2)",       /* 3 */
2228         "sram emulating flash", /* 4 */
2229         _unknown,       /* 5 */
2230         _unknown,       /* 6 */
2231         _unknown,       /* 7 */
2232 };
2233
2234 static const char *_yes_or_no(uint32_t v)
2235 {
2236         if (v)
2237                 return "YES";
2238         else
2239                 return "NO";
2240 }
2241
2242 static const char *const _rc_freq[] = {
2243         "4 MHz", "8 MHz", "12 MHz", "reserved"
2244 };
2245
2246 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
2247 {
2248         uint32_t v;
2249         uint32_t rcen;
2250
2251         v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2252         LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2253         v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2254         LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2255         rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2256         LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2257         v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2258         LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2259
2260         pChip->cfg.rc_freq = 0;
2261         if (rcen) {
2262                 switch (v) {
2263                         default:
2264                                 pChip->cfg.rc_freq = 0;
2265                                 break;
2266                         case 0:
2267                                 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2268                                 break;
2269                         case 1:
2270                                 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2271                                 break;
2272                         case 2:
2273                                 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2274                                 break;
2275                 }
2276         }
2277
2278         v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2279         LOG_USER("(startup clks, time= %f uSecs)",
2280                 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2281         v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2282         LOG_USER("(mainosc source: %s)",
2283                 v ? "external xtal" : "internal RC");
2284
2285         v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2286         LOG_USER("(clock failure enabled: %s)",
2287                 _yes_or_no(v));
2288 }
2289
2290 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
2291 {
2292         int x;
2293         uint32_t v;
2294         const char *cp;
2295
2296         sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2297         LOG_USER_N("\n");
2298
2299         v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2300         LOG_USER("%s", eproc_names[v]);
2301
2302         v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2303         LOG_USER("%s", nvpsize[v]);
2304
2305         v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2306         LOG_USER("%s", nvpsize2[v]);
2307
2308         v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2309         LOG_USER("%s", sramsize[v]);
2310
2311         v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2312         cp = _unknown;
2313         for (x = 0; archnames[x].name; x++) {
2314                 if (v == archnames[x].value) {
2315                         cp = archnames[x].name;
2316                         break;
2317                 }
2318         }
2319
2320         LOG_USER("%s", cp);
2321
2322         v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2323         LOG_USER("%s", nvptype[v]);
2324
2325         v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2326         LOG_USER("(exists: %s)", _yes_or_no(v));
2327 }
2328
2329 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
2330 {
2331         uint32_t v;
2332
2333         v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2334         LOG_USER("(main ready: %s)", _yes_or_no(v));
2335
2336         v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2337
2338         v = (v * pChip->cfg.slow_freq) / 16;
2339         pChip->cfg.mainosc_freq = v;
2340
2341         LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2342                 _tomhz(v),
2343                 pChip->cfg.slow_freq / 1000,
2344                 pChip->cfg.slow_freq % 1000);
2345 }
2346
2347 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
2348 {
2349         uint32_t mula, diva;
2350
2351         diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2352         LOG_USER_N("\n");
2353         mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2354         LOG_USER_N("\n");
2355         pChip->cfg.plla_freq = 0;
2356         if (mula == 0)
2357                 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2358         else if (diva == 0)
2359                 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2360         else if (diva == 1) {
2361                 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
2362                 LOG_USER("\tPLLA Freq: %3.03f MHz",
2363                         _tomhz(pChip->cfg.plla_freq));
2364         }
2365 }
2366
2367 static void sam3_explain_mckr(struct sam3_chip *pChip)
2368 {
2369         uint32_t css, pres, fin = 0;
2370         int pdiv = 0;
2371         const char *cp = NULL;
2372
2373         css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2374         switch (css & 3) {
2375                 case 0:
2376                         fin = pChip->cfg.slow_freq;
2377                         cp = "slowclk";
2378                         break;
2379                 case 1:
2380                         fin = pChip->cfg.mainosc_freq;
2381                         cp  = "mainosc";
2382                         break;
2383                 case 2:
2384                         fin = pChip->cfg.plla_freq;
2385                         cp  = "plla";
2386                         break;
2387                 case 3:
2388                         if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2389                                 fin = 480 * 1000 * 1000;
2390                                 cp = "upll";
2391                         } else {
2392                                 fin = 0;
2393                                 cp  = "upll (*ERROR* UPLL is disabled)";
2394                         }
2395                         break;
2396                 default:
2397                         assert(0);
2398                         break;
2399         }
2400
2401         LOG_USER("%s (%3.03f Mhz)",
2402                 cp,
2403                 _tomhz(fin));
2404         pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2405         switch (pres & 0x07) {
2406                 case 0:
2407                         pdiv = 1;
2408                         cp = "selected clock";
2409                         break;
2410                 case 1:
2411                         pdiv = 2;
2412                         cp = "clock/2";
2413                         break;
2414                 case 2:
2415                         pdiv = 4;
2416                         cp = "clock/4";
2417                         break;
2418                 case 3:
2419                         pdiv = 8;
2420                         cp = "clock/8";
2421                         break;
2422                 case 4:
2423                         pdiv = 16;
2424                         cp = "clock/16";
2425                         break;
2426                 case 5:
2427                         pdiv = 32;
2428                         cp = "clock/32";
2429                         break;
2430                 case 6:
2431                         pdiv = 64;
2432                         cp = "clock/64";
2433                         break;
2434                 case 7:
2435                         pdiv = 6;
2436                         cp = "clock/6";
2437                         break;
2438                 default:
2439                         assert(0);
2440                         break;
2441         }
2442         LOG_USER("(%s)", cp);
2443         fin = fin / pdiv;
2444         /* sam3 has a *SINGLE* clock - */
2445         /* other at91 series parts have divisors for these. */
2446         pChip->cfg.cpu_freq = fin;
2447         pChip->cfg.mclk_freq = fin;
2448         pChip->cfg.fclk_freq = fin;
2449         LOG_USER("\t\tResult CPU Freq: %3.03f",
2450                 _tomhz(fin));
2451 }
2452
2453 #if 0
2454 static struct sam3_chip *target2sam3(struct target *pTarget)
2455 {
2456         struct sam3_chip *pChip;
2457
2458         if (pTarget == NULL)
2459                 return NULL;
2460
2461         pChip = all_sam3_chips;
2462         while (pChip) {
2463                 if (pChip->target == pTarget)
2464                         break;  /* return below */
2465                 else
2466                         pChip = pChip->next;
2467         }
2468         return pChip;
2469 }
2470 #endif
2471
2472 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2473 {
2474         /* this function exists to help */
2475         /* keep funky offsetof() errors */
2476         /* and casting from causing bugs */
2477
2478         /* By using prototypes - we can detect what would */
2479         /* be casting errors. */
2480
2481         return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2482 }
2483
2484
2485 #define SAM3_ENTRY(NAME, FUNC)  { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2486                                                   struct sam3_cfg, \
2487                                                   NAME), # NAME, FUNC }
2488 static const struct sam3_reg_list sam3_all_regs[] = {
2489         SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2490         SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2491         SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2492         SAM3_ENTRY(CKGR_UCKR, NULL),
2493         SAM3_ENTRY(PMC_FSMR, NULL),
2494         SAM3_ENTRY(PMC_FSPR, NULL),
2495         SAM3_ENTRY(PMC_IMR, NULL),
2496         SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2497         SAM3_ENTRY(PMC_PCK0, NULL),
2498         SAM3_ENTRY(PMC_PCK1, NULL),
2499         SAM3_ENTRY(PMC_PCK2, NULL),
2500         SAM3_ENTRY(PMC_PCSR, NULL),
2501         SAM3_ENTRY(PMC_SCSR, NULL),
2502         SAM3_ENTRY(PMC_SR, NULL),
2503         SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2504         SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2505         SAM3_ENTRY(CHIPID_EXID, NULL),
2506         SAM3_ENTRY(CHIPID_EXID2, NULL),
2507         /* TERMINATE THE LIST */
2508         { .name = NULL }
2509 };
2510 #undef SAM3_ENTRY
2511
2512 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2513 {
2514         return (struct sam3_bank_private *)(bank->driver_priv);
2515 }
2516
2517 /**
2518  * Given a pointer to where it goes in the structure,
2519  * determine the register name, address from the all registers table.
2520  */
2521 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2522 {
2523         const struct sam3_reg_list *pReg;
2524
2525         pReg = &(sam3_all_regs[0]);
2526         while (pReg->name) {
2527                 uint32_t *pPossible;
2528
2529                 /* calculate where this one go.. */
2530                 /* it is "possibly" this register. */
2531
2532                 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2533
2534                 /* well? Is it this register */
2535                 if (pPossible == goes_here) {
2536                         /* Jump for joy! */
2537                         return pReg;
2538                 }
2539
2540                 /* next... */
2541                 pReg++;
2542         }
2543         /* This is *TOTAL*PANIC* - we are totally screwed. */
2544         LOG_ERROR("INVALID SAM3 REGISTER");
2545         return NULL;
2546 }
2547
2548 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2549 {
2550         const struct sam3_reg_list *pReg;
2551         int r;
2552
2553         pReg = sam3_GetReg(pChip, goes_here);
2554         if (!pReg)
2555                 return ERROR_FAIL;
2556
2557         r = target_read_u32(pChip->target, pReg->address, goes_here);
2558         if (r != ERROR_OK) {
2559                 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2560                         pReg->name, (unsigned)(pReg->address), r);
2561         }
2562         return r;
2563 }
2564
2565 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2566 {
2567         int r;
2568         const struct sam3_reg_list *pReg;
2569
2570         pReg = &(sam3_all_regs[0]);
2571         while (pReg->name) {
2572                 r = sam3_ReadThisReg(pChip,
2573                                 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2574                 if (r != ERROR_OK) {
2575                         LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
2576                                 pReg->name, ((unsigned)(pReg->address)), r);
2577                         return r;
2578                 }
2579                 pReg++;
2580         }
2581
2582         /* Chip identification register
2583         *
2584         * Unfortunately, the chip identification register is not at
2585         * a constant address across all of the SAM3 series'. As a
2586         * consequence, a simple heuristic is used to find where it's
2587         * at...
2588         *
2589         * If the contents at the first address is zero, then we know
2590         * that the second address is where the chip id register is.
2591         * We can deduce this because for those SAM's that have the
2592         * chip id @ 0x400e0940, the first address, 0x400e0740, is
2593         * located in the memory map of the Power Management Controller
2594         * (PMC). Furthermore, the address is not used by the PMC.
2595         * So when read, the memory controller returns zero.*/
2596         if (pChip->cfg.CHIPID_CIDR == 0)        {
2597                 /*Put the correct CIDR and EXID values in the pChip structure */
2598                 pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
2599                 pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
2600         }
2601         return ERROR_OK;
2602 }
2603
2604 static int sam3_GetInfo(struct sam3_chip *pChip)
2605 {
2606         const struct sam3_reg_list *pReg;
2607         uint32_t regval;
2608
2609         pReg = &(sam3_all_regs[0]);
2610         while (pReg->name) {
2611                 /* display all regs */
2612                 LOG_DEBUG("Start: %s", pReg->name);
2613                 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2614                 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2615                         REG_NAME_WIDTH,
2616                         pReg->name,
2617                         pReg->address,
2618                         regval);
2619                 if (pReg->explain_func)
2620                         (*(pReg->explain_func))(pChip);
2621                 LOG_DEBUG("End: %s", pReg->name);
2622                 pReg++;
2623         }
2624         LOG_USER("   rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2625         LOG_USER("  mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2626         LOG_USER("     plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2627         LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2628         LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2629
2630         LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2631                 pChip->cfg.unique_id[0],
2632                 pChip->cfg.unique_id[1],
2633                 pChip->cfg.unique_id[2],
2634                 pChip->cfg.unique_id[3]);
2635
2636         return ERROR_OK;
2637 }
2638
2639 static int sam3_erase_check(struct flash_bank *bank)
2640 {
2641         int x;
2642
2643         LOG_DEBUG("Here");
2644         if (bank->target->state != TARGET_HALTED) {
2645                 LOG_ERROR("Target not halted");
2646                 return ERROR_TARGET_NOT_HALTED;
2647         }
2648         if (0 == bank->num_sectors) {
2649                 LOG_ERROR("Target: not supported/not probed");
2650                 return ERROR_FAIL;
2651         }
2652
2653         LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2654         for (x = 0; x < bank->num_sectors; x++)
2655                 bank->sectors[x].is_erased = 1;
2656
2657         LOG_DEBUG("Done");
2658         return ERROR_OK;
2659 }
2660
2661 static int sam3_protect_check(struct flash_bank *bank)
2662 {
2663         int r;
2664         uint32_t v = 0;
2665         unsigned x;
2666         struct sam3_bank_private *pPrivate;
2667
2668         LOG_DEBUG("Begin");
2669         if (bank->target->state != TARGET_HALTED) {
2670                 LOG_ERROR("Target not halted");
2671                 return ERROR_TARGET_NOT_HALTED;
2672         }
2673
2674         pPrivate = get_sam3_bank_private(bank);
2675         if (!pPrivate) {
2676                 LOG_ERROR("no private for this bank?");
2677                 return ERROR_FAIL;
2678         }
2679         if (!(pPrivate->probed))
2680                 return ERROR_FLASH_BANK_NOT_PROBED;
2681
2682         r = FLASHD_GetLockBits(pPrivate, &v);
2683         if (r != ERROR_OK) {
2684                 LOG_DEBUG("Failed: %d", r);
2685                 return r;
2686         }
2687
2688         for (x = 0; x < pPrivate->nsectors; x++)
2689                 bank->sectors[x].is_protected = (!!(v & (1 << x)));
2690         LOG_DEBUG("Done");
2691         return ERROR_OK;
2692 }
2693
2694 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2695 {
2696         struct sam3_chip *pChip;
2697
2698         pChip = all_sam3_chips;
2699
2700         /* is this an existing chip? */
2701         while (pChip) {
2702                 if (pChip->target == bank->target)
2703                         break;
2704                 pChip = pChip->next;
2705         }
2706
2707         if (!pChip) {
2708                 /* this is a *NEW* chip */
2709                 pChip = calloc(1, sizeof(struct sam3_chip));
2710                 if (!pChip) {
2711                         LOG_ERROR("NO RAM!");
2712                         return ERROR_FAIL;
2713                 }
2714                 pChip->target = bank->target;
2715                 /* insert at head */
2716                 pChip->next = all_sam3_chips;
2717                 all_sam3_chips = pChip;
2718                 pChip->target = bank->target;
2719                 /* assumption is this runs at 32khz */
2720                 pChip->cfg.slow_freq = 32768;
2721                 pChip->probed = 0;
2722         }
2723
2724         switch (bank->base) {
2725                 default:
2726                         LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2727                         "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2728                         "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
2729                         ((unsigned int)(bank->base)),
2730                         ((unsigned int)(FLASH_BANK0_BASE_U)),
2731                         ((unsigned int)(FLASH_BANK1_BASE_U)),
2732                         ((unsigned int)(FLASH_BANK_BASE_S)),
2733                         ((unsigned int)(FLASH_BANK_BASE_N)),
2734                         ((unsigned int)(FLASH_BANK0_BASE_AX)),
2735                     ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
2736                     ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
2737                         return ERROR_FAIL;
2738                         break;
2739
2740                 /* at91sam3s and at91sam3n series only has bank 0*/
2741                 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
2742                 case FLASH_BANK_BASE_S:
2743                 case FLASH_BANK0_BASE_U:
2744                         bank->driver_priv = &(pChip->details.bank[0]);
2745                         bank->bank_number = 0;
2746                         pChip->details.bank[0].pChip = pChip;
2747                         pChip->details.bank[0].pBank = bank;
2748                         break;
2749
2750                 /* Bank 1 of at91sam3u or at91sam3ax series */
2751                 case FLASH_BANK1_BASE_U:
2752                 case FLASH_BANK1_BASE_256K_AX:
2753                 case FLASH_BANK1_BASE_512K_AX:
2754                         bank->driver_priv = &(pChip->details.bank[1]);
2755                         bank->bank_number = 1;
2756                         pChip->details.bank[1].pChip = pChip;
2757                         pChip->details.bank[1].pBank = bank;
2758                         break;
2759         }
2760
2761         /* we initialize after probing. */
2762         return ERROR_OK;
2763 }
2764
2765 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
2766 {
2767         const struct sam3_chip_details *pDetails;
2768         struct sam3_chip *pChip;
2769         struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
2770         unsigned x;
2771
2772         LOG_DEBUG("Begin");
2773         pDetails = all_sam3_details;
2774         while (pDetails->name) {
2775                 /* Compare cidr without version bits */
2776                 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2777                         break;
2778                 else
2779                         pDetails++;
2780         }
2781         if (pDetails->name == NULL) {
2782                 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2783                         (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2784                 /* Help the victim, print details about the chip */
2785                 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2786                         pPrivate->pChip->cfg.CHIPID_CIDR);
2787                 sam3_explain_chipid_cidr(pPrivate->pChip);
2788                 return ERROR_FAIL;
2789         }
2790
2791         /* DANGER: THERE ARE DRAGONS HERE */
2792
2793         /* get our pChip - it is going */
2794         /* to be over-written shortly */
2795         pChip = pPrivate->pChip;
2796
2797         /* Note that, in reality: */
2798         /*  */
2799         /*     pPrivate = &(pChip->details.bank[0]) */
2800         /* or  pPrivate = &(pChip->details.bank[1]) */
2801         /*  */
2802
2803         /* save the "bank" pointers */
2804         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
2805                 saved_banks[x] = pChip->details.bank[x].pBank;
2806
2807         /* Overwrite the "details" structure. */
2808         memcpy(&(pPrivate->pChip->details),
2809                 pDetails,
2810                 sizeof(pPrivate->pChip->details));
2811
2812         /* now fix the ghosted pointers */
2813         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2814                 pChip->details.bank[x].pChip = pChip;
2815                 pChip->details.bank[x].pBank = saved_banks[x];
2816         }
2817
2818         /* update the *BANK*SIZE* */
2819
2820         LOG_DEBUG("End");
2821         return ERROR_OK;
2822 }
2823
2824 static int _sam3_probe(struct flash_bank *bank, int noise)
2825 {
2826         unsigned x;
2827         int r;
2828         struct sam3_bank_private *pPrivate;
2829
2830
2831         LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2832         if (bank->target->state != TARGET_HALTED) {
2833                 LOG_ERROR("Target not halted");
2834                 return ERROR_TARGET_NOT_HALTED;
2835         }
2836
2837         pPrivate = get_sam3_bank_private(bank);
2838         if (!pPrivate) {
2839                 LOG_ERROR("Invalid/unknown bank number");
2840                 return ERROR_FAIL;
2841         }
2842
2843         r = sam3_ReadAllRegs(pPrivate->pChip);
2844         if (r != ERROR_OK)
2845                 return r;
2846
2847         LOG_DEBUG("Here");
2848         if (pPrivate->pChip->probed)
2849                 r = sam3_GetInfo(pPrivate->pChip);
2850         else
2851                 r = sam3_GetDetails(pPrivate);
2852         if (r != ERROR_OK)
2853                 return r;
2854
2855         /* update the flash bank size */
2856         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2857                 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2858                         bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2859                         break;
2860                 }
2861         }
2862
2863         if (bank->sectors == NULL) {
2864                 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2865                 if (bank->sectors == NULL) {
2866                         LOG_ERROR("No memory!");
2867                         return ERROR_FAIL;
2868                 }
2869                 bank->num_sectors = pPrivate->nsectors;
2870
2871                 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2872                         bank->sectors[x].size = pPrivate->sector_size;
2873                         bank->sectors[x].offset = x * (pPrivate->sector_size);
2874                         /* mark as unknown */
2875                         bank->sectors[x].is_erased = -1;
2876                         bank->sectors[x].is_protected = -1;
2877                 }
2878         }
2879
2880         pPrivate->probed = 1;
2881
2882         r = sam3_protect_check(bank);
2883         if (r != ERROR_OK)
2884                 return r;
2885
2886         LOG_DEBUG("Bank = %d, nbanks = %d",
2887                 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2888         if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2889                 /* read unique id, */
2890                 /* it appears to be associated with the *last* flash bank. */
2891                 FLASHD_ReadUniqueID(pPrivate);
2892         }
2893
2894         return r;
2895 }
2896
2897 static int sam3_probe(struct flash_bank *bank)
2898 {
2899         return _sam3_probe(bank, 1);
2900 }
2901
2902 static int sam3_auto_probe(struct flash_bank *bank)
2903 {
2904         return _sam3_probe(bank, 0);
2905 }
2906
2907 static int sam3_erase(struct flash_bank *bank, int first, int last)
2908 {
2909         struct sam3_bank_private *pPrivate;
2910         int r;
2911
2912         LOG_DEBUG("Here");
2913         if (bank->target->state != TARGET_HALTED) {
2914                 LOG_ERROR("Target not halted");
2915                 return ERROR_TARGET_NOT_HALTED;
2916         }
2917
2918         r = sam3_auto_probe(bank);
2919         if (r != ERROR_OK) {
2920                 LOG_DEBUG("Here,r=%d", r);
2921                 return r;
2922         }
2923
2924         pPrivate = get_sam3_bank_private(bank);
2925         if (!(pPrivate->probed))
2926                 return ERROR_FLASH_BANK_NOT_PROBED;
2927
2928         if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2929                 /* whole chip */
2930                 LOG_DEBUG("Here");
2931                 return FLASHD_EraseEntireBank(pPrivate);
2932         }
2933         LOG_INFO("sam3 auto-erases while programing (request ignored)");
2934         return ERROR_OK;
2935 }
2936
2937 static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
2938 {
2939         struct sam3_bank_private *pPrivate;
2940         int r;
2941
2942         LOG_DEBUG("Here");
2943         if (bank->target->state != TARGET_HALTED) {
2944                 LOG_ERROR("Target not halted");
2945                 return ERROR_TARGET_NOT_HALTED;
2946         }
2947
2948         pPrivate = get_sam3_bank_private(bank);
2949         if (!(pPrivate->probed))
2950                 return ERROR_FLASH_BANK_NOT_PROBED;
2951
2952         if (set)
2953                 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2954         else
2955                 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2956         LOG_DEBUG("End: r=%d", r);
2957
2958         return r;
2959
2960 }
2961
2962 static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)
2963 {
2964         if (bank->target->state != TARGET_HALTED) {
2965                 LOG_ERROR("Target not halted");
2966                 return ERROR_TARGET_NOT_HALTED;
2967         }
2968         buf[0] = 0;
2969         return ERROR_OK;
2970 }
2971
2972 static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2973 {
2974         uint32_t adr;
2975         int r;
2976
2977         adr = pagenum * pPrivate->page_size;
2978         adr += adr + pPrivate->base_address;
2979
2980         r = target_read_memory(pPrivate->pChip->target,
2981                         adr,
2982                         4,                                      /* THIS*MUST*BE* in 32bit values */
2983                         pPrivate->page_size / 4,
2984                         buf);
2985         if (r != ERROR_OK)
2986                 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
2987                         (unsigned int)(adr));
2988         return r;
2989 }
2990
2991 /* The code below is basically this: */
2992 /* compiled with */
2993 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
2994 /*  */
2995 /* Only the *CPU* can write to the flash buffer. */
2996 /* the DAP cannot... so - we download this 28byte thing */
2997 /* Run the algorithm - (below) */
2998 /* to program the device */
2999 /*  */
3000 /* ======================================== */
3001 /* #include <stdint.h> */
3002 /*  */
3003 /* struct foo { */
3004 /*   uint32_t *dst; */
3005 /*   const uint32_t *src; */
3006 /*   int   n; */
3007 /*   volatile uint32_t *base; */
3008 /*   uint32_t   cmd; */
3009 /* }; */
3010 /*  */
3011 /*  */
3012 /* uint32_t sam3_function(struct foo *p) */
3013 /* { */
3014 /*   volatile uint32_t *v; */
3015 /*   uint32_t *d; */
3016 /*   const uint32_t *s; */
3017 /*   int   n; */
3018 /*   uint32_t r; */
3019 /*  */
3020 /*   d = p->dst; */
3021 /*   s = p->src; */
3022 /*   n = p->n; */
3023 /*  */
3024 /*   do { */
3025 /*     *d++ = *s++; */
3026 /*   } while (--n) */
3027 /*     ; */
3028 /*  */
3029 /*   v = p->base; */
3030 /*  */
3031 /*   v[ 1 ] = p->cmd; */
3032 /*   do { */
3033 /*     r = v[8/4]; */
3034 /*   } while (!(r&1)) */
3035 /*     ; */
3036 /*   return r; */
3037 /* } */
3038 /* ======================================== */
3039
3040 static const uint8_t
3041         sam3_page_write_opcodes[] = {
3042         /*  24 0000 0446                mov     r4, r0 */
3043         0x04, 0x46,
3044         /*  25 0002 6168                ldr     r1, [r4, #4] */
3045         0x61, 0x68,
3046         /*  26 0004 0068                ldr     r0, [r0, #0] */
3047         0x00, 0x68,
3048         /*  27 0006 A268                ldr     r2, [r4, #8] */
3049         0xa2, 0x68,
3050         /*  28                          @ lr needed for prologue */
3051         /*  29                  .L2: */
3052         /*  30 0008 51F8043B            ldr     r3, [r1], #4 */
3053         0x51, 0xf8, 0x04, 0x3b,
3054         /*  31 000c 12F1FF32            adds    r2, r2, #-1 */
3055         0x12, 0xf1, 0xff, 0x32,
3056         /*  32 0010 40F8043B            str     r3, [r0], #4 */
3057         0x40, 0xf8, 0x04, 0x3b,
3058         /*  33 0014 F8D1                bne     .L2 */
3059         0xf8, 0xd1,
3060         /*  34 0016 E268                ldr     r2, [r4, #12] */
3061         0xe2, 0x68,
3062         /*  35 0018 2369                ldr     r3, [r4, #16] */
3063         0x23, 0x69,
3064         /*  36 001a 5360                str     r3, [r2, #4] */
3065         0x53, 0x60,
3066         /*  37 001c 0832                adds    r2, r2, #8 */
3067         0x08, 0x32,
3068         /*  38                  .L4: */
3069         /*  39 001e 1068                ldr     r0, [r2, #0] */
3070         0x10, 0x68,
3071         /*  40 0020 10F0010F            tst     r0, #1 */
3072         0x10, 0xf0, 0x01, 0x0f,
3073         /*  41 0024 FBD0                beq     .L4 */
3074         0xfb, 0xd0,
3075         0x00, 0xBE                              /* bkpt #0 */
3076 };
3077
3078 static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3079 {
3080         uint32_t adr;
3081         uint32_t status;
3082         uint32_t fmr;   /* EEFC Flash Mode Register */
3083         int r;
3084
3085         adr = pagenum * pPrivate->page_size;
3086         adr += (adr + pPrivate->base_address);
3087
3088         /* Get flash mode register value */
3089         r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
3090         if (r != ERROR_OK)
3091                 LOG_DEBUG("Error Read failed: read flash mode register");
3092
3093         /* Clear flash wait state field */
3094         fmr &= 0xfffff0ff;
3095
3096         /* set FWS (flash wait states) field in the FMR (flash mode register) */
3097         fmr |= (pPrivate->flash_wait_states << 8);
3098
3099         LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3100         r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
3101         if (r != ERROR_OK)
3102                 LOG_DEBUG("Error Write failed: set flash mode register");
3103
3104         LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3105         r = target_write_memory(pPrivate->pChip->target,
3106                         adr,
3107                         4,                                      /* THIS*MUST*BE* in 32bit values */
3108                         pPrivate->page_size / 4,
3109                         buf);
3110         if (r != ERROR_OK) {
3111                 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3112                         (unsigned int)(adr));
3113                 return r;
3114         }
3115
3116         r = EFC_PerformCommand(pPrivate,
3117                         /* send Erase & Write Page */
3118                         AT91C_EFC_FCMD_EWP,
3119                         pagenum,
3120                         &status);
3121
3122         if (r != ERROR_OK)
3123                 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3124                         (unsigned int)(adr));
3125         if (status & (1 << 2)) {
3126                 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3127                 return ERROR_FAIL;
3128         }
3129         if (status & (1 << 1)) {
3130                 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3131                 return ERROR_FAIL;
3132         }
3133         return ERROR_OK;
3134 }
3135
3136 static int sam3_write(struct flash_bank *bank,
3137         uint8_t *buffer,
3138         uint32_t offset,
3139         uint32_t count)
3140 {
3141         int n;
3142         unsigned page_cur;
3143         unsigned page_end;
3144         int r;
3145         unsigned page_offset;
3146         struct sam3_bank_private *pPrivate;
3147         uint8_t *pagebuffer;
3148
3149         /* incase we bail further below, set this to null */
3150         pagebuffer = NULL;
3151
3152         /* ignore dumb requests */
3153         if (count == 0) {
3154                 r = ERROR_OK;
3155                 goto done;
3156         }
3157
3158         if (bank->target->state != TARGET_HALTED) {
3159                 LOG_ERROR("Target not halted");
3160                 r = ERROR_TARGET_NOT_HALTED;
3161                 goto done;
3162         }
3163
3164         pPrivate = get_sam3_bank_private(bank);
3165         if (!(pPrivate->probed)) {
3166                 r = ERROR_FLASH_BANK_NOT_PROBED;
3167                 goto done;
3168         }
3169
3170         if ((offset + count) > pPrivate->size_bytes) {
3171                 LOG_ERROR("Flash write error - past end of bank");
3172                 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3173                         (unsigned int)(offset),
3174                         (unsigned int)(count),
3175                         (unsigned int)(pPrivate->size_bytes));
3176                 r = ERROR_FAIL;
3177                 goto done;
3178         }
3179
3180         pagebuffer = malloc(pPrivate->page_size);
3181         if (!pagebuffer) {
3182                 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
3183                 r = ERROR_FAIL;
3184                 goto done;
3185         }
3186
3187         /* what page do we start & end in? */
3188         page_cur = offset / pPrivate->page_size;
3189         page_end = (offset + count - 1) / pPrivate->page_size;
3190
3191         LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3192         LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3193
3194         /* Special case: all one page */
3195         /*  */
3196         /* Otherwise: */
3197         /*    (1) non-aligned start */
3198         /*    (2) body pages */
3199         /*    (3) non-aligned end. */
3200
3201         /* Handle special case - all one page. */
3202         if (page_cur == page_end) {
3203                 LOG_DEBUG("Special case, all in one page");
3204                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3205                 if (r != ERROR_OK)
3206                         goto done;
3207
3208                 page_offset = (offset & (pPrivate->page_size-1));
3209                 memcpy(pagebuffer + page_offset,
3210                         buffer,
3211                         count);
3212
3213                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3214                 if (r != ERROR_OK)
3215                         goto done;
3216                 r = ERROR_OK;
3217                 goto done;
3218         }
3219
3220         /* non-aligned start */
3221         page_offset = offset & (pPrivate->page_size - 1);
3222         if (page_offset) {
3223                 LOG_DEBUG("Not-Aligned start");
3224                 /* read the partial */
3225                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3226                 if (r != ERROR_OK)
3227                         goto done;
3228
3229                 /* over-write with new data */
3230                 n = (pPrivate->page_size - page_offset);
3231                 memcpy(pagebuffer + page_offset,
3232                         buffer,
3233                         n);
3234
3235                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3236                 if (r != ERROR_OK)
3237                         goto done;
3238
3239                 count  -= n;
3240                 offset += n;
3241                 buffer += n;
3242                 page_cur++;
3243         }
3244
3245         /* By checking that offset is correct here, we also
3246         fix a clang warning */
3247         assert(offset % pPrivate->page_size == 0);
3248
3249         /* intermediate large pages */
3250         /* also - the final *terminal* */
3251         /* if that terminal page is a full page */
3252         LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3253                 (int)page_cur, (int)page_end, (unsigned int)(count));
3254
3255         while ((page_cur < page_end) &&
3256                         (count >= pPrivate->page_size)) {
3257                 r = sam3_page_write(pPrivate, page_cur, buffer);
3258                 if (r != ERROR_OK)
3259                         goto done;
3260                 count -= pPrivate->page_size;
3261                 buffer += pPrivate->page_size;
3262                 page_cur += 1;
3263         }
3264
3265         /* terminal partial page? */
3266         if (count) {
3267                 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3268                 /* we have a partial page */
3269                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3270                 if (r != ERROR_OK)
3271                         goto done;
3272                                         /* data goes at start */
3273                 memcpy(pagebuffer, buffer, count);
3274                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3275                 if (r != ERROR_OK)
3276                         goto done;
3277                 buffer += count;
3278         }
3279         LOG_DEBUG("Done!");
3280         r = ERROR_OK;
3281 done:
3282         if (pagebuffer)
3283                 free(pagebuffer);
3284         return r;
3285 }
3286
3287 COMMAND_HANDLER(sam3_handle_info_command)
3288 {
3289         struct sam3_chip *pChip;
3290         pChip = get_current_sam3(CMD_CTX);
3291         if (!pChip)
3292                 return ERROR_OK;
3293
3294         unsigned x;
3295         int r;
3296
3297         /* bank0 must exist before we can do anything */
3298         if (pChip->details.bank[0].pBank == NULL) {
3299                 x = 0;
3300 need_define:
3301                 command_print(CMD_CTX,
3302                         "Please define bank %d via command: flash bank %s ... ",
3303                         x,
3304                         at91sam3_flash.name);
3305                 return ERROR_FAIL;
3306         }
3307
3308         /* if bank 0 is not probed, then probe it */
3309         if (!(pChip->details.bank[0].probed)) {
3310                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3311                 if (r != ERROR_OK)
3312                         return ERROR_FAIL;
3313         }
3314         /* above guarantees the "chip details" structure is valid */
3315         /* and thus, bank private areas are valid */
3316         /* and we have a SAM3 chip, what a concept! */
3317
3318         /* auto-probe other banks, 0 done above */
3319         for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3320                 /* skip banks not present */
3321                 if (!(pChip->details.bank[x].present))
3322                         continue;
3323
3324                 if (pChip->details.bank[x].pBank == NULL)
3325                         goto need_define;
3326
3327                 if (pChip->details.bank[x].probed)
3328                         continue;
3329
3330                 r = sam3_auto_probe(pChip->details.bank[x].pBank);
3331                 if (r != ERROR_OK)
3332                         return r;
3333         }
3334
3335         r = sam3_GetInfo(pChip);
3336         if (r != ERROR_OK) {
3337                 LOG_DEBUG("Sam3Info, Failed %d", r);
3338                 return r;
3339         }
3340
3341         return ERROR_OK;
3342 }
3343
3344 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3345 {
3346         unsigned x, v;
3347         int r, who;
3348         struct sam3_chip *pChip;
3349
3350         pChip = get_current_sam3(CMD_CTX);
3351         if (!pChip)
3352                 return ERROR_OK;
3353
3354         if (pChip->target->state != TARGET_HALTED) {
3355                 LOG_ERROR("sam3 - target not halted");
3356                 return ERROR_TARGET_NOT_HALTED;
3357         }
3358
3359         if (pChip->details.bank[0].pBank == NULL) {
3360                 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3361                         at91sam3_flash.name);
3362                 return ERROR_FAIL;
3363         }
3364         if (!pChip->details.bank[0].probed) {
3365                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3366                 if (r != ERROR_OK)
3367                         return r;
3368         }
3369
3370         switch (CMD_ARGC) {
3371                 default:
3372                         return ERROR_COMMAND_SYNTAX_ERROR;
3373                         break;
3374                 case 0:
3375                         goto showall;
3376                         break;
3377                 case 1:
3378                         who = -1;
3379                         break;
3380                 case 2:
3381                         if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3382                                 who = -1;
3383                         else {
3384                                 uint32_t v32;
3385                                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3386                                 who = v32;
3387                         }
3388                         break;
3389         }
3390
3391         if (0 == strcmp("show", CMD_ARGV[0])) {
3392                 if (who == -1) {
3393 showall:
3394                         r = ERROR_OK;
3395                         for (x = 0; x < pChip->details.n_gpnvms; x++) {
3396                                 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3397                                 if (r != ERROR_OK)
3398                                         break;
3399                                 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
3400                         }
3401                         return r;
3402                 }
3403                 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3404                         r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3405                         command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
3406                         return r;
3407                 } else {
3408                         command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
3409                         return ERROR_COMMAND_SYNTAX_ERROR;
3410                 }
3411         }
3412
3413         if (who == -1) {
3414                 command_print(CMD_CTX, "Missing GPNVM number");
3415                 return ERROR_COMMAND_SYNTAX_ERROR;
3416         }
3417
3418         if (0 == strcmp("set", CMD_ARGV[0]))
3419                 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3420         else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3421                  (0 == strcmp("clear", CMD_ARGV[0])))                   /* quietly accept both */
3422                 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3423         else {
3424                 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3425                 r = ERROR_COMMAND_SYNTAX_ERROR;
3426         }
3427         return r;
3428 }
3429
3430 COMMAND_HANDLER(sam3_handle_slowclk_command)
3431 {
3432         struct sam3_chip *pChip;
3433
3434         pChip = get_current_sam3(CMD_CTX);
3435         if (!pChip)
3436                 return ERROR_OK;
3437
3438         switch (CMD_ARGC) {
3439                 case 0:
3440                         /* show */
3441                         break;
3442                 case 1:
3443                 {
3444                         /* set */
3445                         uint32_t v;
3446                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3447                         if (v > 200000) {
3448                                 /* absurd slow clock of 200Khz? */
3449                                 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3450                                 return ERROR_COMMAND_SYNTAX_ERROR;
3451                         }
3452                         pChip->cfg.slow_freq = v;
3453                         break;
3454                 }
3455                 default:
3456                         /* error */
3457                         command_print(CMD_CTX, "Too many parameters");
3458                         return ERROR_COMMAND_SYNTAX_ERROR;
3459                         break;
3460         }
3461         command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3462                 (int)(pChip->cfg.slow_freq / 1000),
3463                 (int)(pChip->cfg.slow_freq % 1000));
3464         return ERROR_OK;
3465 }
3466
3467 static const struct command_registration at91sam3_exec_command_handlers[] = {
3468         {
3469                 .name = "gpnvm",
3470                 .handler = sam3_handle_gpnvm_command,
3471                 .mode = COMMAND_EXEC,
3472                 .usage = "[('clr'|'set'|'show') bitnum]",
3473                 .help = "Without arguments, shows all bits in the gpnvm "
3474                         "register.  Otherwise, clears, sets, or shows one "
3475                         "General Purpose Non-Volatile Memory (gpnvm) bit.",
3476         },
3477         {
3478                 .name = "info",
3479                 .handler = sam3_handle_info_command,
3480                 .mode = COMMAND_EXEC,
3481                 .help = "Print information about the current at91sam3 chip"
3482                         "and its flash configuration.",
3483         },
3484         {
3485                 .name = "slowclk",
3486                 .handler = sam3_handle_slowclk_command,
3487                 .mode = COMMAND_EXEC,
3488                 .usage = "[clock_hz]",
3489                 .help = "Display or set the slowclock frequency "
3490                         "(default 32768 Hz).",
3491         },
3492         COMMAND_REGISTRATION_DONE
3493 };
3494 static const struct command_registration at91sam3_command_handlers[] = {
3495         {
3496                 .name = "at91sam3",
3497                 .mode = COMMAND_ANY,
3498                 .help = "at91sam3 flash command group",
3499                 .usage = "",
3500                 .chain = at91sam3_exec_command_handlers,
3501         },
3502         COMMAND_REGISTRATION_DONE
3503 };
3504
3505 struct flash_driver at91sam3_flash = {
3506         .name = "at91sam3",
3507         .commands = at91sam3_command_handlers,
3508         .flash_bank_command = sam3_flash_bank_command,
3509         .erase = sam3_erase,
3510         .protect = sam3_protect,
3511         .write = sam3_write,
3512         .read = default_flash_read,
3513         .probe = sam3_probe,
3514         .auto_probe = sam3_auto_probe,
3515         .erase_check = sam3_erase_check,
3516         .protect_check = sam3_protect_check,
3517         .info = sam3_info,
3518 };