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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Duane Ellis                                     *
   3  *   openocd@duaneellis.com                                                *
   4  *                                                                         *
   5  *   Copyright (C) 2010 by Olaf Lüke (at91sam3s* support)                  *
   6  *   olaf@uni-paderborn.de                                                 *
   7  *                                                                         *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23 ****************************************************************************/
  24
  25 /* Some of the the lower level code was based on code supplied by
  26  * ATMEL under this copyright. */
  27
  28 /* BEGIN ATMEL COPYRIGHT */
  29 /* ----------------------------------------------------------------------------
  30  *         ATMEL Microcontroller Software Support
  31  * ----------------------------------------------------------------------------
  32  * Copyright (c) 2009, Atmel Corporation
  33  *
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions are met:
  38  *
  39  * - Redistributions of source code must retain the above copyright notice,
  40  * this list of conditions and the disclaimer below.
  41  *
  42  * Atmel's name may not be used to endorse or promote products derived from
  43  * this software without specific prior written permission.
  44  *
  45  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  46  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  47  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  48  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  49  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  50  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  51  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  52  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  53  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  54  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  55  * ----------------------------------------------------------------------------
  56  */
  57 /* END ATMEL COPYRIGHT */
  58
  59 #ifdef HAVE_CONFIG_H
  60 #include "config.h"
  61 #endif
  62
  63
  64 #include "imp.h"
  65 #include <helper/time_support.h>
  66
  67 #define REG_NAME_WIDTH  (12)
  68
  69 // at91sam3u series (has one or two flash banks)
  70 #define FLASH_BANK0_BASE_U   0x00080000
  71 #define FLASH_BANK1_BASE_U   0x00100000
  72
  73 // at91sam3s series (has always one flash bank)
  74 #define FLASH_BANK_BASE_S   0x00400000
  75
  76 #define         AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor
  77 #define         AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page
  78 #define         AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock
  79 #define         AT91C_EFC_FCMD_EWP                  (0x3) // (EFC) Erase Page and Write Page
  80 #define         AT91C_EFC_FCMD_EWPL                 (0x4) // (EFC) Erase Page and Write Page then Lock
  81 #define         AT91C_EFC_FCMD_EA                   (0x5) // (EFC) Erase All
  82 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
  83 // #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane?
  84 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
  85 // #define      AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages?
  86 #define         AT91C_EFC_FCMD_SLB                  (0x8) // (EFC) Set Lock Bit
  87 #define         AT91C_EFC_FCMD_CLB                  (0x9) // (EFC) Clear Lock Bit
  88 #define         AT91C_EFC_FCMD_GLB                  (0xA) // (EFC) Get Lock Bit
  89 #define         AT91C_EFC_FCMD_SFB                  (0xB) // (EFC) Set Fuse Bit
  90 #define         AT91C_EFC_FCMD_CFB                  (0xC) // (EFC) Clear Fuse Bit
  91 #define         AT91C_EFC_FCMD_GFB                  (0xD) // (EFC) Get Fuse Bit
  92 #define         AT91C_EFC_FCMD_STUI                 (0xE) // (EFC) Start Read Unique ID
  93 #define         AT91C_EFC_FCMD_SPUI                 (0xF) // (EFC) Stop Read Unique ID
  94
  95 #define  offset_EFC_FMR   0
  96 #define  offset_EFC_FCR   4
  97 #define  offset_EFC_FSR   8
  98 #define  offset_EFC_FRR   12
  99
 100
 101 extern struct flash_driver at91sam3_flash;
 102
 103 static float
 104 _tomhz(uint32_t freq_hz)
 105 {
 106         float f;
 107
 108         f = ((float)(freq_hz)) / 1000000.0;
 109         return f;
 110 }
 111
 112 // How the chip is configured.
 113 struct sam3_cfg {
 114         uint32_t unique_id[4];
 115
 116         uint32_t slow_freq;
 117         uint32_t rc_freq;
 118         uint32_t mainosc_freq;
 119         uint32_t plla_freq;
 120         uint32_t mclk_freq;
 121         uint32_t cpu_freq;
 122         uint32_t fclk_freq;
 123         uint32_t pclk0_freq;
 124         uint32_t pclk1_freq;
 125         uint32_t pclk2_freq;
 126
 127
 128 #define SAM3_CHIPID_CIDR          (0x400E0740)
 129         uint32_t CHIPID_CIDR;
 130 #define SAM3_CHIPID_EXID          (0x400E0744)
 131         uint32_t CHIPID_EXID;
 132
 133 #define SAM3_SUPC_CR              (0x400E1210)
 134         uint32_t SUPC_CR;
 135
 136 #define SAM3_PMC_BASE             (0x400E0400)
 137 #define SAM3_PMC_SCSR             (SAM3_PMC_BASE + 0x0008)
 138         uint32_t PMC_SCSR;
 139 #define SAM3_PMC_PCSR             (SAM3_PMC_BASE + 0x0018)
 140         uint32_t PMC_PCSR;
 141 #define SAM3_CKGR_UCKR            (SAM3_PMC_BASE + 0x001c)
 142         uint32_t CKGR_UCKR;
 143 #define SAM3_CKGR_MOR             (SAM3_PMC_BASE + 0x0020)
 144         uint32_t CKGR_MOR;
 145 #define SAM3_CKGR_MCFR            (SAM3_PMC_BASE + 0x0024)
 146         uint32_t CKGR_MCFR;
 147 #define SAM3_CKGR_PLLAR           (SAM3_PMC_BASE + 0x0028)
 148         uint32_t CKGR_PLLAR;
 149 #define SAM3_PMC_MCKR             (SAM3_PMC_BASE + 0x0030)
 150         uint32_t PMC_MCKR;
 151 #define SAM3_PMC_PCK0             (SAM3_PMC_BASE + 0x0040)
 152         uint32_t PMC_PCK0;
 153 #define SAM3_PMC_PCK1             (SAM3_PMC_BASE + 0x0044)
 154         uint32_t PMC_PCK1;
 155 #define SAM3_PMC_PCK2             (SAM3_PMC_BASE + 0x0048)
 156         uint32_t PMC_PCK2;
 157 #define SAM3_PMC_SR               (SAM3_PMC_BASE + 0x0068)
 158         uint32_t PMC_SR;
 159 #define SAM3_PMC_IMR              (SAM3_PMC_BASE + 0x006c)
 160         uint32_t PMC_IMR;
 161 #define SAM3_PMC_FSMR             (SAM3_PMC_BASE + 0x0070)
 162         uint32_t PMC_FSMR;
 163 #define SAM3_PMC_FSPR             (SAM3_PMC_BASE + 0x0074)
 164         uint32_t PMC_FSPR;
 165 };
 166
 167
 168 struct sam3_bank_private {
 169         int probed;
 170         // DANGER: THERE ARE DRAGONS HERE..
 171         // NOTE: If you add more 'ghost' pointers
 172         // be aware that you must *manually* update
 173         // these pointers in the function sam3_GetDetails()
 174         // See the comment "Here there be dragons"
 175
 176         // so we can find the chip we belong to
 177         struct sam3_chip *pChip;
 178         // so we can find the orginal bank pointer
 179         struct flash_bank *pBank;
 180         unsigned bank_number;
 181         uint32_t controller_address;
 182         uint32_t base_address;
 183         bool present;
 184         unsigned size_bytes;
 185         unsigned nsectors;
 186         unsigned sector_size;
 187         unsigned page_size;
 188 };
 189
 190 struct sam3_chip_details {
 191         // THERE ARE DRAGONS HERE..
 192         // note: If you add pointers here
 193         // becareful about them as they
 194         // may need to be updated inside
 195         // the function: "sam3_GetDetails()
 196         // which copy/overwrites the
 197         // 'runtime' copy of this structure
 198         uint32_t chipid_cidr;
 199         const char *name;
 200
 201         unsigned n_gpnvms;
 202 #define SAM3_N_NVM_BITS 3
 203         unsigned  gpnvm[SAM3_N_NVM_BITS];
 204         unsigned  total_flash_size;
 205         unsigned  total_sram_size;
 206         unsigned  n_banks;
 207 #define SAM3_MAX_FLASH_BANKS 2
 208         // these are "initialized" from the global const data
 209         struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
 210 };
 211
 212
 213 struct sam3_chip {
 214         struct sam3_chip *next;
 215         int    probed;
 216
 217         // this is "initialized" from the global const structure
 218         struct sam3_chip_details details;
 219         struct target *target;
 220         struct sam3_cfg cfg;
 221 };
 222
 223
 224 struct sam3_reg_list {
 225         uint32_t address;  size_t struct_offset; const char *name;
 226         void (*explain_func)(struct sam3_chip *pInfo);
 227 };
 228
 229
 230 static struct sam3_chip *all_sam3_chips;
 231
 232 static struct sam3_chip *
 233 get_current_sam3(struct command_context *cmd_ctx)
 234 {
 235         struct target *t;
 236         static struct sam3_chip *p;
 237
 238         t = get_current_target(cmd_ctx);
 239         if (!t) {
 240                 command_print(cmd_ctx, "No current target?");
 241                 return NULL;
 242         }
 243
 244         p = all_sam3_chips;
 245         if (!p) {
 246                 // this should not happen
 247                 // the command is not registered until the chip is created?
 248                 command_print(cmd_ctx, "No SAM3 chips exist?");
 249                 return NULL;
 250         }
 251
 252         while (p) {
 253                 if (p->target == t) {
 254                         return p;
 255                 }
 256                 p = p->next;
 257         }
 258         command_print(cmd_ctx, "Cannot find SAM3 chip?");
 259         return NULL;
 260 }
 261
 262
 263 // these are used to *initialize* the "pChip->details" structure.
 264 static const struct sam3_chip_details all_sam3_details[] = {
 265         // Start at91sam3u* series
 266         {
 267                 .chipid_cidr    = 0x28100960,
 268                 .name           = "at91sam3u4e",
 269                 .total_flash_size     = 256 * 1024,
 270                 .total_sram_size      = 52 * 1024,
 271                 .n_gpnvms       = 3,
 272                 .n_banks        = 2,
 273
 274                 // System boots at address 0x0
 275                 // gpnvm[1] = selects boot code
 276                 //     if gpnvm[1] == 0
 277                 //         boot is via "SAMBA" (rom)
 278                 //     else
 279                 //         boot is via FLASH
 280                 //         Selection is via gpnvm[2]
 281                 //     endif
 282                 //
 283                 // NOTE: banks 0 & 1 switch places
 284                 //     if gpnvm[2] == 0
 285                 //         Bank0 is the boot rom
 286                 //      else
 287                 //         Bank1 is the boot rom
 288                 //      endif
 289 //              .bank[0] = {
 290                 {
 291                   {
 292                         .probed = 0,
 293                         .pChip  = NULL,
 294                         .pBank  = NULL,
 295                         .bank_number = 0,
 296                         .base_address = FLASH_BANK0_BASE_U,
 297                         .controller_address = 0x400e0800,
 298                         .present = 1,
 299                         .size_bytes = 128 * 1024,
 300                         .nsectors   = 16,
 301                         .sector_size = 8192,
 302                         .page_size   = 256,
 303                   },
 304
 305 //              .bank[1] = {
 306                   {
 307                         .probed = 0,
 308                         .pChip  = NULL,
 309                         .pBank  = NULL,
 310                         .bank_number = 1,
 311                         .base_address = FLASH_BANK1_BASE_U,
 312                         .controller_address = 0x400e0a00,
 313                         .present = 1,
 314                         .size_bytes = 128 * 1024,
 315                         .nsectors   = 16,
 316                         .sector_size = 8192,
 317                         .page_size   = 256,
 318                   },
 319                 },
 320         },
 321
 322         {
 323                 .chipid_cidr    = 0x281a0760,
 324                 .name           = "at91sam3u2e",
 325                 .total_flash_size     = 128 * 1024,
 326                 .total_sram_size      =  36 * 1024,
 327                 .n_gpnvms       = 2,
 328                 .n_banks        = 1,
 329
 330                 // System boots at address 0x0
 331                 // gpnvm[1] = selects boot code
 332                 //     if gpnvm[1] == 0
 333                 //         boot is via "SAMBA" (rom)
 334                 //     else
 335                 //         boot is via FLASH
 336                 //         Selection is via gpnvm[2]
 337                 //     endif
 338 //              .bank[0] = {
 339                 {
 340                   {
 341                         .probed = 0,
 342                         .pChip  = NULL,
 343                         .pBank  = NULL,
 344                         .bank_number = 0,
 345                         .base_address = FLASH_BANK0_BASE_U,
 346                         .controller_address = 0x400e0800,
 347                         .present = 1,
 348                         .size_bytes = 128 * 1024,
 349                         .nsectors   = 16,
 350                         .sector_size = 8192,
 351                         .page_size   = 256,
 352                   },
 353 //                .bank[1] = {
 354                   {
 355                         .present = 0,
 356                         .probed = 0,
 357                         .bank_number = 1,
 358                   },
 359                 },
 360         },
 361         {
 362                 .chipid_cidr    = 0x28190560,
 363                 .name           = "at91sam3u1e",
 364                 .total_flash_size     = 64 * 1024,
 365                 .total_sram_size      = 20 * 1024,
 366                 .n_gpnvms       = 2,
 367                 .n_banks        = 1,
 368
 369                 // System boots at address 0x0
 370                 // gpnvm[1] = selects boot code
 371                 //     if gpnvm[1] == 0
 372                 //         boot is via "SAMBA" (rom)
 373                 //     else
 374                 //         boot is via FLASH
 375                 //         Selection is via gpnvm[2]
 376                 //     endif
 377                 //
 378
 379 //              .bank[0] = {
 380                 {
 381                   {
 382                         .probed = 0,
 383                         .pChip  = NULL,
 384                         .pBank  = NULL,
 385                         .bank_number = 0,
 386                         .base_address = FLASH_BANK0_BASE_U,
 387                         .controller_address = 0x400e0800,
 388                         .present = 1,
 389                         .size_bytes =  64 * 1024,
 390                         .nsectors   =  8,
 391                         .sector_size = 8192,
 392                         .page_size   = 256,
 393                   },
 394
 395 //              .bank[1] = {
 396                   {
 397                         .present = 0,
 398                         .probed = 0,
 399                         .bank_number = 1,
 400                   },
 401                 },
 402         },
 403
 404         {
 405                 .chipid_cidr    = 0x28000960,
 406                 .name           = "at91sam3u4c",
 407                 .total_flash_size     = 256 * 1024,
 408                 .total_sram_size      = 52 * 1024,
 409                 .n_gpnvms       = 3,
 410                 .n_banks        = 2,
 411
 412                 // System boots at address 0x0
 413                 // gpnvm[1] = selects boot code
 414                 //     if gpnvm[1] == 0
 415                 //         boot is via "SAMBA" (rom)
 416                 //     else
 417                 //         boot is via FLASH
 418                 //         Selection is via gpnvm[2]
 419                 //     endif
 420                 //
 421                 // NOTE: banks 0 & 1 switch places
 422                 //     if gpnvm[2] == 0
 423                 //         Bank0 is the boot rom
 424                 //      else
 425                 //         Bank1 is the boot rom
 426                 //      endif
 427                 {
 428                   {
 429 //              .bank[0] = {
 430                         .probed = 0,
 431                         .pChip  = NULL,
 432                         .pBank  = NULL,
 433                         .bank_number = 0,
 434                         .base_address = FLASH_BANK0_BASE_U,
 435                         .controller_address = 0x400e0800,
 436                         .present = 1,
 437                         .size_bytes = 128 * 1024,
 438                         .nsectors   = 16,
 439                         .sector_size = 8192,
 440                         .page_size   = 256,
 441                   },
 442 //              .bank[1] = {
 443                   {
 444                         .probed = 0,
 445                         .pChip  = NULL,
 446                         .pBank  = NULL,
 447                         .bank_number = 1,
 448                         .base_address = FLASH_BANK1_BASE_U,
 449                         .controller_address = 0x400e0a00,
 450                         .present = 1,
 451                         .size_bytes = 128 * 1024,
 452                         .nsectors   = 16,
 453                         .sector_size = 8192,
 454                         .page_size   = 256,
 455                   },
 456                 },
 457         },
 458
 459         {
 460                 .chipid_cidr    = 0x280a0760,
 461                 .name           = "at91sam3u2c",
 462                 .total_flash_size     = 128 * 1024,
 463                 .total_sram_size      = 36 * 1024,
 464                 .n_gpnvms       = 2,
 465                 .n_banks        = 1,
 466
 467                 // System boots at address 0x0
 468                 // gpnvm[1] = selects boot code
 469                 //     if gpnvm[1] == 0
 470                 //         boot is via "SAMBA" (rom)
 471                 //     else
 472                 //         boot is via FLASH
 473                 //         Selection is via gpnvm[2]
 474                 //     endif
 475                 {
 476 //              .bank[0] = {
 477                   {
 478                         .probed = 0,
 479                         .pChip  = NULL,
 480                         .pBank  = NULL,
 481                         .bank_number = 0,
 482                         .base_address = FLASH_BANK0_BASE_U,
 483                         .controller_address = 0x400e0800,
 484                         .present = 1,
 485                         .size_bytes = 128 * 1024,
 486                         .nsectors   = 16,
 487                         .sector_size = 8192,
 488                         .page_size   = 256,
 489                   },
 490 //              .bank[1] = {
 491                   {
 492                         .present = 0,
 493                         .probed = 0,
 494                         .bank_number = 1,
 495                   },
 496                 },
 497         },
 498         {
 499                 .chipid_cidr    = 0x28090560,
 500                 .name           = "at91sam3u1c",
 501                 .total_flash_size     = 64 * 1024,
 502                 .total_sram_size      = 20 * 1024,
 503                 .n_gpnvms       = 2,
 504                 .n_banks        = 1,
 505
 506                 // System boots at address 0x0
 507                 // gpnvm[1] = selects boot code
 508                 //     if gpnvm[1] == 0
 509                 //         boot is via "SAMBA" (rom)
 510                 //     else
 511                 //         boot is via FLASH
 512                 //         Selection is via gpnvm[2]
 513                 //     endif
 514                 //
 515
 516                 {
 517 //              .bank[0] = {
 518                   {
 519                         .probed = 0,
 520                         .pChip  = NULL,
 521                         .pBank  = NULL,
 522                         .bank_number = 0,
 523                         .base_address = FLASH_BANK0_BASE_U,
 524                         .controller_address = 0x400e0800,
 525                         .present = 1,
 526                         .size_bytes =  64 * 1024,
 527                         .nsectors   =  8,
 528                         .sector_size = 8192,
 529                         .page_size   = 256,
 530                   },
 531 //              .bank[1] = {
 532                   {
 533                         .present = 0,
 534                         .probed = 0,
 535                         .bank_number = 1,
 536
 537                   },
 538                 },
 539         },
 540
 541         // Start at91sam3s* series
 542
 543         // Note: The preliminary at91sam3s datasheet says on page 302
 544         // that the flash controller is at address 0x400E0800.
 545         // This is _not_ the case, the controller resides at address 0x400e0a0.
 546         {
 547                 .chipid_cidr    = 0x28A00960,
 548                 .name           = "at91sam3s4c",
 549                 .total_flash_size     = 256 * 1024,
 550                 .total_sram_size      = 48 * 1024,
 551                 .n_gpnvms       = 2,
 552                 .n_banks        = 1,
 553                 {
 554 //              .bank[0] = {
 555                   {
 556                         .probed = 0,
 557                         .pChip  = NULL,
 558                         .pBank  = NULL,
 559                         .bank_number = 0,
 560                         .base_address = FLASH_BANK_BASE_S,
 561
 562                         .controller_address = 0x400e0a00,
 563                         .present = 1,
 564                         .size_bytes =  256 * 1024,
 565                         .nsectors   =  32,
 566                         .sector_size = 8192,
 567                         .page_size   = 256,
 568                   },
 569 //              .bank[1] = {
 570                   {
 571                         .present = 0,
 572                         .probed = 0,
 573                         .bank_number = 1,
 574
 575                   },
 576                 },
 577         },
 578
 579         {
 580                 .chipid_cidr    = 0x28900960,
 581                 .name           = "at91sam3s4b",
 582                 .total_flash_size     = 256 * 1024,
 583                 .total_sram_size      = 48 * 1024,
 584                 .n_gpnvms       = 2,
 585                 .n_banks        = 1,
 586                 {
 587 //              .bank[0] = {
 588                   {
 589                         .probed = 0,
 590                         .pChip  = NULL,
 591                         .pBank  = NULL,
 592                         .bank_number = 0,
 593                         .base_address = FLASH_BANK_BASE_S,
 594
 595                         .controller_address = 0x400e0a00,
 596                         .present = 1,
 597                         .size_bytes =  256 * 1024,
 598                         .nsectors   =  32,
 599                         .sector_size = 8192,
 600                         .page_size   = 256,
 601                   },
 602 //              .bank[1] = {
 603                   {
 604                         .present = 0,
 605                         .probed = 0,
 606                         .bank_number = 1,
 607
 608                   },
 609                 },
 610         },
 611         {
 612                 .chipid_cidr    = 0x28800960,
 613                 .name           = "at91sam3s4a",
 614                 .total_flash_size     = 256 * 1024,
 615                 .total_sram_size      = 48 * 1024,
 616                 .n_gpnvms       = 2,
 617                 .n_banks        = 1,
 618                 {
 619 //              .bank[0] = {
 620                   {
 621                         .probed = 0,
 622                         .pChip  = NULL,
 623                         .pBank  = NULL,
 624                         .bank_number = 0,
 625                         .base_address = FLASH_BANK_BASE_S,
 626
 627                         .controller_address = 0x400e0a00,
 628                         .present = 1,
 629                         .size_bytes =  256 * 1024,
 630                         .nsectors   =  32,
 631                         .sector_size = 8192,
 632                         .page_size   = 256,
 633                   },
 634 //              .bank[1] = {
 635                   {
 636                         .present = 0,
 637                         .probed = 0,
 638                         .bank_number = 1,
 639
 640                   },
 641                 },
 642         },
 643         {
 644                 .chipid_cidr    = 0x28AA0760,
 645                 .name           = "at91sam3s2c",
 646                 .total_flash_size     = 128 * 1024,
 647                 .total_sram_size      = 32 * 1024,
 648                 .n_gpnvms       = 2,
 649                 .n_banks        = 1,
 650                 {
 651 //              .bank[0] = {
 652                   {
 653                         .probed = 0,
 654                         .pChip  = NULL,
 655                         .pBank  = NULL,
 656                         .bank_number = 0,
 657                         .base_address = FLASH_BANK_BASE_S,
 658
 659                         .controller_address = 0x400e0a00,
 660                         .present = 1,
 661                         .size_bytes =  128 * 1024,
 662                         .nsectors   =  16,
 663                         .sector_size = 8192,
 664                         .page_size   = 256,
 665                   },
 666 //              .bank[1] = {
 667                   {
 668                         .present = 0,
 669                         .probed = 0,
 670                         .bank_number = 1,
 671
 672                   },
 673                 },
 674         },
 675         {
 676                 .chipid_cidr    = 0x289A0760,
 677                 .name           = "at91sam3s2b",
 678                 .total_flash_size     = 128 * 1024,
 679                 .total_sram_size      = 32 * 1024,
 680                 .n_gpnvms       = 2,
 681                 .n_banks        = 1,
 682                 {
 683 //              .bank[0] = {
 684                   {
 685                         .probed = 0,
 686                         .pChip  = NULL,
 687                         .pBank  = NULL,
 688                         .bank_number = 0,
 689                         .base_address = FLASH_BANK_BASE_S,
 690
 691                         .controller_address = 0x400e0a00,
 692                         .present = 1,
 693                         .size_bytes =  128 * 1024,
 694                         .nsectors   =  16,
 695                         .sector_size = 8192,
 696                         .page_size   = 256,
 697                   },
 698 //              .bank[1] = {
 699                   {
 700                         .present = 0,
 701                         .probed = 0,
 702                         .bank_number = 1,
 703
 704                   },
 705                 },
 706         },
 707         {
 708                 .chipid_cidr    = 0x288A0760,
 709                 .name           = "at91sam3s2a",
 710                 .total_flash_size     = 128 * 1024,
 711                 .total_sram_size      = 32 * 1024,
 712                 .n_gpnvms       = 2,
 713                 .n_banks        = 1,
 714                 {
 715 //              .bank[0] = {
 716                   {
 717                         .probed = 0,
 718                         .pChip  = NULL,
 719                         .pBank  = NULL,
 720                         .bank_number = 0,
 721                         .base_address = FLASH_BANK_BASE_S,
 722
 723                         .controller_address = 0x400e0a00,
 724                         .present = 1,
 725                         .size_bytes =  128 * 1024,
 726                         .nsectors   =  16,
 727                         .sector_size = 8192,
 728                         .page_size   = 256,
 729                   },
 730 //              .bank[1] = {
 731                   {
 732                         .present = 0,
 733                         .probed = 0,
 734                         .bank_number = 1,
 735
 736                   },
 737                 },
 738         },
 739         {
 740                 .chipid_cidr    = 0x28A90560,
 741                 .name           = "at91sam3s1c",
 742                 .total_flash_size     = 64 * 1024,
 743                 .total_sram_size      = 16 * 1024,
 744                 .n_gpnvms       = 2,
 745                 .n_banks        = 1,
 746                 {
 747 //              .bank[0] = {
 748                   {
 749                         .probed = 0,
 750                         .pChip  = NULL,
 751                         .pBank  = NULL,
 752                         .bank_number = 0,
 753                         .base_address = FLASH_BANK_BASE_S,
 754
 755                         .controller_address = 0x400e0a00,
 756                         .present = 1,
 757                         .size_bytes =  64 * 1024,
 758                         .nsectors   =  8,
 759                         .sector_size = 8192,
 760                         .page_size   = 256,
 761                   },
 762 //              .bank[1] = {
 763                   {
 764                         .present = 0,
 765                         .probed = 0,
 766                         .bank_number = 1,
 767
 768                   },
 769                 },
 770         },
 771         {
 772                 .chipid_cidr    = 0x28990560,
 773                 .name           = "at91sam3s1b",
 774                 .total_flash_size     = 64 * 1024,
 775                 .total_sram_size      = 16 * 1024,
 776                 .n_gpnvms       = 2,
 777                 .n_banks        = 1,
 778                 {
 779 //              .bank[0] = {
 780                   {
 781                         .probed = 0,
 782                         .pChip  = NULL,
 783                         .pBank  = NULL,
 784                         .bank_number = 0,
 785                         .base_address = FLASH_BANK_BASE_S,
 786
 787                         .controller_address = 0x400e0a00,
 788                         .present = 1,
 789                         .size_bytes =  64 * 1024,
 790                         .nsectors   =  8,
 791                         .sector_size = 8192,
 792                         .page_size   = 256,
 793                   },
 794 //              .bank[1] = {
 795                   {
 796                         .present = 0,
 797                         .probed = 0,
 798                         .bank_number = 1,
 799
 800                   },
 801                 },
 802         },
 803         {
 804                 .chipid_cidr    = 0x28890560,
 805                 .name           = "at91sam3s1a",
 806                 .total_flash_size     = 64 * 1024,
 807                 .total_sram_size      = 16 * 1024,
 808                 .n_gpnvms       = 2,
 809                 .n_banks        = 1,
 810                 {
 811 //              .bank[0] = {
 812                   {
 813                         .probed = 0,
 814                         .pChip  = NULL,
 815                         .pBank  = NULL,
 816                         .bank_number = 0,
 817                         .base_address = FLASH_BANK_BASE_S,
 818
 819                         .controller_address = 0x400e0a00,
 820                         .present = 1,
 821                         .size_bytes =  64 * 1024,
 822                         .nsectors   =  8,
 823                         .sector_size = 8192,
 824                         .page_size   = 256,
 825                   },
 826 //              .bank[1] = {
 827                   {
 828                         .present = 0,
 829                         .probed = 0,
 830                         .bank_number = 1,
 831
 832                   },
 833                 },
 834         },
 835         // terminate
 836         {
 837                 .chipid_cidr    = 0,
 838                 .name                   = NULL,
 839         }
 840 };
 841
 842 /* Globals above */
 843 /***********************************************************************
 844  **********************************************************************
 845  **********************************************************************
 846  **********************************************************************
 847  **********************************************************************
 848  **********************************************************************/
 849 /* *ATMEL* style code - from the SAM3 driver code */
 850
 851 /**
 852  * Get the current status of the EEFC and
 853  * the value of some status bits (LOCKE, PROGE).
 854  * @param pPrivate - info about the bank
 855  * @param v        - result goes here
 856  */
 857 static int
 858 EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
 859 {
 860         int r;
 861         r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FSR, v);
 862         LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
 863                           (unsigned int)(*v),
 864                           ((unsigned int)((*v >> 2) & 1)),
 865                           ((unsigned int)((*v >> 1) & 1)),
 866                           ((unsigned int)((*v >> 0) & 1)));
 867
 868         return r;
 869 }
 870
 871 /**
 872  * Get the result of the last executed command.
 873  * @param pPrivate - info about the bank
 874  * @param v        - result goes here
 875  */
 876 static int
 877 EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
 878 {
 879         int r;
 880         uint32_t rv;
 881         r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FRR, &rv);
 882         if (v) {
 883                 *v = rv;
 884         }
 885         LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
 886         return r;
 887 }
 888
 889 static int
 890 EFC_StartCommand(struct sam3_bank_private *pPrivate,
 891                                  unsigned command, unsigned argument)
 892 {
 893         uint32_t n,v;
 894         int r;
 895         int retry;
 896
 897         retry = 0;
 898  do_retry:
 899
 900     // Check command & argument
 901     switch (command) {
 902
 903         case AT91C_EFC_FCMD_WP:
 904         case AT91C_EFC_FCMD_WPL:
 905         case AT91C_EFC_FCMD_EWP:
 906         case AT91C_EFC_FCMD_EWPL:
 907                 // case AT91C_EFC_FCMD_EPL:
 908                 // case AT91C_EFC_FCMD_EPA:
 909         case AT91C_EFC_FCMD_SLB:
 910         case AT91C_EFC_FCMD_CLB:
 911                 n = (pPrivate->size_bytes / pPrivate->page_size);
 912                 if (argument >= n) {
 913                         LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
 914                 }
 915                 break;
 916
 917         case AT91C_EFC_FCMD_SFB:
 918         case AT91C_EFC_FCMD_CFB:
 919                 if (argument >= pPrivate->pChip->details.n_gpnvms) {
 920                         LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
 921                                           pPrivate->pChip->details.n_gpnvms);
 922                 }
 923                 break;
 924
 925         case AT91C_EFC_FCMD_GETD:
 926         case AT91C_EFC_FCMD_EA:
 927         case AT91C_EFC_FCMD_GLB:
 928         case AT91C_EFC_FCMD_GFB:
 929         case AT91C_EFC_FCMD_STUI:
 930         case AT91C_EFC_FCMD_SPUI:
 931                 if (argument != 0) {
 932                         LOG_ERROR("Argument is meaningless for cmd: %d", command);
 933                 }
 934                 break;
 935         default:
 936                 LOG_ERROR("Unknown command %d", command);
 937                 break;
 938     }
 939
 940         if (command == AT91C_EFC_FCMD_SPUI) {
 941                 // this is a very special situation.
 942                 // Situation (1) - error/retry - see below
 943                 //      And we are being called recursively
 944                 // Situation (2) - normal, finished reading unique id
 945         } else {
 946                 // it should be "ready"
 947                 EFC_GetStatus(pPrivate, &v);
 948                 if (v & 1) {
 949                         // then it is ready
 950                         // we go on
 951                 } else {
 952                         if (retry) {
 953                                 // we have done this before
 954                                 // the controller is not responding.
 955                                 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate->bank_number);
 956                                 return ERROR_FAIL;
 957                         } else {
 958                                 retry++;
 959                                 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
 960                                                   pPrivate->bank_number);
 961                                 // we do that by issuing the *STOP* command
 962                                 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
 963                                 // above is recursive, and further recursion is blocked by
 964                                 // if (command == AT91C_EFC_FCMD_SPUI) above
 965                                 goto do_retry;
 966                         }
 967                 }
 968         }
 969
 970         v = (0x5A << 24) | (argument << 8) | command;
 971         LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
 972         r = target_write_u32(pPrivate->pBank->target,
 973                                                   pPrivate->controller_address + offset_EFC_FCR,
 974                                                   v);
 975         if (r != ERROR_OK) {
 976                 LOG_DEBUG("Error Write failed");
 977         }
 978         return r;
 979 }
 980
 981 /**
 982  * Performs the given command and wait until its completion (or an error).
 983  * @param pPrivate - info about the bank
 984  * @param command  - Command to perform.
 985  * @param argument - Optional command argument.
 986  * @param status   - put command status bits here
 987  */
 988 static int
 989 EFC_PerformCommand(struct sam3_bank_private *pPrivate,
 990                                         unsigned command,
 991                                         unsigned argument,
 992                                         uint32_t *status)
 993 {
 994
 995         int r;
 996         uint32_t v;
 997         long long ms_now, ms_end;
 998
 999         // default
1000         if (status) {
1001                 *status = 0;
1002         }
1003
1004         r = EFC_StartCommand(pPrivate, command, argument);
1005         if (r != ERROR_OK) {
1006                 return r;
1007         }
1008
1009         ms_end = 500 + timeval_ms();
1010
1011
1012     do {
1013                 r = EFC_GetStatus(pPrivate, &v);
1014                 if (r != ERROR_OK) {
1015                         return r;
1016                 }
1017                 ms_now = timeval_ms();
1018                 if (ms_now > ms_end) {
1019                         // error
1020                         LOG_ERROR("Command timeout");
1021                         return ERROR_FAIL;
1022                 }
1023     }
1024     while ((v & 1) == 0)
1025                 ;
1026
1027         // error bits..
1028         if (status) {
1029                 *status = (v & 0x6);
1030         }
1031         return ERROR_OK;
1032
1033 }
1034
1035
1036
1037
1038
1039 /**
1040  * Read the unique ID.
1041  * @param pPrivate - info about the bank
1042  * The unique ID is stored in the 'pPrivate' structure.
1043  */
1044 static int
1045 FLASHD_ReadUniqueID (struct sam3_bank_private *pPrivate)
1046 {
1047         int r;
1048         uint32_t v;
1049         int x;
1050         // assume 0
1051     pPrivate->pChip->cfg.unique_id[0] = 0;
1052     pPrivate->pChip->cfg.unique_id[1] = 0;
1053     pPrivate->pChip->cfg.unique_id[2] = 0;
1054     pPrivate->pChip->cfg.unique_id[3] = 0;
1055
1056         LOG_DEBUG("Begin");
1057         r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1058         if (r < 0) {
1059                 return r;
1060         }
1061
1062         for (x = 0 ; x < 4 ; x++) {
1063                 r = target_read_u32(pPrivate->pChip->target,
1064                                                          pPrivate->pBank->base + (x * 4),
1065                                                          &v);
1066                 if (r < 0) {
1067                         return r;
1068                 }
1069                 pPrivate->pChip->cfg.unique_id[x] = v;
1070         }
1071
1072     r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1073         LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1074                           r,
1075                           (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1076                           (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1077                           (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1078                           (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1079         return r;
1080
1081 }
1082
1083 /**
1084  * Erases the entire flash.
1085  * @param pPrivate - the info about the bank.
1086  */
1087 static int
1088 FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
1089 {
1090         LOG_DEBUG("Here");
1091         return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1092 }
1093
1094
1095
1096 /**
1097  * Gets current GPNVM state.
1098  * @param pPrivate - info about the bank.
1099  * @param gpnvm    -  GPNVM bit index.
1100  * @param puthere  - result stored here.
1101  */
1102 //------------------------------------------------------------------------------
1103 static int
1104 FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1105 {
1106         uint32_t v;
1107         int r;
1108
1109         LOG_DEBUG("Here");
1110         if (pPrivate->bank_number != 0) {
1111                 LOG_ERROR("GPNVM only works with Bank0");
1112                 return ERROR_FAIL;
1113         }
1114
1115         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1116                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1117                                   gpnvm,pPrivate->pChip->details.n_gpnvms);
1118                 return ERROR_FAIL;
1119         }
1120
1121     // Get GPNVMs status
1122         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1123         if (r != ERROR_OK) {
1124                 LOG_ERROR("Failed");
1125                 return r;
1126         }
1127
1128     r = EFC_GetResult(pPrivate, &v);
1129
1130         if (puthere) {
1131                 // Check if GPNVM is set
1132                 // get the bit and make it a 0/1
1133                 *puthere = (v >> gpnvm) & 1;
1134         }
1135
1136         return r;
1137 }
1138
1139
1140
1141
1142 /**
1143  * Clears the selected GPNVM bit.
1144  * @param pPrivate info about the bank
1145  * @param gpnvm GPNVM index.
1146  * @returns 0 if successful; otherwise returns an error code.
1147  */
1148 static int
1149 FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1150 {
1151         int r;
1152         unsigned v;
1153
1154         LOG_DEBUG("Here");
1155         if (pPrivate->bank_number != 0) {
1156                 LOG_ERROR("GPNVM only works with Bank0");
1157                 return ERROR_FAIL;
1158         }
1159
1160         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1161                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1162                                   gpnvm,pPrivate->pChip->details.n_gpnvms);
1163                 return ERROR_FAIL;
1164         }
1165
1166         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1167         if (r != ERROR_OK) {
1168                 LOG_DEBUG("Failed: %d",r);
1169                 return r;
1170         }
1171         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1172         LOG_DEBUG("End: %d",r);
1173         return r;
1174 }
1175
1176
1177
1178 /**
1179  * Sets the selected GPNVM bit.
1180  * @param pPrivate info about the bank
1181  * @param gpnvm GPNVM index.
1182  */
1183 static int
1184 FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1185 {
1186         int r;
1187         unsigned v;
1188
1189         if (pPrivate->bank_number != 0) {
1190                 LOG_ERROR("GPNVM only works with Bank0");
1191                 return ERROR_FAIL;
1192         }
1193
1194         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1195                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1196                                   gpnvm,pPrivate->pChip->details.n_gpnvms);
1197                 return ERROR_FAIL;
1198         }
1199
1200         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1201         if (r != ERROR_OK) {
1202                 return r;
1203         }
1204         if (v) {
1205                 // already set
1206                 r = ERROR_OK;
1207         } else {
1208                 // set it
1209                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1210         }
1211         return r;
1212 }
1213
1214
1215 /**
1216  * Returns a bit field (at most 64) of locked regions within a page.
1217  * @param pPrivate info about the bank
1218  * @param v where to store locked bits
1219  */
1220 static int
1221 FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
1222 {
1223         int r;
1224         LOG_DEBUG("Here");
1225     r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1226         if (r == ERROR_OK) {
1227                 r = EFC_GetResult(pPrivate, v);
1228         }
1229         LOG_DEBUG("End: %d",r);
1230         return r;
1231 }
1232
1233
1234 /**
1235  * Unlocks all the regions in the given address range.
1236  * @param pPrivate info about the bank
1237  * @param start_sector first sector to unlock
1238  * @param end_sector last (inclusive) to unlock
1239  */
1240
1241 static int
1242 FLASHD_Unlock(struct sam3_bank_private *pPrivate,
1243                            unsigned start_sector,
1244                            unsigned end_sector)
1245 {
1246         int r;
1247         uint32_t status;
1248         uint32_t pg;
1249         uint32_t pages_per_sector;
1250
1251         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1252
1253     /* Unlock all pages */
1254     while (start_sector <= end_sector) {
1255                 pg = start_sector * pages_per_sector;
1256
1257         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1258         if (r != ERROR_OK) {
1259             return r;
1260         }
1261         start_sector++;
1262     }
1263
1264     return ERROR_OK;
1265 }
1266
1267
1268 /**
1269  * Locks regions
1270  * @param pPrivate - info about the bank
1271  * @param start_sector - first sector to lock
1272  * @param end_sector   - last sector (inclusive) to lock
1273  */
1274 static int
1275 FLASHD_Lock(struct sam3_bank_private *pPrivate,
1276                          unsigned start_sector,
1277                          unsigned end_sector)
1278 {
1279         uint32_t status;
1280         uint32_t pg;
1281         uint32_t pages_per_sector;
1282         int r;
1283
1284         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1285
1286     /* Lock all pages */
1287     while (start_sector <= end_sector) {
1288                 pg = start_sector * pages_per_sector;
1289
1290         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1291         if (r != ERROR_OK) {
1292             return r;
1293         }
1294         start_sector++;
1295     }
1296     return ERROR_OK;
1297 }
1298
1299
1300 /****** END SAM3 CODE ********/
1301
1302 /* begin helpful debug code */
1303 // print the fieldname, the field value, in dec & hex, and return field value
1304 static uint32_t
1305 sam3_reg_fieldname(struct sam3_chip *pChip,
1306                                         const char *regname,
1307                                         uint32_t value,
1308                                         unsigned shift,
1309                                         unsigned width)
1310 {
1311         uint32_t v;
1312         int hwidth, dwidth;
1313
1314
1315         // extract the field
1316         v = value >> shift;
1317         v = v & ((1 << width)-1);
1318         if (width <= 16) {
1319                 hwidth = 4;
1320                 dwidth = 5;
1321         } else {
1322                 hwidth = 8;
1323                 dwidth = 12;
1324         }
1325
1326         // show the basics
1327         LOG_USER_N("\t%*s: %*d [0x%0*x] ",
1328                                   REG_NAME_WIDTH, regname,
1329                                   dwidth, v,
1330                                   hwidth, v);
1331         return v;
1332 }
1333
1334
1335 static const char _unknown[] = "unknown";
1336 static const char * const eproc_names[] = {
1337         _unknown,                                       // 0
1338         "arm946es",                                     // 1
1339         "arm7tdmi",                                     // 2
1340         "cortex-m3",                            // 3
1341         "arm920t",                                      // 4
1342         "arm926ejs",                            // 5
1343         _unknown,                                       // 6
1344         _unknown,                                       // 7
1345         _unknown,                                       // 8
1346         _unknown,                                       // 9
1347         _unknown,                                       // 10
1348         _unknown,                                       // 11
1349         _unknown,                                       // 12
1350         _unknown,                                       // 13
1351         _unknown,                                       // 14
1352         _unknown,                                       // 15
1353 };
1354
1355 #define nvpsize2 nvpsize                // these two tables are identical
1356 static const char * const nvpsize[] = {
1357         "none",                                         //  0
1358         "8K bytes",                                     //  1
1359         "16K bytes",                            //  2
1360         "32K bytes",                            //  3
1361         _unknown,                                       //  4
1362         "64K bytes",                            //  5
1363         _unknown,                                       //  6
1364         "128K bytes",                           //  7
1365         _unknown,                                       //  8
1366         "256K bytes",                           //  9
1367         "512K bytes",                           // 10
1368         _unknown,                                       // 11
1369         "1024K bytes",                          // 12
1370         _unknown,                                       // 13
1371         "2048K bytes",                          // 14
1372         _unknown,                                       // 15
1373 };
1374
1375
1376 static const char * const sramsize[] = {
1377         "48K Bytes",                            //  0
1378         "1K Bytes",                                     //  1
1379         "2K Bytes",                                     //  2
1380         "6K Bytes",                                     //  3
1381         "112K Bytes",                           //  4
1382         "4K Bytes",                                     //  5
1383         "80K Bytes",                            //  6
1384         "160K Bytes",                           //  7
1385         "8K Bytes",                                     //  8
1386         "16K Bytes",                            //  9
1387         "32K Bytes",                            // 10
1388         "64K Bytes",                            // 11
1389         "128K Bytes",                           // 12
1390         "256K Bytes",                           // 13
1391         "96K Bytes",                            // 14
1392         "512K Bytes",                           // 15
1393
1394 };
1395
1396 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1397         { 0x19,  "AT91SAM9xx Series"                                            },
1398         { 0x29,  "AT91SAM9XExx Series"                                          },
1399         { 0x34,  "AT91x34 Series"                                                       },
1400         { 0x37,  "CAP7 Series"                                                          },
1401         { 0x39,  "CAP9 Series"                                                          },
1402         { 0x3B,  "CAP11 Series"                                                         },
1403         { 0x40,  "AT91x40 Series"                                                       },
1404         { 0x42,  "AT91x42 Series"                                                       },
1405         { 0x55,  "AT91x55 Series"                                                       },
1406         { 0x60,  "AT91SAM7Axx Series"                                           },
1407         { 0x61,  "AT91SAM7AQxx Series"                                          },
1408         { 0x63,  "AT91x63 Series"                                                       },
1409         { 0x70,  "AT91SAM7Sxx Series"                                           },
1410         { 0x71,  "AT91SAM7XCxx Series"                                          },
1411         { 0x72,  "AT91SAM7SExx Series"                                          },
1412         { 0x73,  "AT91SAM7Lxx Series"                                           },
1413         { 0x75,  "AT91SAM7Xxx Series"                                           },
1414         { 0x76,  "AT91SAM7SLxx Series"                                          },
1415         { 0x80,  "ATSAM3UxC Series (100-pin version)"           },
1416         { 0x81,  "ATSAM3UxE Series (144-pin version)"           },
1417         { 0x83,  "ATSAM3AxC Series (100-pin version)"           },
1418         { 0x84,  "ATSAM3XxC Series (100-pin version)"           },
1419         { 0x85,  "ATSAM3XxE Series (144-pin version)"           },
1420         { 0x86,  "ATSAM3XxG Series (208/217-pin version)"       },
1421         { 0x88,  "ATSAM3SxA Series (48-pin version)"            },
1422         { 0x89,  "ATSAM3SxB Series (64-pin version)"            },
1423         { 0x8A,  "ATSAM3SxC Series (100-pin version)"           },
1424         { 0x92,  "AT91x92 Series"                                                       },
1425         { 0xF0,  "AT75Cxx Series"                                                       },
1426         { -1, NULL },
1427
1428 };
1429
1430 static const char * const nvptype[] = {
1431         "rom", // 0
1432         "romless or onchip flash", // 1
1433         "embedded flash memory", // 2
1434         "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1435         "sram emulating flash", // 4
1436         _unknown, // 5
1437         _unknown, // 6
1438         _unknown, // 7
1439
1440 };
1441
1442 static const char *_yes_or_no(uint32_t v)
1443 {
1444         if (v) {
1445                 return "YES";
1446         } else {
1447                 return "NO";
1448         }
1449 }
1450
1451 static const char * const _rc_freq[] = {
1452         "4 MHz", "8 MHz", "12 MHz", "reserved"
1453 };
1454
1455 static void
1456 sam3_explain_ckgr_mor(struct sam3_chip *pChip)
1457 {
1458         uint32_t v;
1459         uint32_t rcen;
1460
1461         v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1462         LOG_USER_N("(main xtal enabled: %s)\n",
1463                                   _yes_or_no(v));
1464         v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1465         LOG_USER_N("(main osc bypass: %s)\n",
1466                                   _yes_or_no(v));
1467         rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
1468         LOG_USER_N("(onchip RC-OSC enabled: %s)\n",
1469                                   _yes_or_no(rcen));
1470         v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1471         LOG_USER_N("(onchip RC-OSC freq: %s)\n",
1472                                   _rc_freq[v]);
1473
1474         pChip->cfg.rc_freq = 0;
1475         if (rcen) {
1476                 switch (v) {
1477                 default:
1478                         pChip->cfg.rc_freq = 0;
1479                 case 0:
1480                         pChip->cfg.rc_freq = 4 * 1000 * 1000;
1481                         break;
1482                 case 1:
1483                         pChip->cfg.rc_freq = 8 * 1000 * 1000;
1484                         break;
1485                 case 2:
1486                         pChip->cfg.rc_freq = 12* 1000 * 1000;
1487                         break;
1488                 }
1489         }
1490
1491         v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1492         LOG_USER_N("(startup clks, time= %f uSecs)\n",
1493                                   ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1494         v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1495         LOG_USER_N("(mainosc source: %s)\n",
1496                                   v ? "external xtal" : "internal RC");
1497
1498         v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1499         LOG_USER_N("(clock failure enabled: %s)\n",
1500                                  _yes_or_no(v));
1501 }
1502
1503
1504
1505 static void
1506 sam3_explain_chipid_cidr(struct sam3_chip *pChip)
1507 {
1508         int x;
1509         uint32_t v;
1510         const char *cp;
1511
1512         sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1513         LOG_USER_N("\n");
1514
1515         v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1516         LOG_USER_N("%s\n", eproc_names[v]);
1517
1518         v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1519         LOG_USER_N("%s\n", nvpsize[v]);
1520
1521         v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1522         LOG_USER_N("%s\n", nvpsize2[v]);
1523
1524         v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
1525         LOG_USER_N("%s\n", sramsize[ v ]);
1526
1527         v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1528         cp = _unknown;
1529         for (x = 0 ; archnames[x].name ; x++) {
1530                 if (v == archnames[x].value) {
1531                         cp = archnames[x].name;
1532                         break;
1533                 }
1534         }
1535
1536         LOG_USER_N("%s\n", cp);
1537
1538         v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1539         LOG_USER_N("%s\n", nvptype[ v ]);
1540
1541         v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1542         LOG_USER_N("(exists: %s)\n", _yes_or_no(v));
1543 }
1544
1545 static void
1546 sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
1547 {
1548         uint32_t v;
1549
1550
1551         v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1552         LOG_USER_N("(main ready: %s)\n", _yes_or_no(v));
1553
1554         v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1555
1556         v = (v * pChip->cfg.slow_freq) / 16;
1557         pChip->cfg.mainosc_freq = v;
1558
1559         LOG_USER_N("(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1560                                  _tomhz(v),
1561                                  pChip->cfg.slow_freq / 1000,
1562                                  pChip->cfg.slow_freq % 1000);
1563
1564 }
1565
1566 static void
1567 sam3_explain_ckgr_plla(struct sam3_chip *pChip)
1568 {
1569         uint32_t mula,diva;
1570
1571         diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1572         LOG_USER_N("\n");
1573         mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1574         LOG_USER_N("\n");
1575         pChip->cfg.plla_freq = 0;
1576         if (mula == 0) {
1577                 LOG_USER_N("\tPLLA Freq: (Disabled,mula = 0)\n");
1578         } else if (diva == 0) {
1579                 LOG_USER_N("\tPLLA Freq: (Disabled,diva = 0)\n");
1580         } else if (diva == 1) {
1581                 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
1582                 LOG_USER_N("\tPLLA Freq: %3.03f MHz\n",
1583                                          _tomhz(pChip->cfg.plla_freq));
1584         }
1585 }
1586
1587
1588 static void
1589 sam3_explain_mckr(struct sam3_chip *pChip)
1590 {
1591         uint32_t css, pres, fin = 0;
1592         int pdiv = 0;
1593         const char *cp = NULL;
1594
1595         css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1596         switch (css & 3) {
1597         case 0:
1598                 fin = pChip->cfg.slow_freq;
1599                 cp = "slowclk";
1600                 break;
1601         case 1:
1602                 fin = pChip->cfg.mainosc_freq;
1603                 cp  = "mainosc";
1604                 break;
1605         case 2:
1606                 fin = pChip->cfg.plla_freq;
1607                 cp  = "plla";
1608                 break;
1609         case 3:
1610                 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1611                         fin = 480 * 1000 * 1000;
1612                         cp = "upll";
1613                 } else {
1614                         fin = 0;
1615                         cp  = "upll (*ERROR* UPLL is disabled)";
1616                 }
1617                 break;
1618         default:
1619                 assert(0);
1620                 break;
1621         }
1622
1623         LOG_USER_N("%s (%3.03f Mhz)\n",
1624                                   cp,
1625                                   _tomhz(fin));
1626         pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1627         switch (pres & 0x07) {
1628         case 0:
1629                 pdiv = 1;
1630                 cp = "selected clock";
1631         case 1:
1632                 pdiv = 2;
1633                 cp = "clock/2";
1634                 break;
1635         case 2:
1636                 pdiv = 4;
1637                 cp = "clock/4";
1638                 break;
1639         case 3:
1640                 pdiv = 8;
1641                 cp = "clock/8";
1642                 break;
1643         case 4:
1644                 pdiv = 16;
1645                 cp = "clock/16";
1646                 break;
1647         case 5:
1648                 pdiv = 32;
1649                 cp = "clock/32";
1650                 break;
1651         case 6:
1652                 pdiv = 64;
1653                 cp = "clock/64";
1654                 break;
1655         case 7:
1656                 pdiv = 6;
1657                 cp = "clock/6";
1658                 break;
1659         default:
1660                 assert(0);
1661                 break;
1662         }
1663         LOG_USER_N("(%s)\n", cp);
1664         fin = fin / pdiv;
1665         // sam3 has a *SINGLE* clock -
1666         // other at91 series parts have divisors for these.
1667         pChip->cfg.cpu_freq = fin;
1668         pChip->cfg.mclk_freq = fin;
1669         pChip->cfg.fclk_freq = fin;
1670         LOG_USER_N("\t\tResult CPU Freq: %3.03f\n",
1671                                   _tomhz(fin));
1672 }
1673
1674 #if 0
1675 static struct sam3_chip *
1676 target2sam3(struct target *pTarget)
1677 {
1678         struct sam3_chip *pChip;
1679
1680         if (pTarget == NULL) {
1681                 return NULL;
1682         }
1683
1684         pChip = all_sam3_chips;
1685         while (pChip) {
1686                 if (pChip->target == pTarget) {
1687                         break; // return below
1688                 } else {
1689                         pChip = pChip->next;
1690                 }
1691         }
1692         return pChip;
1693 }
1694 #endif
1695
1696 static uint32_t *
1697 sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
1698 {
1699         // this function exists to help
1700         // keep funky offsetof() errors
1701         // and casting from causing bugs
1702
1703         // By using prototypes - we can detect what would
1704         // be casting errors.
1705
1706         return ((uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset));
1707 }
1708
1709
1710 #define SAM3_ENTRY(NAME, FUNC)  { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1711 static const struct sam3_reg_list sam3_all_regs[] = {
1712         SAM3_ENTRY(CKGR_MOR , sam3_explain_ckgr_mor),
1713         SAM3_ENTRY(CKGR_MCFR , sam3_explain_ckgr_mcfr),
1714         SAM3_ENTRY(CKGR_PLLAR , sam3_explain_ckgr_plla),
1715         SAM3_ENTRY(CKGR_UCKR , NULL),
1716         SAM3_ENTRY(PMC_FSMR , NULL),
1717         SAM3_ENTRY(PMC_FSPR , NULL),
1718         SAM3_ENTRY(PMC_IMR , NULL),
1719         SAM3_ENTRY(PMC_MCKR , sam3_explain_mckr),
1720         SAM3_ENTRY(PMC_PCK0 , NULL),
1721         SAM3_ENTRY(PMC_PCK1 , NULL),
1722         SAM3_ENTRY(PMC_PCK2 , NULL),
1723         SAM3_ENTRY(PMC_PCSR , NULL),
1724         SAM3_ENTRY(PMC_SCSR , NULL),
1725         SAM3_ENTRY(PMC_SR , NULL),
1726         SAM3_ENTRY(CHIPID_CIDR , sam3_explain_chipid_cidr),
1727         SAM3_ENTRY(CHIPID_EXID , NULL),
1728         SAM3_ENTRY(SUPC_CR, NULL),
1729
1730         // TERMINATE THE LIST
1731         { .name = NULL }
1732 };
1733 #undef SAM3_ENTRY
1734
1735
1736
1737
1738 static struct sam3_bank_private *
1739 get_sam3_bank_private(struct flash_bank *bank)
1740 {
1741         return (struct sam3_bank_private *)(bank->driver_priv);
1742 }
1743
1744 /**
1745  * Given a pointer to where it goes in the structure,
1746  * determine the register name, address from the all registers table.
1747  */
1748 static const struct sam3_reg_list *
1749 sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
1750 {
1751         const struct sam3_reg_list *pReg;
1752
1753         pReg = &(sam3_all_regs[0]);
1754         while (pReg->name) {
1755                 uint32_t *pPossible;
1756
1757                 // calculate where this one go..
1758                 // it is "possibly" this register.
1759
1760                 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1761
1762                 // well? Is it this register
1763                 if (pPossible == goes_here) {
1764                         // Jump for joy!
1765                         return pReg;
1766                 }
1767
1768                 // next...
1769                 pReg++;
1770         }
1771         // This is *TOTAL*PANIC* - we are totally screwed.
1772         LOG_ERROR("INVALID SAM3 REGISTER");
1773         return NULL;
1774 }
1775
1776
1777 static int
1778 sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
1779 {
1780         const struct sam3_reg_list *pReg;
1781         int r;
1782
1783         pReg = sam3_GetReg(pChip, goes_here);
1784         if (!pReg) {
1785                 return ERROR_FAIL;
1786         }
1787
1788         r = target_read_u32(pChip->target, pReg->address, goes_here);
1789         if (r != ERROR_OK) {
1790                 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1791                                   pReg->name, (unsigned)(pReg->address), r);
1792         }
1793         return r;
1794 }
1795
1796
1797
1798 static int
1799 sam3_ReadAllRegs(struct sam3_chip *pChip)
1800 {
1801         int r;
1802         const struct sam3_reg_list *pReg;
1803
1804         pReg = &(sam3_all_regs[0]);
1805         while (pReg->name) {
1806                 r = sam3_ReadThisReg(pChip,
1807                                                                   sam3_get_reg_ptr(&(pChip->cfg), pReg));
1808                 if (r != ERROR_OK) {
1809                         LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1810                                           pReg->name, ((unsigned)(pReg->address)), r);
1811                         return r;
1812                 }
1813
1814                 pReg++;
1815         }
1816
1817         return ERROR_OK;
1818 }
1819
1820
1821 static int
1822 sam3_GetInfo(struct sam3_chip *pChip)
1823 {
1824         const struct sam3_reg_list *pReg;
1825         uint32_t regval;
1826
1827         pReg = &(sam3_all_regs[0]);
1828         while (pReg->name) {
1829                 // display all regs
1830                 LOG_DEBUG("Start: %s", pReg->name);
1831                 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
1832                 LOG_USER_N("%*s: [0x%08x] -> 0x%08x\n",
1833                                          REG_NAME_WIDTH,
1834                                          pReg->name,
1835                                          pReg->address,
1836                                          regval);
1837                 if (pReg->explain_func) {
1838                         (*(pReg->explain_func))(pChip);
1839                 }
1840                 LOG_DEBUG("End: %s", pReg->name);
1841                 pReg++;
1842         }
1843         LOG_USER_N("   rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
1844         LOG_USER_N("  mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
1845         LOG_USER_N("     plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
1846         LOG_USER_N(" cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
1847         LOG_USER_N("mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
1848
1849
1850         LOG_USER_N(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1851                                   pChip->cfg.unique_id[0],
1852                                   pChip->cfg.unique_id[1],
1853                                   pChip->cfg.unique_id[2],
1854                                   pChip->cfg.unique_id[3]);
1855
1856
1857         return ERROR_OK;
1858 }
1859
1860
1861 static int
1862 sam3_erase_check(struct flash_bank *bank)
1863 {
1864         int x;
1865
1866         LOG_DEBUG("Here");
1867         if (bank->target->state != TARGET_HALTED) {
1868                 LOG_ERROR("Target not halted");
1869                 return ERROR_TARGET_NOT_HALTED;
1870         }
1871         if (0 == bank->num_sectors) {
1872                 LOG_ERROR("Target: not supported/not probed\n");
1873                 return ERROR_FAIL;
1874         }
1875
1876         LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1877         for (x = 0 ; x < bank->num_sectors ; x++) {
1878                 bank->sectors[x].is_erased = 1;
1879         }
1880
1881         LOG_DEBUG("Done");
1882         return ERROR_OK;
1883 }
1884
1885 static int
1886 sam3_protect_check(struct flash_bank *bank)
1887 {
1888         int r;
1889         uint32_t v=0;
1890         unsigned x;
1891         struct sam3_bank_private *pPrivate;
1892
1893         LOG_DEBUG("Begin");
1894         if (bank->target->state != TARGET_HALTED) {
1895                 LOG_ERROR("Target not halted");
1896                 return ERROR_TARGET_NOT_HALTED;
1897         }
1898
1899         pPrivate = get_sam3_bank_private(bank);
1900         if (!pPrivate) {
1901                 LOG_ERROR("no private for this bank?");
1902                 return ERROR_FAIL;
1903         }
1904         if (!(pPrivate->probed)) {
1905                 return ERROR_FLASH_BANK_NOT_PROBED;
1906         }
1907
1908         r = FLASHD_GetLockBits(pPrivate , &v);
1909         if (r != ERROR_OK) {
1910                 LOG_DEBUG("Failed: %d",r);
1911                 return r;
1912         }
1913
1914         for (x = 0 ; x < pPrivate->nsectors ; x++) {
1915                 bank->sectors[x].is_protected = (!!(v & (1 << x)));
1916         }
1917         LOG_DEBUG("Done");
1918         return ERROR_OK;
1919 }
1920
1921 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
1922 {
1923         struct sam3_chip *pChip;
1924
1925         pChip = all_sam3_chips;
1926
1927         // is this an existing chip?
1928         while (pChip) {
1929                 if (pChip->target == bank->target) {
1930                         break;
1931                 }
1932                 pChip = pChip->next;
1933         }
1934
1935         if (!pChip) {
1936                 // this is a *NEW* chip
1937                 pChip = calloc(1, sizeof(struct sam3_chip));
1938                 if (!pChip) {
1939                         LOG_ERROR("NO RAM!");
1940                         return ERROR_FAIL;
1941                 }
1942                 pChip->target = bank->target;
1943                 // insert at head
1944                 pChip->next = all_sam3_chips;
1945                 all_sam3_chips = pChip;
1946                 pChip->target = bank->target;
1947                 // assumption is this runs at 32khz
1948                 pChip->cfg.slow_freq = 32768;
1949                 pChip->probed = 0;
1950         }
1951
1952         switch (bank->base) {
1953         default:
1954                 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
1955                         [at91sam3u series] or 0x%08x [at91sam3s series])",
1956                                   ((unsigned int)(bank->base)),
1957                                   ((unsigned int)(FLASH_BANK0_BASE_U)),
1958                                   ((unsigned int)(FLASH_BANK1_BASE_U)),
1959                                   ((unsigned int)(FLASH_BANK_BASE_S)));
1960                 return ERROR_FAIL;
1961                 break;
1962
1963         // at91sam3u series
1964         case FLASH_BANK0_BASE_U:
1965                 bank->driver_priv = &(pChip->details.bank[0]);
1966                 bank->bank_number = 0;
1967                 pChip->details.bank[0].pChip = pChip;
1968                 pChip->details.bank[0].pBank = bank;
1969                 break;
1970         case FLASH_BANK1_BASE_U:
1971                 bank->driver_priv = &(pChip->details.bank[1]);
1972                 bank->bank_number = 1;
1973                 pChip->details.bank[1].pChip = pChip;
1974                 pChip->details.bank[1].pBank = bank;
1975
1976         // at91sam3s series
1977         case FLASH_BANK_BASE_S:
1978                 bank->driver_priv = &(pChip->details.bank[0]);
1979                 bank->bank_number = 0;
1980                 pChip->details.bank[0].pChip = pChip;
1981                 pChip->details.bank[0].pBank = bank;
1982                 break;
1983         }
1984
1985         // we initialize after probing.
1986         return ERROR_OK;
1987 }
1988
1989 static int
1990 sam3_GetDetails(struct sam3_bank_private *pPrivate)
1991 {
1992         const struct sam3_chip_details *pDetails;
1993         struct sam3_chip *pChip;
1994         struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
1995         unsigned x;
1996
1997         LOG_DEBUG("Begin");
1998         pDetails = all_sam3_details;
1999         while (pDetails->name) {
2000                 if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) {
2001                         break;
2002                 } else {
2003                         pDetails++;
2004                 }
2005         }
2006         if (pDetails->name == NULL) {
2007                 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
2008                                   (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2009                 // Help the victim, print details about the chip
2010                 LOG_INFO_N("SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
2011                                                 pPrivate->pChip->cfg.CHIPID_CIDR);
2012                 sam3_explain_chipid_cidr(pPrivate->pChip);
2013                 return ERROR_FAIL;
2014         }
2015
2016         // DANGER: THERE ARE DRAGONS HERE
2017
2018         // get our pChip - it is going
2019         // to be over-written shortly
2020         pChip = pPrivate->pChip;
2021
2022         // Note that, in reality:
2023         //
2024         //     pPrivate = &(pChip->details.bank[0])
2025         // or  pPrivate = &(pChip->details.bank[1])
2026         //
2027
2028         // save the "bank" pointers
2029         for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2030                 saved_banks[ x ] = pChip->details.bank[x].pBank;
2031         }
2032
2033         // Overwrite the "details" structure.
2034         memcpy(&(pPrivate->pChip->details),
2035                         pDetails,
2036                         sizeof(pPrivate->pChip->details));
2037
2038         // now fix the ghosted pointers
2039         for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2040                 pChip->details.bank[x].pChip = pChip;
2041                 pChip->details.bank[x].pBank = saved_banks[x];
2042         }
2043
2044         // update the *BANK*SIZE*
2045
2046         LOG_DEBUG("End");
2047         return ERROR_OK;
2048 }
2049
2050
2051
2052 static int
2053 _sam3_probe(struct flash_bank *bank, int noise)
2054 {
2055         unsigned x;
2056         int r;
2057         struct sam3_bank_private *pPrivate;
2058
2059
2060         LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2061         if (bank->target->state != TARGET_HALTED)
2062         {
2063                 LOG_ERROR("Target not halted");
2064                 return ERROR_TARGET_NOT_HALTED;
2065         }
2066
2067         pPrivate = get_sam3_bank_private(bank);
2068         if (!pPrivate) {
2069                 LOG_ERROR("Invalid/unknown bank number\n");
2070                 return ERROR_FAIL;
2071         }
2072
2073         r = sam3_ReadAllRegs(pPrivate->pChip);
2074         if (r != ERROR_OK) {
2075                 return r;
2076         }
2077
2078
2079         LOG_DEBUG("Here");
2080         if (pPrivate->pChip->probed) {
2081                 r = sam3_GetInfo(pPrivate->pChip);
2082         } else {
2083                 r = sam3_GetDetails(pPrivate);
2084         }
2085         if (r != ERROR_OK) {
2086                 return r;
2087         }
2088
2089         // update the flash bank size
2090         for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2091                 if (bank->base == pPrivate->pChip->details.bank[0].base_address) {
2092                         bank->size =  pPrivate->pChip->details.bank[0].size_bytes;
2093                         break;
2094                 }
2095         }
2096
2097         if (bank->sectors == NULL) {
2098                 bank->sectors     = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2099                 if (bank->sectors == NULL) {
2100                         LOG_ERROR("No memory!");
2101                         return ERROR_FAIL;
2102                 }
2103                 bank->num_sectors = pPrivate->nsectors;
2104
2105                 for (x = 0 ; ((int)(x)) < bank->num_sectors ; x++) {
2106                         bank->sectors[x].size         = pPrivate->sector_size;
2107                         bank->sectors[x].offset       = x * (pPrivate->sector_size);
2108                         // mark as unknown
2109                         bank->sectors[x].is_erased    = -1;
2110                         bank->sectors[x].is_protected = -1;
2111                 }
2112         }
2113
2114         pPrivate->probed = 1;
2115
2116         r = sam3_protect_check(bank);
2117         if (r != ERROR_OK) {
2118                 return r;
2119         }
2120
2121         LOG_DEBUG("Bank = %d, nbanks = %d",
2122                           pPrivate->bank_number , pPrivate->pChip->details.n_banks);
2123         if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2124                 // read unique id,
2125                 // it appears to be associated with the *last* flash bank.
2126                 FLASHD_ReadUniqueID(pPrivate);
2127         }
2128
2129         return r;
2130 }
2131
2132 static int
2133 sam3_probe(struct flash_bank *bank)
2134 {
2135         return _sam3_probe(bank, 1);
2136 }
2137
2138 static int
2139 sam3_auto_probe(struct flash_bank *bank)
2140 {
2141         return _sam3_probe(bank, 0);
2142 }
2143
2144
2145
2146 static int
2147 sam3_erase(struct flash_bank *bank, int first, int last)
2148 {
2149         struct sam3_bank_private *pPrivate;
2150         int r;
2151
2152         LOG_DEBUG("Here");
2153         if (bank->target->state != TARGET_HALTED) {
2154                 LOG_ERROR("Target not halted");
2155                 return ERROR_TARGET_NOT_HALTED;
2156         }
2157
2158         r = sam3_auto_probe(bank);
2159         if (r != ERROR_OK) {
2160                 LOG_DEBUG("Here,r=%d",r);
2161                 return r;
2162         }
2163
2164         pPrivate = get_sam3_bank_private(bank);
2165         if (!(pPrivate->probed)) {
2166                 return ERROR_FLASH_BANK_NOT_PROBED;
2167         }
2168
2169         if ((first == 0) && ((last + 1)== ((int)(pPrivate->nsectors)))) {
2170                 // whole chip
2171                 LOG_DEBUG("Here");
2172                 return FLASHD_EraseEntireBank(pPrivate);
2173         }
2174         LOG_INFO("sam3 auto-erases while programing (request ignored)");
2175         return ERROR_OK;
2176 }
2177
2178 static int
2179 sam3_protect(struct flash_bank *bank, int set, int first, int last)
2180 {
2181         struct sam3_bank_private *pPrivate;
2182         int r;
2183
2184         LOG_DEBUG("Here");
2185         if (bank->target->state != TARGET_HALTED) {
2186                 LOG_ERROR("Target not halted");
2187                 return ERROR_TARGET_NOT_HALTED;
2188         }
2189
2190         pPrivate = get_sam3_bank_private(bank);
2191         if (!(pPrivate->probed)) {
2192                 return ERROR_FLASH_BANK_NOT_PROBED;
2193         }
2194
2195         if (set) {
2196                 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2197         } else {
2198                 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2199         }
2200         LOG_DEBUG("End: r=%d",r);
2201
2202         return r;
2203
2204 }
2205
2206
2207 static int
2208 sam3_info(struct flash_bank *bank, char *buf, int buf_size)
2209 {
2210         if (bank->target->state != TARGET_HALTED) {
2211                 LOG_ERROR("Target not halted");
2212                 return ERROR_TARGET_NOT_HALTED;
2213         }
2214         buf[ 0 ] = 0;
2215         return ERROR_OK;
2216 }
2217
2218 static int
2219 sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2220 {
2221         uint32_t adr;
2222         int r;
2223
2224         adr = pagenum * pPrivate->page_size;
2225         adr += adr + pPrivate->base_address;
2226
2227         r = target_read_memory(pPrivate->pChip->target,
2228                                                         adr,
2229                                                         4, /* THIS*MUST*BE* in 32bit values */
2230                                                         pPrivate->page_size / 4,
2231                                                         buf);
2232         if (r != ERROR_OK) {
2233                 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr));
2234         }
2235         return r;
2236 }
2237
2238 // The code below is basically this:
2239 // compiled with
2240 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
2241 //
2242 // Only the *CPU* can write to the flash buffer.
2243 // the DAP cannot... so - we download this 28byte thing
2244 // Run the algorithm - (below)
2245 // to program the device
2246 //
2247 // ========================================
2248 // #include <stdint.h>
2249 //
2250 // struct foo {
2251 //   uint32_t *dst;
2252 //   const uint32_t *src;
2253 //   int   n;
2254 //   volatile uint32_t *base;
2255 //   uint32_t   cmd;
2256 // };
2257 //
2258 //
2259 // uint32_t sam3_function(struct foo *p)
2260 // {
2261 //   volatile uint32_t *v;
2262 //   uint32_t *d;
2263 //   const uint32_t *s;
2264 //   int   n;
2265 //   uint32_t r;
2266 //
2267 //   d = p->dst;
2268 //   s = p->src;
2269 //   n = p->n;
2270 //
2271 //   do {
2272 //     *d++ = *s++;
2273 //   } while (--n)
2274 //     ;
2275 //
2276 //   v = p->base;
2277 //
2278 //   v[ 1 ] = p->cmd;
2279 //   do {
2280 //     r = v[8/4];
2281 //   } while (!(r&1))
2282 //     ;
2283 //   return r;
2284 // }
2285 // ========================================
2286
2287
2288
2289 static const uint8_t
2290 sam3_page_write_opcodes[] = {
2291         //  24 0000 0446                mov     r4, r0
2292         0x04,0x46,
2293         //  25 0002 6168                ldr     r1, [r4, #4]
2294         0x61,0x68,
2295         //  26 0004 0068                ldr     r0, [r0, #0]
2296         0x00,0x68,
2297         //  27 0006 A268                ldr     r2, [r4, #8]
2298         0xa2,0x68,
2299         //  28                          @ lr needed for prologue
2300         //  29                  .L2:
2301         //  30 0008 51F8043B            ldr     r3, [r1], #4
2302         0x51,0xf8,0x04,0x3b,
2303         //  31 000c 12F1FF32            adds    r2, r2, #-1
2304         0x12,0xf1,0xff,0x32,
2305         //  32 0010 40F8043B            str     r3, [r0], #4
2306         0x40,0xf8,0x04,0x3b,
2307         //  33 0014 F8D1                bne     .L2
2308         0xf8,0xd1,
2309         //  34 0016 E268                ldr     r2, [r4, #12]
2310         0xe2,0x68,
2311         //  35 0018 2369                ldr     r3, [r4, #16]
2312         0x23,0x69,
2313         //  36 001a 5360                str     r3, [r2, #4]
2314         0x53,0x60,
2315         //  37 001c 0832                adds    r2, r2, #8
2316         0x08,0x32,
2317         //  38                  .L4:
2318         //  39 001e 1068                ldr     r0, [r2, #0]
2319         0x10,0x68,
2320         //  40 0020 10F0010F            tst     r0, #1
2321         0x10,0xf0,0x01,0x0f,
2322         //  41 0024 FBD0                beq     .L4
2323         0xfb,0xd0,
2324         0x00,0xBE                               /* bkpt #0 */
2325 };
2326
2327
2328 static int
2329 sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2330 {
2331         uint32_t adr;
2332         uint32_t status;
2333         int r;
2334
2335         adr = pagenum * pPrivate->page_size;
2336         adr += (adr + pPrivate->base_address);
2337
2338         LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2339         r = target_write_memory(pPrivate->pChip->target,
2340                                                          adr,
2341                                                          4, /* THIS*MUST*BE* in 32bit values */
2342                                                          pPrivate->page_size / 4,
2343                                                          buf);
2344         if (r != ERROR_OK) {
2345                 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr));
2346                 return r;
2347         }
2348
2349         r = EFC_PerformCommand(pPrivate,
2350                                                         // send Erase & Write Page
2351                                                         AT91C_EFC_FCMD_EWP,
2352                                                         pagenum,
2353                                                         &status);
2354
2355         if (r != ERROR_OK) {
2356                 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr));
2357         }
2358         if (status & (1 << 2)) {
2359                 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2360                 return ERROR_FAIL;
2361         }
2362         if (status & (1 << 1)) {
2363                 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2364                 return ERROR_FAIL;
2365         }
2366         return ERROR_OK;
2367 }
2368
2369
2370
2371
2372
2373 static int
2374 sam3_write(struct flash_bank *bank,
2375                    uint8_t *buffer,
2376                    uint32_t offset,
2377                    uint32_t count)
2378 {
2379         int n;
2380         unsigned page_cur;
2381         unsigned page_end;
2382         int r;
2383         unsigned page_offset;
2384         struct sam3_bank_private *pPrivate;
2385         uint8_t *pagebuffer;
2386
2387         // incase we bail further below, set this to null
2388         pagebuffer = NULL;
2389
2390         // ignore dumb requests
2391         if (count == 0) {
2392                 r = ERROR_OK;
2393                 goto done;
2394         }
2395
2396         if (bank->target->state != TARGET_HALTED) {
2397                 LOG_ERROR("Target not halted");
2398                 r = ERROR_TARGET_NOT_HALTED;
2399                 goto done;
2400         }
2401
2402         pPrivate = get_sam3_bank_private(bank);
2403         if (!(pPrivate->probed)) {
2404                 r = ERROR_FLASH_BANK_NOT_PROBED;
2405                 goto done;
2406         }
2407
2408
2409         if ((offset + count) > pPrivate->size_bytes) {
2410                 LOG_ERROR("Flash write error - past end of bank");
2411                 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2412                                   (unsigned int)(offset),
2413                                   (unsigned int)(count),
2414                                   (unsigned int)(pPrivate->size_bytes));
2415                 r = ERROR_FAIL;
2416                 goto done;
2417         }
2418
2419         pagebuffer = malloc(pPrivate->page_size);
2420         if( !pagebuffer ){
2421                 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2422                 r = ERROR_FAIL;
2423                 goto done;
2424         }
2425
2426         // what page do we start & end in?
2427         page_cur = offset / pPrivate->page_size;
2428         page_end = (offset + count - 1) / pPrivate->page_size;
2429
2430         LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2431         LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2432
2433         // Special case: all one page
2434         //
2435         // Otherwise:
2436         //    (1) non-aligned start
2437         //    (2) body pages
2438         //    (3) non-aligned end.
2439
2440         // Handle special case - all one page.
2441         if (page_cur == page_end) {
2442                 LOG_DEBUG("Special case, all in one page");
2443                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2444                 if (r != ERROR_OK) {
2445                         goto done;
2446                 }
2447
2448                 page_offset = (offset & (pPrivate->page_size-1));
2449                 memcpy(pagebuffer + page_offset,
2450                                 buffer,
2451                                 count);
2452
2453                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2454                 if (r != ERROR_OK) {
2455                         goto done;
2456                 }
2457                 r = ERROR_OK;
2458                 goto done;
2459         }
2460
2461         // non-aligned start
2462         page_offset = offset & (pPrivate->page_size - 1);
2463         if (page_offset) {
2464                 LOG_DEBUG("Not-Aligned start");
2465                 // read the partial
2466                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2467                 if (r != ERROR_OK) {
2468                         goto done;
2469                 }
2470
2471                 // over-write with new data
2472                 n = (pPrivate->page_size - page_offset);
2473                 memcpy(pagebuffer + page_offset,
2474                                 buffer,
2475                                 n);
2476
2477                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2478                 if (r != ERROR_OK) {
2479                         goto done;
2480                 }
2481
2482                 count  -= n;
2483                 offset += n;
2484                 buffer += n;
2485                 page_cur++;
2486         }
2487
2488         // intermediate large pages
2489         // also - the final *terminal*
2490         // if that terminal page is a full page
2491         LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2492                           (int)page_cur, (int)page_end, (unsigned int)(count));
2493
2494         while ((page_cur < page_end) &&
2495                    (count >= pPrivate->page_size)) {
2496                 r = sam3_page_write(pPrivate, page_cur, buffer);
2497                 if (r != ERROR_OK) {
2498                         goto done;
2499                 }
2500                 count    -= pPrivate->page_size;
2501                 buffer   += pPrivate->page_size;
2502                 page_cur += 1;
2503         }
2504
2505         // terminal partial page?
2506         if (count) {
2507                 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2508                 // we have a partial page
2509                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2510                 if (r != ERROR_OK) {
2511                         goto done;
2512                 }
2513                 // data goes at start
2514                 memcpy(pagebuffer, buffer, count);
2515                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2516                 if (r != ERROR_OK) {
2517                         goto done;
2518                 }
2519                 buffer += count;
2520                 count  -= count;
2521         }
2522         LOG_DEBUG("Done!");
2523         r = ERROR_OK;
2524  done:
2525         if( pagebuffer ){
2526                 free(pagebuffer);
2527         }
2528         return r;
2529 }
2530
2531 COMMAND_HANDLER(sam3_handle_info_command)
2532 {
2533         struct sam3_chip *pChip;
2534         unsigned x;
2535         int r;
2536
2537         pChip = get_current_sam3(CMD_CTX);
2538         if (!pChip) {
2539                 return ERROR_OK;
2540         }
2541
2542         r = 0;
2543
2544         // bank0 must exist before we can do anything
2545         if (pChip->details.bank[0].pBank == NULL) {
2546                 x = 0;
2547         need_define:
2548                 command_print(CMD_CTX,
2549                                            "Please define bank %d via command: flash bank %s ... ",
2550                                            x,
2551                                            at91sam3_flash.name);
2552                 return ERROR_FAIL;
2553         }
2554
2555         // if bank 0 is not probed, then probe it
2556         if (!(pChip->details.bank[0].probed)) {
2557                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2558                 if (r != ERROR_OK) {
2559                         return ERROR_FAIL;
2560                 }
2561         }
2562         // above guarantees the "chip details" structure is valid
2563         // and thus, bank private areas are valid
2564         // and we have a SAM3 chip, what a concept!
2565
2566
2567         // auto-probe other banks, 0 done above
2568     for (x = 1 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2569                 // skip banks not present
2570                 if (!(pChip->details.bank[x].present)) {
2571                         continue;
2572                 }
2573
2574                 if (pChip->details.bank[x].pBank == NULL) {
2575                         goto need_define;
2576                 }
2577
2578                 if (pChip->details.bank[x].probed) {
2579                         continue;
2580                 }
2581
2582                 r = sam3_auto_probe(pChip->details.bank[x].pBank);
2583                 if (r != ERROR_OK) {
2584                         return r;
2585                 }
2586         }
2587
2588
2589         r = sam3_GetInfo(pChip);
2590         if (r != ERROR_OK) {
2591                 LOG_DEBUG("Sam3Info, Failed %d\n",r);
2592                 return r;
2593         }
2594
2595         return ERROR_OK;
2596 }
2597
2598 COMMAND_HANDLER(sam3_handle_gpnvm_command)
2599 {
2600         unsigned x,v;
2601         int r,who;
2602         struct sam3_chip *pChip;
2603
2604         pChip = get_current_sam3(CMD_CTX);
2605         if (!pChip) {
2606                 return ERROR_OK;
2607         }
2608
2609         if (pChip->target->state != TARGET_HALTED) {
2610                 LOG_ERROR("sam3 - target not halted");
2611                 return ERROR_TARGET_NOT_HALTED;
2612         }
2613
2614
2615         if (pChip->details.bank[0].pBank == NULL) {
2616                 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2617                                            at91sam3_flash.name);
2618                 return ERROR_FAIL;
2619         }
2620         if (!pChip->details.bank[0].probed) {
2621                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2622                 if (r != ERROR_OK) {
2623                         return r;
2624                 }
2625         }
2626
2627
2628         switch (CMD_ARGC) {
2629         default:
2630                 command_print(CMD_CTX,"Too many parameters\n");
2631                 return ERROR_COMMAND_SYNTAX_ERROR;
2632                 break;
2633         case 0:
2634                 who = -1;
2635                 goto showall;
2636                 break;
2637         case 1:
2638                 who = -1;
2639                 break;
2640         case 2:
2641                 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all"))) {
2642                         who = -1;
2643                 } else {
2644                         uint32_t v32;
2645                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2646                         who = v32;
2647                 }
2648                 break;
2649         }
2650
2651         if (0 == strcmp("show", CMD_ARGV[0])) {
2652                 if (who == -1) {
2653 showall:
2654                         r = ERROR_OK;
2655                         for (x = 0 ; x < pChip->details.n_gpnvms ; x++) {
2656                                 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2657                                 if (r != ERROR_OK) {
2658                                         break;
2659                                 }
2660                                 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
2661                         }
2662                         return r;
2663                 }
2664                 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2665                         r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2666                         command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
2667                         return r;
2668                 } else {
2669                         command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
2670                         return ERROR_COMMAND_SYNTAX_ERROR;
2671                 }
2672         }
2673
2674         if (who == -1) {
2675                 command_print(CMD_CTX, "Missing GPNVM number");
2676                 return ERROR_COMMAND_SYNTAX_ERROR;
2677         }
2678
2679         if (0 == strcmp("set", CMD_ARGV[0])) {
2680                 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2681         } else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
2682                            (0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both
2683                 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2684         } else {
2685                 command_print(CMD_CTX, "Unkown command: %s", CMD_ARGV[0]);
2686                 r = ERROR_COMMAND_SYNTAX_ERROR;
2687         }
2688         return r;
2689 }
2690
2691 COMMAND_HANDLER(sam3_handle_slowclk_command)
2692 {
2693         struct sam3_chip *pChip;
2694
2695         pChip = get_current_sam3(CMD_CTX);
2696         if (!pChip) {
2697                 return ERROR_OK;
2698         }
2699
2700
2701         switch (CMD_ARGC) {
2702         case 0:
2703                 // show
2704                 break;
2705         case 1:
2706         {
2707                 // set
2708                 uint32_t v;
2709                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
2710                 if (v > 200000) {
2711                         // absurd slow clock of 200Khz?
2712                         command_print(CMD_CTX,"Absurd/illegal slow clock freq: %d\n", (int)(v));
2713                         return ERROR_COMMAND_SYNTAX_ERROR;
2714                 }
2715                 pChip->cfg.slow_freq = v;
2716                 break;
2717         }
2718         default:
2719                 // error
2720                 command_print(CMD_CTX,"Too many parameters");
2721                 return ERROR_COMMAND_SYNTAX_ERROR;
2722                 break;
2723         }
2724         command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
2725                                    (int)(pChip->cfg.slow_freq/ 1000),
2726                                    (int)(pChip->cfg.slow_freq% 1000));
2727         return ERROR_OK;
2728 }
2729
2730 static const struct command_registration at91sam3_exec_command_handlers[] = {
2731         {
2732                 .name = "gpnvm",
2733                 .handler = sam3_handle_gpnvm_command,
2734                 .mode = COMMAND_EXEC,
2735                 .usage = "[('clr'|'set'|'show') bitnum]",
2736                 .help = "Without arguments, shows all bits in the gpnvm "
2737                         "register.  Otherwise, clears, sets, or shows one "
2738                         "General Purpose Non-Volatile Memory (gpnvm) bit.",
2739         },
2740         {
2741                 .name = "info",
2742                 .handler = sam3_handle_info_command,
2743                 .mode = COMMAND_EXEC,
2744                 .help = "Print information about the current at91sam3 chip"
2745                         "and its flash configuration.",
2746         },
2747         {
2748                 .name = "slowclk",
2749                 .handler = sam3_handle_slowclk_command,
2750                 .mode = COMMAND_EXEC,
2751                 .usage = "[clock_hz]",
2752                 .help = "Display or set the slowclock frequency "
2753                         "(default 32768 Hz).",
2754         },
2755         COMMAND_REGISTRATION_DONE
2756 };
2757 static const struct command_registration at91sam3_command_handlers[] = {
2758         {
2759                 .name = "at91sam3",
2760                 .mode = COMMAND_ANY,
2761                 .help = "at91sam3 flash command group",
2762                 .chain = at91sam3_exec_command_handlers,
2763         },
2764         COMMAND_REGISTRATION_DONE
2765 };
2766
2767 struct flash_driver at91sam3_flash = {
2768         .name = "at91sam3",
2769         .commands = at91sam3_command_handlers,
2770         .flash_bank_command = sam3_flash_bank_command,
2771         .erase = sam3_erase,
2772         .protect = sam3_protect,
2773         .write = sam3_write,
2774         .read = default_flash_read,
2775         .probe = sam3_probe,
2776         .auto_probe = sam3_auto_probe,
2777         .erase_check = sam3_erase_check,
2778         .protect_check = sam3_protect_check,
2779         .info = sam3_info,
2780 };