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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Duane Ellis                                     *
   3  *   openocd@duaneellis.com                                                *
   4  *                                                                         *
   5  *   Copyright (C) 2010 by Olaf Lüke (at91sam3s* support)                  *
   6  *   olaf@uni-paderborn.de                                                 *
   7  *                                                                                                                                                 *
   8  *   Copyright (C) 2011 by Olivier Schonken (at91sam3x* support)           *                                          *
   9  *                     and Jim Norris                                      *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24 ****************************************************************************/
  25
  26 /* Some of the the lower level code was based on code supplied by
  27  * ATMEL under this copyright. */
  28
  29 /* BEGIN ATMEL COPYRIGHT */
  30 /* ----------------------------------------------------------------------------
  31  *         ATMEL Microcontroller Software Support
  32  * ----------------------------------------------------------------------------
  33  * Copyright (c) 2009, Atmel Corporation
  34  *
  35  * All rights reserved.
  36  *
  37  * Redistribution and use in source and binary forms, with or without
  38  * modification, are permitted provided that the following conditions are met:
  39  *
  40  * - Redistributions of source code must retain the above copyright notice,
  41  * this list of conditions and the disclaimer below.
  42  *
  43  * Atmel's name may not be used to endorse or promote products derived from
  44  * this software without specific prior written permission.
  45  *
  46  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  47  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  48  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  49  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  50  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  51  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  52  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  53  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  54  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  55  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  56  * ----------------------------------------------------------------------------
  57  */
  58 /* END ATMEL COPYRIGHT */
  59
  60 #ifdef HAVE_CONFIG_H
  61 #include "config.h"
  62 #endif
  63
  64 #include "imp.h"
  65 #include <helper/time_support.h>
  66
  67 #define REG_NAME_WIDTH  (12)
  68
  69 /* at91sam3u series (has one or two flash banks) */
  70 #define FLASH_BANK0_BASE_U   0x00080000
  71 #define FLASH_BANK1_BASE_U   0x00100000
  72
  73 /* at91sam3s series (has always one flash bank) */
  74 #define FLASH_BANK_BASE_S   0x00400000
  75
  76 /* at91sam3n series (has always one flash bank) */
  77 #define FLASH_BANK_BASE_N   0x00400000
  78
  79 /* at91sam3a/x series has two flash banks*/
  80 #define FLASH_BANK0_BASE_AX                     0x00080000
  81 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
  82 #define FLASH_BANK1_BASE_256K_AX        0x000A0000
  83 #define FLASH_BANK1_BASE_512K_AX        0x000C0000
  84
  85 #define         AT91C_EFC_FCMD_GETD                 (0x0)       /* (EFC) Get Flash Descriptor */
  86 #define         AT91C_EFC_FCMD_WP                   (0x1)       /* (EFC) Write Page */
  87 #define         AT91C_EFC_FCMD_WPL                  (0x2)       /* (EFC) Write Page and Lock */
  88 #define         AT91C_EFC_FCMD_EWP                  (0x3)       /* (EFC) Erase Page and Write Page */
  89 #define         AT91C_EFC_FCMD_EWPL                 (0x4)       /* (EFC) Erase Page and Write Page
  90                                                                  * then Lock */
  91 #define         AT91C_EFC_FCMD_EA                   (0x5)       /* (EFC) Erase All */
  92 /* cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
  93 /* #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane? */
  94 /* cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
  95 /* #define      AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages? */
  96 #define         AT91C_EFC_FCMD_SLB                  (0x8)       /* (EFC) Set Lock Bit */
  97 #define         AT91C_EFC_FCMD_CLB                  (0x9)       /* (EFC) Clear Lock Bit */
  98 #define         AT91C_EFC_FCMD_GLB                  (0xA)       /* (EFC) Get Lock Bit */
  99 #define         AT91C_EFC_FCMD_SFB                  (0xB)       /* (EFC) Set Fuse Bit */
 100 #define         AT91C_EFC_FCMD_CFB                  (0xC)       /* (EFC) Clear Fuse Bit */
 101 #define         AT91C_EFC_FCMD_GFB                  (0xD)       /* (EFC) Get Fuse Bit */
 102 #define         AT91C_EFC_FCMD_STUI                 (0xE)       /* (EFC) Start Read Unique ID */
 103 #define         AT91C_EFC_FCMD_SPUI                 (0xF)       /* (EFC) Stop Read Unique ID */
 104
 105 #define  offset_EFC_FMR   0
 106 #define  offset_EFC_FCR   4
 107 #define  offset_EFC_FSR   8
 108 #define  offset_EFC_FRR   12
 109
 110 extern struct flash_driver at91sam3_flash;
 111
 112 static float _tomhz(uint32_t freq_hz)
 113 {
 114         float f;
 115
 116         f = ((float)(freq_hz)) / 1000000.0;
 117         return f;
 118 }
 119
 120 /* How the chip is configured. */
 121 struct sam3_cfg {
 122         uint32_t unique_id[4];
 123
 124         uint32_t slow_freq;
 125         uint32_t rc_freq;
 126         uint32_t mainosc_freq;
 127         uint32_t plla_freq;
 128         uint32_t mclk_freq;
 129         uint32_t cpu_freq;
 130         uint32_t fclk_freq;
 131         uint32_t pclk0_freq;
 132         uint32_t pclk1_freq;
 133         uint32_t pclk2_freq;
 134
 135
 136 #define SAM3_CHIPID_CIDR          (0x400E0740)
 137         uint32_t CHIPID_CIDR;
 138 #define SAM3_CHIPID_CIDR2         (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
 139         uint32_t CHIPID_CIDR2;
 140 #define SAM3_CHIPID_EXID          (0x400E0744)
 141         uint32_t CHIPID_EXID;
 142 #define SAM3_CHIPID_EXID2         (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
 143         uint32_t CHIPID_EXID2;
 144
 145
 146 #define SAM3_PMC_BASE             (0x400E0400)
 147 #define SAM3_PMC_SCSR             (SAM3_PMC_BASE + 0x0008)
 148         uint32_t PMC_SCSR;
 149 #define SAM3_PMC_PCSR             (SAM3_PMC_BASE + 0x0018)
 150         uint32_t PMC_PCSR;
 151 #define SAM3_CKGR_UCKR            (SAM3_PMC_BASE + 0x001c)
 152         uint32_t CKGR_UCKR;
 153 #define SAM3_CKGR_MOR             (SAM3_PMC_BASE + 0x0020)
 154         uint32_t CKGR_MOR;
 155 #define SAM3_CKGR_MCFR            (SAM3_PMC_BASE + 0x0024)
 156         uint32_t CKGR_MCFR;
 157 #define SAM3_CKGR_PLLAR           (SAM3_PMC_BASE + 0x0028)
 158         uint32_t CKGR_PLLAR;
 159 #define SAM3_PMC_MCKR             (SAM3_PMC_BASE + 0x0030)
 160         uint32_t PMC_MCKR;
 161 #define SAM3_PMC_PCK0             (SAM3_PMC_BASE + 0x0040)
 162         uint32_t PMC_PCK0;
 163 #define SAM3_PMC_PCK1             (SAM3_PMC_BASE + 0x0044)
 164         uint32_t PMC_PCK1;
 165 #define SAM3_PMC_PCK2             (SAM3_PMC_BASE + 0x0048)
 166         uint32_t PMC_PCK2;
 167 #define SAM3_PMC_SR               (SAM3_PMC_BASE + 0x0068)
 168         uint32_t PMC_SR;
 169 #define SAM3_PMC_IMR              (SAM3_PMC_BASE + 0x006c)
 170         uint32_t PMC_IMR;
 171 #define SAM3_PMC_FSMR             (SAM3_PMC_BASE + 0x0070)
 172         uint32_t PMC_FSMR;
 173 #define SAM3_PMC_FSPR             (SAM3_PMC_BASE + 0x0074)
 174         uint32_t PMC_FSPR;
 175 };
 176
 177 /*
 178  * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
 179  * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
 180  * the flash wait state (FWS) should be set to 6. It seems like that the
 181  * cause of the problem is not the flash itself, but the flash write
 182  * buffer. Ie the wait states have to be set before writing into the
 183  * buffer.
 184  * Tested and confirmed with SAM3N and SAM3U
 185  */
 186
 187 struct sam3_bank_private {
 188         int probed;
 189         /* DANGER: THERE ARE DRAGONS HERE.. */
 190         /* NOTE: If you add more 'ghost' pointers */
 191         /* be aware that you must *manually* update */
 192         /* these pointers in the function sam3_GetDetails() */
 193         /* See the comment "Here there be dragons" */
 194
 195         /* so we can find the chip we belong to */
 196         struct sam3_chip *pChip;
 197         /* so we can find the orginal bank pointer */
 198         struct flash_bank *pBank;
 199         unsigned bank_number;
 200         uint32_t controller_address;
 201         uint32_t base_address;
 202         uint32_t flash_wait_states;
 203         bool present;
 204         unsigned size_bytes;
 205         unsigned nsectors;
 206         unsigned sector_size;
 207         unsigned page_size;
 208 };
 209
 210 struct sam3_chip_details {
 211         /* THERE ARE DRAGONS HERE.. */
 212         /* note: If you add pointers here */
 213         /* becareful about them as they */
 214         /* may need to be updated inside */
 215         /* the function: "sam3_GetDetails() */
 216         /* which copy/overwrites the */
 217         /* 'runtime' copy of this structure */
 218         uint32_t chipid_cidr;
 219         const char *name;
 220
 221         unsigned n_gpnvms;
 222 #define SAM3_N_NVM_BITS 3
 223         unsigned gpnvm[SAM3_N_NVM_BITS];
 224         unsigned total_flash_size;
 225         unsigned total_sram_size;
 226         unsigned n_banks;
 227 #define SAM3_MAX_FLASH_BANKS 2
 228         /* these are "initialized" from the global const data */
 229         struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
 230 };
 231
 232 struct sam3_chip {
 233         struct sam3_chip *next;
 234         int probed;
 235
 236         /* this is "initialized" from the global const structure */
 237         struct sam3_chip_details details;
 238         struct target *target;
 239         struct sam3_cfg cfg;
 240 };
 241
 242
 243 struct sam3_reg_list {
 244         uint32_t address;  size_t struct_offset; const char *name;
 245         void (*explain_func)(struct sam3_chip *pInfo);
 246 };
 247
 248 static struct sam3_chip *all_sam3_chips;
 249
 250 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
 251 {
 252         struct target *t;
 253         static struct sam3_chip *p;
 254
 255         t = get_current_target(cmd_ctx);
 256         if (!t) {
 257                 command_print(cmd_ctx, "No current target?");
 258                 return NULL;
 259         }
 260
 261         p = all_sam3_chips;
 262         if (!p) {
 263                 /* this should not happen */
 264                 /* the command is not registered until the chip is created? */
 265                 command_print(cmd_ctx, "No SAM3 chips exist?");
 266                 return NULL;
 267         }
 268
 269         while (p) {
 270                 if (p->target == t)
 271                         return p;
 272                 p = p->next;
 273         }
 274         command_print(cmd_ctx, "Cannot find SAM3 chip?");
 275         return NULL;
 276 }
 277
 278 /* these are used to *initialize* the "pChip->details" structure. */
 279 static const struct sam3_chip_details all_sam3_details[] = {
 280         /* Start at91sam3u* series */
 281         {
 282                 .chipid_cidr    = 0x28100960,
 283                 .name           = "at91sam3u4e",
 284                 .total_flash_size     = 256 * 1024,
 285                 .total_sram_size      = 52 * 1024,
 286                 .n_gpnvms       = 3,
 287                 .n_banks        = 2,
 288
 289                 /* System boots at address 0x0 */
 290                 /* gpnvm[1] = selects boot code */
 291                 /*     if gpnvm[1] == 0 */
 292                 /*         boot is via "SAMBA" (rom) */
 293                 /*     else */
 294                 /*         boot is via FLASH */
 295                 /*         Selection is via gpnvm[2] */
 296                 /*     endif */
 297                 /*  */
 298                 /* NOTE: banks 0 & 1 switch places */
 299                 /*     if gpnvm[2] == 0 */
 300                 /*         Bank0 is the boot rom */
 301                 /*      else */
 302                 /*         Bank1 is the boot rom */
 303                 /*      endif */
 304 /*              .bank[0] = { */
 305                 {
 306                         {
 307                                 .probed = 0,
 308                                 .pChip  = NULL,
 309                                 .pBank  = NULL,
 310                                 .bank_number = 0,
 311                                 .base_address = FLASH_BANK0_BASE_U,
 312                                 .controller_address = 0x400e0800,
 313                                 .flash_wait_states = 6, /* workaround silicon bug */
 314                                 .present = 1,
 315                                 .size_bytes = 128 * 1024,
 316                                 .nsectors   = 16,
 317                                 .sector_size = 8192,
 318                                 .page_size   = 256,
 319                         },
 320
 321 /*              .bank[1] = { */
 322                         {
 323                                 .probed = 0,
 324                                 .pChip  = NULL,
 325                                 .pBank  = NULL,
 326                                 .bank_number = 1,
 327                                 .base_address = FLASH_BANK1_BASE_U,
 328                                 .controller_address = 0x400e0a00,
 329                                 .flash_wait_states = 6, /* workaround silicon bug */
 330                                 .present = 1,
 331                                 .size_bytes = 128 * 1024,
 332                                 .nsectors   = 16,
 333                                 .sector_size = 8192,
 334                                 .page_size   = 256,
 335                         },
 336                 },
 337         },
 338
 339         {
 340                 .chipid_cidr    = 0x281a0760,
 341                 .name           = "at91sam3u2e",
 342                 .total_flash_size     = 128 * 1024,
 343                 .total_sram_size      = 36 * 1024,
 344                 .n_gpnvms       = 2,
 345                 .n_banks        = 1,
 346
 347                 /* System boots at address 0x0 */
 348                 /* gpnvm[1] = selects boot code */
 349                 /*     if gpnvm[1] == 0 */
 350                 /*         boot is via "SAMBA" (rom) */
 351                 /*     else */
 352                 /*         boot is via FLASH */
 353                 /*         Selection is via gpnvm[2] */
 354                 /*     endif */
 355 /*              .bank[0] = { */
 356                 {
 357                         {
 358                                 .probed = 0,
 359                                 .pChip  = NULL,
 360                                 .pBank  = NULL,
 361                                 .bank_number = 0,
 362                                 .base_address = FLASH_BANK0_BASE_U,
 363                                 .controller_address = 0x400e0800,
 364                                 .flash_wait_states = 6, /* workaround silicon bug */
 365                                 .present = 1,
 366                                 .size_bytes = 128 * 1024,
 367                                 .nsectors   = 16,
 368                                 .sector_size = 8192,
 369                                 .page_size   = 256,
 370                         },
 371 /*                .bank[1] = { */
 372                         {
 373                                 .present = 0,
 374                                 .probed = 0,
 375                                 .bank_number = 1,
 376                         },
 377                 },
 378         },
 379         {
 380                 .chipid_cidr    = 0x28190560,
 381                 .name           = "at91sam3u1e",
 382                 .total_flash_size     = 64 * 1024,
 383                 .total_sram_size      = 20 * 1024,
 384                 .n_gpnvms       = 2,
 385                 .n_banks        = 1,
 386
 387                 /* System boots at address 0x0 */
 388                 /* gpnvm[1] = selects boot code */
 389                 /*     if gpnvm[1] == 0 */
 390                 /*         boot is via "SAMBA" (rom) */
 391                 /*     else */
 392                 /*         boot is via FLASH */
 393                 /*         Selection is via gpnvm[2] */
 394                 /*     endif */
 395                 /*  */
 396
 397 /*              .bank[0] = { */
 398                 {
 399                         {
 400                                 .probed = 0,
 401                                 .pChip  = NULL,
 402                                 .pBank  = NULL,
 403                                 .bank_number = 0,
 404                                 .base_address = FLASH_BANK0_BASE_U,
 405                                 .controller_address = 0x400e0800,
 406                                 .flash_wait_states = 6, /* workaround silicon bug */
 407                                 .present = 1,
 408                                 .size_bytes = 64 * 1024,
 409                                 .nsectors   = 8,
 410                                 .sector_size = 8192,
 411                                 .page_size   = 256,
 412                         },
 413
 414 /*              .bank[1] = { */
 415                         {
 416                                 .present = 0,
 417                                 .probed = 0,
 418                                 .bank_number = 1,
 419                         },
 420                 },
 421         },
 422
 423         {
 424                 .chipid_cidr    = 0x28000960,
 425                 .name           = "at91sam3u4c",
 426                 .total_flash_size     = 256 * 1024,
 427                 .total_sram_size      = 52 * 1024,
 428                 .n_gpnvms       = 3,
 429                 .n_banks        = 2,
 430
 431                 /* System boots at address 0x0 */
 432                 /* gpnvm[1] = selects boot code */
 433                 /*     if gpnvm[1] == 0 */
 434                 /*         boot is via "SAMBA" (rom) */
 435                 /*     else */
 436                 /*         boot is via FLASH */
 437                 /*         Selection is via gpnvm[2] */
 438                 /*     endif */
 439                 /*  */
 440                 /* NOTE: banks 0 & 1 switch places */
 441                 /*     if gpnvm[2] == 0 */
 442                 /*         Bank0 is the boot rom */
 443                 /*      else */
 444                 /*         Bank1 is the boot rom */
 445                 /*      endif */
 446                 {
 447                         {
 448 /*              .bank[0] = { */
 449                                 .probed = 0,
 450                                 .pChip  = NULL,
 451                                 .pBank  = NULL,
 452                                 .bank_number = 0,
 453                                 .base_address = FLASH_BANK0_BASE_U,
 454                                 .controller_address = 0x400e0800,
 455                                 .flash_wait_states = 6, /* workaround silicon bug */
 456                                 .present = 1,
 457                                 .size_bytes = 128 * 1024,
 458                                 .nsectors   = 16,
 459                                 .sector_size = 8192,
 460                                 .page_size   = 256,
 461                         },
 462 /*              .bank[1] = { */
 463                         {
 464                                 .probed = 0,
 465                                 .pChip  = NULL,
 466                                 .pBank  = NULL,
 467                                 .bank_number = 1,
 468                                 .base_address = FLASH_BANK1_BASE_U,
 469                                 .controller_address = 0x400e0a00,
 470                                 .flash_wait_states = 6, /* workaround silicon bug */
 471                                 .present = 1,
 472                                 .size_bytes = 128 * 1024,
 473                                 .nsectors   = 16,
 474                                 .sector_size = 8192,
 475                                 .page_size   = 256,
 476                         },
 477                 },
 478         },
 479
 480         {
 481                 .chipid_cidr    = 0x280a0760,
 482                 .name           = "at91sam3u2c",
 483                 .total_flash_size     = 128 * 1024,
 484                 .total_sram_size      = 36 * 1024,
 485                 .n_gpnvms       = 2,
 486                 .n_banks        = 1,
 487
 488                 /* System boots at address 0x0 */
 489                 /* gpnvm[1] = selects boot code */
 490                 /*     if gpnvm[1] == 0 */
 491                 /*         boot is via "SAMBA" (rom) */
 492                 /*     else */
 493                 /*         boot is via FLASH */
 494                 /*         Selection is via gpnvm[2] */
 495                 /*     endif */
 496                 {
 497 /*              .bank[0] = { */
 498                         {
 499                                 .probed = 0,
 500                                 .pChip  = NULL,
 501                                 .pBank  = NULL,
 502                                 .bank_number = 0,
 503                                 .base_address = FLASH_BANK0_BASE_U,
 504                                 .controller_address = 0x400e0800,
 505                                 .flash_wait_states = 6, /* workaround silicon bug */
 506                                 .present = 1,
 507                                 .size_bytes = 128 * 1024,
 508                                 .nsectors   = 16,
 509                                 .sector_size = 8192,
 510                                 .page_size   = 256,
 511                         },
 512 /*              .bank[1] = { */
 513                         {
 514                                 .present = 0,
 515                                 .probed = 0,
 516                                 .bank_number = 1,
 517                         },
 518                 },
 519         },
 520         {
 521                 .chipid_cidr    = 0x28090560,
 522                 .name           = "at91sam3u1c",
 523                 .total_flash_size     = 64 * 1024,
 524                 .total_sram_size      = 20 * 1024,
 525                 .n_gpnvms       = 2,
 526                 .n_banks        = 1,
 527
 528                 /* System boots at address 0x0 */
 529                 /* gpnvm[1] = selects boot code */
 530                 /*     if gpnvm[1] == 0 */
 531                 /*         boot is via "SAMBA" (rom) */
 532                 /*     else */
 533                 /*         boot is via FLASH */
 534                 /*         Selection is via gpnvm[2] */
 535                 /*     endif */
 536                 /*  */
 537
 538                 {
 539 /*              .bank[0] = { */
 540                         {
 541                                 .probed = 0,
 542                                 .pChip  = NULL,
 543                                 .pBank  = NULL,
 544                                 .bank_number = 0,
 545                                 .base_address = FLASH_BANK0_BASE_U,
 546                                 .controller_address = 0x400e0800,
 547                                 .flash_wait_states = 6, /* workaround silicon bug */
 548                                 .present = 1,
 549                                 .size_bytes = 64 * 1024,
 550                                 .nsectors   = 8,
 551                                 .sector_size = 8192,
 552                                 .page_size   = 256,
 553                         },
 554 /*              .bank[1] = { */
 555                         {
 556                                 .present = 0,
 557                                 .probed = 0,
 558                                 .bank_number = 1,
 559
 560                         },
 561                 },
 562         },
 563
 564         /* Start at91sam3s* series */
 565
 566         /* Note: The preliminary at91sam3s datasheet says on page 302 */
 567         /* that the flash controller is at address 0x400E0800. */
 568         /* This is _not_ the case, the controller resides at address 0x400e0a0. */
 569         {
 570                 .chipid_cidr    = 0x28A00960,
 571                 .name           = "at91sam3s4c",
 572                 .total_flash_size     = 256 * 1024,
 573                 .total_sram_size      = 48 * 1024,
 574                 .n_gpnvms       = 2,
 575                 .n_banks        = 1,
 576                 {
 577 /*              .bank[0] = { */
 578                         {
 579                                 .probed = 0,
 580                                 .pChip  = NULL,
 581                                 .pBank  = NULL,
 582                                 .bank_number = 0,
 583                                 .base_address = FLASH_BANK_BASE_S,
 584                                 .controller_address = 0x400e0a00,
 585                                 .flash_wait_states = 6, /* workaround silicon bug */
 586                                 .present = 1,
 587                                 .size_bytes = 256 * 1024,
 588                                 .nsectors   = 16,
 589                                 .sector_size = 16384,
 590                                 .page_size   = 256,
 591                         },
 592 /*              .bank[1] = { */
 593                         {
 594                                 .present = 0,
 595                                 .probed = 0,
 596                                 .bank_number = 1,
 597
 598                         },
 599                 },
 600         },
 601
 602         {
 603                 .chipid_cidr    = 0x28900960,
 604                 .name           = "at91sam3s4b",
 605                 .total_flash_size     = 256 * 1024,
 606                 .total_sram_size      = 48 * 1024,
 607                 .n_gpnvms       = 2,
 608                 .n_banks        = 1,
 609                 {
 610 /*              .bank[0] = { */
 611                         {
 612                                 .probed = 0,
 613                                 .pChip  = NULL,
 614                                 .pBank  = NULL,
 615                                 .bank_number = 0,
 616                                 .base_address = FLASH_BANK_BASE_S,
 617                                 .controller_address = 0x400e0a00,
 618                                 .flash_wait_states = 6, /* workaround silicon bug */
 619                                 .present = 1,
 620                                 .size_bytes = 256 * 1024,
 621                                 .nsectors   = 16,
 622                                 .sector_size = 16384,
 623                                 .page_size   = 256,
 624                         },
 625 /*              .bank[1] = { */
 626                         {
 627                                 .present = 0,
 628                                 .probed = 0,
 629                                 .bank_number = 1,
 630
 631                         },
 632                 },
 633         },
 634         {
 635                 .chipid_cidr    = 0x28800960,
 636                 .name           = "at91sam3s4a",
 637                 .total_flash_size     = 256 * 1024,
 638                 .total_sram_size      = 48 * 1024,
 639                 .n_gpnvms       = 2,
 640                 .n_banks        = 1,
 641                 {
 642 /*              .bank[0] = { */
 643                         {
 644                                 .probed = 0,
 645                                 .pChip  = NULL,
 646                                 .pBank  = NULL,
 647                                 .bank_number = 0,
 648                                 .base_address = FLASH_BANK_BASE_S,
 649                                 .controller_address = 0x400e0a00,
 650                                 .flash_wait_states = 6, /* workaround silicon bug */
 651                                 .present = 1,
 652                                 .size_bytes = 256 * 1024,
 653                                 .nsectors   = 16,
 654                                 .sector_size = 16384,
 655                                 .page_size   = 256,
 656                         },
 657 /*              .bank[1] = { */
 658                         {
 659                                 .present = 0,
 660                                 .probed = 0,
 661                                 .bank_number = 1,
 662
 663                         },
 664                 },
 665         },
 666         {
 667                 .chipid_cidr    = 0x28AA0760,
 668                 .name           = "at91sam3s2c",
 669                 .total_flash_size     = 128 * 1024,
 670                 .total_sram_size      = 32 * 1024,
 671                 .n_gpnvms       = 2,
 672                 .n_banks        = 1,
 673                 {
 674 /*              .bank[0] = { */
 675                         {
 676                                 .probed = 0,
 677                                 .pChip  = NULL,
 678                                 .pBank  = NULL,
 679                                 .bank_number = 0,
 680                                 .base_address = FLASH_BANK_BASE_S,
 681                                 .controller_address = 0x400e0a00,
 682                                 .flash_wait_states = 6, /* workaround silicon bug */
 683                                 .present = 1,
 684                                 .size_bytes = 128 * 1024,
 685                                 .nsectors   = 8,
 686                                 .sector_size = 16384,
 687                                 .page_size   = 256,
 688                         },
 689 /*              .bank[1] = { */
 690                         {
 691                                 .present = 0,
 692                                 .probed = 0,
 693                                 .bank_number = 1,
 694
 695                         },
 696                 },
 697         },
 698         {
 699                 .chipid_cidr    = 0x289A0760,
 700                 .name           = "at91sam3s2b",
 701                 .total_flash_size     = 128 * 1024,
 702                 .total_sram_size      = 32 * 1024,
 703                 .n_gpnvms       = 2,
 704                 .n_banks        = 1,
 705                 {
 706 /*              .bank[0] = { */
 707                         {
 708                                 .probed = 0,
 709                                 .pChip  = NULL,
 710                                 .pBank  = NULL,
 711                                 .bank_number = 0,
 712                                 .base_address = FLASH_BANK_BASE_S,
 713                                 .controller_address = 0x400e0a00,
 714                                 .flash_wait_states = 6, /* workaround silicon bug */
 715                                 .present = 1,
 716                                 .size_bytes = 128 * 1024,
 717                                 .nsectors   = 8,
 718                                 .sector_size = 16384,
 719                                 .page_size   = 256,
 720                         },
 721 /*              .bank[1] = { */
 722                         {
 723                                 .present = 0,
 724                                 .probed = 0,
 725                                 .bank_number = 1,
 726
 727                         },
 728                 },
 729         },
 730         {
 731                 .chipid_cidr    = 0x288A0760,
 732                 .name           = "at91sam3s2a",
 733                 .total_flash_size     = 128 * 1024,
 734                 .total_sram_size      = 32 * 1024,
 735                 .n_gpnvms       = 2,
 736                 .n_banks        = 1,
 737                 {
 738 /*              .bank[0] = { */
 739                         {
 740                                 .probed = 0,
 741                                 .pChip  = NULL,
 742                                 .pBank  = NULL,
 743                                 .bank_number = 0,
 744                                 .base_address = FLASH_BANK_BASE_S,
 745                                 .controller_address = 0x400e0a00,
 746                                 .flash_wait_states = 6, /* workaround silicon bug */
 747                                 .present = 1,
 748                                 .size_bytes = 128 * 1024,
 749                                 .nsectors   = 8,
 750                                 .sector_size = 16384,
 751                                 .page_size   = 256,
 752                         },
 753 /*              .bank[1] = { */
 754                         {
 755                                 .present = 0,
 756                                 .probed = 0,
 757                                 .bank_number = 1,
 758
 759                         },
 760                 },
 761         },
 762         {
 763                 .chipid_cidr    = 0x28A90560,
 764                 .name           = "at91sam3s1c",
 765                 .total_flash_size     = 64 * 1024,
 766                 .total_sram_size      = 16 * 1024,
 767                 .n_gpnvms       = 2,
 768                 .n_banks        = 1,
 769                 {
 770 /*              .bank[0] = { */
 771                         {
 772                                 .probed = 0,
 773                                 .pChip  = NULL,
 774                                 .pBank  = NULL,
 775                                 .bank_number = 0,
 776                                 .base_address = FLASH_BANK_BASE_S,
 777                                 .controller_address = 0x400e0a00,
 778                                 .flash_wait_states = 6, /* workaround silicon bug */
 779                                 .present = 1,
 780                                 .size_bytes = 64 * 1024,
 781                                 .nsectors   = 4,
 782                                 .sector_size = 16384,
 783                                 .page_size   = 256,
 784                         },
 785 /*              .bank[1] = { */
 786                         {
 787                                 .present = 0,
 788                                 .probed = 0,
 789                                 .bank_number = 1,
 790
 791                         },
 792                 },
 793         },
 794         {
 795                 .chipid_cidr    = 0x28990560,
 796                 .name           = "at91sam3s1b",
 797                 .total_flash_size     = 64 * 1024,
 798                 .total_sram_size      = 16 * 1024,
 799                 .n_gpnvms       = 2,
 800                 .n_banks        = 1,
 801                 {
 802 /*              .bank[0] = { */
 803                         {
 804                                 .probed = 0,
 805                                 .pChip  = NULL,
 806                                 .pBank  = NULL,
 807                                 .bank_number = 0,
 808                                 .base_address = FLASH_BANK_BASE_S,
 809                                 .controller_address = 0x400e0a00,
 810                                 .flash_wait_states = 6, /* workaround silicon bug */
 811                                 .present = 1,
 812                                 .size_bytes = 64 * 1024,
 813                                 .nsectors   = 4,
 814                                 .sector_size = 16384,
 815                                 .page_size   = 256,
 816                         },
 817 /*              .bank[1] = { */
 818                         {
 819                                 .present = 0,
 820                                 .probed = 0,
 821                                 .bank_number = 1,
 822
 823                         },
 824                 },
 825         },
 826         {
 827                 .chipid_cidr    = 0x28890560,
 828                 .name           = "at91sam3s1a",
 829                 .total_flash_size     = 64 * 1024,
 830                 .total_sram_size      = 16 * 1024,
 831                 .n_gpnvms       = 2,
 832                 .n_banks        = 1,
 833                 {
 834 /*              .bank[0] = { */
 835                         {
 836                                 .probed = 0,
 837                                 .pChip  = NULL,
 838                                 .pBank  = NULL,
 839                                 .bank_number = 0,
 840                                 .base_address = FLASH_BANK_BASE_S,
 841                                 .controller_address = 0x400e0a00,
 842                                 .flash_wait_states = 6, /* workaround silicon bug */
 843                                 .present = 1,
 844                                 .size_bytes = 64 * 1024,
 845                                 .nsectors   = 4,
 846                                 .sector_size = 16384,
 847                                 .page_size   = 256,
 848                         },
 849 /*              .bank[1] = { */
 850                         {
 851                                 .present = 0,
 852                                 .probed = 0,
 853                                 .bank_number = 1,
 854
 855                         },
 856                 },
 857         },
 858
 859         /* Start at91sam3n* series */
 860         {
 861                 .chipid_cidr    = 0x29540960,
 862                 .name           = "at91sam3n4c",
 863                 .total_flash_size     = 256 * 1024,
 864                 .total_sram_size      = 24 * 1024,
 865                 .n_gpnvms       = 3,
 866                 .n_banks        = 1,
 867
 868                 /* System boots at address 0x0 */
 869                 /* gpnvm[1] = selects boot code */
 870                 /*     if gpnvm[1] == 0 */
 871                 /*         boot is via "SAMBA" (rom) */
 872                 /*     else */
 873                 /*         boot is via FLASH */
 874                 /*         Selection is via gpnvm[2] */
 875                 /*     endif */
 876                 /*  */
 877                 /* NOTE: banks 0 & 1 switch places */
 878                 /*     if gpnvm[2] == 0 */
 879                 /*         Bank0 is the boot rom */
 880                 /*      else */
 881                 /*         Bank1 is the boot rom */
 882                 /*      endif */
 883 /*              .bank[0] = { */
 884                 {
 885                         {
 886                                 .probed = 0,
 887                                 .pChip  = NULL,
 888                                 .pBank  = NULL,
 889                                 .bank_number = 0,
 890                                 .base_address = FLASH_BANK_BASE_N,
 891                                 .controller_address = 0x400e0A00,
 892                                 .flash_wait_states = 6, /* workaround silicon bug */
 893                                 .present = 1,
 894                                 .size_bytes = 256 * 1024,
 895                                 .nsectors   = 16,
 896                                 .sector_size = 16384,
 897                                 .page_size   = 256,
 898                         },
 899
 900 /*              .bank[1] = { */
 901                         {
 902                                 .present = 0,
 903                                 .probed = 0,
 904                                 .bank_number = 1,
 905                         },
 906                 },
 907         },
 908
 909         {
 910                 .chipid_cidr    = 0x29440960,
 911                 .name           = "at91sam3n4b",
 912                 .total_flash_size     = 256 * 1024,
 913                 .total_sram_size      = 24 * 1024,
 914                 .n_gpnvms       = 3,
 915                 .n_banks        = 1,
 916
 917                 /* System boots at address 0x0 */
 918                 /* gpnvm[1] = selects boot code */
 919                 /*     if gpnvm[1] == 0 */
 920                 /*         boot is via "SAMBA" (rom) */
 921                 /*     else */
 922                 /*         boot is via FLASH */
 923                 /*         Selection is via gpnvm[2] */
 924                 /*     endif */
 925                 /*  */
 926                 /* NOTE: banks 0 & 1 switch places */
 927                 /*     if gpnvm[2] == 0 */
 928                 /*         Bank0 is the boot rom */
 929                 /*      else */
 930                 /*         Bank1 is the boot rom */
 931                 /*      endif */
 932 /*              .bank[0] = { */
 933                 {
 934                         {
 935                                 .probed = 0,
 936                                 .pChip  = NULL,
 937                                 .pBank  = NULL,
 938                                 .bank_number = 0,
 939                                 .base_address = FLASH_BANK_BASE_N,
 940                                 .controller_address = 0x400e0A00,
 941                                 .flash_wait_states = 6, /* workaround silicon bug */
 942                                 .present = 1,
 943                                 .size_bytes = 256 * 1024,
 944                                 .nsectors   = 16,
 945                                 .sector_size = 16384,
 946                                 .page_size   = 256,
 947                         },
 948
 949 /*              .bank[1] = { */
 950                         {
 951                                 .present = 0,
 952                                 .probed = 0,
 953                                 .bank_number = 1,
 954                         },
 955                 },
 956         },
 957
 958         {
 959                 .chipid_cidr    = 0x29340960,
 960                 .name           = "at91sam3n4a",
 961                 .total_flash_size     = 256 * 1024,
 962                 .total_sram_size      = 24 * 1024,
 963                 .n_gpnvms       = 3,
 964                 .n_banks        = 1,
 965
 966                 /* System boots at address 0x0 */
 967                 /* gpnvm[1] = selects boot code */
 968                 /*     if gpnvm[1] == 0 */
 969                 /*         boot is via "SAMBA" (rom) */
 970                 /*     else */
 971                 /*         boot is via FLASH */
 972                 /*         Selection is via gpnvm[2] */
 973                 /*     endif */
 974                 /*  */
 975                 /* NOTE: banks 0 & 1 switch places */
 976                 /*     if gpnvm[2] == 0 */
 977                 /*         Bank0 is the boot rom */
 978                 /*      else */
 979                 /*         Bank1 is the boot rom */
 980                 /*      endif */
 981 /*              .bank[0] = { */
 982                 {
 983                         {
 984                                 .probed = 0,
 985                                 .pChip  = NULL,
 986                                 .pBank  = NULL,
 987                                 .bank_number = 0,
 988                                 .base_address = FLASH_BANK_BASE_N,
 989                                 .controller_address = 0x400e0A00,
 990                                 .flash_wait_states = 6, /* workaround silicon bug */
 991                                 .present = 1,
 992                                 .size_bytes = 256 * 1024,
 993                                 .nsectors   = 16,
 994                                 .sector_size = 16384,
 995                                 .page_size   = 256,
 996                         },
 997
 998 /*              .bank[1] = { */
 999                         {
1000                                 .present = 0,
1001                                 .probed = 0,
1002                                 .bank_number = 1,
1003                         },
1004                 },
1005         },
1006
1007         {
1008                 .chipid_cidr    = 0x29590760,
1009                 .name           = "at91sam3n2c",
1010                 .total_flash_size     = 128 * 1024,
1011                 .total_sram_size      = 16 * 1024,
1012                 .n_gpnvms       = 3,
1013                 .n_banks        = 1,
1014
1015                 /* System boots at address 0x0 */
1016                 /* gpnvm[1] = selects boot code */
1017                 /*     if gpnvm[1] == 0 */
1018                 /*         boot is via "SAMBA" (rom) */
1019                 /*     else */
1020                 /*         boot is via FLASH */
1021                 /*         Selection is via gpnvm[2] */
1022                 /*     endif */
1023                 /*  */
1024                 /* NOTE: banks 0 & 1 switch places */
1025                 /*     if gpnvm[2] == 0 */
1026                 /*         Bank0 is the boot rom */
1027                 /*      else */
1028                 /*         Bank1 is the boot rom */
1029                 /*      endif */
1030 /*              .bank[0] = { */
1031                 {
1032                         {
1033                                 .probed = 0,
1034                                 .pChip  = NULL,
1035                                 .pBank  = NULL,
1036                                 .bank_number = 0,
1037                                 .base_address = FLASH_BANK_BASE_N,
1038                                 .controller_address = 0x400e0A00,
1039                                 .flash_wait_states = 6, /* workaround silicon bug */
1040                                 .present = 1,
1041                                 .size_bytes = 128 * 1024,
1042                                 .nsectors   = 8,
1043                                 .sector_size = 16384,
1044                                 .page_size   = 256,
1045                         },
1046
1047 /*              .bank[1] = { */
1048                         {
1049                                 .present = 0,
1050                                 .probed = 0,
1051                                 .bank_number = 1,
1052                         },
1053                 },
1054         },
1055
1056         {
1057                 .chipid_cidr    = 0x29490760,
1058                 .name           = "at91sam3n2b",
1059                 .total_flash_size     = 128 * 1024,
1060                 .total_sram_size      = 16 * 1024,
1061                 .n_gpnvms       = 3,
1062                 .n_banks        = 1,
1063
1064                 /* System boots at address 0x0 */
1065                 /* gpnvm[1] = selects boot code */
1066                 /*     if gpnvm[1] == 0 */
1067                 /*         boot is via "SAMBA" (rom) */
1068                 /*     else */
1069                 /*         boot is via FLASH */
1070                 /*         Selection is via gpnvm[2] */
1071                 /*     endif */
1072                 /*  */
1073                 /* NOTE: banks 0 & 1 switch places */
1074                 /*     if gpnvm[2] == 0 */
1075                 /*         Bank0 is the boot rom */
1076                 /*      else */
1077                 /*         Bank1 is the boot rom */
1078                 /*      endif */
1079 /*              .bank[0] = { */
1080                 {
1081                         {
1082                                 .probed = 0,
1083                                 .pChip  = NULL,
1084                                 .pBank  = NULL,
1085                                 .bank_number = 0,
1086                                 .base_address = FLASH_BANK_BASE_N,
1087                                 .controller_address = 0x400e0A00,
1088                                 .flash_wait_states = 6, /* workaround silicon bug */
1089                                 .present = 1,
1090                                 .size_bytes = 128 * 1024,
1091                                 .nsectors   = 8,
1092                                 .sector_size = 16384,
1093                                 .page_size   = 256,
1094                         },
1095
1096 /*              .bank[1] = { */
1097                         {
1098                                 .present = 0,
1099                                 .probed = 0,
1100                                 .bank_number = 1,
1101                         },
1102                 },
1103         },
1104
1105         {
1106                 .chipid_cidr    = 0x29390760,
1107                 .name           = "at91sam3n2a",
1108                 .total_flash_size     = 128 * 1024,
1109                 .total_sram_size      = 16 * 1024,
1110                 .n_gpnvms       = 3,
1111                 .n_banks        = 1,
1112
1113                 /* System boots at address 0x0 */
1114                 /* gpnvm[1] = selects boot code */
1115                 /*     if gpnvm[1] == 0 */
1116                 /*         boot is via "SAMBA" (rom) */
1117                 /*     else */
1118                 /*         boot is via FLASH */
1119                 /*         Selection is via gpnvm[2] */
1120                 /*     endif */
1121                 /*  */
1122                 /* NOTE: banks 0 & 1 switch places */
1123                 /*     if gpnvm[2] == 0 */
1124                 /*         Bank0 is the boot rom */
1125                 /*      else */
1126                 /*         Bank1 is the boot rom */
1127                 /*      endif */
1128 /*              .bank[0] = { */
1129                 {
1130                         {
1131                                 .probed = 0,
1132                                 .pChip  = NULL,
1133                                 .pBank  = NULL,
1134                                 .bank_number = 0,
1135                                 .base_address = FLASH_BANK_BASE_N,
1136                                 .controller_address = 0x400e0A00,
1137                                 .flash_wait_states = 6, /* workaround silicon bug */
1138                                 .present = 1,
1139                                 .size_bytes = 128 * 1024,
1140                                 .nsectors   = 8,
1141                                 .sector_size = 16384,
1142                                 .page_size   = 256,
1143                         },
1144
1145 /*              .bank[1] = { */
1146                         {
1147                                 .present = 0,
1148                                 .probed = 0,
1149                                 .bank_number = 1,
1150                         },
1151                 },
1152         },
1153
1154         {
1155                 .chipid_cidr    = 0x29580560,
1156                 .name           = "at91sam3n1c",
1157                 .total_flash_size     = 64 * 1024,
1158                 .total_sram_size      = 8 * 1024,
1159                 .n_gpnvms       = 3,
1160                 .n_banks        = 1,
1161
1162                 /* System boots at address 0x0 */
1163                 /* gpnvm[1] = selects boot code */
1164                 /*     if gpnvm[1] == 0 */
1165                 /*         boot is via "SAMBA" (rom) */
1166                 /*     else */
1167                 /*         boot is via FLASH */
1168                 /*         Selection is via gpnvm[2] */
1169                 /*     endif */
1170                 /*  */
1171                 /* NOTE: banks 0 & 1 switch places */
1172                 /*     if gpnvm[2] == 0 */
1173                 /*         Bank0 is the boot rom */
1174                 /*      else */
1175                 /*         Bank1 is the boot rom */
1176                 /*      endif */
1177 /*              .bank[0] = { */
1178                 {
1179                         {
1180                                 .probed = 0,
1181                                 .pChip  = NULL,
1182                                 .pBank  = NULL,
1183                                 .bank_number = 0,
1184                                 .base_address = FLASH_BANK_BASE_N,
1185                                 .controller_address = 0x400e0A00,
1186                                 .flash_wait_states = 6, /* workaround silicon bug */
1187                                 .present = 1,
1188                                 .size_bytes = 64 * 1024,
1189                                 .nsectors   = 4,
1190                                 .sector_size = 16384,
1191                                 .page_size   = 256,
1192                         },
1193
1194 /*              .bank[1] = { */
1195                         {
1196                                 .present = 0,
1197                                 .probed = 0,
1198                                 .bank_number = 1,
1199                         },
1200                 },
1201         },
1202
1203         {
1204                 .chipid_cidr    = 0x29480560,
1205                 .name           = "at91sam3n1b",
1206                 .total_flash_size     = 64 * 1024,
1207                 .total_sram_size      = 8 * 1024,
1208                 .n_gpnvms       = 3,
1209                 .n_banks        = 1,
1210
1211                 /* System boots at address 0x0 */
1212                 /* gpnvm[1] = selects boot code */
1213                 /*     if gpnvm[1] == 0 */
1214                 /*         boot is via "SAMBA" (rom) */
1215                 /*     else */
1216                 /*         boot is via FLASH */
1217                 /*         Selection is via gpnvm[2] */
1218                 /*     endif */
1219                 /*  */
1220                 /* NOTE: banks 0 & 1 switch places */
1221                 /*     if gpnvm[2] == 0 */
1222                 /*         Bank0 is the boot rom */
1223                 /*      else */
1224                 /*         Bank1 is the boot rom */
1225                 /*      endif */
1226 /*              .bank[0] = { */
1227                 {
1228                         {
1229                                 .probed = 0,
1230                                 .pChip  = NULL,
1231                                 .pBank  = NULL,
1232                                 .bank_number = 0,
1233                                 .base_address = FLASH_BANK_BASE_N,
1234                                 .controller_address = 0x400e0A00,
1235                                 .flash_wait_states = 6, /* workaround silicon bug */
1236                                 .present = 1,
1237                                 .size_bytes = 64 * 1024,
1238                                 .nsectors   = 4,
1239                                 .sector_size = 16384,
1240                                 .page_size   = 256,
1241                         },
1242
1243 /*              .bank[1] = { */
1244                         {
1245                                 .present = 0,
1246                                 .probed = 0,
1247                                 .bank_number = 1,
1248                         },
1249                 },
1250         },
1251
1252         {
1253                 .chipid_cidr    = 0x29380560,
1254                 .name           = "at91sam3n1a",
1255                 .total_flash_size     = 64 * 1024,
1256                 .total_sram_size      = 8 * 1024,
1257                 .n_gpnvms       = 3,
1258                 .n_banks        = 1,
1259
1260                 /* System boots at address 0x0 */
1261                 /* gpnvm[1] = selects boot code */
1262                 /*     if gpnvm[1] == 0 */
1263                 /*         boot is via "SAMBA" (rom) */
1264                 /*     else */
1265                 /*         boot is via FLASH */
1266                 /*         Selection is via gpnvm[2] */
1267                 /*     endif */
1268                 /*  */
1269                 /* NOTE: banks 0 & 1 switch places */
1270                 /*     if gpnvm[2] == 0 */
1271                 /*         Bank0 is the boot rom */
1272                 /*      else */
1273                 /*         Bank1 is the boot rom */
1274                 /*      endif */
1275 /*              .bank[0] = { */
1276                 {
1277                         {
1278                                 .probed = 0,
1279                                 .pChip  = NULL,
1280                                 .pBank  = NULL,
1281                                 .bank_number = 0,
1282                                 .base_address = FLASH_BANK_BASE_N,
1283                                 .controller_address = 0x400e0A00,
1284                                 .flash_wait_states = 6, /* workaround silicon bug */
1285                                 .present = 1,
1286                                 .size_bytes = 64 * 1024,
1287                                 .nsectors   = 4,
1288                                 .sector_size = 16384,
1289                                 .page_size   = 256,
1290                         },
1291
1292 /*              .bank[1] = { */
1293                         {
1294                                 .present = 0,
1295                                 .probed = 0,
1296                                 .bank_number = 1,
1297                         },
1298                 },
1299         },
1300
1301         /* Start at91sam3a series*/
1302         /* System boots at address 0x0 */
1303         /* gpnvm[1] = selects boot code */
1304         /*     if gpnvm[1] == 0 */
1305         /*         boot is via "SAMBA" (rom) */
1306         /*     else */
1307         /*         boot is via FLASH */
1308         /*         Selection is via gpnvm[2] */
1309         /*     endif */
1310         /*  */
1311         /* NOTE: banks 0 & 1 switch places */
1312         /*     if gpnvm[2] == 0 */
1313         /*         Bank0 is the boot rom */
1314         /*      else */
1315         /*         Bank1 is the boot rom */
1316         /*      endif */
1317
1318         {
1319                 .chipid_cidr    = 0x283E0A60,
1320                 .name           = "at91sam3a8c",
1321                 .total_flash_size     = 512 * 1024,
1322                 .total_sram_size      = 96 * 1024,
1323                 .n_gpnvms       = 3,
1324                 .n_banks        = 2,
1325                 {
1326 /*              .bank[0] = { */
1327                   {
1328                         .probed = 0,
1329                         .pChip  = NULL,
1330                         .pBank  = NULL,
1331                         .bank_number = 0,
1332                         .base_address = FLASH_BANK0_BASE_AX,
1333                         .controller_address = 0x400e0a00,
1334                         .flash_wait_states = 6, /* workaround silicon bug */
1335                         .present = 1,
1336                         .size_bytes =  256 * 1024,
1337                         .nsectors   =  16,
1338                         .sector_size = 16384,
1339                         .page_size   = 256,
1340                   },
1341 /*              .bank[1] = { */
1342                   {
1343                         .probed = 0,
1344                         .pChip  = NULL,
1345                         .pBank  = NULL,
1346                         .bank_number = 1,
1347                         .base_address = FLASH_BANK1_BASE_512K_AX,
1348                         .controller_address = 0x400e0c00,
1349                         .flash_wait_states = 6, /* workaround silicon bug */
1350                         .present = 1,
1351                         .size_bytes =  256 * 1024,
1352                         .nsectors   =  16,
1353                         .sector_size = 16384,
1354                         .page_size   = 256,
1355
1356                   },
1357                 },
1358         },
1359         {
1360                 .chipid_cidr    = 0x283B0960,
1361                 .name           = "at91sam3a4c",
1362                 .total_flash_size     = 256 * 1024,
1363                 .total_sram_size      = 64 * 1024,
1364                 .n_gpnvms       = 3,
1365                 .n_banks        = 2,
1366                 {
1367 /*              .bank[0] = { */
1368                   {
1369                         .probed = 0,
1370                         .pChip  = NULL,
1371                         .pBank  = NULL,
1372                         .bank_number = 0,
1373                         .base_address = FLASH_BANK0_BASE_AX,
1374                         .controller_address = 0x400e0a00,
1375                         .flash_wait_states = 6, /* workaround silicon bug */
1376                         .present = 1,
1377                         .size_bytes =  128 * 1024,
1378                         .nsectors   =  8,
1379                         .sector_size = 16384,
1380                         .page_size   = 256,
1381                   },
1382 /*              .bank[1] = { */
1383                   {
1384                         .probed = 0,
1385                         .pChip  = NULL,
1386                         .pBank  = NULL,
1387                         .bank_number = 1,
1388                         .base_address = FLASH_BANK1_BASE_256K_AX,
1389                         .controller_address = 0x400e0c00,
1390                         .flash_wait_states = 6, /* workaround silicon bug */
1391                         .present = 1,
1392                         .size_bytes =  128 * 1024,
1393                         .nsectors   =  8,
1394                         .sector_size = 16384,
1395                         .page_size   = 256,
1396
1397                   },
1398                 },
1399         },
1400
1401         /* Start at91sam3x* series */
1402         /* System boots at address 0x0 */
1403         /* gpnvm[1] = selects boot code */
1404         /*     if gpnvm[1] == 0 */
1405         /*         boot is via "SAMBA" (rom) */
1406         /*     else */
1407         /*         boot is via FLASH */
1408         /*         Selection is via gpnvm[2] */
1409         /*     endif */
1410         /*  */
1411         /* NOTE: banks 0 & 1 switch places */
1412         /*     if gpnvm[2] == 0 */
1413         /*         Bank0 is the boot rom */
1414         /*      else */
1415         /*         Bank1 is the boot rom */
1416         /*      endif */
1417         {
1418                 .chipid_cidr    = 0x286E0A20,
1419                 .name           = "at91sam3x8h",
1420                 .total_flash_size     = 512 * 1024,
1421                 .total_sram_size      = 96 * 1024,
1422                 .n_gpnvms       = 3,
1423                 .n_banks        = 2,
1424                 {
1425 /*              .bank[0] = { */
1426                   {
1427                         .probed = 0,
1428                         .pChip  = NULL,
1429                         .pBank  = NULL,
1430                         .bank_number = 0,
1431                         .base_address = FLASH_BANK0_BASE_AX,
1432                         .controller_address = 0x400e0a00,
1433                         .flash_wait_states = 6, /* workaround silicon bug */
1434                         .present = 1,
1435                         .size_bytes =  256 * 1024,
1436                         .nsectors   =  16,
1437                         .sector_size = 16384,
1438                         .page_size   = 256,
1439                   },
1440 /*              .bank[1] = { */
1441                   {
1442                         .probed = 0,
1443                         .pChip  = NULL,
1444                         .pBank  = NULL,
1445                         .bank_number = 1,
1446                         .base_address = FLASH_BANK1_BASE_512K_AX,
1447                         .controller_address = 0x400e0c00,
1448                         .flash_wait_states = 6, /* workaround silicon bug */
1449                         .present = 1,
1450                         .size_bytes =  256 * 1024,
1451                         .nsectors   =  16,
1452                         .sector_size = 16384,
1453                         .page_size   = 256,
1454
1455                   },
1456                 },
1457         },
1458         {
1459                 .chipid_cidr    = 0x285E0A60,
1460                 .name           = "at91sam3x8e",
1461                 .total_flash_size     = 512 * 1024,
1462                 .total_sram_size      = 96 * 1024,
1463                 .n_gpnvms       = 3,
1464                 .n_banks        = 2,
1465                 {
1466 /*              .bank[0] = { */
1467                   {
1468                         .probed = 0,
1469                         .pChip  = NULL,
1470                         .pBank  = NULL,
1471                         .bank_number = 0,
1472                         .base_address = FLASH_BANK0_BASE_AX,
1473                         .controller_address = 0x400e0a00,
1474                         .flash_wait_states = 6, /* workaround silicon bug */
1475                         .present = 1,
1476                         .size_bytes =  256 * 1024,
1477                         .nsectors   =  16,
1478                         .sector_size = 16384,
1479                         .page_size   = 256,
1480                   },
1481 /*              .bank[1] = { */
1482                   {
1483                         .probed = 0,
1484                         .pChip  = NULL,
1485                         .pBank  = NULL,
1486                         .bank_number = 1,
1487                         .base_address = FLASH_BANK1_BASE_512K_AX,
1488                         .controller_address = 0x400e0c00,
1489                         .flash_wait_states = 6, /* workaround silicon bug */
1490                         .present = 1,
1491                         .size_bytes =  256 * 1024,
1492                         .nsectors   =  16,
1493                         .sector_size = 16384,
1494                         .page_size   = 256,
1495
1496                   },
1497                 },
1498         },
1499         {
1500                 .chipid_cidr    = 0x284E0A60,
1501                 .name           = "at91sam3x8c",
1502                 .total_flash_size     = 512 * 1024,
1503                 .total_sram_size      = 96 * 1024,
1504                 .n_gpnvms       = 3,
1505                 .n_banks        = 2,
1506                 {
1507 /*              .bank[0] = { */
1508                   {
1509                         .probed = 0,
1510                         .pChip  = NULL,
1511                         .pBank  = NULL,
1512                         .bank_number = 0,
1513                         .base_address = FLASH_BANK0_BASE_AX,
1514                         .controller_address = 0x400e0a00,
1515                         .flash_wait_states = 6, /* workaround silicon bug */
1516                         .present = 1,
1517                         .size_bytes =  256 * 1024,
1518                         .nsectors   =  16,
1519                         .sector_size = 16384,
1520                         .page_size   = 256,
1521                   },
1522 /*              .bank[1] = { */
1523                   {
1524                         .probed = 0,
1525                         .pChip  = NULL,
1526                         .pBank  = NULL,
1527                         .bank_number = 1,
1528                         .base_address = FLASH_BANK1_BASE_512K_AX ,
1529                         .controller_address = 0x400e0c00,
1530                         .flash_wait_states = 6, /* workaround silicon bug */
1531                         .present = 1,
1532                         .size_bytes =  256 * 1024,
1533                         .nsectors   =  16,
1534                         .sector_size = 16384,
1535                         .page_size   = 256,
1536
1537                   },
1538                 },
1539         },
1540         {
1541                 .chipid_cidr    = 0x285B0960,
1542                 .name           = "at91sam3x4e",
1543                 .total_flash_size     = 256 * 1024,
1544                 .total_sram_size      = 64 * 1024,
1545                 .n_gpnvms       = 3,
1546                 .n_banks        = 2,
1547                 {
1548 /*              .bank[0] = { */
1549                   {
1550                         .probed = 0,
1551                         .pChip  = NULL,
1552                         .pBank  = NULL,
1553                         .bank_number = 0,
1554                         .base_address = FLASH_BANK0_BASE_AX,
1555                         .controller_address = 0x400e0a00,
1556                         .flash_wait_states = 6, /* workaround silicon bug */
1557                         .present = 1,
1558                         .size_bytes =  128 * 1024,
1559                         .nsectors   =  8,
1560                         .sector_size = 16384,
1561                         .page_size   = 256,
1562                   },
1563 /*              .bank[1] = { */
1564                   {
1565                         .probed = 0,
1566                         .pChip  = NULL,
1567                         .pBank  = NULL,
1568                         .bank_number = 1,
1569                         .base_address = FLASH_BANK1_BASE_256K_AX,
1570                         .controller_address = 0x400e0c00,
1571                         .flash_wait_states = 6, /* workaround silicon bug */
1572                         .present = 1,
1573                         .size_bytes =  128 * 1024,
1574                         .nsectors   =  8,
1575                         .sector_size = 16384,
1576                         .page_size   = 256,
1577
1578                   },
1579                 },
1580         },
1581         {
1582                 .chipid_cidr    = 0x284B0960,
1583                 .name           = "at91sam3x4c",
1584                 .total_flash_size     = 256 * 1024,
1585                 .total_sram_size      = 64 * 1024,
1586                 .n_gpnvms       = 3,
1587                 .n_banks        = 2,
1588                 {
1589 /*              .bank[0] = { */
1590                   {
1591                         .probed = 0,
1592                         .pChip  = NULL,
1593                         .pBank  = NULL,
1594                         .bank_number = 0,
1595                         .base_address = FLASH_BANK0_BASE_AX,
1596                         .controller_address = 0x400e0a00,
1597                         .flash_wait_states = 6, /* workaround silicon bug */
1598                         .present = 1,
1599                         .size_bytes =  128 * 1024,
1600                         .nsectors   =  8,
1601                         .sector_size = 16384,
1602                         .page_size   = 256,
1603                   },
1604 /*              .bank[1] = { */
1605                   {
1606                         .probed = 0,
1607                         .pChip  = NULL,
1608                         .pBank  = NULL,
1609                         .bank_number = 1,
1610                         .base_address = FLASH_BANK1_BASE_256K_AX,
1611                         .controller_address = 0x400e0c00,
1612                         .flash_wait_states = 6, /* workaround silicon bug */
1613                         .present = 1,
1614                         .size_bytes =  128 * 1024,
1615                         .nsectors   =  8,
1616                         .sector_size = 16384,
1617                         .page_size   = 256,
1618
1619                   },
1620                 },
1621         },
1622         /* terminate */
1623         {
1624                 .chipid_cidr    = 0,
1625                 .name                   = NULL,
1626         }
1627 };
1628
1629 /* Globals above */
1630 /***********************************************************************
1631  **********************************************************************
1632  **********************************************************************
1633  **********************************************************************
1634  **********************************************************************
1635  **********************************************************************/
1636 /* *ATMEL* style code - from the SAM3 driver code */
1637
1638 /**
1639  * Get the current status of the EEFC and
1640  * the value of some status bits (LOCKE, PROGE).
1641  * @param pPrivate - info about the bank
1642  * @param v        - result goes here
1643  */
1644 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
1645 {
1646         int r;
1647         r = target_read_u32(pPrivate->pChip->target,
1648                         pPrivate->controller_address + offset_EFC_FSR,
1649                         v);
1650         LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1651                 (unsigned int)(*v),
1652                 ((unsigned int)((*v >> 2) & 1)),
1653                 ((unsigned int)((*v >> 1) & 1)),
1654                 ((unsigned int)((*v >> 0) & 1)));
1655
1656         return r;
1657 }
1658
1659 /**
1660  * Get the result of the last executed command.
1661  * @param pPrivate - info about the bank
1662  * @param v        - result goes here
1663  */
1664 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
1665 {
1666         int r;
1667         uint32_t rv;
1668         r = target_read_u32(pPrivate->pChip->target,
1669                         pPrivate->controller_address + offset_EFC_FRR,
1670                         &rv);
1671         if (v)
1672                 *v = rv;
1673         LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1674         return r;
1675 }
1676
1677 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
1678         unsigned command, unsigned argument)
1679 {
1680         uint32_t n, v;
1681         int r;
1682         int retry;
1683
1684         retry = 0;
1685 do_retry:
1686
1687         /* Check command & argument */
1688         switch (command) {
1689
1690                 case AT91C_EFC_FCMD_WP:
1691                 case AT91C_EFC_FCMD_WPL:
1692                 case AT91C_EFC_FCMD_EWP:
1693                 case AT91C_EFC_FCMD_EWPL:
1694                 /* case AT91C_EFC_FCMD_EPL: */
1695                 /* case AT91C_EFC_FCMD_EPA: */
1696                 case AT91C_EFC_FCMD_SLB:
1697                 case AT91C_EFC_FCMD_CLB:
1698                         n = (pPrivate->size_bytes / pPrivate->page_size);
1699                         if (argument >= n)
1700                                 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1701                         break;
1702
1703                 case AT91C_EFC_FCMD_SFB:
1704                 case AT91C_EFC_FCMD_CFB:
1705                         if (argument >= pPrivate->pChip->details.n_gpnvms) {
1706                                 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1707                                                 pPrivate->pChip->details.n_gpnvms);
1708                         }
1709                         break;
1710
1711                 case AT91C_EFC_FCMD_GETD:
1712                 case AT91C_EFC_FCMD_EA:
1713                 case AT91C_EFC_FCMD_GLB:
1714                 case AT91C_EFC_FCMD_GFB:
1715                 case AT91C_EFC_FCMD_STUI:
1716                 case AT91C_EFC_FCMD_SPUI:
1717                         if (argument != 0)
1718                                 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1719                         break;
1720                 default:
1721                         LOG_ERROR("Unknown command %d", command);
1722                         break;
1723         }
1724
1725         if (command == AT91C_EFC_FCMD_SPUI) {
1726                 /* this is a very special situation. */
1727                 /* Situation (1) - error/retry - see below */
1728                 /*      And we are being called recursively */
1729                 /* Situation (2) - normal, finished reading unique id */
1730         } else {
1731                 /* it should be "ready" */
1732                 EFC_GetStatus(pPrivate, &v);
1733                 if (v & 1) {
1734                         /* then it is ready */
1735                         /* we go on */
1736                 } else {
1737                         if (retry) {
1738                                 /* we have done this before */
1739                                 /* the controller is not responding. */
1740                                 LOG_ERROR("flash controller(%d) is not ready! Error",
1741                                         pPrivate->bank_number);
1742                                 return ERROR_FAIL;
1743                         } else {
1744                                 retry++;
1745                                 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1746                                         pPrivate->bank_number);
1747                                 /* we do that by issuing the *STOP* command */
1748                                 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1749                                 /* above is recursive, and further recursion is blocked by */
1750                                 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1751                                 goto do_retry;
1752                         }
1753                 }
1754         }
1755
1756         v = (0x5A << 24) | (argument << 8) | command;
1757         LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1758         r = target_write_u32(pPrivate->pBank->target,
1759                         pPrivate->controller_address + offset_EFC_FCR, v);
1760         if (r != ERROR_OK)
1761                 LOG_DEBUG("Error Write failed");
1762         return r;
1763 }
1764
1765 /**
1766  * Performs the given command and wait until its completion (or an error).
1767  * @param pPrivate - info about the bank
1768  * @param command  - Command to perform.
1769  * @param argument - Optional command argument.
1770  * @param status   - put command status bits here
1771  */
1772 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
1773         unsigned command,
1774         unsigned argument,
1775         uint32_t *status)
1776 {
1777
1778         int r;
1779         uint32_t v;
1780         long long ms_now, ms_end;
1781
1782         /* default */
1783         if (status)
1784                 *status = 0;
1785
1786         r = EFC_StartCommand(pPrivate, command, argument);
1787         if (r != ERROR_OK)
1788                 return r;
1789
1790         ms_end = 500 + timeval_ms();
1791
1792         do {
1793                 r = EFC_GetStatus(pPrivate, &v);
1794                 if (r != ERROR_OK)
1795                         return r;
1796                 ms_now = timeval_ms();
1797                 if (ms_now > ms_end) {
1798                         /* error */
1799                         LOG_ERROR("Command timeout");
1800                         return ERROR_FAIL;
1801                 }
1802         } while ((v & 1) == 0);
1803
1804         /* error bits.. */
1805         if (status)
1806                 *status = (v & 0x6);
1807         return ERROR_OK;
1808
1809 }
1810
1811 /**
1812  * Read the unique ID.
1813  * @param pPrivate - info about the bank
1814  * The unique ID is stored in the 'pPrivate' structure.
1815  */
1816 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
1817 {
1818         int r;
1819         uint32_t v;
1820         int x;
1821         /* assume 0 */
1822         pPrivate->pChip->cfg.unique_id[0] = 0;
1823         pPrivate->pChip->cfg.unique_id[1] = 0;
1824         pPrivate->pChip->cfg.unique_id[2] = 0;
1825         pPrivate->pChip->cfg.unique_id[3] = 0;
1826
1827         LOG_DEBUG("Begin");
1828         r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1829         if (r < 0)
1830                 return r;
1831
1832         for (x = 0; x < 4; x++) {
1833                 r = target_read_u32(pPrivate->pChip->target,
1834                                 pPrivate->pBank->base + (x * 4),
1835                                 &v);
1836                 if (r < 0)
1837                         return r;
1838                 pPrivate->pChip->cfg.unique_id[x] = v;
1839         }
1840
1841         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1842         LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1843                 r,
1844                 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1845                 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1846                 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1847                 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1848         return r;
1849
1850 }
1851
1852 /**
1853  * Erases the entire flash.
1854  * @param pPrivate - the info about the bank.
1855  */
1856 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
1857 {
1858         LOG_DEBUG("Here");
1859         return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1860 }
1861
1862 /**
1863  * Gets current GPNVM state.
1864  * @param pPrivate - info about the bank.
1865  * @param gpnvm    -  GPNVM bit index.
1866  * @param puthere  - result stored here.
1867  */
1868 /* ------------------------------------------------------------------------------ */
1869 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1870 {
1871         uint32_t v;
1872         int r;
1873
1874         LOG_DEBUG("Here");
1875         if (pPrivate->bank_number != 0) {
1876                 LOG_ERROR("GPNVM only works with Bank0");
1877                 return ERROR_FAIL;
1878         }
1879
1880         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1881                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1882                         gpnvm, pPrivate->pChip->details.n_gpnvms);
1883                 return ERROR_FAIL;
1884         }
1885
1886         /* Get GPNVMs status */
1887         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1888         if (r != ERROR_OK) {
1889                 LOG_ERROR("Failed");
1890                 return r;
1891         }
1892
1893         r = EFC_GetResult(pPrivate, &v);
1894
1895         if (puthere) {
1896                 /* Check if GPNVM is set */
1897                 /* get the bit and make it a 0/1 */
1898                 *puthere = (v >> gpnvm) & 1;
1899         }
1900
1901         return r;
1902 }
1903
1904 /**
1905  * Clears the selected GPNVM bit.
1906  * @param pPrivate info about the bank
1907  * @param gpnvm GPNVM index.
1908  * @returns 0 if successful; otherwise returns an error code.
1909  */
1910 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1911 {
1912         int r;
1913         unsigned v;
1914
1915         LOG_DEBUG("Here");
1916         if (pPrivate->bank_number != 0) {
1917                 LOG_ERROR("GPNVM only works with Bank0");
1918                 return ERROR_FAIL;
1919         }
1920
1921         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1922                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1923                         gpnvm, pPrivate->pChip->details.n_gpnvms);
1924                 return ERROR_FAIL;
1925         }
1926
1927         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1928         if (r != ERROR_OK) {
1929                 LOG_DEBUG("Failed: %d", r);
1930                 return r;
1931         }
1932         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1933         LOG_DEBUG("End: %d", r);
1934         return r;
1935 }
1936
1937 /**
1938  * Sets the selected GPNVM bit.
1939  * @param pPrivate info about the bank
1940  * @param gpnvm GPNVM index.
1941  */
1942 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1943 {
1944         int r;
1945         unsigned v;
1946
1947         if (pPrivate->bank_number != 0) {
1948                 LOG_ERROR("GPNVM only works with Bank0");
1949                 return ERROR_FAIL;
1950         }
1951
1952         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1953                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1954                         gpnvm, pPrivate->pChip->details.n_gpnvms);
1955                 return ERROR_FAIL;
1956         }
1957
1958         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1959         if (r != ERROR_OK)
1960                 return r;
1961         if (v) {
1962                 /* already set */
1963                 r = ERROR_OK;
1964         } else {
1965                 /* set it */
1966                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1967         }
1968         return r;
1969 }
1970
1971 /**
1972  * Returns a bit field (at most 64) of locked regions within a page.
1973  * @param pPrivate info about the bank
1974  * @param v where to store locked bits
1975  */
1976 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
1977 {
1978         int r;
1979         LOG_DEBUG("Here");
1980         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1981         if (r == ERROR_OK)
1982                 r = EFC_GetResult(pPrivate, v);
1983         LOG_DEBUG("End: %d", r);
1984         return r;
1985 }
1986
1987 /**
1988  * Unlocks all the regions in the given address range.
1989  * @param pPrivate info about the bank
1990  * @param start_sector first sector to unlock
1991  * @param end_sector last (inclusive) to unlock
1992  */
1993
1994 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
1995         unsigned start_sector,
1996         unsigned end_sector)
1997 {
1998         int r;
1999         uint32_t status;
2000         uint32_t pg;
2001         uint32_t pages_per_sector;
2002
2003         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2004
2005         /* Unlock all pages */
2006         while (start_sector <= end_sector) {
2007                 pg = start_sector * pages_per_sector;
2008
2009                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
2010                 if (r != ERROR_OK)
2011                         return r;
2012                 start_sector++;
2013         }
2014
2015         return ERROR_OK;
2016 }
2017
2018 /**
2019  * Locks regions
2020  * @param pPrivate - info about the bank
2021  * @param start_sector - first sector to lock
2022  * @param end_sector   - last sector (inclusive) to lock
2023  */
2024 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
2025         unsigned start_sector,
2026         unsigned end_sector)
2027 {
2028         uint32_t status;
2029         uint32_t pg;
2030         uint32_t pages_per_sector;
2031         int r;
2032
2033         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2034
2035         /* Lock all pages */
2036         while (start_sector <= end_sector) {
2037                 pg = start_sector * pages_per_sector;
2038
2039                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
2040                 if (r != ERROR_OK)
2041                         return r;
2042                 start_sector++;
2043         }
2044         return ERROR_OK;
2045 }
2046
2047 /****** END SAM3 CODE ********/
2048
2049 /* begin helpful debug code */
2050 /* print the fieldname, the field value, in dec & hex, and return field value */
2051 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
2052         const char *regname,
2053         uint32_t value,
2054         unsigned shift,
2055         unsigned width)
2056 {
2057         uint32_t v;
2058         int hwidth, dwidth;
2059
2060
2061         /* extract the field */
2062         v = value >> shift;
2063         v = v & ((1 << width)-1);
2064         if (width <= 16) {
2065                 hwidth = 4;
2066                 dwidth = 5;
2067         } else {
2068                 hwidth = 8;
2069                 dwidth = 12;
2070         }
2071
2072         /* show the basics */
2073         LOG_USER_N("\t%*s: %*d [0x%0*x] ",
2074                 REG_NAME_WIDTH, regname,
2075                 dwidth, v,
2076                 hwidth, v);
2077         return v;
2078 }
2079
2080 static const char _unknown[] = "unknown";
2081 static const char *const eproc_names[] = {
2082         _unknown,                                       /* 0 */
2083         "arm946es",                                     /* 1 */
2084         "arm7tdmi",                                     /* 2 */
2085         "cortex-m3",                            /* 3 */
2086         "arm920t",                                      /* 4 */
2087         "arm926ejs",                            /* 5 */
2088         _unknown,                                       /* 6 */
2089         _unknown,                                       /* 7 */
2090         _unknown,                                       /* 8 */
2091         _unknown,                                       /* 9 */
2092         _unknown,                                       /* 10 */
2093         _unknown,                                       /* 11 */
2094         _unknown,                                       /* 12 */
2095         _unknown,                                       /* 13 */
2096         _unknown,                                       /* 14 */
2097         _unknown,                                       /* 15 */
2098 };
2099
2100 #define nvpsize2 nvpsize                /* these two tables are identical */
2101 static const char *const nvpsize[] = {
2102         "none",                                         /*  0 */
2103         "8K bytes",                                     /*  1 */
2104         "16K bytes",                            /*  2 */
2105         "32K bytes",                            /*  3 */
2106         _unknown,                                       /*  4 */
2107         "64K bytes",                            /*  5 */
2108         _unknown,                                       /*  6 */
2109         "128K bytes",                           /*  7 */
2110         _unknown,                                       /*  8 */
2111         "256K bytes",                           /*  9 */
2112         "512K bytes",                           /* 10 */
2113         _unknown,                                       /* 11 */
2114         "1024K bytes",                          /* 12 */
2115         _unknown,                                       /* 13 */
2116         "2048K bytes",                          /* 14 */
2117         _unknown,                                       /* 15 */
2118 };
2119
2120 static const char *const sramsize[] = {
2121         "48K Bytes",                            /*  0 */
2122         "1K Bytes",                                     /*  1 */
2123         "2K Bytes",                                     /*  2 */
2124         "6K Bytes",                                     /*  3 */
2125         "112K Bytes",                           /*  4 */
2126         "4K Bytes",                                     /*  5 */
2127         "80K Bytes",                            /*  6 */
2128         "160K Bytes",                           /*  7 */
2129         "8K Bytes",                                     /*  8 */
2130         "16K Bytes",                            /*  9 */
2131         "32K Bytes",                            /* 10 */
2132         "64K Bytes",                            /* 11 */
2133         "128K Bytes",                           /* 12 */
2134         "256K Bytes",                           /* 13 */
2135         "96K Bytes",                            /* 14 */
2136         "512K Bytes",                           /* 15 */
2137
2138 };
2139
2140 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2141         { 0x19,  "AT91SAM9xx Series"                                            },
2142         { 0x29,  "AT91SAM9XExx Series"                                          },
2143         { 0x34,  "AT91x34 Series"                                                       },
2144         { 0x37,  "CAP7 Series"                                                          },
2145         { 0x39,  "CAP9 Series"                                                          },
2146         { 0x3B,  "CAP11 Series"                                                         },
2147         { 0x40,  "AT91x40 Series"                                                       },
2148         { 0x42,  "AT91x42 Series"                                                       },
2149         { 0x55,  "AT91x55 Series"                                                       },
2150         { 0x60,  "AT91SAM7Axx Series"                                           },
2151         { 0x61,  "AT91SAM7AQxx Series"                                          },
2152         { 0x63,  "AT91x63 Series"                                                       },
2153         { 0x70,  "AT91SAM7Sxx Series"                                           },
2154         { 0x71,  "AT91SAM7XCxx Series"                                          },
2155         { 0x72,  "AT91SAM7SExx Series"                                          },
2156         { 0x73,  "AT91SAM7Lxx Series"                                           },
2157         { 0x75,  "AT91SAM7Xxx Series"                                           },
2158         { 0x76,  "AT91SAM7SLxx Series"                                          },
2159         { 0x80,  "ATSAM3UxC Series (100-pin version)"           },
2160         { 0x81,  "ATSAM3UxE Series (144-pin version)"           },
2161         { 0x83,  "ATSAM3AxC Series (100-pin version)"           },
2162         { 0x84,  "ATSAM3XxC Series (100-pin version)"           },
2163         { 0x85,  "ATSAM3XxE Series (144-pin version)"           },
2164         { 0x86,  "ATSAM3XxG Series (208/217-pin version)"       },
2165         { 0x88,  "ATSAM3SxA Series (48-pin version)"            },
2166         { 0x89,  "ATSAM3SxB Series (64-pin version)"            },
2167         { 0x8A,  "ATSAM3SxC Series (100-pin version)"           },
2168         { 0x92,  "AT91x92 Series"                                                       },
2169         { 0x93,  "ATSAM3NxA Series (48-pin version)"            },
2170         { 0x94,  "ATSAM3NxB Series (64-pin version)"            },
2171         { 0x95,  "ATSAM3NxC Series (100-pin version)"           },
2172         { 0x98,  "ATSAM3SDxA Series (48-pin version)"           },
2173         { 0x99,  "ATSAM3SDxB Series (64-pin version)"           },
2174         { 0x9A,  "ATSAM3SDxC Series (100-pin version)"          },
2175         { 0xA5,  "ATSAM5A"                                                              },
2176         { 0xF0,  "AT75Cxx Series"                                                       },
2177         { -1, NULL },
2178 };
2179
2180 static const char *const nvptype[] = {
2181         "rom",  /* 0 */
2182         "romless or onchip flash",      /* 1 */
2183         "embedded flash memory",/* 2 */
2184         "rom(nvpsiz) + embedded flash (nvpsiz2)",       /* 3 */
2185         "sram emulating flash", /* 4 */
2186         _unknown,       /* 5 */
2187         _unknown,       /* 6 */
2188         _unknown,       /* 7 */
2189 };
2190
2191 static const char *_yes_or_no(uint32_t v)
2192 {
2193         if (v)
2194                 return "YES";
2195         else
2196                 return "NO";
2197 }
2198
2199 static const char *const _rc_freq[] = {
2200         "4 MHz", "8 MHz", "12 MHz", "reserved"
2201 };
2202
2203 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
2204 {
2205         uint32_t v;
2206         uint32_t rcen;
2207
2208         v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2209         LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2210         v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2211         LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2212         rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2213         LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2214         v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2215         LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2216
2217         pChip->cfg.rc_freq = 0;
2218         if (rcen) {
2219                 switch (v) {
2220                         default:
2221                                 pChip->cfg.rc_freq = 0;
2222                                 break;
2223                         case 0:
2224                                 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2225                                 break;
2226                         case 1:
2227                                 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2228                                 break;
2229                         case 2:
2230                                 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2231                                 break;
2232                 }
2233         }
2234
2235         v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2236         LOG_USER("(startup clks, time= %f uSecs)",
2237                 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2238         v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2239         LOG_USER("(mainosc source: %s)",
2240                 v ? "external xtal" : "internal RC");
2241
2242         v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2243         LOG_USER("(clock failure enabled: %s)",
2244                 _yes_or_no(v));
2245 }
2246
2247 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
2248 {
2249         int x;
2250         uint32_t v;
2251         const char *cp;
2252
2253         sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2254         LOG_USER_N("\n");
2255
2256         v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2257         LOG_USER("%s", eproc_names[v]);
2258
2259         v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2260         LOG_USER("%s", nvpsize[v]);
2261
2262         v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2263         LOG_USER("%s", nvpsize2[v]);
2264
2265         v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2266         LOG_USER("%s", sramsize[v]);
2267
2268         v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2269         cp = _unknown;
2270         for (x = 0; archnames[x].name; x++) {
2271                 if (v == archnames[x].value) {
2272                         cp = archnames[x].name;
2273                         break;
2274                 }
2275         }
2276
2277         LOG_USER("%s", cp);
2278
2279         v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2280         LOG_USER("%s", nvptype[v]);
2281
2282         v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2283         LOG_USER("(exists: %s)", _yes_or_no(v));
2284 }
2285
2286 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
2287 {
2288         uint32_t v;
2289
2290         v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2291         LOG_USER("(main ready: %s)", _yes_or_no(v));
2292
2293         v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2294
2295         v = (v * pChip->cfg.slow_freq) / 16;
2296         pChip->cfg.mainosc_freq = v;
2297
2298         LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2299                 _tomhz(v),
2300                 pChip->cfg.slow_freq / 1000,
2301                 pChip->cfg.slow_freq % 1000);
2302 }
2303
2304 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
2305 {
2306         uint32_t mula, diva;
2307
2308         diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2309         LOG_USER_N("\n");
2310         mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2311         LOG_USER_N("\n");
2312         pChip->cfg.plla_freq = 0;
2313         if (mula == 0)
2314                 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2315         else if (diva == 0)
2316                 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2317         else if (diva == 1) {
2318                 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
2319                 LOG_USER("\tPLLA Freq: %3.03f MHz",
2320                         _tomhz(pChip->cfg.plla_freq));
2321         }
2322 }
2323
2324 static void sam3_explain_mckr(struct sam3_chip *pChip)
2325 {
2326         uint32_t css, pres, fin = 0;
2327         int pdiv = 0;
2328         const char *cp = NULL;
2329
2330         css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2331         switch (css & 3) {
2332                 case 0:
2333                         fin = pChip->cfg.slow_freq;
2334                         cp = "slowclk";
2335                         break;
2336                 case 1:
2337                         fin = pChip->cfg.mainosc_freq;
2338                         cp  = "mainosc";
2339                         break;
2340                 case 2:
2341                         fin = pChip->cfg.plla_freq;
2342                         cp  = "plla";
2343                         break;
2344                 case 3:
2345                         if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2346                                 fin = 480 * 1000 * 1000;
2347                                 cp = "upll";
2348                         } else {
2349                                 fin = 0;
2350                                 cp  = "upll (*ERROR* UPLL is disabled)";
2351                         }
2352                         break;
2353                 default:
2354                         assert(0);
2355                         break;
2356         }
2357
2358         LOG_USER("%s (%3.03f Mhz)",
2359                 cp,
2360                 _tomhz(fin));
2361         pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2362         switch (pres & 0x07) {
2363                 case 0:
2364                         pdiv = 1;
2365                         cp = "selected clock";
2366                         break;
2367                 case 1:
2368                         pdiv = 2;
2369                         cp = "clock/2";
2370                         break;
2371                 case 2:
2372                         pdiv = 4;
2373                         cp = "clock/4";
2374                         break;
2375                 case 3:
2376                         pdiv = 8;
2377                         cp = "clock/8";
2378                         break;
2379                 case 4:
2380                         pdiv = 16;
2381                         cp = "clock/16";
2382                         break;
2383                 case 5:
2384                         pdiv = 32;
2385                         cp = "clock/32";
2386                         break;
2387                 case 6:
2388                         pdiv = 64;
2389                         cp = "clock/64";
2390                         break;
2391                 case 7:
2392                         pdiv = 6;
2393                         cp = "clock/6";
2394                         break;
2395                 default:
2396                         assert(0);
2397                         break;
2398         }
2399         LOG_USER("(%s)", cp);
2400         fin = fin / pdiv;
2401         /* sam3 has a *SINGLE* clock - */
2402         /* other at91 series parts have divisors for these. */
2403         pChip->cfg.cpu_freq = fin;
2404         pChip->cfg.mclk_freq = fin;
2405         pChip->cfg.fclk_freq = fin;
2406         LOG_USER("\t\tResult CPU Freq: %3.03f",
2407                 _tomhz(fin));
2408 }
2409
2410 #if 0
2411 static struct sam3_chip *target2sam3(struct target *pTarget)
2412 {
2413         struct sam3_chip *pChip;
2414
2415         if (pTarget == NULL)
2416                 return NULL;
2417
2418         pChip = all_sam3_chips;
2419         while (pChip) {
2420                 if (pChip->target == pTarget)
2421                         break;  /* return below */
2422                 else
2423                         pChip = pChip->next;
2424         }
2425         return pChip;
2426 }
2427 #endif
2428
2429 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2430 {
2431         /* this function exists to help */
2432         /* keep funky offsetof() errors */
2433         /* and casting from causing bugs */
2434
2435         /* By using prototypes - we can detect what would */
2436         /* be casting errors. */
2437
2438         return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2439 }
2440
2441
2442 #define SAM3_ENTRY(NAME, FUNC)  { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2443                                                   struct sam3_cfg, \
2444                                                   NAME), # NAME, FUNC }
2445 static const struct sam3_reg_list sam3_all_regs[] = {
2446         SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2447         SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2448         SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2449         SAM3_ENTRY(CKGR_UCKR, NULL),
2450         SAM3_ENTRY(PMC_FSMR, NULL),
2451         SAM3_ENTRY(PMC_FSPR, NULL),
2452         SAM3_ENTRY(PMC_IMR, NULL),
2453         SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2454         SAM3_ENTRY(PMC_PCK0, NULL),
2455         SAM3_ENTRY(PMC_PCK1, NULL),
2456         SAM3_ENTRY(PMC_PCK2, NULL),
2457         SAM3_ENTRY(PMC_PCSR, NULL),
2458         SAM3_ENTRY(PMC_SCSR, NULL),
2459         SAM3_ENTRY(PMC_SR, NULL),
2460         SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2461         SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2462         SAM3_ENTRY(CHIPID_EXID, NULL),
2463         SAM3_ENTRY(CHIPID_EXID2, NULL),
2464         /* TERMINATE THE LIST */
2465         { .name = NULL }
2466 };
2467 #undef SAM3_ENTRY
2468
2469 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2470 {
2471         return (struct sam3_bank_private *)(bank->driver_priv);
2472 }
2473
2474 /**
2475  * Given a pointer to where it goes in the structure,
2476  * determine the register name, address from the all registers table.
2477  */
2478 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2479 {
2480         const struct sam3_reg_list *pReg;
2481
2482         pReg = &(sam3_all_regs[0]);
2483         while (pReg->name) {
2484                 uint32_t *pPossible;
2485
2486                 /* calculate where this one go.. */
2487                 /* it is "possibly" this register. */
2488
2489                 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2490
2491                 /* well? Is it this register */
2492                 if (pPossible == goes_here) {
2493                         /* Jump for joy! */
2494                         return pReg;
2495                 }
2496
2497                 /* next... */
2498                 pReg++;
2499         }
2500         /* This is *TOTAL*PANIC* - we are totally screwed. */
2501         LOG_ERROR("INVALID SAM3 REGISTER");
2502         return NULL;
2503 }
2504
2505 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2506 {
2507         const struct sam3_reg_list *pReg;
2508         int r;
2509
2510         pReg = sam3_GetReg(pChip, goes_here);
2511         if (!pReg)
2512                 return ERROR_FAIL;
2513
2514         r = target_read_u32(pChip->target, pReg->address, goes_here);
2515         if (r != ERROR_OK) {
2516                 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2517                         pReg->name, (unsigned)(pReg->address), r);
2518         }
2519         return r;
2520 }
2521
2522 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2523 {
2524         int r;
2525         const struct sam3_reg_list *pReg;
2526
2527         pReg = &(sam3_all_regs[0]);
2528         while (pReg->name) {
2529                 r = sam3_ReadThisReg(pChip,
2530                                 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2531                 if (r != ERROR_OK) {
2532                         LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
2533                                 pReg->name, ((unsigned)(pReg->address)), r);
2534                         return r;
2535                 }
2536                 pReg++;
2537         }
2538
2539         /* Chip identification register
2540         *
2541         * Unfortunately, the chip identification register is not at
2542         * a constant address across all of the SAM3 series'. As a
2543         * consequence, a simple heuristic is used to find where it's
2544         * at...
2545         *
2546         * If the contents at the first address is zero, then we know
2547         * that the second address is where the chip id register is.
2548         * We can deduce this because for those SAM's that have the
2549         * chip id @ 0x400e0940, the first address, 0x400e0740, is
2550         * located in the memory map of the Power Management Controller
2551         * (PMC). Furthermore, the address is not used by the PMC.
2552         * So when read, the memory controller returns zero.*/
2553         if (pChip->cfg.CHIPID_CIDR == 0)        {
2554                 /*Put the correct CIDR and EXID values in the pChip structure */
2555                 pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
2556                 pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
2557         }
2558         return ERROR_OK;
2559 }
2560
2561 static int sam3_GetInfo(struct sam3_chip *pChip)
2562 {
2563         const struct sam3_reg_list *pReg;
2564         uint32_t regval;
2565
2566         pReg = &(sam3_all_regs[0]);
2567         while (pReg->name) {
2568                 /* display all regs */
2569                 LOG_DEBUG("Start: %s", pReg->name);
2570                 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2571                 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2572                         REG_NAME_WIDTH,
2573                         pReg->name,
2574                         pReg->address,
2575                         regval);
2576                 if (pReg->explain_func)
2577                         (*(pReg->explain_func))(pChip);
2578                 LOG_DEBUG("End: %s", pReg->name);
2579                 pReg++;
2580         }
2581         LOG_USER("   rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2582         LOG_USER("  mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2583         LOG_USER("     plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2584         LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2585         LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2586
2587         LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2588                 pChip->cfg.unique_id[0],
2589                 pChip->cfg.unique_id[1],
2590                 pChip->cfg.unique_id[2],
2591                 pChip->cfg.unique_id[3]);
2592
2593         return ERROR_OK;
2594 }
2595
2596 static int sam3_erase_check(struct flash_bank *bank)
2597 {
2598         int x;
2599
2600         LOG_DEBUG("Here");
2601         if (bank->target->state != TARGET_HALTED) {
2602                 LOG_ERROR("Target not halted");
2603                 return ERROR_TARGET_NOT_HALTED;
2604         }
2605         if (0 == bank->num_sectors) {
2606                 LOG_ERROR("Target: not supported/not probed");
2607                 return ERROR_FAIL;
2608         }
2609
2610         LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2611         for (x = 0; x < bank->num_sectors; x++)
2612                 bank->sectors[x].is_erased = 1;
2613
2614         LOG_DEBUG("Done");
2615         return ERROR_OK;
2616 }
2617
2618 static int sam3_protect_check(struct flash_bank *bank)
2619 {
2620         int r;
2621         uint32_t v = 0;
2622         unsigned x;
2623         struct sam3_bank_private *pPrivate;
2624
2625         LOG_DEBUG("Begin");
2626         if (bank->target->state != TARGET_HALTED) {
2627                 LOG_ERROR("Target not halted");
2628                 return ERROR_TARGET_NOT_HALTED;
2629         }
2630
2631         pPrivate = get_sam3_bank_private(bank);
2632         if (!pPrivate) {
2633                 LOG_ERROR("no private for this bank?");
2634                 return ERROR_FAIL;
2635         }
2636         if (!(pPrivate->probed))
2637                 return ERROR_FLASH_BANK_NOT_PROBED;
2638
2639         r = FLASHD_GetLockBits(pPrivate, &v);
2640         if (r != ERROR_OK) {
2641                 LOG_DEBUG("Failed: %d", r);
2642                 return r;
2643         }
2644
2645         for (x = 0; x < pPrivate->nsectors; x++)
2646                 bank->sectors[x].is_protected = (!!(v & (1 << x)));
2647         LOG_DEBUG("Done");
2648         return ERROR_OK;
2649 }
2650
2651 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2652 {
2653         struct sam3_chip *pChip;
2654
2655         pChip = all_sam3_chips;
2656
2657         /* is this an existing chip? */
2658         while (pChip) {
2659                 if (pChip->target == bank->target)
2660                         break;
2661                 pChip = pChip->next;
2662         }
2663
2664         if (!pChip) {
2665                 /* this is a *NEW* chip */
2666                 pChip = calloc(1, sizeof(struct sam3_chip));
2667                 if (!pChip) {
2668                         LOG_ERROR("NO RAM!");
2669                         return ERROR_FAIL;
2670                 }
2671                 pChip->target = bank->target;
2672                 /* insert at head */
2673                 pChip->next = all_sam3_chips;
2674                 all_sam3_chips = pChip;
2675                 pChip->target = bank->target;
2676                 /* assumption is this runs at 32khz */
2677                 pChip->cfg.slow_freq = 32768;
2678                 pChip->probed = 0;
2679         }
2680
2681         switch (bank->base) {
2682                 default:
2683                         LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2684                         "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2685                         "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
2686                         ((unsigned int)(bank->base)),
2687                         ((unsigned int)(FLASH_BANK0_BASE_U)),
2688                         ((unsigned int)(FLASH_BANK1_BASE_U)),
2689                         ((unsigned int)(FLASH_BANK_BASE_S)),
2690                         ((unsigned int)(FLASH_BANK_BASE_N)),
2691                         ((unsigned int)(FLASH_BANK0_BASE_AX)),
2692                     ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
2693                     ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
2694                         return ERROR_FAIL;
2695                         break;
2696
2697                 /* at91sam3s and at91sam3n series only has bank 0*/
2698                 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
2699                 case FLASH_BANK_BASE_S:
2700                 case FLASH_BANK0_BASE_U:
2701                         bank->driver_priv = &(pChip->details.bank[0]);
2702                         bank->bank_number = 0;
2703                         pChip->details.bank[0].pChip = pChip;
2704                         pChip->details.bank[0].pBank = bank;
2705                         break;
2706
2707                 /* Bank 1 of at91sam3u or at91sam3ax series */
2708                 case FLASH_BANK1_BASE_U:
2709                 case FLASH_BANK1_BASE_256K_AX:
2710                 case FLASH_BANK1_BASE_512K_AX:
2711                         bank->driver_priv = &(pChip->details.bank[1]);
2712                         bank->bank_number = 1;
2713                         pChip->details.bank[1].pChip = pChip;
2714                         pChip->details.bank[1].pBank = bank;
2715                         break;
2716         }
2717
2718         /* we initialize after probing. */
2719         return ERROR_OK;
2720 }
2721
2722 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
2723 {
2724         const struct sam3_chip_details *pDetails;
2725         struct sam3_chip *pChip;
2726         struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
2727         unsigned x;
2728
2729         LOG_DEBUG("Begin");
2730         pDetails = all_sam3_details;
2731         while (pDetails->name) {
2732                 /* Compare cidr without version bits */
2733                 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2734                         break;
2735                 else
2736                         pDetails++;
2737         }
2738         if (pDetails->name == NULL) {
2739                 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2740                         (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2741                 /* Help the victim, print details about the chip */
2742                 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2743                         pPrivate->pChip->cfg.CHIPID_CIDR);
2744                 sam3_explain_chipid_cidr(pPrivate->pChip);
2745                 return ERROR_FAIL;
2746         }
2747
2748         /* DANGER: THERE ARE DRAGONS HERE */
2749
2750         /* get our pChip - it is going */
2751         /* to be over-written shortly */
2752         pChip = pPrivate->pChip;
2753
2754         /* Note that, in reality: */
2755         /*  */
2756         /*     pPrivate = &(pChip->details.bank[0]) */
2757         /* or  pPrivate = &(pChip->details.bank[1]) */
2758         /*  */
2759
2760         /* save the "bank" pointers */
2761         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
2762                 saved_banks[x] = pChip->details.bank[x].pBank;
2763
2764         /* Overwrite the "details" structure. */
2765         memcpy(&(pPrivate->pChip->details),
2766                 pDetails,
2767                 sizeof(pPrivate->pChip->details));
2768
2769         /* now fix the ghosted pointers */
2770         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2771                 pChip->details.bank[x].pChip = pChip;
2772                 pChip->details.bank[x].pBank = saved_banks[x];
2773         }
2774
2775         /* update the *BANK*SIZE* */
2776
2777         LOG_DEBUG("End");
2778         return ERROR_OK;
2779 }
2780
2781 static int _sam3_probe(struct flash_bank *bank, int noise)
2782 {
2783         unsigned x;
2784         int r;
2785         struct sam3_bank_private *pPrivate;
2786
2787
2788         LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2789         if (bank->target->state != TARGET_HALTED) {
2790                 LOG_ERROR("Target not halted");
2791                 return ERROR_TARGET_NOT_HALTED;
2792         }
2793
2794         pPrivate = get_sam3_bank_private(bank);
2795         if (!pPrivate) {
2796                 LOG_ERROR("Invalid/unknown bank number");
2797                 return ERROR_FAIL;
2798         }
2799
2800         r = sam3_ReadAllRegs(pPrivate->pChip);
2801         if (r != ERROR_OK)
2802                 return r;
2803
2804         LOG_DEBUG("Here");
2805         if (pPrivate->pChip->probed)
2806                 r = sam3_GetInfo(pPrivate->pChip);
2807         else
2808                 r = sam3_GetDetails(pPrivate);
2809         if (r != ERROR_OK)
2810                 return r;
2811
2812         /* update the flash bank size */
2813         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2814                 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2815                         bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2816                         break;
2817                 }
2818         }
2819
2820         if (bank->sectors == NULL) {
2821                 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2822                 if (bank->sectors == NULL) {
2823                         LOG_ERROR("No memory!");
2824                         return ERROR_FAIL;
2825                 }
2826                 bank->num_sectors = pPrivate->nsectors;
2827
2828                 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2829                         bank->sectors[x].size = pPrivate->sector_size;
2830                         bank->sectors[x].offset = x * (pPrivate->sector_size);
2831                         /* mark as unknown */
2832                         bank->sectors[x].is_erased = -1;
2833                         bank->sectors[x].is_protected = -1;
2834                 }
2835         }
2836
2837         pPrivate->probed = 1;
2838
2839         r = sam3_protect_check(bank);
2840         if (r != ERROR_OK)
2841                 return r;
2842
2843         LOG_DEBUG("Bank = %d, nbanks = %d",
2844                 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2845         if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2846                 /* read unique id, */
2847                 /* it appears to be associated with the *last* flash bank. */
2848                 FLASHD_ReadUniqueID(pPrivate);
2849         }
2850
2851         return r;
2852 }
2853
2854 static int sam3_probe(struct flash_bank *bank)
2855 {
2856         return _sam3_probe(bank, 1);
2857 }
2858
2859 static int sam3_auto_probe(struct flash_bank *bank)
2860 {
2861         return _sam3_probe(bank, 0);
2862 }
2863
2864 static int sam3_erase(struct flash_bank *bank, int first, int last)
2865 {
2866         struct sam3_bank_private *pPrivate;
2867         int r;
2868
2869         LOG_DEBUG("Here");
2870         if (bank->target->state != TARGET_HALTED) {
2871                 LOG_ERROR("Target not halted");
2872                 return ERROR_TARGET_NOT_HALTED;
2873         }
2874
2875         r = sam3_auto_probe(bank);
2876         if (r != ERROR_OK) {
2877                 LOG_DEBUG("Here,r=%d", r);
2878                 return r;
2879         }
2880
2881         pPrivate = get_sam3_bank_private(bank);
2882         if (!(pPrivate->probed))
2883                 return ERROR_FLASH_BANK_NOT_PROBED;
2884
2885         if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2886                 /* whole chip */
2887                 LOG_DEBUG("Here");
2888                 return FLASHD_EraseEntireBank(pPrivate);
2889         }
2890         LOG_INFO("sam3 auto-erases while programing (request ignored)");
2891         return ERROR_OK;
2892 }
2893
2894 static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
2895 {
2896         struct sam3_bank_private *pPrivate;
2897         int r;
2898
2899         LOG_DEBUG("Here");
2900         if (bank->target->state != TARGET_HALTED) {
2901                 LOG_ERROR("Target not halted");
2902                 return ERROR_TARGET_NOT_HALTED;
2903         }
2904
2905         pPrivate = get_sam3_bank_private(bank);
2906         if (!(pPrivate->probed))
2907                 return ERROR_FLASH_BANK_NOT_PROBED;
2908
2909         if (set)
2910                 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2911         else
2912                 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2913         LOG_DEBUG("End: r=%d", r);
2914
2915         return r;
2916
2917 }
2918
2919 static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)
2920 {
2921         if (bank->target->state != TARGET_HALTED) {
2922                 LOG_ERROR("Target not halted");
2923                 return ERROR_TARGET_NOT_HALTED;
2924         }
2925         buf[0] = 0;
2926         return ERROR_OK;
2927 }
2928
2929 static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2930 {
2931         uint32_t adr;
2932         int r;
2933
2934         adr = pagenum * pPrivate->page_size;
2935         adr += adr + pPrivate->base_address;
2936
2937         r = target_read_memory(pPrivate->pChip->target,
2938                         adr,
2939                         4,                                      /* THIS*MUST*BE* in 32bit values */
2940                         pPrivate->page_size / 4,
2941                         buf);
2942         if (r != ERROR_OK)
2943                 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
2944                         (unsigned int)(adr));
2945         return r;
2946 }
2947
2948 /* The code below is basically this: */
2949 /* compiled with */
2950 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
2951 /*  */
2952 /* Only the *CPU* can write to the flash buffer. */
2953 /* the DAP cannot... so - we download this 28byte thing */
2954 /* Run the algorithm - (below) */
2955 /* to program the device */
2956 /*  */
2957 /* ======================================== */
2958 /* #include <stdint.h> */
2959 /*  */
2960 /* struct foo { */
2961 /*   uint32_t *dst; */
2962 /*   const uint32_t *src; */
2963 /*   int   n; */
2964 /*   volatile uint32_t *base; */
2965 /*   uint32_t   cmd; */
2966 /* }; */
2967 /*  */
2968 /*  */
2969 /* uint32_t sam3_function(struct foo *p) */
2970 /* { */
2971 /*   volatile uint32_t *v; */
2972 /*   uint32_t *d; */
2973 /*   const uint32_t *s; */
2974 /*   int   n; */
2975 /*   uint32_t r; */
2976 /*  */
2977 /*   d = p->dst; */
2978 /*   s = p->src; */
2979 /*   n = p->n; */
2980 /*  */
2981 /*   do { */
2982 /*     *d++ = *s++; */
2983 /*   } while (--n) */
2984 /*     ; */
2985 /*  */
2986 /*   v = p->base; */
2987 /*  */
2988 /*   v[ 1 ] = p->cmd; */
2989 /*   do { */
2990 /*     r = v[8/4]; */
2991 /*   } while (!(r&1)) */
2992 /*     ; */
2993 /*   return r; */
2994 /* } */
2995 /* ======================================== */
2996
2997 static const uint8_t
2998         sam3_page_write_opcodes[] = {
2999         /*  24 0000 0446                mov     r4, r0 */
3000         0x04, 0x46,
3001         /*  25 0002 6168                ldr     r1, [r4, #4] */
3002         0x61, 0x68,
3003         /*  26 0004 0068                ldr     r0, [r0, #0] */
3004         0x00, 0x68,
3005         /*  27 0006 A268                ldr     r2, [r4, #8] */
3006         0xa2, 0x68,
3007         /*  28                          @ lr needed for prologue */
3008         /*  29                  .L2: */
3009         /*  30 0008 51F8043B            ldr     r3, [r1], #4 */
3010         0x51, 0xf8, 0x04, 0x3b,
3011         /*  31 000c 12F1FF32            adds    r2, r2, #-1 */
3012         0x12, 0xf1, 0xff, 0x32,
3013         /*  32 0010 40F8043B            str     r3, [r0], #4 */
3014         0x40, 0xf8, 0x04, 0x3b,
3015         /*  33 0014 F8D1                bne     .L2 */
3016         0xf8, 0xd1,
3017         /*  34 0016 E268                ldr     r2, [r4, #12] */
3018         0xe2, 0x68,
3019         /*  35 0018 2369                ldr     r3, [r4, #16] */
3020         0x23, 0x69,
3021         /*  36 001a 5360                str     r3, [r2, #4] */
3022         0x53, 0x60,
3023         /*  37 001c 0832                adds    r2, r2, #8 */
3024         0x08, 0x32,
3025         /*  38                  .L4: */
3026         /*  39 001e 1068                ldr     r0, [r2, #0] */
3027         0x10, 0x68,
3028         /*  40 0020 10F0010F            tst     r0, #1 */
3029         0x10, 0xf0, 0x01, 0x0f,
3030         /*  41 0024 FBD0                beq     .L4 */
3031         0xfb, 0xd0,
3032         0x00, 0xBE                              /* bkpt #0 */
3033 };
3034
3035 static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3036 {
3037         uint32_t adr;
3038         uint32_t status;
3039         uint32_t fmr;   /* EEFC Flash Mode Register */
3040         int r;
3041
3042         adr = pagenum * pPrivate->page_size;
3043         adr += (adr + pPrivate->base_address);
3044
3045         /* Get flash mode register value */
3046         r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
3047         if (r != ERROR_OK)
3048                 LOG_DEBUG("Error Read failed: read flash mode register");
3049
3050         /* Clear flash wait state field */
3051         fmr &= 0xfffff0ff;
3052
3053         /* set FWS (flash wait states) field in the FMR (flash mode register) */
3054         fmr |= (pPrivate->flash_wait_states << 8);
3055
3056         LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3057         r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
3058         if (r != ERROR_OK)
3059                 LOG_DEBUG("Error Write failed: set flash mode register");
3060
3061         LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3062         r = target_write_memory(pPrivate->pChip->target,
3063                         adr,
3064                         4,                                      /* THIS*MUST*BE* in 32bit values */
3065                         pPrivate->page_size / 4,
3066                         buf);
3067         if (r != ERROR_OK) {
3068                 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3069                         (unsigned int)(adr));
3070                 return r;
3071         }
3072
3073         r = EFC_PerformCommand(pPrivate,
3074                         /* send Erase & Write Page */
3075                         AT91C_EFC_FCMD_EWP,
3076                         pagenum,
3077                         &status);
3078
3079         if (r != ERROR_OK)
3080                 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3081                         (unsigned int)(adr));
3082         if (status & (1 << 2)) {
3083                 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3084                 return ERROR_FAIL;
3085         }
3086         if (status & (1 << 1)) {
3087                 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3088                 return ERROR_FAIL;
3089         }
3090         return ERROR_OK;
3091 }
3092
3093 static int sam3_write(struct flash_bank *bank,
3094         uint8_t *buffer,
3095         uint32_t offset,
3096         uint32_t count)
3097 {
3098         int n;
3099         unsigned page_cur;
3100         unsigned page_end;
3101         int r;
3102         unsigned page_offset;
3103         struct sam3_bank_private *pPrivate;
3104         uint8_t *pagebuffer;
3105
3106         /* incase we bail further below, set this to null */
3107         pagebuffer = NULL;
3108
3109         /* ignore dumb requests */
3110         if (count == 0) {
3111                 r = ERROR_OK;
3112                 goto done;
3113         }
3114
3115         if (bank->target->state != TARGET_HALTED) {
3116                 LOG_ERROR("Target not halted");
3117                 r = ERROR_TARGET_NOT_HALTED;
3118                 goto done;
3119         }
3120
3121         pPrivate = get_sam3_bank_private(bank);
3122         if (!(pPrivate->probed)) {
3123                 r = ERROR_FLASH_BANK_NOT_PROBED;
3124                 goto done;
3125         }
3126
3127         if ((offset + count) > pPrivate->size_bytes) {
3128                 LOG_ERROR("Flash write error - past end of bank");
3129                 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3130                         (unsigned int)(offset),
3131                         (unsigned int)(count),
3132                         (unsigned int)(pPrivate->size_bytes));
3133                 r = ERROR_FAIL;
3134                 goto done;
3135         }
3136
3137         pagebuffer = malloc(pPrivate->page_size);
3138         if (!pagebuffer) {
3139                 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
3140                 r = ERROR_FAIL;
3141                 goto done;
3142         }
3143
3144         /* what page do we start & end in? */
3145         page_cur = offset / pPrivate->page_size;
3146         page_end = (offset + count - 1) / pPrivate->page_size;
3147
3148         LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3149         LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3150
3151         /* Special case: all one page */
3152         /*  */
3153         /* Otherwise: */
3154         /*    (1) non-aligned start */
3155         /*    (2) body pages */
3156         /*    (3) non-aligned end. */
3157
3158         /* Handle special case - all one page. */
3159         if (page_cur == page_end) {
3160                 LOG_DEBUG("Special case, all in one page");
3161                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3162                 if (r != ERROR_OK)
3163                         goto done;
3164
3165                 page_offset = (offset & (pPrivate->page_size-1));
3166                 memcpy(pagebuffer + page_offset,
3167                         buffer,
3168                         count);
3169
3170                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3171                 if (r != ERROR_OK)
3172                         goto done;
3173                 r = ERROR_OK;
3174                 goto done;
3175         }
3176
3177         /* non-aligned start */
3178         page_offset = offset & (pPrivate->page_size - 1);
3179         if (page_offset) {
3180                 LOG_DEBUG("Not-Aligned start");
3181                 /* read the partial */
3182                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3183                 if (r != ERROR_OK)
3184                         goto done;
3185
3186                 /* over-write with new data */
3187                 n = (pPrivate->page_size - page_offset);
3188                 memcpy(pagebuffer + page_offset,
3189                         buffer,
3190                         n);
3191
3192                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3193                 if (r != ERROR_OK)
3194                         goto done;
3195
3196                 count  -= n;
3197                 offset += n;
3198                 buffer += n;
3199                 page_cur++;
3200         }
3201
3202         /* By checking that offset is correct here, we also
3203         fix a clang warning */
3204         assert(offset % pPrivate->page_size == 0);
3205
3206         /* intermediate large pages */
3207         /* also - the final *terminal* */
3208         /* if that terminal page is a full page */
3209         LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3210                 (int)page_cur, (int)page_end, (unsigned int)(count));
3211
3212         while ((page_cur < page_end) &&
3213                         (count >= pPrivate->page_size)) {
3214                 r = sam3_page_write(pPrivate, page_cur, buffer);
3215                 if (r != ERROR_OK)
3216                         goto done;
3217                 count -= pPrivate->page_size;
3218                 buffer += pPrivate->page_size;
3219                 page_cur += 1;
3220         }
3221
3222         /* terminal partial page? */
3223         if (count) {
3224                 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3225                 /* we have a partial page */
3226                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3227                 if (r != ERROR_OK)
3228                         goto done;
3229                                         /* data goes at start */
3230                 memcpy(pagebuffer, buffer, count);
3231                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3232                 if (r != ERROR_OK)
3233                         goto done;
3234                 buffer += count;
3235         }
3236         LOG_DEBUG("Done!");
3237         r = ERROR_OK;
3238 done:
3239         if (pagebuffer)
3240                 free(pagebuffer);
3241         return r;
3242 }
3243
3244 COMMAND_HANDLER(sam3_handle_info_command)
3245 {
3246         struct sam3_chip *pChip;
3247         pChip = get_current_sam3(CMD_CTX);
3248         if (!pChip)
3249                 return ERROR_OK;
3250
3251         unsigned x;
3252         int r;
3253
3254         /* bank0 must exist before we can do anything */
3255         if (pChip->details.bank[0].pBank == NULL) {
3256                 x = 0;
3257 need_define:
3258                 command_print(CMD_CTX,
3259                         "Please define bank %d via command: flash bank %s ... ",
3260                         x,
3261                         at91sam3_flash.name);
3262                 return ERROR_FAIL;
3263         }
3264
3265         /* if bank 0 is not probed, then probe it */
3266         if (!(pChip->details.bank[0].probed)) {
3267                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3268                 if (r != ERROR_OK)
3269                         return ERROR_FAIL;
3270         }
3271         /* above guarantees the "chip details" structure is valid */
3272         /* and thus, bank private areas are valid */
3273         /* and we have a SAM3 chip, what a concept! */
3274
3275         /* auto-probe other banks, 0 done above */
3276         for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3277                 /* skip banks not present */
3278                 if (!(pChip->details.bank[x].present))
3279                         continue;
3280
3281                 if (pChip->details.bank[x].pBank == NULL)
3282                         goto need_define;
3283
3284                 if (pChip->details.bank[x].probed)
3285                         continue;
3286
3287                 r = sam3_auto_probe(pChip->details.bank[x].pBank);
3288                 if (r != ERROR_OK)
3289                         return r;
3290         }
3291
3292         r = sam3_GetInfo(pChip);
3293         if (r != ERROR_OK) {
3294                 LOG_DEBUG("Sam3Info, Failed %d", r);
3295                 return r;
3296         }
3297
3298         return ERROR_OK;
3299 }
3300
3301 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3302 {
3303         unsigned x, v;
3304         int r, who;
3305         struct sam3_chip *pChip;
3306
3307         pChip = get_current_sam3(CMD_CTX);
3308         if (!pChip)
3309                 return ERROR_OK;
3310
3311         if (pChip->target->state != TARGET_HALTED) {
3312                 LOG_ERROR("sam3 - target not halted");
3313                 return ERROR_TARGET_NOT_HALTED;
3314         }
3315
3316         if (pChip->details.bank[0].pBank == NULL) {
3317                 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3318                         at91sam3_flash.name);
3319                 return ERROR_FAIL;
3320         }
3321         if (!pChip->details.bank[0].probed) {
3322                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3323                 if (r != ERROR_OK)
3324                         return r;
3325         }
3326
3327         switch (CMD_ARGC) {
3328                 default:
3329                         return ERROR_COMMAND_SYNTAX_ERROR;
3330                         break;
3331                 case 0:
3332                         goto showall;
3333                         break;
3334                 case 1:
3335                         who = -1;
3336                         break;
3337                 case 2:
3338                         if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3339                                 who = -1;
3340                         else {
3341                                 uint32_t v32;
3342                                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3343                                 who = v32;
3344                         }
3345                         break;
3346         }
3347
3348         if (0 == strcmp("show", CMD_ARGV[0])) {
3349                 if (who == -1) {
3350 showall:
3351                         r = ERROR_OK;
3352                         for (x = 0; x < pChip->details.n_gpnvms; x++) {
3353                                 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3354                                 if (r != ERROR_OK)
3355                                         break;
3356                                 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
3357                         }
3358                         return r;
3359                 }
3360                 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3361                         r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3362                         command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
3363                         return r;
3364                 } else {
3365                         command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
3366                         return ERROR_COMMAND_SYNTAX_ERROR;
3367                 }
3368         }
3369
3370         if (who == -1) {
3371                 command_print(CMD_CTX, "Missing GPNVM number");
3372                 return ERROR_COMMAND_SYNTAX_ERROR;
3373         }
3374
3375         if (0 == strcmp("set", CMD_ARGV[0]))
3376                 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3377         else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3378                  (0 == strcmp("clear", CMD_ARGV[0])))                   /* quietly accept both */
3379                 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3380         else {
3381                 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3382                 r = ERROR_COMMAND_SYNTAX_ERROR;
3383         }
3384         return r;
3385 }
3386
3387 COMMAND_HANDLER(sam3_handle_slowclk_command)
3388 {
3389         struct sam3_chip *pChip;
3390
3391         pChip = get_current_sam3(CMD_CTX);
3392         if (!pChip)
3393                 return ERROR_OK;
3394
3395         switch (CMD_ARGC) {
3396                 case 0:
3397                         /* show */
3398                         break;
3399                 case 1:
3400                 {
3401                         /* set */
3402                         uint32_t v;
3403                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3404                         if (v > 200000) {
3405                                 /* absurd slow clock of 200Khz? */
3406                                 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3407                                 return ERROR_COMMAND_SYNTAX_ERROR;
3408                         }
3409                         pChip->cfg.slow_freq = v;
3410                         break;
3411                 }
3412                 default:
3413                         /* error */
3414                         command_print(CMD_CTX, "Too many parameters");
3415                         return ERROR_COMMAND_SYNTAX_ERROR;
3416                         break;
3417         }
3418         command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3419                 (int)(pChip->cfg.slow_freq / 1000),
3420                 (int)(pChip->cfg.slow_freq % 1000));
3421         return ERROR_OK;
3422 }
3423
3424 static const struct command_registration at91sam3_exec_command_handlers[] = {
3425         {
3426                 .name = "gpnvm",
3427                 .handler = sam3_handle_gpnvm_command,
3428                 .mode = COMMAND_EXEC,
3429                 .usage = "[('clr'|'set'|'show') bitnum]",
3430                 .help = "Without arguments, shows all bits in the gpnvm "
3431                         "register.  Otherwise, clears, sets, or shows one "
3432                         "General Purpose Non-Volatile Memory (gpnvm) bit.",
3433         },
3434         {
3435                 .name = "info",
3436                 .handler = sam3_handle_info_command,
3437                 .mode = COMMAND_EXEC,
3438                 .help = "Print information about the current at91sam3 chip"
3439                         "and its flash configuration.",
3440         },
3441         {
3442                 .name = "slowclk",
3443                 .handler = sam3_handle_slowclk_command,
3444                 .mode = COMMAND_EXEC,
3445                 .usage = "[clock_hz]",
3446                 .help = "Display or set the slowclock frequency "
3447                         "(default 32768 Hz).",
3448         },
3449         COMMAND_REGISTRATION_DONE
3450 };
3451 static const struct command_registration at91sam3_command_handlers[] = {
3452         {
3453                 .name = "at91sam3",
3454                 .mode = COMMAND_ANY,
3455                 .help = "at91sam3 flash command group",
3456                 .usage = "",
3457                 .chain = at91sam3_exec_command_handlers,
3458         },
3459         COMMAND_REGISTRATION_DONE
3460 };
3461
3462 struct flash_driver at91sam3_flash = {
3463         .name = "at91sam3",
3464         .commands = at91sam3_command_handlers,
3465         .flash_bank_command = sam3_flash_bank_command,
3466         .erase = sam3_erase,
3467         .protect = sam3_protect,
3468         .write = sam3_write,
3469         .read = default_flash_read,
3470         .probe = sam3_probe,
3471         .auto_probe = sam3_auto_probe,
3472         .erase_check = sam3_erase_check,
3473         .protect_check = sam3_protect_check,
3474         .info = sam3_info,
3475 };