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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Duane Ellis                                     *
   3  *   openocd@duaneellis.com                                                *
   4  *                                                                         *
   5  *   Copyright (C) 2010 by Olaf Lüke (at91sam3s* support)                  *
   6  *   olaf@uni-paderborn.de                                                 *
   7  *                                                                         *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23 ****************************************************************************/
  24
  25 /* Some of the the lower level code was based on code supplied by
  26  * ATMEL under this copyright. */
  27
  28 /* BEGIN ATMEL COPYRIGHT */
  29 /* ----------------------------------------------------------------------------
  30  *         ATMEL Microcontroller Software Support
  31  * ----------------------------------------------------------------------------
  32  * Copyright (c) 2009, Atmel Corporation
  33  *
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions are met:
  38  *
  39  * - Redistributions of source code must retain the above copyright notice,
  40  * this list of conditions and the disclaimer below.
  41  *
  42  * Atmel's name may not be used to endorse or promote products derived from
  43  * this software without specific prior written permission.
  44  *
  45  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  46  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  47  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  48  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  49  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  50  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  51  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  52  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  53  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  54  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  55  * ----------------------------------------------------------------------------
  56  */
  57 /* END ATMEL COPYRIGHT */
  58
  59 #ifdef HAVE_CONFIG_H
  60 #include "config.h"
  61 #endif
  62
  63
  64 #include "imp.h"
  65 #include "at91sam3.h"
  66 #include <helper/time_support.h>
  67
  68 #define REG_NAME_WIDTH  (12)
  69
  70 // at91sam3u series (has one or two flash banks)
  71 #define FLASH_BANK0_BASE_U   0x00080000
  72 #define FLASH_BANK1_BASE_U   0x00100000
  73
  74 // at91sam3s series (has always one flash bank)
  75 #define FLASH_BANK_BASE_S   0x00400000
  76
  77 #define         AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor
  78 #define         AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page
  79 #define         AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock
  80 #define         AT91C_EFC_FCMD_EWP                  (0x3) // (EFC) Erase Page and Write Page
  81 #define         AT91C_EFC_FCMD_EWPL                 (0x4) // (EFC) Erase Page and Write Page then Lock
  82 #define         AT91C_EFC_FCMD_EA                   (0x5) // (EFC) Erase All
  83 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
  84 // #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane?
  85 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
  86 // #define      AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages?
  87 #define         AT91C_EFC_FCMD_SLB                  (0x8) // (EFC) Set Lock Bit
  88 #define         AT91C_EFC_FCMD_CLB                  (0x9) // (EFC) Clear Lock Bit
  89 #define         AT91C_EFC_FCMD_GLB                  (0xA) // (EFC) Get Lock Bit
  90 #define         AT91C_EFC_FCMD_SFB                  (0xB) // (EFC) Set Fuse Bit
  91 #define         AT91C_EFC_FCMD_CFB                  (0xC) // (EFC) Clear Fuse Bit
  92 #define         AT91C_EFC_FCMD_GFB                  (0xD) // (EFC) Get Fuse Bit
  93 #define         AT91C_EFC_FCMD_STUI                 (0xE) // (EFC) Start Read Unique ID
  94 #define         AT91C_EFC_FCMD_SPUI                 (0xF) // (EFC) Stop Read Unique ID
  95
  96 #define  offset_EFC_FMR   0
  97 #define  offset_EFC_FCR   4
  98 #define  offset_EFC_FSR   8
  99 #define  offset_EFC_FRR   12
 100
 101
 102 static float
 103 _tomhz(uint32_t freq_hz)
 104 {
 105         float f;
 106
 107         f = ((float)(freq_hz)) / 1000000.0;
 108         return f;
 109 }
 110
 111 // How the chip is configured.
 112 struct sam3_cfg {
 113         uint32_t unique_id[4];
 114
 115         uint32_t slow_freq;
 116         uint32_t rc_freq;
 117         uint32_t mainosc_freq;
 118         uint32_t plla_freq;
 119         uint32_t mclk_freq;
 120         uint32_t cpu_freq;
 121         uint32_t fclk_freq;
 122         uint32_t pclk0_freq;
 123         uint32_t pclk1_freq;
 124         uint32_t pclk2_freq;
 125
 126
 127 #define SAM3_CHIPID_CIDR          (0x400E0740)
 128         uint32_t CHIPID_CIDR;
 129 #define SAM3_CHIPID_EXID          (0x400E0744)
 130         uint32_t CHIPID_EXID;
 131
 132 #define SAM3_SUPC_CR              (0x400E1210)
 133         uint32_t SUPC_CR;
 134
 135 #define SAM3_PMC_BASE             (0x400E0400)
 136 #define SAM3_PMC_SCSR             (SAM3_PMC_BASE + 0x0008)
 137         uint32_t PMC_SCSR;
 138 #define SAM3_PMC_PCSR             (SAM3_PMC_BASE + 0x0018)
 139         uint32_t PMC_PCSR;
 140 #define SAM3_CKGR_UCKR            (SAM3_PMC_BASE + 0x001c)
 141         uint32_t CKGR_UCKR;
 142 #define SAM3_CKGR_MOR             (SAM3_PMC_BASE + 0x0020)
 143         uint32_t CKGR_MOR;
 144 #define SAM3_CKGR_MCFR            (SAM3_PMC_BASE + 0x0024)
 145         uint32_t CKGR_MCFR;
 146 #define SAM3_CKGR_PLLAR           (SAM3_PMC_BASE + 0x0028)
 147         uint32_t CKGR_PLLAR;
 148 #define SAM3_PMC_MCKR             (SAM3_PMC_BASE + 0x0030)
 149         uint32_t PMC_MCKR;
 150 #define SAM3_PMC_PCK0             (SAM3_PMC_BASE + 0x0040)
 151         uint32_t PMC_PCK0;
 152 #define SAM3_PMC_PCK1             (SAM3_PMC_BASE + 0x0044)
 153         uint32_t PMC_PCK1;
 154 #define SAM3_PMC_PCK2             (SAM3_PMC_BASE + 0x0048)
 155         uint32_t PMC_PCK2;
 156 #define SAM3_PMC_SR               (SAM3_PMC_BASE + 0x0068)
 157         uint32_t PMC_SR;
 158 #define SAM3_PMC_IMR              (SAM3_PMC_BASE + 0x006c)
 159         uint32_t PMC_IMR;
 160 #define SAM3_PMC_FSMR             (SAM3_PMC_BASE + 0x0070)
 161         uint32_t PMC_FSMR;
 162 #define SAM3_PMC_FSPR             (SAM3_PMC_BASE + 0x0074)
 163         uint32_t PMC_FSPR;
 164 };
 165
 166
 167 struct sam3_bank_private {
 168         int probed;
 169         // DANGER: THERE ARE DRAGONS HERE..
 170         // NOTE: If you add more 'ghost' pointers
 171         // be aware that you must *manually* update
 172         // these pointers in the function sam3_GetDetails()
 173         // See the comment "Here there be dragons"
 174
 175         // so we can find the chip we belong to
 176         struct sam3_chip *pChip;
 177         // so we can find the orginal bank pointer
 178         struct flash_bank *pBank;
 179         unsigned bank_number;
 180         uint32_t controller_address;
 181         uint32_t base_address;
 182         bool present;
 183         unsigned size_bytes;
 184         unsigned nsectors;
 185         unsigned sector_size;
 186         unsigned page_size;
 187 };
 188
 189 struct sam3_chip_details {
 190         // THERE ARE DRAGONS HERE..
 191         // note: If you add pointers here
 192         // becareful about them as they
 193         // may need to be updated inside
 194         // the function: "sam3_GetDetails()
 195         // which copy/overwrites the
 196         // 'runtime' copy of this structure
 197         uint32_t chipid_cidr;
 198         const char *name;
 199
 200         unsigned n_gpnvms;
 201 #define SAM3_N_NVM_BITS 3
 202         unsigned  gpnvm[SAM3_N_NVM_BITS];
 203         unsigned  total_flash_size;
 204         unsigned  total_sram_size;
 205         unsigned  n_banks;
 206 #define SAM3_MAX_FLASH_BANKS 2
 207         // these are "initialized" from the global const data
 208         struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
 209 };
 210
 211
 212 struct sam3_chip {
 213         struct sam3_chip *next;
 214         int    probed;
 215
 216         // this is "initialized" from the global const structure
 217         struct sam3_chip_details details;
 218         struct target *target;
 219         struct sam3_cfg cfg;
 220 };
 221
 222
 223 struct sam3_reg_list {
 224         uint32_t address;  size_t struct_offset; const char *name;
 225         void (*explain_func)(struct sam3_chip *pInfo);
 226 };
 227
 228
 229 static struct sam3_chip *all_sam3_chips;
 230
 231 static struct sam3_chip *
 232 get_current_sam3(struct command_context *cmd_ctx)
 233 {
 234         struct target *t;
 235         static struct sam3_chip *p;
 236
 237         t = get_current_target(cmd_ctx);
 238         if (!t) {
 239                 command_print(cmd_ctx, "No current target?");
 240                 return NULL;
 241         }
 242
 243         p = all_sam3_chips;
 244         if (!p) {
 245                 // this should not happen
 246                 // the command is not registered until the chip is created?
 247                 command_print(cmd_ctx, "No SAM3 chips exist?");
 248                 return NULL;
 249         }
 250
 251         while (p) {
 252                 if (p->target == t) {
 253                         return p;
 254                 }
 255                 p = p->next;
 256         }
 257         command_print(cmd_ctx, "Cannot find SAM3 chip?");
 258         return NULL;
 259 }
 260
 261
 262 // these are used to *initialize* the "pChip->details" structure.
 263 static const struct sam3_chip_details all_sam3_details[] = {
 264         // Start at91sam3u* series
 265         {
 266                 .chipid_cidr    = 0x28100960,
 267                 .name           = "at91sam3u4e",
 268                 .total_flash_size     = 256 * 1024,
 269                 .total_sram_size      = 52 * 1024,
 270                 .n_gpnvms       = 3,
 271                 .n_banks        = 2,
 272
 273                 // System boots at address 0x0
 274                 // gpnvm[1] = selects boot code
 275                 //     if gpnvm[1] == 0
 276                 //         boot is via "SAMBA" (rom)
 277                 //     else
 278                 //         boot is via FLASH
 279                 //         Selection is via gpnvm[2]
 280                 //     endif
 281                 //
 282                 // NOTE: banks 0 & 1 switch places
 283                 //     if gpnvm[2] == 0
 284                 //         Bank0 is the boot rom
 285                 //      else
 286                 //         Bank1 is the boot rom
 287                 //      endif
 288 //              .bank[0] = {
 289                 {
 290                   {
 291                         .probed = 0,
 292                         .pChip  = NULL,
 293                         .pBank  = NULL,
 294                         .bank_number = 0,
 295                         .base_address = FLASH_BANK0_BASE_U,
 296                         .controller_address = 0x400e0800,
 297                         .present = 1,
 298                         .size_bytes = 128 * 1024,
 299                         .nsectors   = 16,
 300                         .sector_size = 8192,
 301                         .page_size   = 256,
 302                   },
 303
 304 //              .bank[1] = {
 305                   {
 306                         .probed = 0,
 307                         .pChip  = NULL,
 308                         .pBank  = NULL,
 309                         .bank_number = 1,
 310                         .base_address = FLASH_BANK1_BASE_U,
 311                         .controller_address = 0x400e0a00,
 312                         .present = 1,
 313                         .size_bytes = 128 * 1024,
 314                         .nsectors   = 16,
 315                         .sector_size = 8192,
 316                         .page_size   = 256,
 317                   },
 318                 },
 319         },
 320
 321         {
 322                 .chipid_cidr    = 0x281a0760,
 323                 .name           = "at91sam3u2e",
 324                 .total_flash_size     = 128 * 1024,
 325                 .total_sram_size      =  36 * 1024,
 326                 .n_gpnvms       = 2,
 327                 .n_banks        = 1,
 328
 329                 // System boots at address 0x0
 330                 // gpnvm[1] = selects boot code
 331                 //     if gpnvm[1] == 0
 332                 //         boot is via "SAMBA" (rom)
 333                 //     else
 334                 //         boot is via FLASH
 335                 //         Selection is via gpnvm[2]
 336                 //     endif
 337 //              .bank[0] = {
 338                 {
 339                   {
 340                         .probed = 0,
 341                         .pChip  = NULL,
 342                         .pBank  = NULL,
 343                         .bank_number = 0,
 344                         .base_address = FLASH_BANK0_BASE_U,
 345                         .controller_address = 0x400e0800,
 346                         .present = 1,
 347                         .size_bytes = 128 * 1024,
 348                         .nsectors   = 16,
 349                         .sector_size = 8192,
 350                         .page_size   = 256,
 351                   },
 352 //                .bank[1] = {
 353                   {
 354                         .present = 0,
 355                         .probed = 0,
 356                         .bank_number = 1,
 357                   },
 358                 },
 359         },
 360         {
 361                 .chipid_cidr    = 0x28190560,
 362                 .name           = "at91sam3u1e",
 363                 .total_flash_size     = 64 * 1024,
 364                 .total_sram_size      = 20 * 1024,
 365                 .n_gpnvms       = 2,
 366                 .n_banks        = 1,
 367
 368                 // System boots at address 0x0
 369                 // gpnvm[1] = selects boot code
 370                 //     if gpnvm[1] == 0
 371                 //         boot is via "SAMBA" (rom)
 372                 //     else
 373                 //         boot is via FLASH
 374                 //         Selection is via gpnvm[2]
 375                 //     endif
 376                 //
 377
 378 //              .bank[0] = {
 379                 {
 380                   {
 381                         .probed = 0,
 382                         .pChip  = NULL,
 383                         .pBank  = NULL,
 384                         .bank_number = 0,
 385                         .base_address = FLASH_BANK0_BASE_U,
 386                         .controller_address = 0x400e0800,
 387                         .present = 1,
 388                         .size_bytes =  64 * 1024,
 389                         .nsectors   =  8,
 390                         .sector_size = 8192,
 391                         .page_size   = 256,
 392                   },
 393
 394 //              .bank[1] = {
 395                   {
 396                         .present = 0,
 397                         .probed = 0,
 398                         .bank_number = 1,
 399                   },
 400                 },
 401         },
 402
 403         {
 404                 .chipid_cidr    = 0x28000960,
 405                 .name           = "at91sam3u4c",
 406                 .total_flash_size     = 256 * 1024,
 407                 .total_sram_size      = 52 * 1024,
 408                 .n_gpnvms       = 3,
 409                 .n_banks        = 2,
 410
 411                 // System boots at address 0x0
 412                 // gpnvm[1] = selects boot code
 413                 //     if gpnvm[1] == 0
 414                 //         boot is via "SAMBA" (rom)
 415                 //     else
 416                 //         boot is via FLASH
 417                 //         Selection is via gpnvm[2]
 418                 //     endif
 419                 //
 420                 // NOTE: banks 0 & 1 switch places
 421                 //     if gpnvm[2] == 0
 422                 //         Bank0 is the boot rom
 423                 //      else
 424                 //         Bank1 is the boot rom
 425                 //      endif
 426                 {
 427                   {
 428 //              .bank[0] = {
 429                         .probed = 0,
 430                         .pChip  = NULL,
 431                         .pBank  = NULL,
 432                         .bank_number = 0,
 433                         .base_address = FLASH_BANK0_BASE_U,
 434                         .controller_address = 0x400e0800,
 435                         .present = 1,
 436                         .size_bytes = 128 * 1024,
 437                         .nsectors   = 16,
 438                         .sector_size = 8192,
 439                         .page_size   = 256,
 440                   },
 441 //              .bank[1] = {
 442                   {
 443                         .probed = 0,
 444                         .pChip  = NULL,
 445                         .pBank  = NULL,
 446                         .bank_number = 1,
 447                         .base_address = FLASH_BANK1_BASE_U,
 448                         .controller_address = 0x400e0a00,
 449                         .present = 1,
 450                         .size_bytes = 128 * 1024,
 451                         .nsectors   = 16,
 452                         .sector_size = 8192,
 453                         .page_size   = 256,
 454                   },
 455                 },
 456         },
 457
 458         {
 459                 .chipid_cidr    = 0x280a0760,
 460                 .name           = "at91sam3u2c",
 461                 .total_flash_size     = 128 * 1024,
 462                 .total_sram_size      = 36 * 1024,
 463                 .n_gpnvms       = 2,
 464                 .n_banks        = 1,
 465
 466                 // System boots at address 0x0
 467                 // gpnvm[1] = selects boot code
 468                 //     if gpnvm[1] == 0
 469                 //         boot is via "SAMBA" (rom)
 470                 //     else
 471                 //         boot is via FLASH
 472                 //         Selection is via gpnvm[2]
 473                 //     endif
 474                 {
 475 //              .bank[0] = {
 476                   {
 477                         .probed = 0,
 478                         .pChip  = NULL,
 479                         .pBank  = NULL,
 480                         .bank_number = 0,
 481                         .base_address = FLASH_BANK0_BASE_U,
 482                         .controller_address = 0x400e0800,
 483                         .present = 1,
 484                         .size_bytes = 128 * 1024,
 485                         .nsectors   = 16,
 486                         .sector_size = 8192,
 487                         .page_size   = 256,
 488                   },
 489 //              .bank[1] = {
 490                   {
 491                         .present = 0,
 492                         .probed = 0,
 493                         .bank_number = 1,
 494                   },
 495                 },
 496         },
 497         {
 498                 .chipid_cidr    = 0x28090560,
 499                 .name           = "at91sam3u1c",
 500                 .total_flash_size     = 64 * 1024,
 501                 .total_sram_size      = 20 * 1024,
 502                 .n_gpnvms       = 2,
 503                 .n_banks        = 1,
 504
 505                 // System boots at address 0x0
 506                 // gpnvm[1] = selects boot code
 507                 //     if gpnvm[1] == 0
 508                 //         boot is via "SAMBA" (rom)
 509                 //     else
 510                 //         boot is via FLASH
 511                 //         Selection is via gpnvm[2]
 512                 //     endif
 513                 //
 514
 515                 {
 516 //              .bank[0] = {
 517                   {
 518                         .probed = 0,
 519                         .pChip  = NULL,
 520                         .pBank  = NULL,
 521                         .bank_number = 0,
 522                         .base_address = FLASH_BANK0_BASE_U,
 523                         .controller_address = 0x400e0800,
 524                         .present = 1,
 525                         .size_bytes =  64 * 1024,
 526                         .nsectors   =  8,
 527                         .sector_size = 8192,
 528                         .page_size   = 256,
 529                   },
 530 //              .bank[1] = {
 531                   {
 532                         .present = 0,
 533                         .probed = 0,
 534                         .bank_number = 1,
 535
 536                   },
 537                 },
 538         },
 539
 540         // Start at91sam3s* series
 541
 542         // Note: The preliminary at91sam3s datasheet says on page 302
 543         // that the flash controller is at address 0x400E0800.
 544         // This is _not_ the case, the controller resides at address 0x400e0a0.
 545         {
 546                 .chipid_cidr    = 0x28A00960,
 547                 .name           = "at91sam3s4c",
 548                 .total_flash_size     = 256 * 1024,
 549                 .total_sram_size      = 48 * 1024,
 550                 .n_gpnvms       = 2,
 551                 .n_banks        = 1,
 552                 {
 553 //              .bank[0] = {
 554                   {
 555                         .probed = 0,
 556                         .pChip  = NULL,
 557                         .pBank  = NULL,
 558                         .bank_number = 0,
 559                         .base_address = FLASH_BANK_BASE_S,
 560
 561                         .controller_address = 0x400e0a00,
 562                         .present = 1,
 563                         .size_bytes =  256 * 1024,
 564                         .nsectors   =  32,
 565                         .sector_size = 8192,
 566                         .page_size   = 256,
 567                   },
 568 //              .bank[1] = {
 569                   {
 570                         .present = 0,
 571                         .probed = 0,
 572                         .bank_number = 1,
 573
 574                   },
 575                 },
 576         },
 577
 578         {
 579                 .chipid_cidr    = 0x28900960,
 580                 .name           = "at91sam3s4b",
 581                 .total_flash_size     = 256 * 1024,
 582                 .total_sram_size      = 48 * 1024,
 583                 .n_gpnvms       = 2,
 584                 .n_banks        = 1,
 585                 {
 586 //              .bank[0] = {
 587                   {
 588                         .probed = 0,
 589                         .pChip  = NULL,
 590                         .pBank  = NULL,
 591                         .bank_number = 0,
 592                         .base_address = FLASH_BANK_BASE_S,
 593
 594                         .controller_address = 0x400e0a00,
 595                         .present = 1,
 596                         .size_bytes =  256 * 1024,
 597                         .nsectors   =  32,
 598                         .sector_size = 8192,
 599                         .page_size   = 256,
 600                   },
 601 //              .bank[1] = {
 602                   {
 603                         .present = 0,
 604                         .probed = 0,
 605                         .bank_number = 1,
 606
 607                   },
 608                 },
 609         },
 610         {
 611                 .chipid_cidr    = 0x28800960,
 612                 .name           = "at91sam3s4a",
 613                 .total_flash_size     = 256 * 1024,
 614                 .total_sram_size      = 48 * 1024,
 615                 .n_gpnvms       = 2,
 616                 .n_banks        = 1,
 617                 {
 618 //              .bank[0] = {
 619                   {
 620                         .probed = 0,
 621                         .pChip  = NULL,
 622                         .pBank  = NULL,
 623                         .bank_number = 0,
 624                         .base_address = FLASH_BANK_BASE_S,
 625
 626                         .controller_address = 0x400e0a00,
 627                         .present = 1,
 628                         .size_bytes =  256 * 1024,
 629                         .nsectors   =  32,
 630                         .sector_size = 8192,
 631                         .page_size   = 256,
 632                   },
 633 //              .bank[1] = {
 634                   {
 635                         .present = 0,
 636                         .probed = 0,
 637                         .bank_number = 1,
 638
 639                   },
 640                 },
 641         },
 642         {
 643                 .chipid_cidr    = 0x28AA0760,
 644                 .name           = "at91sam3s2c",
 645                 .total_flash_size     = 128 * 1024,
 646                 .total_sram_size      = 32 * 1024,
 647                 .n_gpnvms       = 2,
 648                 .n_banks        = 1,
 649                 {
 650 //              .bank[0] = {
 651                   {
 652                         .probed = 0,
 653                         .pChip  = NULL,
 654                         .pBank  = NULL,
 655                         .bank_number = 0,
 656                         .base_address = FLASH_BANK_BASE_S,
 657
 658                         .controller_address = 0x400e0a00,
 659                         .present = 1,
 660                         .size_bytes =  128 * 1024,
 661                         .nsectors   =  16,
 662                         .sector_size = 8192,
 663                         .page_size   = 256,
 664                   },
 665 //              .bank[1] = {
 666                   {
 667                         .present = 0,
 668                         .probed = 0,
 669                         .bank_number = 1,
 670
 671                   },
 672                 },
 673         },
 674         {
 675                 .chipid_cidr    = 0x289A0760,
 676                 .name           = "at91sam3s2b",
 677                 .total_flash_size     = 128 * 1024,
 678                 .total_sram_size      = 32 * 1024,
 679                 .n_gpnvms       = 2,
 680                 .n_banks        = 1,
 681                 {
 682 //              .bank[0] = {
 683                   {
 684                         .probed = 0,
 685                         .pChip  = NULL,
 686                         .pBank  = NULL,
 687                         .bank_number = 0,
 688                         .base_address = FLASH_BANK_BASE_S,
 689
 690                         .controller_address = 0x400e0a00,
 691                         .present = 1,
 692                         .size_bytes =  128 * 1024,
 693                         .nsectors   =  16,
 694                         .sector_size = 8192,
 695                         .page_size   = 256,
 696                   },
 697 //              .bank[1] = {
 698                   {
 699                         .present = 0,
 700                         .probed = 0,
 701                         .bank_number = 1,
 702
 703                   },
 704                 },
 705         },
 706         {
 707                 .chipid_cidr    = 0x288A0760,
 708                 .name           = "at91sam3s2a",
 709                 .total_flash_size     = 128 * 1024,
 710                 .total_sram_size      = 32 * 1024,
 711                 .n_gpnvms       = 2,
 712                 .n_banks        = 1,
 713                 {
 714 //              .bank[0] = {
 715                   {
 716                         .probed = 0,
 717                         .pChip  = NULL,
 718                         .pBank  = NULL,
 719                         .bank_number = 0,
 720                         .base_address = FLASH_BANK_BASE_S,
 721
 722                         .controller_address = 0x400e0a00,
 723                         .present = 1,
 724                         .size_bytes =  128 * 1024,
 725                         .nsectors   =  16,
 726                         .sector_size = 8192,
 727                         .page_size   = 256,
 728                   },
 729 //              .bank[1] = {
 730                   {
 731                         .present = 0,
 732                         .probed = 0,
 733                         .bank_number = 1,
 734
 735                   },
 736                 },
 737         },
 738         {
 739                 .chipid_cidr    = 0x28A90560,
 740                 .name           = "at91sam3s1c",
 741                 .total_flash_size     = 64 * 1024,
 742                 .total_sram_size      = 16 * 1024,
 743                 .n_gpnvms       = 2,
 744                 .n_banks        = 1,
 745                 {
 746 //              .bank[0] = {
 747                   {
 748                         .probed = 0,
 749                         .pChip  = NULL,
 750                         .pBank  = NULL,
 751                         .bank_number = 0,
 752                         .base_address = FLASH_BANK_BASE_S,
 753
 754                         .controller_address = 0x400e0a00,
 755                         .present = 1,
 756                         .size_bytes =  64 * 1024,
 757                         .nsectors   =  8,
 758                         .sector_size = 8192,
 759                         .page_size   = 256,
 760                   },
 761 //              .bank[1] = {
 762                   {
 763                         .present = 0,
 764                         .probed = 0,
 765                         .bank_number = 1,
 766
 767                   },
 768                 },
 769         },
 770         {
 771                 .chipid_cidr    = 0x28990560,
 772                 .name           = "at91sam3s1b",
 773                 .total_flash_size     = 64 * 1024,
 774                 .total_sram_size      = 16 * 1024,
 775                 .n_gpnvms       = 2,
 776                 .n_banks        = 1,
 777                 {
 778 //              .bank[0] = {
 779                   {
 780                         .probed = 0,
 781                         .pChip  = NULL,
 782                         .pBank  = NULL,
 783                         .bank_number = 0,
 784                         .base_address = FLASH_BANK_BASE_S,
 785
 786                         .controller_address = 0x400e0a00,
 787                         .present = 1,
 788                         .size_bytes =  64 * 1024,
 789                         .nsectors   =  8,
 790                         .sector_size = 8192,
 791                         .page_size   = 256,
 792                   },
 793 //              .bank[1] = {
 794                   {
 795                         .present = 0,
 796                         .probed = 0,
 797                         .bank_number = 1,
 798
 799                   },
 800                 },
 801         },
 802         {
 803                 .chipid_cidr    = 0x28890560,
 804                 .name           = "at91sam3s1a",
 805                 .total_flash_size     = 64 * 1024,
 806                 .total_sram_size      = 16 * 1024,
 807                 .n_gpnvms       = 2,
 808                 .n_banks        = 1,
 809                 {
 810 //              .bank[0] = {
 811                   {
 812                         .probed = 0,
 813                         .pChip  = NULL,
 814                         .pBank  = NULL,
 815                         .bank_number = 0,
 816                         .base_address = FLASH_BANK_BASE_S,
 817
 818                         .controller_address = 0x400e0a00,
 819                         .present = 1,
 820                         .size_bytes =  64 * 1024,
 821                         .nsectors   =  8,
 822                         .sector_size = 8192,
 823                         .page_size   = 256,
 824                   },
 825 //              .bank[1] = {
 826                   {
 827                         .present = 0,
 828                         .probed = 0,
 829                         .bank_number = 1,
 830
 831                   },
 832                 },
 833         },
 834         // terminate
 835         {
 836                 .chipid_cidr    = 0,
 837                 .name                   = NULL,
 838         }
 839 };
 840
 841 /* Globals above */
 842 /***********************************************************************
 843  **********************************************************************
 844  **********************************************************************
 845  **********************************************************************
 846  **********************************************************************
 847  **********************************************************************/
 848 /* *ATMEL* style code - from the SAM3 driver code */
 849
 850 /**
 851  * Get the current status of the EEFC and
 852  * the value of some status bits (LOCKE, PROGE).
 853  * @param pPrivate - info about the bank
 854  * @param v        - result goes here
 855  */
 856 static int
 857 EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
 858 {
 859         int r;
 860         r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FSR, v);
 861         LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
 862                           (unsigned int)(*v),
 863                           ((unsigned int)((*v >> 2) & 1)),
 864                           ((unsigned int)((*v >> 1) & 1)),
 865                           ((unsigned int)((*v >> 0) & 1)));
 866
 867         return r;
 868 }
 869
 870 /**
 871  * Get the result of the last executed command.
 872  * @param pPrivate - info about the bank
 873  * @param v        - result goes here
 874  */
 875 static int
 876 EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
 877 {
 878         int r;
 879         uint32_t rv;
 880         r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FRR, &rv);
 881         if (v) {
 882                 *v = rv;
 883         }
 884         LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
 885         return r;
 886 }
 887
 888 static int
 889 EFC_StartCommand(struct sam3_bank_private *pPrivate,
 890                                  unsigned command, unsigned argument)
 891 {
 892         uint32_t n,v;
 893         int r;
 894         int retry;
 895
 896         retry = 0;
 897  do_retry:
 898
 899     // Check command & argument
 900     switch (command) {
 901
 902         case AT91C_EFC_FCMD_WP:
 903         case AT91C_EFC_FCMD_WPL:
 904         case AT91C_EFC_FCMD_EWP:
 905         case AT91C_EFC_FCMD_EWPL:
 906                 // case AT91C_EFC_FCMD_EPL:
 907                 // case AT91C_EFC_FCMD_EPA:
 908         case AT91C_EFC_FCMD_SLB:
 909         case AT91C_EFC_FCMD_CLB:
 910                 n = (pPrivate->size_bytes / pPrivate->page_size);
 911                 if (argument >= n) {
 912                         LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
 913                 }
 914                 break;
 915
 916         case AT91C_EFC_FCMD_SFB:
 917         case AT91C_EFC_FCMD_CFB:
 918                 if (argument >= pPrivate->pChip->details.n_gpnvms) {
 919                         LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
 920                                           pPrivate->pChip->details.n_gpnvms);
 921                 }
 922                 break;
 923
 924         case AT91C_EFC_FCMD_GETD:
 925         case AT91C_EFC_FCMD_EA:
 926         case AT91C_EFC_FCMD_GLB:
 927         case AT91C_EFC_FCMD_GFB:
 928         case AT91C_EFC_FCMD_STUI:
 929         case AT91C_EFC_FCMD_SPUI:
 930                 if (argument != 0) {
 931                         LOG_ERROR("Argument is meaningless for cmd: %d", command);
 932                 }
 933                 break;
 934         default:
 935                 LOG_ERROR("Unknown command %d", command);
 936                 break;
 937     }
 938
 939         if (command == AT91C_EFC_FCMD_SPUI) {
 940                 // this is a very special situation.
 941                 // Situation (1) - error/retry - see below
 942                 //      And we are being called recursively
 943                 // Situation (2) - normal, finished reading unique id
 944         } else {
 945                 // it should be "ready"
 946                 EFC_GetStatus(pPrivate, &v);
 947                 if (v & 1) {
 948                         // then it is ready
 949                         // we go on
 950                 } else {
 951                         if (retry) {
 952                                 // we have done this before
 953                                 // the controller is not responding.
 954                                 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate->bank_number);
 955                                 return ERROR_FAIL;
 956                         } else {
 957                                 retry++;
 958                                 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
 959                                                   pPrivate->bank_number);
 960                                 // we do that by issuing the *STOP* command
 961                                 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
 962                                 // above is recursive, and further recursion is blocked by
 963                                 // if (command == AT91C_EFC_FCMD_SPUI) above
 964                                 goto do_retry;
 965                         }
 966                 }
 967         }
 968
 969         v = (0x5A << 24) | (argument << 8) | command;
 970         LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
 971         r = target_write_u32(pPrivate->pBank->target,
 972                                                   pPrivate->controller_address + offset_EFC_FCR,
 973                                                   v);
 974         if (r != ERROR_OK) {
 975                 LOG_DEBUG("Error Write failed");
 976         }
 977         return r;
 978 }
 979
 980 /**
 981  * Performs the given command and wait until its completion (or an error).
 982  * @param pPrivate - info about the bank
 983  * @param command  - Command to perform.
 984  * @param argument - Optional command argument.
 985  * @param status   - put command status bits here
 986  */
 987 static int
 988 EFC_PerformCommand(struct sam3_bank_private *pPrivate,
 989                                         unsigned command,
 990                                         unsigned argument,
 991                                         uint32_t *status)
 992 {
 993
 994         int r;
 995         uint32_t v;
 996         long long ms_now, ms_end;
 997
 998         // default
 999         if (status) {
1000                 *status = 0;
1001         }
1002
1003         r = EFC_StartCommand(pPrivate, command, argument);
1004         if (r != ERROR_OK) {
1005                 return r;
1006         }
1007
1008         ms_end = 500 + timeval_ms();
1009
1010
1011     do {
1012                 r = EFC_GetStatus(pPrivate, &v);
1013                 if (r != ERROR_OK) {
1014                         return r;
1015                 }
1016                 ms_now = timeval_ms();
1017                 if (ms_now > ms_end) {
1018                         // error
1019                         LOG_ERROR("Command timeout");
1020                         return ERROR_FAIL;
1021                 }
1022     }
1023     while ((v & 1) == 0)
1024                 ;
1025
1026         // error bits..
1027         if (status) {
1028                 *status = (v & 0x6);
1029         }
1030         return ERROR_OK;
1031
1032 }
1033
1034
1035
1036
1037
1038 /**
1039  * Read the unique ID.
1040  * @param pPrivate - info about the bank
1041  * The unique ID is stored in the 'pPrivate' structure.
1042  */
1043 static int
1044 FLASHD_ReadUniqueID (struct sam3_bank_private *pPrivate)
1045 {
1046         int r;
1047         uint32_t v;
1048         int x;
1049         // assume 0
1050     pPrivate->pChip->cfg.unique_id[0] = 0;
1051     pPrivate->pChip->cfg.unique_id[1] = 0;
1052     pPrivate->pChip->cfg.unique_id[2] = 0;
1053     pPrivate->pChip->cfg.unique_id[3] = 0;
1054
1055         LOG_DEBUG("Begin");
1056         r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1057         if (r < 0) {
1058                 return r;
1059         }
1060
1061         for (x = 0 ; x < 4 ; x++) {
1062                 r = target_read_u32(pPrivate->pChip->target,
1063                                                          pPrivate->pBank->base + (x * 4),
1064                                                          &v);
1065                 if (r < 0) {
1066                         return r;
1067                 }
1068                 pPrivate->pChip->cfg.unique_id[x] = v;
1069         }
1070
1071     r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1072         LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1073                           r,
1074                           (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1075                           (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1076                           (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1077                           (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1078         return r;
1079
1080 }
1081
1082 /**
1083  * Erases the entire flash.
1084  * @param pPrivate - the info about the bank.
1085  */
1086 static int
1087 FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
1088 {
1089         LOG_DEBUG("Here");
1090         return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1091 }
1092
1093
1094
1095 /**
1096  * Gets current GPNVM state.
1097  * @param pPrivate - info about the bank.
1098  * @param gpnvm    -  GPNVM bit index.
1099  * @param puthere  - result stored here.
1100  */
1101 //------------------------------------------------------------------------------
1102 static int
1103 FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1104 {
1105         uint32_t v;
1106         int r;
1107
1108         LOG_DEBUG("Here");
1109         if (pPrivate->bank_number != 0) {
1110                 LOG_ERROR("GPNVM only works with Bank0");
1111                 return ERROR_FAIL;
1112         }
1113
1114         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1115                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1116                                   gpnvm,pPrivate->pChip->details.n_gpnvms);
1117                 return ERROR_FAIL;
1118         }
1119
1120     // Get GPNVMs status
1121         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1122         if (r != ERROR_OK) {
1123                 LOG_ERROR("Failed");
1124                 return r;
1125         }
1126
1127     r = EFC_GetResult(pPrivate, &v);
1128
1129         if (puthere) {
1130                 // Check if GPNVM is set
1131                 // get the bit and make it a 0/1
1132                 *puthere = (v >> gpnvm) & 1;
1133         }
1134
1135         return r;
1136 }
1137
1138
1139
1140
1141 /**
1142  * Clears the selected GPNVM bit.
1143  * @param pPrivate info about the bank
1144  * @param gpnvm GPNVM index.
1145  * @returns 0 if successful; otherwise returns an error code.
1146  */
1147 static int
1148 FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1149 {
1150         int r;
1151         unsigned v;
1152
1153         LOG_DEBUG("Here");
1154         if (pPrivate->bank_number != 0) {
1155                 LOG_ERROR("GPNVM only works with Bank0");
1156                 return ERROR_FAIL;
1157         }
1158
1159         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1160                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1161                                   gpnvm,pPrivate->pChip->details.n_gpnvms);
1162                 return ERROR_FAIL;
1163         }
1164
1165         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1166         if (r != ERROR_OK) {
1167                 LOG_DEBUG("Failed: %d",r);
1168                 return r;
1169         }
1170         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1171         LOG_DEBUG("End: %d",r);
1172         return r;
1173 }
1174
1175
1176
1177 /**
1178  * Sets the selected GPNVM bit.
1179  * @param pPrivate info about the bank
1180  * @param gpnvm GPNVM index.
1181  */
1182 static int
1183 FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1184 {
1185         int r;
1186         unsigned v;
1187
1188         if (pPrivate->bank_number != 0) {
1189                 LOG_ERROR("GPNVM only works with Bank0");
1190                 return ERROR_FAIL;
1191         }
1192
1193         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1194                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1195                                   gpnvm,pPrivate->pChip->details.n_gpnvms);
1196                 return ERROR_FAIL;
1197         }
1198
1199         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1200         if (r != ERROR_OK) {
1201                 return r;
1202         }
1203         if (v) {
1204                 // already set
1205                 r = ERROR_OK;
1206         } else {
1207                 // set it
1208                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1209         }
1210         return r;
1211 }
1212
1213
1214 /**
1215  * Returns a bit field (at most 64) of locked regions within a page.
1216  * @param pPrivate info about the bank
1217  * @param v where to store locked bits
1218  */
1219 static int
1220 FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
1221 {
1222         int r;
1223         LOG_DEBUG("Here");
1224     r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1225         if (r == ERROR_OK) {
1226                 r = EFC_GetResult(pPrivate, v);
1227         }
1228         LOG_DEBUG("End: %d",r);
1229         return r;
1230 }
1231
1232
1233 /**
1234  * Unlocks all the regions in the given address range.
1235  * @param pPrivate info about the bank
1236  * @param start_sector first sector to unlock
1237  * @param end_sector last (inclusive) to unlock
1238  */
1239
1240 static int
1241 FLASHD_Unlock(struct sam3_bank_private *pPrivate,
1242                            unsigned start_sector,
1243                            unsigned end_sector)
1244 {
1245         int r;
1246         uint32_t status;
1247         uint32_t pg;
1248         uint32_t pages_per_sector;
1249
1250         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1251
1252     /* Unlock all pages */
1253     while (start_sector <= end_sector) {
1254                 pg = start_sector * pages_per_sector;
1255
1256         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1257         if (r != ERROR_OK) {
1258             return r;
1259         }
1260         start_sector++;
1261     }
1262
1263     return ERROR_OK;
1264 }
1265
1266
1267 /**
1268  * Locks regions
1269  * @param pPrivate - info about the bank
1270  * @param start_sector - first sector to lock
1271  * @param end_sector   - last sector (inclusive) to lock
1272  */
1273 static int
1274 FLASHD_Lock(struct sam3_bank_private *pPrivate,
1275                          unsigned start_sector,
1276                          unsigned end_sector)
1277 {
1278         uint32_t status;
1279         uint32_t pg;
1280         uint32_t pages_per_sector;
1281         int r;
1282
1283         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1284
1285     /* Lock all pages */
1286     while (start_sector <= end_sector) {
1287                 pg = start_sector * pages_per_sector;
1288
1289         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1290         if (r != ERROR_OK) {
1291             return r;
1292         }
1293         start_sector++;
1294     }
1295     return ERROR_OK;
1296 }
1297
1298
1299 /****** END SAM3 CODE ********/
1300
1301 /* begin helpful debug code */
1302 // print the fieldname, the field value, in dec & hex, and return field value
1303 static uint32_t
1304 sam3_reg_fieldname(struct sam3_chip *pChip,
1305                                         const char *regname,
1306                                         uint32_t value,
1307                                         unsigned shift,
1308                                         unsigned width)
1309 {
1310         uint32_t v;
1311         int hwidth, dwidth;
1312
1313
1314         // extract the field
1315         v = value >> shift;
1316         v = v & ((1 << width)-1);
1317         if (width <= 16) {
1318                 hwidth = 4;
1319                 dwidth = 5;
1320         } else {
1321                 hwidth = 8;
1322                 dwidth = 12;
1323         }
1324
1325         // show the basics
1326         LOG_USER_N("\t%*s: %*d [0x%0*x] ",
1327                                   REG_NAME_WIDTH, regname,
1328                                   dwidth, v,
1329                                   hwidth, v);
1330         return v;
1331 }
1332
1333
1334 static const char _unknown[] = "unknown";
1335 static const char * const eproc_names[] = {
1336         _unknown,                                       // 0
1337         "arm946es",                                     // 1
1338         "arm7tdmi",                                     // 2
1339         "cortex-m3",                            // 3
1340         "arm920t",                                      // 4
1341         "arm926ejs",                            // 5
1342         _unknown,                                       // 6
1343         _unknown,                                       // 7
1344         _unknown,                                       // 8
1345         _unknown,                                       // 9
1346         _unknown,                                       // 10
1347         _unknown,                                       // 11
1348         _unknown,                                       // 12
1349         _unknown,                                       // 13
1350         _unknown,                                       // 14
1351         _unknown,                                       // 15
1352 };
1353
1354 #define nvpsize2 nvpsize                // these two tables are identical
1355 static const char * const nvpsize[] = {
1356         "none",                                         //  0
1357         "8K bytes",                                     //  1
1358         "16K bytes",                            //  2
1359         "32K bytes",                            //  3
1360         _unknown,                                       //  4
1361         "64K bytes",                            //  5
1362         _unknown,                                       //  6
1363         "128K bytes",                           //  7
1364         _unknown,                                       //  8
1365         "256K bytes",                           //  9
1366         "512K bytes",                           // 10
1367         _unknown,                                       // 11
1368         "1024K bytes",                          // 12
1369         _unknown,                                       // 13
1370         "2048K bytes",                          // 14
1371         _unknown,                                       // 15
1372 };
1373
1374
1375 static const char * const sramsize[] = {
1376         "48K Bytes",                            //  0
1377         "1K Bytes",                                     //  1
1378         "2K Bytes",                                     //  2
1379         "6K Bytes",                                     //  3
1380         "112K Bytes",                           //  4
1381         "4K Bytes",                                     //  5
1382         "80K Bytes",                            //  6
1383         "160K Bytes",                           //  7
1384         "8K Bytes",                                     //  8
1385         "16K Bytes",                            //  9
1386         "32K Bytes",                            // 10
1387         "64K Bytes",                            // 11
1388         "128K Bytes",                           // 12
1389         "256K Bytes",                           // 13
1390         "96K Bytes",                            // 14
1391         "512K Bytes",                           // 15
1392
1393 };
1394
1395 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1396         { 0x19,  "AT91SAM9xx Series"                                            },
1397         { 0x29,  "AT91SAM9XExx Series"                                          },
1398         { 0x34,  "AT91x34 Series"                                                       },
1399         { 0x37,  "CAP7 Series"                                                          },
1400         { 0x39,  "CAP9 Series"                                                          },
1401         { 0x3B,  "CAP11 Series"                                                         },
1402         { 0x40,  "AT91x40 Series"                                                       },
1403         { 0x42,  "AT91x42 Series"                                                       },
1404         { 0x55,  "AT91x55 Series"                                                       },
1405         { 0x60,  "AT91SAM7Axx Series"                                           },
1406         { 0x61,  "AT91SAM7AQxx Series"                                          },
1407         { 0x63,  "AT91x63 Series"                                                       },
1408         { 0x70,  "AT91SAM7Sxx Series"                                           },
1409         { 0x71,  "AT91SAM7XCxx Series"                                          },
1410         { 0x72,  "AT91SAM7SExx Series"                                          },
1411         { 0x73,  "AT91SAM7Lxx Series"                                           },
1412         { 0x75,  "AT91SAM7Xxx Series"                                           },
1413         { 0x76,  "AT91SAM7SLxx Series"                                          },
1414         { 0x80,  "ATSAM3UxC Series (100-pin version)"           },
1415         { 0x81,  "ATSAM3UxE Series (144-pin version)"           },
1416         { 0x83,  "ATSAM3AxC Series (100-pin version)"           },
1417         { 0x84,  "ATSAM3XxC Series (100-pin version)"           },
1418         { 0x85,  "ATSAM3XxE Series (144-pin version)"           },
1419         { 0x86,  "ATSAM3XxG Series (208/217-pin version)"       },
1420         { 0x88,  "ATSAM3SxA Series (48-pin version)"            },
1421         { 0x89,  "ATSAM3SxB Series (64-pin version)"            },
1422         { 0x8A,  "ATSAM3SxC Series (100-pin version)"           },
1423         { 0x92,  "AT91x92 Series"                                                       },
1424         { 0xF0,  "AT75Cxx Series"                                                       },
1425         { -1, NULL },
1426
1427 };
1428
1429 static const char * const nvptype[] = {
1430         "rom", // 0
1431         "romless or onchip flash", // 1
1432         "embedded flash memory", // 2
1433         "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1434         "sram emulating flash", // 4
1435         _unknown, // 5
1436         _unknown, // 6
1437         _unknown, // 7
1438
1439 };
1440
1441 static const char *_yes_or_no(uint32_t v)
1442 {
1443         if (v) {
1444                 return "YES";
1445         } else {
1446                 return "NO";
1447         }
1448 }
1449
1450 static const char * const _rc_freq[] = {
1451         "4 MHz", "8 MHz", "12 MHz", "reserved"
1452 };
1453
1454 static void
1455 sam3_explain_ckgr_mor(struct sam3_chip *pChip)
1456 {
1457         uint32_t v;
1458         uint32_t rcen;
1459
1460         v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1461         LOG_USER_N("(main xtal enabled: %s)\n",
1462                                   _yes_or_no(v));
1463         v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1464         LOG_USER_N("(main osc bypass: %s)\n",
1465                                   _yes_or_no(v));
1466         rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
1467         LOG_USER_N("(onchip RC-OSC enabled: %s)\n",
1468                                   _yes_or_no(rcen));
1469         v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1470         LOG_USER_N("(onchip RC-OSC freq: %s)\n",
1471                                   _rc_freq[v]);
1472
1473         pChip->cfg.rc_freq = 0;
1474         if (rcen) {
1475                 switch (v) {
1476                 default:
1477                         pChip->cfg.rc_freq = 0;
1478                 case 0:
1479                         pChip->cfg.rc_freq = 4 * 1000 * 1000;
1480                         break;
1481                 case 1:
1482                         pChip->cfg.rc_freq = 8 * 1000 * 1000;
1483                         break;
1484                 case 2:
1485                         pChip->cfg.rc_freq = 12* 1000 * 1000;
1486                         break;
1487                 }
1488         }
1489
1490         v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1491         LOG_USER_N("(startup clks, time= %f uSecs)\n",
1492                                   ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1493         v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1494         LOG_USER_N("(mainosc source: %s)\n",
1495                                   v ? "external xtal" : "internal RC");
1496
1497         v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1498         LOG_USER_N("(clock failure enabled: %s)\n",
1499                                  _yes_or_no(v));
1500 }
1501
1502
1503
1504 static void
1505 sam3_explain_chipid_cidr(struct sam3_chip *pChip)
1506 {
1507         int x;
1508         uint32_t v;
1509         const char *cp;
1510
1511         sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1512         LOG_USER_N("\n");
1513
1514         v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1515         LOG_USER_N("%s\n", eproc_names[v]);
1516
1517         v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1518         LOG_USER_N("%s\n", nvpsize[v]);
1519
1520         v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1521         LOG_USER_N("%s\n", nvpsize2[v]);
1522
1523         v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
1524         LOG_USER_N("%s\n", sramsize[ v ]);
1525
1526         v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1527         cp = _unknown;
1528         for (x = 0 ; archnames[x].name ; x++) {
1529                 if (v == archnames[x].value) {
1530                         cp = archnames[x].name;
1531                         break;
1532                 }
1533         }
1534
1535         LOG_USER_N("%s\n", cp);
1536
1537         v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1538         LOG_USER_N("%s\n", nvptype[ v ]);
1539
1540         v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1541         LOG_USER_N("(exists: %s)\n", _yes_or_no(v));
1542 }
1543
1544 static void
1545 sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
1546 {
1547         uint32_t v;
1548
1549
1550         v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1551         LOG_USER_N("(main ready: %s)\n", _yes_or_no(v));
1552
1553         v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1554
1555         v = (v * pChip->cfg.slow_freq) / 16;
1556         pChip->cfg.mainosc_freq = v;
1557
1558         LOG_USER_N("(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1559                                  _tomhz(v),
1560                                  pChip->cfg.slow_freq / 1000,
1561                                  pChip->cfg.slow_freq % 1000);
1562
1563 }
1564
1565 static void
1566 sam3_explain_ckgr_plla(struct sam3_chip *pChip)
1567 {
1568         uint32_t mula,diva;
1569
1570         diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1571         LOG_USER_N("\n");
1572         mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1573         LOG_USER_N("\n");
1574         pChip->cfg.plla_freq = 0;
1575         if (mula == 0) {
1576                 LOG_USER_N("\tPLLA Freq: (Disabled,mula = 0)\n");
1577         } else if (diva == 0) {
1578                 LOG_USER_N("\tPLLA Freq: (Disabled,diva = 0)\n");
1579         } else if (diva == 1) {
1580                 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
1581                 LOG_USER_N("\tPLLA Freq: %3.03f MHz\n",
1582                                          _tomhz(pChip->cfg.plla_freq));
1583         }
1584 }
1585
1586
1587 static void
1588 sam3_explain_mckr(struct sam3_chip *pChip)
1589 {
1590         uint32_t css, pres, fin = 0;
1591         int pdiv = 0;
1592         const char *cp = NULL;
1593
1594         css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1595         switch (css & 3) {
1596         case 0:
1597                 fin = pChip->cfg.slow_freq;
1598                 cp = "slowclk";
1599                 break;
1600         case 1:
1601                 fin = pChip->cfg.mainosc_freq;
1602                 cp  = "mainosc";
1603                 break;
1604         case 2:
1605                 fin = pChip->cfg.plla_freq;
1606                 cp  = "plla";
1607                 break;
1608         case 3:
1609                 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1610                         fin = 480 * 1000 * 1000;
1611                         cp = "upll";
1612                 } else {
1613                         fin = 0;
1614                         cp  = "upll (*ERROR* UPLL is disabled)";
1615                 }
1616                 break;
1617         default:
1618                 assert(0);
1619                 break;
1620         }
1621
1622         LOG_USER_N("%s (%3.03f Mhz)\n",
1623                                   cp,
1624                                   _tomhz(fin));
1625         pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1626         switch (pres & 0x07) {
1627         case 0:
1628                 pdiv = 1;
1629                 cp = "selected clock";
1630         case 1:
1631                 pdiv = 2;
1632                 cp = "clock/2";
1633                 break;
1634         case 2:
1635                 pdiv = 4;
1636                 cp = "clock/4";
1637                 break;
1638         case 3:
1639                 pdiv = 8;
1640                 cp = "clock/8";
1641                 break;
1642         case 4:
1643                 pdiv = 16;
1644                 cp = "clock/16";
1645                 break;
1646         case 5:
1647                 pdiv = 32;
1648                 cp = "clock/32";
1649                 break;
1650         case 6:
1651                 pdiv = 64;
1652                 cp = "clock/64";
1653                 break;
1654         case 7:
1655                 pdiv = 6;
1656                 cp = "clock/6";
1657                 break;
1658         default:
1659                 assert(0);
1660                 break;
1661         }
1662         LOG_USER_N("(%s)\n", cp);
1663         fin = fin / pdiv;
1664         // sam3 has a *SINGLE* clock -
1665         // other at91 series parts have divisors for these.
1666         pChip->cfg.cpu_freq = fin;
1667         pChip->cfg.mclk_freq = fin;
1668         pChip->cfg.fclk_freq = fin;
1669         LOG_USER_N("\t\tResult CPU Freq: %3.03f\n",
1670                                   _tomhz(fin));
1671 }
1672
1673 #if 0
1674 static struct sam3_chip *
1675 target2sam3(struct target *pTarget)
1676 {
1677         struct sam3_chip *pChip;
1678
1679         if (pTarget == NULL) {
1680                 return NULL;
1681         }
1682
1683         pChip = all_sam3_chips;
1684         while (pChip) {
1685                 if (pChip->target == pTarget) {
1686                         break; // return below
1687                 } else {
1688                         pChip = pChip->next;
1689                 }
1690         }
1691         return pChip;
1692 }
1693 #endif
1694
1695 static uint32_t *
1696 sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
1697 {
1698         // this function exists to help
1699         // keep funky offsetof() errors
1700         // and casting from causing bugs
1701
1702         // By using prototypes - we can detect what would
1703         // be casting errors.
1704
1705         return ((uint32_t *)(((char *)(pCfg)) + pList->struct_offset));
1706 }
1707
1708
1709 #define SAM3_ENTRY(NAME, FUNC)  { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1710 static const struct sam3_reg_list sam3_all_regs[] = {
1711         SAM3_ENTRY(CKGR_MOR , sam3_explain_ckgr_mor),
1712         SAM3_ENTRY(CKGR_MCFR , sam3_explain_ckgr_mcfr),
1713         SAM3_ENTRY(CKGR_PLLAR , sam3_explain_ckgr_plla),
1714         SAM3_ENTRY(CKGR_UCKR , NULL),
1715         SAM3_ENTRY(PMC_FSMR , NULL),
1716         SAM3_ENTRY(PMC_FSPR , NULL),
1717         SAM3_ENTRY(PMC_IMR , NULL),
1718         SAM3_ENTRY(PMC_MCKR , sam3_explain_mckr),
1719         SAM3_ENTRY(PMC_PCK0 , NULL),
1720         SAM3_ENTRY(PMC_PCK1 , NULL),
1721         SAM3_ENTRY(PMC_PCK2 , NULL),
1722         SAM3_ENTRY(PMC_PCSR , NULL),
1723         SAM3_ENTRY(PMC_SCSR , NULL),
1724         SAM3_ENTRY(PMC_SR , NULL),
1725         SAM3_ENTRY(CHIPID_CIDR , sam3_explain_chipid_cidr),
1726         SAM3_ENTRY(CHIPID_EXID , NULL),
1727         SAM3_ENTRY(SUPC_CR, NULL),
1728
1729         // TERMINATE THE LIST
1730         { .name = NULL }
1731 };
1732 #undef SAM3_ENTRY
1733
1734
1735
1736
1737 static struct sam3_bank_private *
1738 get_sam3_bank_private(struct flash_bank *bank)
1739 {
1740         return (struct sam3_bank_private *)(bank->driver_priv);
1741 }
1742
1743 /**
1744  * Given a pointer to where it goes in the structure,
1745  * determine the register name, address from the all registers table.
1746  */
1747 static const struct sam3_reg_list *
1748 sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
1749 {
1750         const struct sam3_reg_list *pReg;
1751
1752         pReg = &(sam3_all_regs[0]);
1753         while (pReg->name) {
1754                 uint32_t *pPossible;
1755
1756                 // calculate where this one go..
1757                 // it is "possibly" this register.
1758
1759                 pPossible = ((uint32_t *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1760
1761                 // well? Is it this register
1762                 if (pPossible == goes_here) {
1763                         // Jump for joy!
1764                         return pReg;
1765                 }
1766
1767                 // next...
1768                 pReg++;
1769         }
1770         // This is *TOTAL*PANIC* - we are totally screwed.
1771         LOG_ERROR("INVALID SAM3 REGISTER");
1772         return NULL;
1773 }
1774
1775
1776 static int
1777 sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
1778 {
1779         const struct sam3_reg_list *pReg;
1780         int r;
1781
1782         pReg = sam3_GetReg(pChip, goes_here);
1783         if (!pReg) {
1784                 return ERROR_FAIL;
1785         }
1786
1787         r = target_read_u32(pChip->target, pReg->address, goes_here);
1788         if (r != ERROR_OK) {
1789                 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1790                                   pReg->name, (unsigned)(pReg->address), r);
1791         }
1792         return r;
1793 }
1794
1795
1796
1797 static int
1798 sam3_ReadAllRegs(struct sam3_chip *pChip)
1799 {
1800         int r;
1801         const struct sam3_reg_list *pReg;
1802
1803         pReg = &(sam3_all_regs[0]);
1804         while (pReg->name) {
1805                 r = sam3_ReadThisReg(pChip,
1806                                                                   sam3_get_reg_ptr(&(pChip->cfg), pReg));
1807                 if (r != ERROR_OK) {
1808                         LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1809                                           pReg->name, ((unsigned)(pReg->address)), r);
1810                         return r;
1811                 }
1812
1813                 pReg++;
1814         }
1815
1816         return ERROR_OK;
1817 }
1818
1819
1820 static int
1821 sam3_GetInfo(struct sam3_chip *pChip)
1822 {
1823         const struct sam3_reg_list *pReg;
1824         uint32_t regval;
1825
1826         pReg = &(sam3_all_regs[0]);
1827         while (pReg->name) {
1828                 // display all regs
1829                 LOG_DEBUG("Start: %s", pReg->name);
1830                 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
1831                 LOG_USER_N("%*s: [0x%08x] -> 0x%08x\n",
1832                                          REG_NAME_WIDTH,
1833                                          pReg->name,
1834                                          pReg->address,
1835                                          regval);
1836                 if (pReg->explain_func) {
1837                         (*(pReg->explain_func))(pChip);
1838                 }
1839                 LOG_DEBUG("End: %s", pReg->name);
1840                 pReg++;
1841         }
1842         LOG_USER_N("   rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
1843         LOG_USER_N("  mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
1844         LOG_USER_N("     plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
1845         LOG_USER_N(" cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
1846         LOG_USER_N("mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
1847
1848
1849         LOG_USER_N(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1850                                   pChip->cfg.unique_id[0],
1851                                   pChip->cfg.unique_id[1],
1852                                   pChip->cfg.unique_id[2],
1853                                   pChip->cfg.unique_id[3]);
1854
1855
1856         return ERROR_OK;
1857 }
1858
1859
1860 static int
1861 sam3_erase_check(struct flash_bank *bank)
1862 {
1863         int x;
1864
1865         LOG_DEBUG("Here");
1866         if (bank->target->state != TARGET_HALTED) {
1867                 LOG_ERROR("Target not halted");
1868                 return ERROR_TARGET_NOT_HALTED;
1869         }
1870         if (0 == bank->num_sectors) {
1871                 LOG_ERROR("Target: not supported/not probed\n");
1872                 return ERROR_FAIL;
1873         }
1874
1875         LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1876         for (x = 0 ; x < bank->num_sectors ; x++) {
1877                 bank->sectors[x].is_erased = 1;
1878         }
1879
1880         LOG_DEBUG("Done");
1881         return ERROR_OK;
1882 }
1883
1884 static int
1885 sam3_protect_check(struct flash_bank *bank)
1886 {
1887         int r;
1888         uint32_t v=0;
1889         unsigned x;
1890         struct sam3_bank_private *pPrivate;
1891
1892         LOG_DEBUG("Begin");
1893         if (bank->target->state != TARGET_HALTED) {
1894                 LOG_ERROR("Target not halted");
1895                 return ERROR_TARGET_NOT_HALTED;
1896         }
1897
1898         pPrivate = get_sam3_bank_private(bank);
1899         if (!pPrivate) {
1900                 LOG_ERROR("no private for this bank?");
1901                 return ERROR_FAIL;
1902         }
1903         if (!(pPrivate->probed)) {
1904                 return ERROR_FLASH_BANK_NOT_PROBED;
1905         }
1906
1907         r = FLASHD_GetLockBits(pPrivate , &v);
1908         if (r != ERROR_OK) {
1909                 LOG_DEBUG("Failed: %d",r);
1910                 return r;
1911         }
1912
1913         for (x = 0 ; x < pPrivate->nsectors ; x++) {
1914                 bank->sectors[x].is_protected = (!!(v & (1 << x)));
1915         }
1916         LOG_DEBUG("Done");
1917         return ERROR_OK;
1918 }
1919
1920 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
1921 {
1922         struct sam3_chip *pChip;
1923
1924         pChip = all_sam3_chips;
1925
1926         // is this an existing chip?
1927         while (pChip) {
1928                 if (pChip->target == bank->target) {
1929                         break;
1930                 }
1931                 pChip = pChip->next;
1932         }
1933
1934         if (!pChip) {
1935                 // this is a *NEW* chip
1936                 pChip = calloc(1, sizeof(struct sam3_chip));
1937                 if (!pChip) {
1938                         LOG_ERROR("NO RAM!");
1939                         return ERROR_FAIL;
1940                 }
1941                 pChip->target = bank->target;
1942                 // insert at head
1943                 pChip->next = all_sam3_chips;
1944                 all_sam3_chips = pChip;
1945                 pChip->target = bank->target;
1946                 // assumption is this runs at 32khz
1947                 pChip->cfg.slow_freq = 32768;
1948                 pChip->probed = 0;
1949         }
1950
1951         switch (bank->base) {
1952         default:
1953                 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
1954                         [at91sam3u series] or 0x%08x [at91sam3s series])",
1955                                   ((unsigned int)(bank->base)),
1956                                   ((unsigned int)(FLASH_BANK0_BASE_U)),
1957                                   ((unsigned int)(FLASH_BANK1_BASE_U)),
1958                                   ((unsigned int)(FLASH_BANK_BASE_S)));
1959                 return ERROR_FAIL;
1960                 break;
1961
1962         // at91sam3u series
1963         case FLASH_BANK0_BASE_U:
1964                 bank->driver_priv = &(pChip->details.bank[0]);
1965                 bank->bank_number = 0;
1966                 pChip->details.bank[0].pChip = pChip;
1967                 pChip->details.bank[0].pBank = bank;
1968                 break;
1969         case FLASH_BANK1_BASE_U:
1970                 bank->driver_priv = &(pChip->details.bank[1]);
1971                 bank->bank_number = 1;
1972                 pChip->details.bank[1].pChip = pChip;
1973                 pChip->details.bank[1].pBank = bank;
1974
1975         // at91sam3s series
1976         case FLASH_BANK_BASE_S:
1977                 bank->driver_priv = &(pChip->details.bank[0]);
1978                 bank->bank_number = 0;
1979                 pChip->details.bank[0].pChip = pChip;
1980                 pChip->details.bank[0].pBank = bank;
1981                 break;
1982         }
1983
1984         // we initialize after probing.
1985         return ERROR_OK;
1986 }
1987
1988 static int
1989 sam3_GetDetails(struct sam3_bank_private *pPrivate)
1990 {
1991         const struct sam3_chip_details *pDetails;
1992         struct sam3_chip *pChip;
1993         struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
1994         unsigned x;
1995
1996         LOG_DEBUG("Begin");
1997         pDetails = all_sam3_details;
1998         while (pDetails->name) {
1999                 if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) {
2000                         break;
2001                 } else {
2002                         pDetails++;
2003                 }
2004         }
2005         if (pDetails->name == NULL) {
2006                 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
2007                                   (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2008                 // Help the victim, print details about the chip
2009                 LOG_INFO_N("SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
2010                                                 pPrivate->pChip->cfg.CHIPID_CIDR);
2011                 sam3_explain_chipid_cidr(pPrivate->pChip);
2012                 return ERROR_FAIL;
2013         }
2014
2015         // DANGER: THERE ARE DRAGONS HERE
2016
2017         // get our pChip - it is going
2018         // to be over-written shortly
2019         pChip = pPrivate->pChip;
2020
2021         // Note that, in reality:
2022         //
2023         //     pPrivate = &(pChip->details.bank[0])
2024         // or  pPrivate = &(pChip->details.bank[1])
2025         //
2026
2027         // save the "bank" pointers
2028         for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2029                 saved_banks[ x ] = pChip->details.bank[x].pBank;
2030         }
2031
2032         // Overwrite the "details" structure.
2033         memcpy(&(pPrivate->pChip->details),
2034                         pDetails,
2035                         sizeof(pPrivate->pChip->details));
2036
2037         // now fix the ghosted pointers
2038         for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2039                 pChip->details.bank[x].pChip = pChip;
2040                 pChip->details.bank[x].pBank = saved_banks[x];
2041         }
2042
2043         // update the *BANK*SIZE*
2044
2045         LOG_DEBUG("End");
2046         return ERROR_OK;
2047 }
2048
2049
2050
2051 static int
2052 _sam3_probe(struct flash_bank *bank, int noise)
2053 {
2054         unsigned x;
2055         int r;
2056         struct sam3_bank_private *pPrivate;
2057
2058
2059         LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2060         if (bank->target->state != TARGET_HALTED)
2061         {
2062                 LOG_ERROR("Target not halted");
2063                 return ERROR_TARGET_NOT_HALTED;
2064         }
2065
2066         pPrivate = get_sam3_bank_private(bank);
2067         if (!pPrivate) {
2068                 LOG_ERROR("Invalid/unknown bank number\n");
2069                 return ERROR_FAIL;
2070         }
2071
2072         r = sam3_ReadAllRegs(pPrivate->pChip);
2073         if (r != ERROR_OK) {
2074                 return r;
2075         }
2076
2077
2078         LOG_DEBUG("Here");
2079         if (pPrivate->pChip->probed) {
2080                 r = sam3_GetInfo(pPrivate->pChip);
2081         } else {
2082                 r = sam3_GetDetails(pPrivate);
2083         }
2084         if (r != ERROR_OK) {
2085                 return r;
2086         }
2087
2088         // update the flash bank size
2089         for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2090                 if (bank->base == pPrivate->pChip->details.bank[0].base_address) {
2091                         bank->size =  pPrivate->pChip->details.bank[0].size_bytes;
2092                         break;
2093                 }
2094         }
2095
2096         if (bank->sectors == NULL) {
2097                 bank->sectors     = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2098                 if (bank->sectors == NULL) {
2099                         LOG_ERROR("No memory!");
2100                         return ERROR_FAIL;
2101                 }
2102                 bank->num_sectors = pPrivate->nsectors;
2103
2104                 for (x = 0 ; ((int)(x)) < bank->num_sectors ; x++) {
2105                         bank->sectors[x].size         = pPrivate->sector_size;
2106                         bank->sectors[x].offset       = x * (pPrivate->sector_size);
2107                         // mark as unknown
2108                         bank->sectors[x].is_erased    = -1;
2109                         bank->sectors[x].is_protected = -1;
2110                 }
2111         }
2112
2113         pPrivate->probed = 1;
2114
2115         r = sam3_protect_check(bank);
2116         if (r != ERROR_OK) {
2117                 return r;
2118         }
2119
2120         LOG_DEBUG("Bank = %d, nbanks = %d",
2121                           pPrivate->bank_number , pPrivate->pChip->details.n_banks);
2122         if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2123                 // read unique id,
2124                 // it appears to be associated with the *last* flash bank.
2125                 FLASHD_ReadUniqueID(pPrivate);
2126         }
2127
2128         return r;
2129 }
2130
2131 static int
2132 sam3_probe(struct flash_bank *bank)
2133 {
2134         return _sam3_probe(bank, 1);
2135 }
2136
2137 static int
2138 sam3_auto_probe(struct flash_bank *bank)
2139 {
2140         return _sam3_probe(bank, 0);
2141 }
2142
2143
2144
2145 static int
2146 sam3_erase(struct flash_bank *bank, int first, int last)
2147 {
2148         struct sam3_bank_private *pPrivate;
2149         int r;
2150
2151         LOG_DEBUG("Here");
2152         if (bank->target->state != TARGET_HALTED) {
2153                 LOG_ERROR("Target not halted");
2154                 return ERROR_TARGET_NOT_HALTED;
2155         }
2156
2157         r = sam3_auto_probe(bank);
2158         if (r != ERROR_OK) {
2159                 LOG_DEBUG("Here,r=%d",r);
2160                 return r;
2161         }
2162
2163         pPrivate = get_sam3_bank_private(bank);
2164         if (!(pPrivate->probed)) {
2165                 return ERROR_FLASH_BANK_NOT_PROBED;
2166         }
2167
2168         if ((first == 0) && ((last + 1)== ((int)(pPrivate->nsectors)))) {
2169                 // whole chip
2170                 LOG_DEBUG("Here");
2171                 return FLASHD_EraseEntireBank(pPrivate);
2172         }
2173         LOG_INFO("sam3 auto-erases while programing (request ignored)");
2174         return ERROR_OK;
2175 }
2176
2177 static int
2178 sam3_protect(struct flash_bank *bank, int set, int first, int last)
2179 {
2180         struct sam3_bank_private *pPrivate;
2181         int r;
2182
2183         LOG_DEBUG("Here");
2184         if (bank->target->state != TARGET_HALTED) {
2185                 LOG_ERROR("Target not halted");
2186                 return ERROR_TARGET_NOT_HALTED;
2187         }
2188
2189         pPrivate = get_sam3_bank_private(bank);
2190         if (!(pPrivate->probed)) {
2191                 return ERROR_FLASH_BANK_NOT_PROBED;
2192         }
2193
2194         if (set) {
2195                 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2196         } else {
2197                 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2198         }
2199         LOG_DEBUG("End: r=%d",r);
2200
2201         return r;
2202
2203 }
2204
2205
2206 static int
2207 sam3_info(struct flash_bank *bank, char *buf, int buf_size)
2208 {
2209         if (bank->target->state != TARGET_HALTED) {
2210                 LOG_ERROR("Target not halted");
2211                 return ERROR_TARGET_NOT_HALTED;
2212         }
2213         buf[ 0 ] = 0;
2214         return ERROR_OK;
2215 }
2216
2217 static int
2218 sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2219 {
2220         uint32_t adr;
2221         int r;
2222
2223         adr = pagenum * pPrivate->page_size;
2224         adr += adr + pPrivate->base_address;
2225
2226         r = target_read_memory(pPrivate->pChip->target,
2227                                                         adr,
2228                                                         4, /* THIS*MUST*BE* in 32bit values */
2229                                                         pPrivate->page_size / 4,
2230                                                         buf);
2231         if (r != ERROR_OK) {
2232                 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr));
2233         }
2234         return r;
2235 }
2236
2237 // The code below is basically this:
2238 // compiled with
2239 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
2240 //
2241 // Only the *CPU* can write to the flash buffer.
2242 // the DAP cannot... so - we download this 28byte thing
2243 // Run the algorithm - (below)
2244 // to program the device
2245 //
2246 // ========================================
2247 // #include <stdint.h>
2248 //
2249 // struct foo {
2250 //   uint32_t *dst;
2251 //   const uint32_t *src;
2252 //   int   n;
2253 //   volatile uint32_t *base;
2254 //   uint32_t   cmd;
2255 // };
2256 //
2257 //
2258 // uint32_t sam3_function(struct foo *p)
2259 // {
2260 //   volatile uint32_t *v;
2261 //   uint32_t *d;
2262 //   const uint32_t *s;
2263 //   int   n;
2264 //   uint32_t r;
2265 //
2266 //   d = p->dst;
2267 //   s = p->src;
2268 //   n = p->n;
2269 //
2270 //   do {
2271 //     *d++ = *s++;
2272 //   } while (--n)
2273 //     ;
2274 //
2275 //   v = p->base;
2276 //
2277 //   v[ 1 ] = p->cmd;
2278 //   do {
2279 //     r = v[8/4];
2280 //   } while (!(r&1))
2281 //     ;
2282 //   return r;
2283 // }
2284 // ========================================
2285
2286
2287
2288 static const uint8_t
2289 sam3_page_write_opcodes[] = {
2290         //  24 0000 0446                mov     r4, r0
2291         0x04,0x46,
2292         //  25 0002 6168                ldr     r1, [r4, #4]
2293         0x61,0x68,
2294         //  26 0004 0068                ldr     r0, [r0, #0]
2295         0x00,0x68,
2296         //  27 0006 A268                ldr     r2, [r4, #8]
2297         0xa2,0x68,
2298         //  28                          @ lr needed for prologue
2299         //  29                  .L2:
2300         //  30 0008 51F8043B            ldr     r3, [r1], #4
2301         0x51,0xf8,0x04,0x3b,
2302         //  31 000c 12F1FF32            adds    r2, r2, #-1
2303         0x12,0xf1,0xff,0x32,
2304         //  32 0010 40F8043B            str     r3, [r0], #4
2305         0x40,0xf8,0x04,0x3b,
2306         //  33 0014 F8D1                bne     .L2
2307         0xf8,0xd1,
2308         //  34 0016 E268                ldr     r2, [r4, #12]
2309         0xe2,0x68,
2310         //  35 0018 2369                ldr     r3, [r4, #16]
2311         0x23,0x69,
2312         //  36 001a 5360                str     r3, [r2, #4]
2313         0x53,0x60,
2314         //  37 001c 0832                adds    r2, r2, #8
2315         0x08,0x32,
2316         //  38                  .L4:
2317         //  39 001e 1068                ldr     r0, [r2, #0]
2318         0x10,0x68,
2319         //  40 0020 10F0010F            tst     r0, #1
2320         0x10,0xf0,0x01,0x0f,
2321         //  41 0024 FBD0                beq     .L4
2322         0xfb,0xd0,
2323         0x00,0xBE                               /* bkpt #0 */
2324 };
2325
2326
2327 static int
2328 sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2329 {
2330         uint32_t adr;
2331         uint32_t status;
2332         int r;
2333
2334         adr = pagenum * pPrivate->page_size;
2335         adr += (adr + pPrivate->base_address);
2336
2337         LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2338         r = target_write_memory(pPrivate->pChip->target,
2339                                                          adr,
2340                                                          4, /* THIS*MUST*BE* in 32bit values */
2341                                                          pPrivate->page_size / 4,
2342                                                          buf);
2343         if (r != ERROR_OK) {
2344                 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr));
2345                 return r;
2346         }
2347
2348         r = EFC_PerformCommand(pPrivate,
2349                                                         // send Erase & Write Page
2350                                                         AT91C_EFC_FCMD_EWP,
2351                                                         pagenum,
2352                                                         &status);
2353
2354         if (r != ERROR_OK) {
2355                 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr));
2356         }
2357         if (status & (1 << 2)) {
2358                 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2359                 return ERROR_FAIL;
2360         }
2361         if (status & (1 << 1)) {
2362                 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2363                 return ERROR_FAIL;
2364         }
2365         return ERROR_OK;
2366 }
2367
2368
2369
2370
2371
2372 static int
2373 sam3_write(struct flash_bank *bank,
2374                    uint8_t *buffer,
2375                    uint32_t offset,
2376                    uint32_t count)
2377 {
2378         int n;
2379         unsigned page_cur;
2380         unsigned page_end;
2381         int r;
2382         unsigned page_offset;
2383         struct sam3_bank_private *pPrivate;
2384         uint8_t *pagebuffer;
2385
2386         // incase we bail further below, set this to null
2387         pagebuffer = NULL;
2388
2389         // ignore dumb requests
2390         if (count == 0) {
2391                 r = ERROR_OK;
2392                 goto done;
2393         }
2394
2395         if (bank->target->state != TARGET_HALTED) {
2396                 LOG_ERROR("Target not halted");
2397                 r = ERROR_TARGET_NOT_HALTED;
2398                 goto done;
2399         }
2400
2401         pPrivate = get_sam3_bank_private(bank);
2402         if (!(pPrivate->probed)) {
2403                 r = ERROR_FLASH_BANK_NOT_PROBED;
2404                 goto done;
2405         }
2406
2407
2408         if ((offset + count) > pPrivate->size_bytes) {
2409                 LOG_ERROR("Flash write error - past end of bank");
2410                 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2411                                   (unsigned int)(offset),
2412                                   (unsigned int)(count),
2413                                   (unsigned int)(pPrivate->size_bytes));
2414                 r = ERROR_FAIL;
2415                 goto done;
2416         }
2417
2418         pagebuffer = malloc(pPrivate->page_size);
2419         if( !pagebuffer ){
2420                 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2421                 r = ERROR_FAIL;
2422                 goto done;
2423         }
2424
2425         // what page do we start & end in?
2426         page_cur = offset / pPrivate->page_size;
2427         page_end = (offset + count - 1) / pPrivate->page_size;
2428
2429         LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2430         LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2431
2432         // Special case: all one page
2433         //
2434         // Otherwise:
2435         //    (1) non-aligned start
2436         //    (2) body pages
2437         //    (3) non-aligned end.
2438
2439         // Handle special case - all one page.
2440         if (page_cur == page_end) {
2441                 LOG_DEBUG("Special case, all in one page");
2442                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2443                 if (r != ERROR_OK) {
2444                         goto done;
2445                 }
2446
2447                 page_offset = (offset & (pPrivate->page_size-1));
2448                 memcpy(pagebuffer + page_offset,
2449                                 buffer,
2450                                 count);
2451
2452                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2453                 if (r != ERROR_OK) {
2454                         goto done;
2455                 }
2456                 r = ERROR_OK;
2457                 goto done;
2458         }
2459
2460         // non-aligned start
2461         page_offset = offset & (pPrivate->page_size - 1);
2462         if (page_offset) {
2463                 LOG_DEBUG("Not-Aligned start");
2464                 // read the partial
2465                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2466                 if (r != ERROR_OK) {
2467                         goto done;
2468                 }
2469
2470                 // over-write with new data
2471                 n = (pPrivate->page_size - page_offset);
2472                 memcpy(pagebuffer + page_offset,
2473                                 buffer,
2474                                 n);
2475
2476                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2477                 if (r != ERROR_OK) {
2478                         goto done;
2479                 }
2480
2481                 count  -= n;
2482                 offset += n;
2483                 buffer += n;
2484                 page_cur++;
2485         }
2486
2487         // intermediate large pages
2488         // also - the final *terminal*
2489         // if that terminal page is a full page
2490         LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2491                           (int)page_cur, (int)page_end, (unsigned int)(count));
2492
2493         while ((page_cur < page_end) &&
2494                    (count >= pPrivate->page_size)) {
2495                 r = sam3_page_write(pPrivate, page_cur, buffer);
2496                 if (r != ERROR_OK) {
2497                         goto done;
2498                 }
2499                 count    -= pPrivate->page_size;
2500                 buffer   += pPrivate->page_size;
2501                 page_cur += 1;
2502         }
2503
2504         // terminal partial page?
2505         if (count) {
2506                 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2507                 // we have a partial page
2508                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2509                 if (r != ERROR_OK) {
2510                         goto done;
2511                 }
2512                 // data goes at start
2513                 memcpy(pagebuffer, buffer, count);
2514                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2515                 if (r != ERROR_OK) {
2516                         goto done;
2517                 }
2518                 buffer += count;
2519                 count  -= count;
2520         }
2521         LOG_DEBUG("Done!");
2522         r = ERROR_OK;
2523  done:
2524         if( pagebuffer ){
2525                 free(pagebuffer);
2526         }
2527         return r;
2528 }
2529
2530 COMMAND_HANDLER(sam3_handle_info_command)
2531 {
2532         struct sam3_chip *pChip;
2533         unsigned x;
2534         int r;
2535
2536         pChip = get_current_sam3(CMD_CTX);
2537         if (!pChip) {
2538                 return ERROR_OK;
2539         }
2540
2541         r = 0;
2542
2543         // bank0 must exist before we can do anything
2544         if (pChip->details.bank[0].pBank == NULL) {
2545                 x = 0;
2546         need_define:
2547                 command_print(CMD_CTX,
2548                                            "Please define bank %d via command: flash bank %s ... ",
2549                                            x,
2550                                            at91sam3_flash.name);
2551                 return ERROR_FAIL;
2552         }
2553
2554         // if bank 0 is not probed, then probe it
2555         if (!(pChip->details.bank[0].probed)) {
2556                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2557                 if (r != ERROR_OK) {
2558                         return ERROR_FAIL;
2559                 }
2560         }
2561         // above guarantees the "chip details" structure is valid
2562         // and thus, bank private areas are valid
2563         // and we have a SAM3 chip, what a concept!
2564
2565
2566         // auto-probe other banks, 0 done above
2567     for (x = 1 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2568                 // skip banks not present
2569                 if (!(pChip->details.bank[x].present)) {
2570                         continue;
2571                 }
2572
2573                 if (pChip->details.bank[x].pBank == NULL) {
2574                         goto need_define;
2575                 }
2576
2577                 if (pChip->details.bank[x].probed) {
2578                         continue;
2579                 }
2580
2581                 r = sam3_auto_probe(pChip->details.bank[x].pBank);
2582                 if (r != ERROR_OK) {
2583                         return r;
2584                 }
2585         }
2586
2587
2588         r = sam3_GetInfo(pChip);
2589         if (r != ERROR_OK) {
2590                 LOG_DEBUG("Sam3Info, Failed %d\n",r);
2591                 return r;
2592         }
2593
2594         return ERROR_OK;
2595 }
2596
2597 COMMAND_HANDLER(sam3_handle_gpnvm_command)
2598 {
2599         unsigned x,v;
2600         int r,who;
2601         struct sam3_chip *pChip;
2602
2603         pChip = get_current_sam3(CMD_CTX);
2604         if (!pChip) {
2605                 return ERROR_OK;
2606         }
2607
2608         if (pChip->target->state != TARGET_HALTED) {
2609                 LOG_ERROR("sam3 - target not halted");
2610                 return ERROR_TARGET_NOT_HALTED;
2611         }
2612
2613
2614         if (pChip->details.bank[0].pBank == NULL) {
2615                 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2616                                            at91sam3_flash.name);
2617                 return ERROR_FAIL;
2618         }
2619         if (!pChip->details.bank[0].probed) {
2620                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2621                 if (r != ERROR_OK) {
2622                         return r;
2623                 }
2624         }
2625
2626
2627         switch (CMD_ARGC) {
2628         default:
2629                 command_print(CMD_CTX,"Too many parameters\n");
2630                 return ERROR_COMMAND_SYNTAX_ERROR;
2631                 break;
2632         case 0:
2633                 who = -1;
2634                 goto showall;
2635                 break;
2636         case 1:
2637                 who = -1;
2638                 break;
2639         case 2:
2640                 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all"))) {
2641                         who = -1;
2642                 } else {
2643                         uint32_t v32;
2644                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2645                         who = v32;
2646                 }
2647                 break;
2648         }
2649
2650         if (0 == strcmp("show", CMD_ARGV[0])) {
2651                 if (who == -1) {
2652 showall:
2653                         r = ERROR_OK;
2654                         for (x = 0 ; x < pChip->details.n_gpnvms ; x++) {
2655                                 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2656                                 if (r != ERROR_OK) {
2657                                         break;
2658                                 }
2659                                 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
2660                         }
2661                         return r;
2662                 }
2663                 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2664                         r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2665                         command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
2666                         return r;
2667                 } else {
2668                         command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
2669                         return ERROR_COMMAND_SYNTAX_ERROR;
2670                 }
2671         }
2672
2673         if (who == -1) {
2674                 command_print(CMD_CTX, "Missing GPNVM number");
2675                 return ERROR_COMMAND_SYNTAX_ERROR;
2676         }
2677
2678         if (0 == strcmp("set", CMD_ARGV[0])) {
2679                 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2680         } else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
2681                            (0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both
2682                 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2683         } else {
2684                 command_print(CMD_CTX, "Unkown command: %s", CMD_ARGV[0]);
2685                 r = ERROR_COMMAND_SYNTAX_ERROR;
2686         }
2687         return r;
2688 }
2689
2690 COMMAND_HANDLER(sam3_handle_slowclk_command)
2691 {
2692         struct sam3_chip *pChip;
2693
2694         pChip = get_current_sam3(CMD_CTX);
2695         if (!pChip) {
2696                 return ERROR_OK;
2697         }
2698
2699
2700         switch (CMD_ARGC) {
2701         case 0:
2702                 // show
2703                 break;
2704         case 1:
2705         {
2706                 // set
2707                 uint32_t v;
2708                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
2709                 if (v > 200000) {
2710                         // absurd slow clock of 200Khz?
2711                         command_print(CMD_CTX,"Absurd/illegal slow clock freq: %d\n", (int)(v));
2712                         return ERROR_COMMAND_SYNTAX_ERROR;
2713                 }
2714                 pChip->cfg.slow_freq = v;
2715                 break;
2716         }
2717         default:
2718                 // error
2719                 command_print(CMD_CTX,"Too many parameters");
2720                 return ERROR_COMMAND_SYNTAX_ERROR;
2721                 break;
2722         }
2723         command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
2724                                    (int)(pChip->cfg.slow_freq/ 1000),
2725                                    (int)(pChip->cfg.slow_freq% 1000));
2726         return ERROR_OK;
2727 }
2728
2729 static const struct command_registration at91sam3_exec_command_handlers[] = {
2730         {
2731                 .name = "gpnvm",
2732                 .handler = sam3_handle_gpnvm_command,
2733                 .mode = COMMAND_EXEC,
2734                 .usage = "[('clr'|'set'|'show') bitnum]",
2735                 .help = "Without arguments, shows all bits in the gpnvm "
2736                         "register.  Otherwise, clears, sets, or shows one "
2737                         "General Purpose Non-Volatile Memory (gpnvm) bit.",
2738         },
2739         {
2740                 .name = "info",
2741                 .handler = sam3_handle_info_command,
2742                 .mode = COMMAND_EXEC,
2743                 .help = "Print information about the current at91sam3 chip"
2744                         "and its flash configuration.",
2745         },
2746         {
2747                 .name = "slowclk",
2748                 .handler = sam3_handle_slowclk_command,
2749                 .mode = COMMAND_EXEC,
2750                 .usage = "[clock_hz]",
2751                 .help = "Display or set the slowclock frequency "
2752                         "(default 32768 Hz).",
2753         },
2754         COMMAND_REGISTRATION_DONE
2755 };
2756 static const struct command_registration at91sam3_command_handlers[] = {
2757         {
2758                 .name = "at91sam3",
2759                 .mode = COMMAND_ANY,
2760                 .help = "at91sam3 flash command group",
2761                 .chain = at91sam3_exec_command_handlers,
2762         },
2763         COMMAND_REGISTRATION_DONE
2764 };
2765
2766 struct flash_driver at91sam3_flash = {
2767         .name = "at91sam3",
2768         .commands = at91sam3_command_handlers,
2769         .flash_bank_command = sam3_flash_bank_command,
2770         .erase = sam3_erase,
2771         .protect = sam3_protect,
2772         .write = sam3_write,
2773         .read = default_flash_read,
2774         .probe = sam3_probe,
2775         .auto_probe = sam3_auto_probe,
2776         .erase_check = sam3_erase_check,
2777         .protect_check = sam3_protect_check,
2778         .info = sam3_info,
2779 };