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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Duane Ellis                                     *
   3  *   openocd@duaneellis.com                                                *
   4  *                                                                         *
   5  *   Copyright (C) 2010 by Olaf Lüke (at91sam3s* support)                  *
   6  *   olaf@uni-paderborn.de                                                 *
   7  *                                                                                                                                                 *
   8  *   Copyright (C) 2011 by Olivier Schonken (at91sam3x* support)           *                                          *
   9  *                     and Jim Norris                                      *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24 ****************************************************************************/
  25
  26 /* Some of the the lower level code was based on code supplied by
  27  * ATMEL under this copyright. */
  28
  29 /* BEGIN ATMEL COPYRIGHT */
  30 /* ----------------------------------------------------------------------------
  31  *         ATMEL Microcontroller Software Support
  32  * ----------------------------------------------------------------------------
  33  * Copyright (c) 2009, Atmel Corporation
  34  *
  35  * All rights reserved.
  36  *
  37  * Redistribution and use in source and binary forms, with or without
  38  * modification, are permitted provided that the following conditions are met:
  39  *
  40  * - Redistributions of source code must retain the above copyright notice,
  41  * this list of conditions and the disclaimer below.
  42  *
  43  * Atmel's name may not be used to endorse or promote products derived from
  44  * this software without specific prior written permission.
  45  *
  46  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  47  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  48  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  49  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  50  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  51  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  52  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  53  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  54  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  55  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  56  * ----------------------------------------------------------------------------
  57  */
  58 /* END ATMEL COPYRIGHT */
  59
  60 #ifdef HAVE_CONFIG_H
  61 #include "config.h"
  62 #endif
  63
  64 #include "imp.h"
  65 #include <helper/time_support.h>
  66
  67 #define REG_NAME_WIDTH  (12)
  68
  69 /* at91sam3u series (has one or two flash banks) */
  70 #define FLASH_BANK0_BASE_U   0x00080000
  71 #define FLASH_BANK1_BASE_U   0x00100000
  72
  73 /* at91sam3s series (has always one flash bank) */
  74 #define FLASH_BANK_BASE_S   0x00400000
  75
  76 /* at91sam3n series (has always one flash bank) */
  77 #define FLASH_BANK_BASE_N   0x00400000
  78
  79 /* at91sam3a/x series has two flash banks*/
  80 #define FLASH_BANK0_BASE_AX                     0x00080000
  81 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
  82 #define FLASH_BANK1_BASE_256K_AX        0x000A0000
  83 #define FLASH_BANK1_BASE_512K_AX        0x000C0000
  84
  85 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
  86 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
  87
  88 #define         AT91C_EFC_FCMD_GETD                 (0x0)       /* (EFC) Get Flash Descriptor */
  89 #define         AT91C_EFC_FCMD_WP                   (0x1)       /* (EFC) Write Page */
  90 #define         AT91C_EFC_FCMD_WPL                  (0x2)       /* (EFC) Write Page and Lock */
  91 #define         AT91C_EFC_FCMD_EWP                  (0x3)       /* (EFC) Erase Page and Write Page */
  92 #define         AT91C_EFC_FCMD_EWPL                 (0x4)       /* (EFC) Erase Page and Write Page
  93                                                                  * then Lock */
  94 #define         AT91C_EFC_FCMD_EA                   (0x5)       /* (EFC) Erase All */
  95 /* cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
  96 /* #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane? */
  97 /* cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
  98 /* #define      AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages? */
  99 #define         AT91C_EFC_FCMD_SLB                  (0x8)       /* (EFC) Set Lock Bit */
 100 #define         AT91C_EFC_FCMD_CLB                  (0x9)       /* (EFC) Clear Lock Bit */
 101 #define         AT91C_EFC_FCMD_GLB                  (0xA)       /* (EFC) Get Lock Bit */
 102 #define         AT91C_EFC_FCMD_SFB                  (0xB)       /* (EFC) Set Fuse Bit */
 103 #define         AT91C_EFC_FCMD_CFB                  (0xC)       /* (EFC) Clear Fuse Bit */
 104 #define         AT91C_EFC_FCMD_GFB                  (0xD)       /* (EFC) Get Fuse Bit */
 105 #define         AT91C_EFC_FCMD_STUI                 (0xE)       /* (EFC) Start Read Unique ID */
 106 #define         AT91C_EFC_FCMD_SPUI                 (0xF)       /* (EFC) Stop Read Unique ID */
 107
 108 #define  offset_EFC_FMR   0
 109 #define  offset_EFC_FCR   4
 110 #define  offset_EFC_FSR   8
 111 #define  offset_EFC_FRR   12
 112
 113 extern struct flash_driver at91sam3_flash;
 114
 115 static float _tomhz(uint32_t freq_hz)
 116 {
 117         float f;
 118
 119         f = ((float)(freq_hz)) / 1000000.0;
 120         return f;
 121 }
 122
 123 /* How the chip is configured. */
 124 struct sam3_cfg {
 125         uint32_t unique_id[4];
 126
 127         uint32_t slow_freq;
 128         uint32_t rc_freq;
 129         uint32_t mainosc_freq;
 130         uint32_t plla_freq;
 131         uint32_t mclk_freq;
 132         uint32_t cpu_freq;
 133         uint32_t fclk_freq;
 134         uint32_t pclk0_freq;
 135         uint32_t pclk1_freq;
 136         uint32_t pclk2_freq;
 137
 138
 139 #define SAM3_CHIPID_CIDR          (0x400E0740)
 140         uint32_t CHIPID_CIDR;
 141 #define SAM3_CHIPID_CIDR2         (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
 142         uint32_t CHIPID_CIDR2;
 143 #define SAM3_CHIPID_EXID          (0x400E0744)
 144         uint32_t CHIPID_EXID;
 145 #define SAM3_CHIPID_EXID2         (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
 146         uint32_t CHIPID_EXID2;
 147
 148
 149 #define SAM3_PMC_BASE             (0x400E0400)
 150 #define SAM3_PMC_SCSR             (SAM3_PMC_BASE + 0x0008)
 151         uint32_t PMC_SCSR;
 152 #define SAM3_PMC_PCSR             (SAM3_PMC_BASE + 0x0018)
 153         uint32_t PMC_PCSR;
 154 #define SAM3_CKGR_UCKR            (SAM3_PMC_BASE + 0x001c)
 155         uint32_t CKGR_UCKR;
 156 #define SAM3_CKGR_MOR             (SAM3_PMC_BASE + 0x0020)
 157         uint32_t CKGR_MOR;
 158 #define SAM3_CKGR_MCFR            (SAM3_PMC_BASE + 0x0024)
 159         uint32_t CKGR_MCFR;
 160 #define SAM3_CKGR_PLLAR           (SAM3_PMC_BASE + 0x0028)
 161         uint32_t CKGR_PLLAR;
 162 #define SAM3_PMC_MCKR             (SAM3_PMC_BASE + 0x0030)
 163         uint32_t PMC_MCKR;
 164 #define SAM3_PMC_PCK0             (SAM3_PMC_BASE + 0x0040)
 165         uint32_t PMC_PCK0;
 166 #define SAM3_PMC_PCK1             (SAM3_PMC_BASE + 0x0044)
 167         uint32_t PMC_PCK1;
 168 #define SAM3_PMC_PCK2             (SAM3_PMC_BASE + 0x0048)
 169         uint32_t PMC_PCK2;
 170 #define SAM3_PMC_SR               (SAM3_PMC_BASE + 0x0068)
 171         uint32_t PMC_SR;
 172 #define SAM3_PMC_IMR              (SAM3_PMC_BASE + 0x006c)
 173         uint32_t PMC_IMR;
 174 #define SAM3_PMC_FSMR             (SAM3_PMC_BASE + 0x0070)
 175         uint32_t PMC_FSMR;
 176 #define SAM3_PMC_FSPR             (SAM3_PMC_BASE + 0x0074)
 177         uint32_t PMC_FSPR;
 178 };
 179
 180 /*
 181  * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
 182  * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
 183  * the flash wait state (FWS) should be set to 6. It seems like that the
 184  * cause of the problem is not the flash itself, but the flash write
 185  * buffer. Ie the wait states have to be set before writing into the
 186  * buffer.
 187  * Tested and confirmed with SAM3N and SAM3U
 188  */
 189
 190 struct sam3_bank_private {
 191         int probed;
 192         /* DANGER: THERE ARE DRAGONS HERE.. */
 193         /* NOTE: If you add more 'ghost' pointers */
 194         /* be aware that you must *manually* update */
 195         /* these pointers in the function sam3_GetDetails() */
 196         /* See the comment "Here there be dragons" */
 197
 198         /* so we can find the chip we belong to */
 199         struct sam3_chip *pChip;
 200         /* so we can find the orginal bank pointer */
 201         struct flash_bank *pBank;
 202         unsigned bank_number;
 203         uint32_t controller_address;
 204         uint32_t base_address;
 205         uint32_t flash_wait_states;
 206         bool present;
 207         unsigned size_bytes;
 208         unsigned nsectors;
 209         unsigned sector_size;
 210         unsigned page_size;
 211 };
 212
 213 struct sam3_chip_details {
 214         /* THERE ARE DRAGONS HERE.. */
 215         /* note: If you add pointers here */
 216         /* becareful about them as they */
 217         /* may need to be updated inside */
 218         /* the function: "sam3_GetDetails() */
 219         /* which copy/overwrites the */
 220         /* 'runtime' copy of this structure */
 221         uint32_t chipid_cidr;
 222         const char *name;
 223
 224         unsigned n_gpnvms;
 225 #define SAM3_N_NVM_BITS 3
 226         unsigned gpnvm[SAM3_N_NVM_BITS];
 227         unsigned total_flash_size;
 228         unsigned total_sram_size;
 229         unsigned n_banks;
 230 #define SAM3_MAX_FLASH_BANKS 2
 231         /* these are "initialized" from the global const data */
 232         struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
 233 };
 234
 235 struct sam3_chip {
 236         struct sam3_chip *next;
 237         int probed;
 238
 239         /* this is "initialized" from the global const structure */
 240         struct sam3_chip_details details;
 241         struct target *target;
 242         struct sam3_cfg cfg;
 243 };
 244
 245
 246 struct sam3_reg_list {
 247         uint32_t address;  size_t struct_offset; const char *name;
 248         void (*explain_func)(struct sam3_chip *pInfo);
 249 };
 250
 251 static struct sam3_chip *all_sam3_chips;
 252
 253 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
 254 {
 255         struct target *t;
 256         static struct sam3_chip *p;
 257
 258         t = get_current_target(cmd_ctx);
 259         if (!t) {
 260                 command_print(cmd_ctx, "No current target?");
 261                 return NULL;
 262         }
 263
 264         p = all_sam3_chips;
 265         if (!p) {
 266                 /* this should not happen */
 267                 /* the command is not registered until the chip is created? */
 268                 command_print(cmd_ctx, "No SAM3 chips exist?");
 269                 return NULL;
 270         }
 271
 272         while (p) {
 273                 if (p->target == t)
 274                         return p;
 275                 p = p->next;
 276         }
 277         command_print(cmd_ctx, "Cannot find SAM3 chip?");
 278         return NULL;
 279 }
 280
 281 /* these are used to *initialize* the "pChip->details" structure. */
 282 static const struct sam3_chip_details all_sam3_details[] = {
 283         /* Start at91sam3u* series */
 284         {
 285                 .chipid_cidr    = 0x28100960,
 286                 .name           = "at91sam3u4e",
 287                 .total_flash_size     = 256 * 1024,
 288                 .total_sram_size      = 52 * 1024,
 289                 .n_gpnvms       = 3,
 290                 .n_banks        = 2,
 291
 292                 /* System boots at address 0x0 */
 293                 /* gpnvm[1] = selects boot code */
 294                 /*     if gpnvm[1] == 0 */
 295                 /*         boot is via "SAMBA" (rom) */
 296                 /*     else */
 297                 /*         boot is via FLASH */
 298                 /*         Selection is via gpnvm[2] */
 299                 /*     endif */
 300                 /*  */
 301                 /* NOTE: banks 0 & 1 switch places */
 302                 /*     if gpnvm[2] == 0 */
 303                 /*         Bank0 is the boot rom */
 304                 /*      else */
 305                 /*         Bank1 is the boot rom */
 306                 /*      endif */
 307 /*              .bank[0] = { */
 308                 {
 309                         {
 310                                 .probed = 0,
 311                                 .pChip  = NULL,
 312                                 .pBank  = NULL,
 313                                 .bank_number = 0,
 314                                 .base_address = FLASH_BANK0_BASE_U,
 315                                 .controller_address = 0x400e0800,
 316                                 .flash_wait_states = 6, /* workaround silicon bug */
 317                                 .present = 1,
 318                                 .size_bytes = 128 * 1024,
 319                                 .nsectors   = 16,
 320                                 .sector_size = 8192,
 321                                 .page_size   = 256,
 322                         },
 323
 324 /*              .bank[1] = { */
 325                         {
 326                                 .probed = 0,
 327                                 .pChip  = NULL,
 328                                 .pBank  = NULL,
 329                                 .bank_number = 1,
 330                                 .base_address = FLASH_BANK1_BASE_U,
 331                                 .controller_address = 0x400e0a00,
 332                                 .flash_wait_states = 6, /* workaround silicon bug */
 333                                 .present = 1,
 334                                 .size_bytes = 128 * 1024,
 335                                 .nsectors   = 16,
 336                                 .sector_size = 8192,
 337                                 .page_size   = 256,
 338                         },
 339                 },
 340         },
 341
 342         {
 343                 .chipid_cidr    = 0x281a0760,
 344                 .name           = "at91sam3u2e",
 345                 .total_flash_size     = 128 * 1024,
 346                 .total_sram_size      = 36 * 1024,
 347                 .n_gpnvms       = 2,
 348                 .n_banks        = 1,
 349
 350                 /* System boots at address 0x0 */
 351                 /* gpnvm[1] = selects boot code */
 352                 /*     if gpnvm[1] == 0 */
 353                 /*         boot is via "SAMBA" (rom) */
 354                 /*     else */
 355                 /*         boot is via FLASH */
 356                 /*         Selection is via gpnvm[2] */
 357                 /*     endif */
 358 /*              .bank[0] = { */
 359                 {
 360                         {
 361                                 .probed = 0,
 362                                 .pChip  = NULL,
 363                                 .pBank  = NULL,
 364                                 .bank_number = 0,
 365                                 .base_address = FLASH_BANK0_BASE_U,
 366                                 .controller_address = 0x400e0800,
 367                                 .flash_wait_states = 6, /* workaround silicon bug */
 368                                 .present = 1,
 369                                 .size_bytes = 128 * 1024,
 370                                 .nsectors   = 16,
 371                                 .sector_size = 8192,
 372                                 .page_size   = 256,
 373                         },
 374 /*                .bank[1] = { */
 375                         {
 376                                 .present = 0,
 377                                 .probed = 0,
 378                                 .bank_number = 1,
 379                         },
 380                 },
 381         },
 382         {
 383                 .chipid_cidr    = 0x28190560,
 384                 .name           = "at91sam3u1e",
 385                 .total_flash_size     = 64 * 1024,
 386                 .total_sram_size      = 20 * 1024,
 387                 .n_gpnvms       = 2,
 388                 .n_banks        = 1,
 389
 390                 /* System boots at address 0x0 */
 391                 /* gpnvm[1] = selects boot code */
 392                 /*     if gpnvm[1] == 0 */
 393                 /*         boot is via "SAMBA" (rom) */
 394                 /*     else */
 395                 /*         boot is via FLASH */
 396                 /*         Selection is via gpnvm[2] */
 397                 /*     endif */
 398                 /*  */
 399
 400 /*              .bank[0] = { */
 401                 {
 402                         {
 403                                 .probed = 0,
 404                                 .pChip  = NULL,
 405                                 .pBank  = NULL,
 406                                 .bank_number = 0,
 407                                 .base_address = FLASH_BANK0_BASE_U,
 408                                 .controller_address = 0x400e0800,
 409                                 .flash_wait_states = 6, /* workaround silicon bug */
 410                                 .present = 1,
 411                                 .size_bytes = 64 * 1024,
 412                                 .nsectors   = 8,
 413                                 .sector_size = 8192,
 414                                 .page_size   = 256,
 415                         },
 416
 417 /*              .bank[1] = { */
 418                         {
 419                                 .present = 0,
 420                                 .probed = 0,
 421                                 .bank_number = 1,
 422                         },
 423                 },
 424         },
 425
 426         {
 427                 .chipid_cidr    = 0x28000960,
 428                 .name           = "at91sam3u4c",
 429                 .total_flash_size     = 256 * 1024,
 430                 .total_sram_size      = 52 * 1024,
 431                 .n_gpnvms       = 3,
 432                 .n_banks        = 2,
 433
 434                 /* System boots at address 0x0 */
 435                 /* gpnvm[1] = selects boot code */
 436                 /*     if gpnvm[1] == 0 */
 437                 /*         boot is via "SAMBA" (rom) */
 438                 /*     else */
 439                 /*         boot is via FLASH */
 440                 /*         Selection is via gpnvm[2] */
 441                 /*     endif */
 442                 /*  */
 443                 /* NOTE: banks 0 & 1 switch places */
 444                 /*     if gpnvm[2] == 0 */
 445                 /*         Bank0 is the boot rom */
 446                 /*      else */
 447                 /*         Bank1 is the boot rom */
 448                 /*      endif */
 449                 {
 450                         {
 451 /*              .bank[0] = { */
 452                                 .probed = 0,
 453                                 .pChip  = NULL,
 454                                 .pBank  = NULL,
 455                                 .bank_number = 0,
 456                                 .base_address = FLASH_BANK0_BASE_U,
 457                                 .controller_address = 0x400e0800,
 458                                 .flash_wait_states = 6, /* workaround silicon bug */
 459                                 .present = 1,
 460                                 .size_bytes = 128 * 1024,
 461                                 .nsectors   = 16,
 462                                 .sector_size = 8192,
 463                                 .page_size   = 256,
 464                         },
 465 /*              .bank[1] = { */
 466                         {
 467                                 .probed = 0,
 468                                 .pChip  = NULL,
 469                                 .pBank  = NULL,
 470                                 .bank_number = 1,
 471                                 .base_address = FLASH_BANK1_BASE_U,
 472                                 .controller_address = 0x400e0a00,
 473                                 .flash_wait_states = 6, /* workaround silicon bug */
 474                                 .present = 1,
 475                                 .size_bytes = 128 * 1024,
 476                                 .nsectors   = 16,
 477                                 .sector_size = 8192,
 478                                 .page_size   = 256,
 479                         },
 480                 },
 481         },
 482
 483         {
 484                 .chipid_cidr    = 0x280a0760,
 485                 .name           = "at91sam3u2c",
 486                 .total_flash_size     = 128 * 1024,
 487                 .total_sram_size      = 36 * 1024,
 488                 .n_gpnvms       = 2,
 489                 .n_banks        = 1,
 490
 491                 /* System boots at address 0x0 */
 492                 /* gpnvm[1] = selects boot code */
 493                 /*     if gpnvm[1] == 0 */
 494                 /*         boot is via "SAMBA" (rom) */
 495                 /*     else */
 496                 /*         boot is via FLASH */
 497                 /*         Selection is via gpnvm[2] */
 498                 /*     endif */
 499                 {
 500 /*              .bank[0] = { */
 501                         {
 502                                 .probed = 0,
 503                                 .pChip  = NULL,
 504                                 .pBank  = NULL,
 505                                 .bank_number = 0,
 506                                 .base_address = FLASH_BANK0_BASE_U,
 507                                 .controller_address = 0x400e0800,
 508                                 .flash_wait_states = 6, /* workaround silicon bug */
 509                                 .present = 1,
 510                                 .size_bytes = 128 * 1024,
 511                                 .nsectors   = 16,
 512                                 .sector_size = 8192,
 513                                 .page_size   = 256,
 514                         },
 515 /*              .bank[1] = { */
 516                         {
 517                                 .present = 0,
 518                                 .probed = 0,
 519                                 .bank_number = 1,
 520                         },
 521                 },
 522         },
 523         {
 524                 .chipid_cidr    = 0x28090560,
 525                 .name           = "at91sam3u1c",
 526                 .total_flash_size     = 64 * 1024,
 527                 .total_sram_size      = 20 * 1024,
 528                 .n_gpnvms       = 2,
 529                 .n_banks        = 1,
 530
 531                 /* System boots at address 0x0 */
 532                 /* gpnvm[1] = selects boot code */
 533                 /*     if gpnvm[1] == 0 */
 534                 /*         boot is via "SAMBA" (rom) */
 535                 /*     else */
 536                 /*         boot is via FLASH */
 537                 /*         Selection is via gpnvm[2] */
 538                 /*     endif */
 539                 /*  */
 540
 541                 {
 542 /*              .bank[0] = { */
 543                         {
 544                                 .probed = 0,
 545                                 .pChip  = NULL,
 546                                 .pBank  = NULL,
 547                                 .bank_number = 0,
 548                                 .base_address = FLASH_BANK0_BASE_U,
 549                                 .controller_address = 0x400e0800,
 550                                 .flash_wait_states = 6, /* workaround silicon bug */
 551                                 .present = 1,
 552                                 .size_bytes = 64 * 1024,
 553                                 .nsectors   = 8,
 554                                 .sector_size = 8192,
 555                                 .page_size   = 256,
 556                         },
 557 /*              .bank[1] = { */
 558                         {
 559                                 .present = 0,
 560                                 .probed = 0,
 561                                 .bank_number = 1,
 562
 563                         },
 564                 },
 565         },
 566
 567         /* Start at91sam3s* series */
 568
 569         /* Note: The preliminary at91sam3s datasheet says on page 302 */
 570         /* that the flash controller is at address 0x400E0800. */
 571         /* This is _not_ the case, the controller resides at address 0x400e0a0. */
 572         {
 573                 .chipid_cidr    = 0x28A00960,
 574                 .name           = "at91sam3s4c",
 575                 .total_flash_size     = 256 * 1024,
 576                 .total_sram_size      = 48 * 1024,
 577                 .n_gpnvms       = 2,
 578                 .n_banks        = 1,
 579                 {
 580 /*              .bank[0] = { */
 581                         {
 582                                 .probed = 0,
 583                                 .pChip  = NULL,
 584                                 .pBank  = NULL,
 585                                 .bank_number = 0,
 586                                 .base_address = FLASH_BANK_BASE_S,
 587                                 .controller_address = 0x400e0a00,
 588                                 .flash_wait_states = 6, /* workaround silicon bug */
 589                                 .present = 1,
 590                                 .size_bytes = 256 * 1024,
 591                                 .nsectors   = 16,
 592                                 .sector_size = 16384,
 593                                 .page_size   = 256,
 594                         },
 595 /*              .bank[1] = { */
 596                         {
 597                                 .present = 0,
 598                                 .probed = 0,
 599                                 .bank_number = 1,
 600
 601                         },
 602                 },
 603         },
 604
 605         {
 606                 .chipid_cidr    = 0x28900960,
 607                 .name           = "at91sam3s4b",
 608                 .total_flash_size     = 256 * 1024,
 609                 .total_sram_size      = 48 * 1024,
 610                 .n_gpnvms       = 2,
 611                 .n_banks        = 1,
 612                 {
 613 /*              .bank[0] = { */
 614                         {
 615                                 .probed = 0,
 616                                 .pChip  = NULL,
 617                                 .pBank  = NULL,
 618                                 .bank_number = 0,
 619                                 .base_address = FLASH_BANK_BASE_S,
 620                                 .controller_address = 0x400e0a00,
 621                                 .flash_wait_states = 6, /* workaround silicon bug */
 622                                 .present = 1,
 623                                 .size_bytes = 256 * 1024,
 624                                 .nsectors   = 16,
 625                                 .sector_size = 16384,
 626                                 .page_size   = 256,
 627                         },
 628 /*              .bank[1] = { */
 629                         {
 630                                 .present = 0,
 631                                 .probed = 0,
 632                                 .bank_number = 1,
 633
 634                         },
 635                 },
 636         },
 637         {
 638                 .chipid_cidr    = 0x28800960,
 639                 .name           = "at91sam3s4a",
 640                 .total_flash_size     = 256 * 1024,
 641                 .total_sram_size      = 48 * 1024,
 642                 .n_gpnvms       = 2,
 643                 .n_banks        = 1,
 644                 {
 645 /*              .bank[0] = { */
 646                         {
 647                                 .probed = 0,
 648                                 .pChip  = NULL,
 649                                 .pBank  = NULL,
 650                                 .bank_number = 0,
 651                                 .base_address = FLASH_BANK_BASE_S,
 652                                 .controller_address = 0x400e0a00,
 653                                 .flash_wait_states = 6, /* workaround silicon bug */
 654                                 .present = 1,
 655                                 .size_bytes = 256 * 1024,
 656                                 .nsectors   = 16,
 657                                 .sector_size = 16384,
 658                                 .page_size   = 256,
 659                         },
 660 /*              .bank[1] = { */
 661                         {
 662                                 .present = 0,
 663                                 .probed = 0,
 664                                 .bank_number = 1,
 665
 666                         },
 667                 },
 668         },
 669         {
 670                 .chipid_cidr    = 0x28AA0760,
 671                 .name           = "at91sam3s2c",
 672                 .total_flash_size     = 128 * 1024,
 673                 .total_sram_size      = 32 * 1024,
 674                 .n_gpnvms       = 2,
 675                 .n_banks        = 1,
 676                 {
 677 /*              .bank[0] = { */
 678                         {
 679                                 .probed = 0,
 680                                 .pChip  = NULL,
 681                                 .pBank  = NULL,
 682                                 .bank_number = 0,
 683                                 .base_address = FLASH_BANK_BASE_S,
 684                                 .controller_address = 0x400e0a00,
 685                                 .flash_wait_states = 6, /* workaround silicon bug */
 686                                 .present = 1,
 687                                 .size_bytes = 128 * 1024,
 688                                 .nsectors   = 8,
 689                                 .sector_size = 16384,
 690                                 .page_size   = 256,
 691                         },
 692 /*              .bank[1] = { */
 693                         {
 694                                 .present = 0,
 695                                 .probed = 0,
 696                                 .bank_number = 1,
 697
 698                         },
 699                 },
 700         },
 701         {
 702                 .chipid_cidr    = 0x289A0760,
 703                 .name           = "at91sam3s2b",
 704                 .total_flash_size     = 128 * 1024,
 705                 .total_sram_size      = 32 * 1024,
 706                 .n_gpnvms       = 2,
 707                 .n_banks        = 1,
 708                 {
 709 /*              .bank[0] = { */
 710                         {
 711                                 .probed = 0,
 712                                 .pChip  = NULL,
 713                                 .pBank  = NULL,
 714                                 .bank_number = 0,
 715                                 .base_address = FLASH_BANK_BASE_S,
 716                                 .controller_address = 0x400e0a00,
 717                                 .flash_wait_states = 6, /* workaround silicon bug */
 718                                 .present = 1,
 719                                 .size_bytes = 128 * 1024,
 720                                 .nsectors   = 8,
 721                                 .sector_size = 16384,
 722                                 .page_size   = 256,
 723                         },
 724 /*              .bank[1] = { */
 725                         {
 726                                 .present = 0,
 727                                 .probed = 0,
 728                                 .bank_number = 1,
 729
 730                         },
 731                 },
 732         },
 733         {
 734                 .chipid_cidr    = 0x29ab0a60,
 735                 .name           = "at91sam3sd8c",
 736                 .total_flash_size     = 512 * 1024,
 737                 .total_sram_size      = 64 * 1024,
 738                 .n_gpnvms       = 3,
 739                 .n_banks        = 2,
 740                 {
 741 /*                      .bank[0] = { */
 742                         {
 743                                 .probed = 0,
 744                                 .pChip  = NULL,
 745                                 .pBank  = NULL,
 746                                 .bank_number = 0,
 747                                 .base_address = FLASH_BANK0_BASE_SD,
 748                                 .controller_address = 0x400e0a00,
 749                                 .flash_wait_states = 6, /* workaround silicon bug */
 750                                 .present = 1,
 751                                 .size_bytes =  256 * 1024,
 752                                 .nsectors   =  16,
 753                                 .sector_size = 16384,
 754                                 .page_size   = 256,
 755                           },
 756 /*                      .bank[1] = { */
 757                           {
 758                                 .probed = 0,
 759                                 .pChip  = NULL,
 760                                 .pBank  = NULL,
 761                                 .bank_number = 1,
 762                                 .base_address = FLASH_BANK1_BASE_512K_SD,
 763                                 .controller_address = 0x400e0a00,
 764                                 .flash_wait_states = 6, /* workaround silicon bug */
 765                                 .present = 1,
 766                                 .size_bytes =  256 * 1024,
 767                                 .nsectors   =  16,
 768                                 .sector_size = 16384,
 769                                 .page_size   = 256,
 770                         },
 771                 },
 772         },
 773         {
 774                 .chipid_cidr    = 0x288A0760,
 775                 .name           = "at91sam3s2a",
 776                 .total_flash_size     = 128 * 1024,
 777                 .total_sram_size      = 32 * 1024,
 778                 .n_gpnvms       = 2,
 779                 .n_banks        = 1,
 780                 {
 781 /*              .bank[0] = { */
 782                         {
 783                                 .probed = 0,
 784                                 .pChip  = NULL,
 785                                 .pBank  = NULL,
 786                                 .bank_number = 0,
 787                                 .base_address = FLASH_BANK_BASE_S,
 788                                 .controller_address = 0x400e0a00,
 789                                 .flash_wait_states = 6, /* workaround silicon bug */
 790                                 .present = 1,
 791                                 .size_bytes = 128 * 1024,
 792                                 .nsectors   = 8,
 793                                 .sector_size = 16384,
 794                                 .page_size   = 256,
 795                         },
 796 /*              .bank[1] = { */
 797                         {
 798                                 .present = 0,
 799                                 .probed = 0,
 800                                 .bank_number = 1,
 801
 802                         },
 803                 },
 804         },
 805         {
 806                 .chipid_cidr    = 0x28A90560,
 807                 .name           = "at91sam3s1c",
 808                 .total_flash_size     = 64 * 1024,
 809                 .total_sram_size      = 16 * 1024,
 810                 .n_gpnvms       = 2,
 811                 .n_banks        = 1,
 812                 {
 813 /*              .bank[0] = { */
 814                         {
 815                                 .probed = 0,
 816                                 .pChip  = NULL,
 817                                 .pBank  = NULL,
 818                                 .bank_number = 0,
 819                                 .base_address = FLASH_BANK_BASE_S,
 820                                 .controller_address = 0x400e0a00,
 821                                 .flash_wait_states = 6, /* workaround silicon bug */
 822                                 .present = 1,
 823                                 .size_bytes = 64 * 1024,
 824                                 .nsectors   = 4,
 825                                 .sector_size = 16384,
 826                                 .page_size   = 256,
 827                         },
 828 /*              .bank[1] = { */
 829                         {
 830                                 .present = 0,
 831                                 .probed = 0,
 832                                 .bank_number = 1,
 833
 834                         },
 835                 },
 836         },
 837         {
 838                 .chipid_cidr    = 0x28990560,
 839                 .name           = "at91sam3s1b",
 840                 .total_flash_size     = 64 * 1024,
 841                 .total_sram_size      = 16 * 1024,
 842                 .n_gpnvms       = 2,
 843                 .n_banks        = 1,
 844                 {
 845 /*              .bank[0] = { */
 846                         {
 847                                 .probed = 0,
 848                                 .pChip  = NULL,
 849                                 .pBank  = NULL,
 850                                 .bank_number = 0,
 851                                 .base_address = FLASH_BANK_BASE_S,
 852                                 .controller_address = 0x400e0a00,
 853                                 .flash_wait_states = 6, /* workaround silicon bug */
 854                                 .present = 1,
 855                                 .size_bytes = 64 * 1024,
 856                                 .nsectors   = 4,
 857                                 .sector_size = 16384,
 858                                 .page_size   = 256,
 859                         },
 860 /*              .bank[1] = { */
 861                         {
 862                                 .present = 0,
 863                                 .probed = 0,
 864                                 .bank_number = 1,
 865
 866                         },
 867                 },
 868         },
 869         {
 870                 .chipid_cidr    = 0x28890560,
 871                 .name           = "at91sam3s1a",
 872                 .total_flash_size     = 64 * 1024,
 873                 .total_sram_size      = 16 * 1024,
 874                 .n_gpnvms       = 2,
 875                 .n_banks        = 1,
 876                 {
 877 /*              .bank[0] = { */
 878                         {
 879                                 .probed = 0,
 880                                 .pChip  = NULL,
 881                                 .pBank  = NULL,
 882                                 .bank_number = 0,
 883                                 .base_address = FLASH_BANK_BASE_S,
 884                                 .controller_address = 0x400e0a00,
 885                                 .flash_wait_states = 6, /* workaround silicon bug */
 886                                 .present = 1,
 887                                 .size_bytes = 64 * 1024,
 888                                 .nsectors   = 4,
 889                                 .sector_size = 16384,
 890                                 .page_size   = 256,
 891                         },
 892 /*              .bank[1] = { */
 893                         {
 894                                 .present = 0,
 895                                 .probed = 0,
 896                                 .bank_number = 1,
 897
 898                         },
 899                 },
 900         },
 901
 902         /* Start at91sam3n* series */
 903         {
 904                 .chipid_cidr    = 0x29540960,
 905                 .name           = "at91sam3n4c",
 906                 .total_flash_size     = 256 * 1024,
 907                 .total_sram_size      = 24 * 1024,
 908                 .n_gpnvms       = 3,
 909                 .n_banks        = 1,
 910
 911                 /* System boots at address 0x0 */
 912                 /* gpnvm[1] = selects boot code */
 913                 /*     if gpnvm[1] == 0 */
 914                 /*         boot is via "SAMBA" (rom) */
 915                 /*     else */
 916                 /*         boot is via FLASH */
 917                 /*         Selection is via gpnvm[2] */
 918                 /*     endif */
 919                 /*  */
 920                 /* NOTE: banks 0 & 1 switch places */
 921                 /*     if gpnvm[2] == 0 */
 922                 /*         Bank0 is the boot rom */
 923                 /*      else */
 924                 /*         Bank1 is the boot rom */
 925                 /*      endif */
 926 /*              .bank[0] = { */
 927                 {
 928                         {
 929                                 .probed = 0,
 930                                 .pChip  = NULL,
 931                                 .pBank  = NULL,
 932                                 .bank_number = 0,
 933                                 .base_address = FLASH_BANK_BASE_N,
 934                                 .controller_address = 0x400e0A00,
 935                                 .flash_wait_states = 6, /* workaround silicon bug */
 936                                 .present = 1,
 937                                 .size_bytes = 256 * 1024,
 938                                 .nsectors   = 16,
 939                                 .sector_size = 16384,
 940                                 .page_size   = 256,
 941                         },
 942
 943 /*              .bank[1] = { */
 944                         {
 945                                 .present = 0,
 946                                 .probed = 0,
 947                                 .bank_number = 1,
 948                         },
 949                 },
 950         },
 951
 952         {
 953                 .chipid_cidr    = 0x29440960,
 954                 .name           = "at91sam3n4b",
 955                 .total_flash_size     = 256 * 1024,
 956                 .total_sram_size      = 24 * 1024,
 957                 .n_gpnvms       = 3,
 958                 .n_banks        = 1,
 959
 960                 /* System boots at address 0x0 */
 961                 /* gpnvm[1] = selects boot code */
 962                 /*     if gpnvm[1] == 0 */
 963                 /*         boot is via "SAMBA" (rom) */
 964                 /*     else */
 965                 /*         boot is via FLASH */
 966                 /*         Selection is via gpnvm[2] */
 967                 /*     endif */
 968                 /*  */
 969                 /* NOTE: banks 0 & 1 switch places */
 970                 /*     if gpnvm[2] == 0 */
 971                 /*         Bank0 is the boot rom */
 972                 /*      else */
 973                 /*         Bank1 is the boot rom */
 974                 /*      endif */
 975 /*              .bank[0] = { */
 976                 {
 977                         {
 978                                 .probed = 0,
 979                                 .pChip  = NULL,
 980                                 .pBank  = NULL,
 981                                 .bank_number = 0,
 982                                 .base_address = FLASH_BANK_BASE_N,
 983                                 .controller_address = 0x400e0A00,
 984                                 .flash_wait_states = 6, /* workaround silicon bug */
 985                                 .present = 1,
 986                                 .size_bytes = 256 * 1024,
 987                                 .nsectors   = 16,
 988                                 .sector_size = 16384,
 989                                 .page_size   = 256,
 990                         },
 991
 992 /*              .bank[1] = { */
 993                         {
 994                                 .present = 0,
 995                                 .probed = 0,
 996                                 .bank_number = 1,
 997                         },
 998                 },
 999         },
1000
1001         {
1002                 .chipid_cidr    = 0x29340960,
1003                 .name           = "at91sam3n4a",
1004                 .total_flash_size     = 256 * 1024,
1005                 .total_sram_size      = 24 * 1024,
1006                 .n_gpnvms       = 3,
1007                 .n_banks        = 1,
1008
1009                 /* System boots at address 0x0 */
1010                 /* gpnvm[1] = selects boot code */
1011                 /*     if gpnvm[1] == 0 */
1012                 /*         boot is via "SAMBA" (rom) */
1013                 /*     else */
1014                 /*         boot is via FLASH */
1015                 /*         Selection is via gpnvm[2] */
1016                 /*     endif */
1017                 /*  */
1018                 /* NOTE: banks 0 & 1 switch places */
1019                 /*     if gpnvm[2] == 0 */
1020                 /*         Bank0 is the boot rom */
1021                 /*      else */
1022                 /*         Bank1 is the boot rom */
1023                 /*      endif */
1024 /*              .bank[0] = { */
1025                 {
1026                         {
1027                                 .probed = 0,
1028                                 .pChip  = NULL,
1029                                 .pBank  = NULL,
1030                                 .bank_number = 0,
1031                                 .base_address = FLASH_BANK_BASE_N,
1032                                 .controller_address = 0x400e0A00,
1033                                 .flash_wait_states = 6, /* workaround silicon bug */
1034                                 .present = 1,
1035                                 .size_bytes = 256 * 1024,
1036                                 .nsectors   = 16,
1037                                 .sector_size = 16384,
1038                                 .page_size   = 256,
1039                         },
1040
1041 /*              .bank[1] = { */
1042                         {
1043                                 .present = 0,
1044                                 .probed = 0,
1045                                 .bank_number = 1,
1046                         },
1047                 },
1048         },
1049
1050         {
1051                 .chipid_cidr    = 0x29590760,
1052                 .name           = "at91sam3n2c",
1053                 .total_flash_size     = 128 * 1024,
1054                 .total_sram_size      = 16 * 1024,
1055                 .n_gpnvms       = 3,
1056                 .n_banks        = 1,
1057
1058                 /* System boots at address 0x0 */
1059                 /* gpnvm[1] = selects boot code */
1060                 /*     if gpnvm[1] == 0 */
1061                 /*         boot is via "SAMBA" (rom) */
1062                 /*     else */
1063                 /*         boot is via FLASH */
1064                 /*         Selection is via gpnvm[2] */
1065                 /*     endif */
1066                 /*  */
1067                 /* NOTE: banks 0 & 1 switch places */
1068                 /*     if gpnvm[2] == 0 */
1069                 /*         Bank0 is the boot rom */
1070                 /*      else */
1071                 /*         Bank1 is the boot rom */
1072                 /*      endif */
1073 /*              .bank[0] = { */
1074                 {
1075                         {
1076                                 .probed = 0,
1077                                 .pChip  = NULL,
1078                                 .pBank  = NULL,
1079                                 .bank_number = 0,
1080                                 .base_address = FLASH_BANK_BASE_N,
1081                                 .controller_address = 0x400e0A00,
1082                                 .flash_wait_states = 6, /* workaround silicon bug */
1083                                 .present = 1,
1084                                 .size_bytes = 128 * 1024,
1085                                 .nsectors   = 8,
1086                                 .sector_size = 16384,
1087                                 .page_size   = 256,
1088                         },
1089
1090 /*              .bank[1] = { */
1091                         {
1092                                 .present = 0,
1093                                 .probed = 0,
1094                                 .bank_number = 1,
1095                         },
1096                 },
1097         },
1098
1099         {
1100                 .chipid_cidr    = 0x29490760,
1101                 .name           = "at91sam3n2b",
1102                 .total_flash_size     = 128 * 1024,
1103                 .total_sram_size      = 16 * 1024,
1104                 .n_gpnvms       = 3,
1105                 .n_banks        = 1,
1106
1107                 /* System boots at address 0x0 */
1108                 /* gpnvm[1] = selects boot code */
1109                 /*     if gpnvm[1] == 0 */
1110                 /*         boot is via "SAMBA" (rom) */
1111                 /*     else */
1112                 /*         boot is via FLASH */
1113                 /*         Selection is via gpnvm[2] */
1114                 /*     endif */
1115                 /*  */
1116                 /* NOTE: banks 0 & 1 switch places */
1117                 /*     if gpnvm[2] == 0 */
1118                 /*         Bank0 is the boot rom */
1119                 /*      else */
1120                 /*         Bank1 is the boot rom */
1121                 /*      endif */
1122 /*              .bank[0] = { */
1123                 {
1124                         {
1125                                 .probed = 0,
1126                                 .pChip  = NULL,
1127                                 .pBank  = NULL,
1128                                 .bank_number = 0,
1129                                 .base_address = FLASH_BANK_BASE_N,
1130                                 .controller_address = 0x400e0A00,
1131                                 .flash_wait_states = 6, /* workaround silicon bug */
1132                                 .present = 1,
1133                                 .size_bytes = 128 * 1024,
1134                                 .nsectors   = 8,
1135                                 .sector_size = 16384,
1136                                 .page_size   = 256,
1137                         },
1138
1139 /*              .bank[1] = { */
1140                         {
1141                                 .present = 0,
1142                                 .probed = 0,
1143                                 .bank_number = 1,
1144                         },
1145                 },
1146         },
1147
1148         {
1149                 .chipid_cidr    = 0x29390760,
1150                 .name           = "at91sam3n2a",
1151                 .total_flash_size     = 128 * 1024,
1152                 .total_sram_size      = 16 * 1024,
1153                 .n_gpnvms       = 3,
1154                 .n_banks        = 1,
1155
1156                 /* System boots at address 0x0 */
1157                 /* gpnvm[1] = selects boot code */
1158                 /*     if gpnvm[1] == 0 */
1159                 /*         boot is via "SAMBA" (rom) */
1160                 /*     else */
1161                 /*         boot is via FLASH */
1162                 /*         Selection is via gpnvm[2] */
1163                 /*     endif */
1164                 /*  */
1165                 /* NOTE: banks 0 & 1 switch places */
1166                 /*     if gpnvm[2] == 0 */
1167                 /*         Bank0 is the boot rom */
1168                 /*      else */
1169                 /*         Bank1 is the boot rom */
1170                 /*      endif */
1171 /*              .bank[0] = { */
1172                 {
1173                         {
1174                                 .probed = 0,
1175                                 .pChip  = NULL,
1176                                 .pBank  = NULL,
1177                                 .bank_number = 0,
1178                                 .base_address = FLASH_BANK_BASE_N,
1179                                 .controller_address = 0x400e0A00,
1180                                 .flash_wait_states = 6, /* workaround silicon bug */
1181                                 .present = 1,
1182                                 .size_bytes = 128 * 1024,
1183                                 .nsectors   = 8,
1184                                 .sector_size = 16384,
1185                                 .page_size   = 256,
1186                         },
1187
1188 /*              .bank[1] = { */
1189                         {
1190                                 .present = 0,
1191                                 .probed = 0,
1192                                 .bank_number = 1,
1193                         },
1194                 },
1195         },
1196
1197         {
1198                 .chipid_cidr    = 0x29580560,
1199                 .name           = "at91sam3n1c",
1200                 .total_flash_size     = 64 * 1024,
1201                 .total_sram_size      = 8 * 1024,
1202                 .n_gpnvms       = 3,
1203                 .n_banks        = 1,
1204
1205                 /* System boots at address 0x0 */
1206                 /* gpnvm[1] = selects boot code */
1207                 /*     if gpnvm[1] == 0 */
1208                 /*         boot is via "SAMBA" (rom) */
1209                 /*     else */
1210                 /*         boot is via FLASH */
1211                 /*         Selection is via gpnvm[2] */
1212                 /*     endif */
1213                 /*  */
1214                 /* NOTE: banks 0 & 1 switch places */
1215                 /*     if gpnvm[2] == 0 */
1216                 /*         Bank0 is the boot rom */
1217                 /*      else */
1218                 /*         Bank1 is the boot rom */
1219                 /*      endif */
1220 /*              .bank[0] = { */
1221                 {
1222                         {
1223                                 .probed = 0,
1224                                 .pChip  = NULL,
1225                                 .pBank  = NULL,
1226                                 .bank_number = 0,
1227                                 .base_address = FLASH_BANK_BASE_N,
1228                                 .controller_address = 0x400e0A00,
1229                                 .flash_wait_states = 6, /* workaround silicon bug */
1230                                 .present = 1,
1231                                 .size_bytes = 64 * 1024,
1232                                 .nsectors   = 4,
1233                                 .sector_size = 16384,
1234                                 .page_size   = 256,
1235                         },
1236
1237 /*              .bank[1] = { */
1238                         {
1239                                 .present = 0,
1240                                 .probed = 0,
1241                                 .bank_number = 1,
1242                         },
1243                 },
1244         },
1245
1246         {
1247                 .chipid_cidr    = 0x29480560,
1248                 .name           = "at91sam3n1b",
1249                 .total_flash_size     = 64 * 1024,
1250                 .total_sram_size      = 8 * 1024,
1251                 .n_gpnvms       = 3,
1252                 .n_banks        = 1,
1253
1254                 /* System boots at address 0x0 */
1255                 /* gpnvm[1] = selects boot code */
1256                 /*     if gpnvm[1] == 0 */
1257                 /*         boot is via "SAMBA" (rom) */
1258                 /*     else */
1259                 /*         boot is via FLASH */
1260                 /*         Selection is via gpnvm[2] */
1261                 /*     endif */
1262                 /*  */
1263                 /* NOTE: banks 0 & 1 switch places */
1264                 /*     if gpnvm[2] == 0 */
1265                 /*         Bank0 is the boot rom */
1266                 /*      else */
1267                 /*         Bank1 is the boot rom */
1268                 /*      endif */
1269 /*              .bank[0] = { */
1270                 {
1271                         {
1272                                 .probed = 0,
1273                                 .pChip  = NULL,
1274                                 .pBank  = NULL,
1275                                 .bank_number = 0,
1276                                 .base_address = FLASH_BANK_BASE_N,
1277                                 .controller_address = 0x400e0A00,
1278                                 .flash_wait_states = 6, /* workaround silicon bug */
1279                                 .present = 1,
1280                                 .size_bytes = 64 * 1024,
1281                                 .nsectors   = 4,
1282                                 .sector_size = 16384,
1283                                 .page_size   = 256,
1284                         },
1285
1286 /*              .bank[1] = { */
1287                         {
1288                                 .present = 0,
1289                                 .probed = 0,
1290                                 .bank_number = 1,
1291                         },
1292                 },
1293         },
1294
1295         {
1296                 .chipid_cidr    = 0x29380560,
1297                 .name           = "at91sam3n1a",
1298                 .total_flash_size     = 64 * 1024,
1299                 .total_sram_size      = 8 * 1024,
1300                 .n_gpnvms       = 3,
1301                 .n_banks        = 1,
1302
1303                 /* System boots at address 0x0 */
1304                 /* gpnvm[1] = selects boot code */
1305                 /*     if gpnvm[1] == 0 */
1306                 /*         boot is via "SAMBA" (rom) */
1307                 /*     else */
1308                 /*         boot is via FLASH */
1309                 /*         Selection is via gpnvm[2] */
1310                 /*     endif */
1311                 /*  */
1312                 /* NOTE: banks 0 & 1 switch places */
1313                 /*     if gpnvm[2] == 0 */
1314                 /*         Bank0 is the boot rom */
1315                 /*      else */
1316                 /*         Bank1 is the boot rom */
1317                 /*      endif */
1318 /*              .bank[0] = { */
1319                 {
1320                         {
1321                                 .probed = 0,
1322                                 .pChip  = NULL,
1323                                 .pBank  = NULL,
1324                                 .bank_number = 0,
1325                                 .base_address = FLASH_BANK_BASE_N,
1326                                 .controller_address = 0x400e0A00,
1327                                 .flash_wait_states = 6, /* workaround silicon bug */
1328                                 .present = 1,
1329                                 .size_bytes = 64 * 1024,
1330                                 .nsectors   = 4,
1331                                 .sector_size = 16384,
1332                                 .page_size   = 256,
1333                         },
1334
1335 /*              .bank[1] = { */
1336                         {
1337                                 .present = 0,
1338                                 .probed = 0,
1339                                 .bank_number = 1,
1340                         },
1341                 },
1342         },
1343
1344         /* Start at91sam3a series*/
1345         /* System boots at address 0x0 */
1346         /* gpnvm[1] = selects boot code */
1347         /*     if gpnvm[1] == 0 */
1348         /*         boot is via "SAMBA" (rom) */
1349         /*     else */
1350         /*         boot is via FLASH */
1351         /*         Selection is via gpnvm[2] */
1352         /*     endif */
1353         /*  */
1354         /* NOTE: banks 0 & 1 switch places */
1355         /*     if gpnvm[2] == 0 */
1356         /*         Bank0 is the boot rom */
1357         /*      else */
1358         /*         Bank1 is the boot rom */
1359         /*      endif */
1360
1361         {
1362                 .chipid_cidr    = 0x283E0A60,
1363                 .name           = "at91sam3a8c",
1364                 .total_flash_size     = 512 * 1024,
1365                 .total_sram_size      = 96 * 1024,
1366                 .n_gpnvms       = 3,
1367                 .n_banks        = 2,
1368                 {
1369 /*              .bank[0] = { */
1370                   {
1371                         .probed = 0,
1372                         .pChip  = NULL,
1373                         .pBank  = NULL,
1374                         .bank_number = 0,
1375                         .base_address = FLASH_BANK0_BASE_AX,
1376                         .controller_address = 0x400e0a00,
1377                         .flash_wait_states = 6, /* workaround silicon bug */
1378                         .present = 1,
1379                         .size_bytes =  256 * 1024,
1380                         .nsectors   =  16,
1381                         .sector_size = 16384,
1382                         .page_size   = 256,
1383                   },
1384 /*              .bank[1] = { */
1385                   {
1386                         .probed = 0,
1387                         .pChip  = NULL,
1388                         .pBank  = NULL,
1389                         .bank_number = 1,
1390                         .base_address = FLASH_BANK1_BASE_512K_AX,
1391                         .controller_address = 0x400e0c00,
1392                         .flash_wait_states = 6, /* workaround silicon bug */
1393                         .present = 1,
1394                         .size_bytes =  256 * 1024,
1395                         .nsectors   =  16,
1396                         .sector_size = 16384,
1397                         .page_size   = 256,
1398
1399                   },
1400                 },
1401         },
1402         {
1403                 .chipid_cidr    = 0x283B0960,
1404                 .name           = "at91sam3a4c",
1405                 .total_flash_size     = 256 * 1024,
1406                 .total_sram_size      = 64 * 1024,
1407                 .n_gpnvms       = 3,
1408                 .n_banks        = 2,
1409                 {
1410 /*              .bank[0] = { */
1411                   {
1412                         .probed = 0,
1413                         .pChip  = NULL,
1414                         .pBank  = NULL,
1415                         .bank_number = 0,
1416                         .base_address = FLASH_BANK0_BASE_AX,
1417                         .controller_address = 0x400e0a00,
1418                         .flash_wait_states = 6, /* workaround silicon bug */
1419                         .present = 1,
1420                         .size_bytes =  128 * 1024,
1421                         .nsectors   =  8,
1422                         .sector_size = 16384,
1423                         .page_size   = 256,
1424                   },
1425 /*              .bank[1] = { */
1426                   {
1427                         .probed = 0,
1428                         .pChip  = NULL,
1429                         .pBank  = NULL,
1430                         .bank_number = 1,
1431                         .base_address = FLASH_BANK1_BASE_256K_AX,
1432                         .controller_address = 0x400e0c00,
1433                         .flash_wait_states = 6, /* workaround silicon bug */
1434                         .present = 1,
1435                         .size_bytes =  128 * 1024,
1436                         .nsectors   =  8,
1437                         .sector_size = 16384,
1438                         .page_size   = 256,
1439
1440                   },
1441                 },
1442         },
1443
1444         /* Start at91sam3x* series */
1445         /* System boots at address 0x0 */
1446         /* gpnvm[1] = selects boot code */
1447         /*     if gpnvm[1] == 0 */
1448         /*         boot is via "SAMBA" (rom) */
1449         /*     else */
1450         /*         boot is via FLASH */
1451         /*         Selection is via gpnvm[2] */
1452         /*     endif */
1453         /*  */
1454         /* NOTE: banks 0 & 1 switch places */
1455         /*     if gpnvm[2] == 0 */
1456         /*         Bank0 is the boot rom */
1457         /*      else */
1458         /*         Bank1 is the boot rom */
1459         /*      endif */
1460         /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1461         {
1462                 .chipid_cidr    = 0x286E0A20,
1463                 .name           = "at91sam3x8h - ES",
1464                 .total_flash_size     = 512 * 1024,
1465                 .total_sram_size      = 96 * 1024,
1466                 .n_gpnvms       = 3,
1467                 .n_banks        = 2,
1468                 {
1469 /*              .bank[0] = { */
1470                   {
1471                         .probed = 0,
1472                         .pChip  = NULL,
1473                         .pBank  = NULL,
1474                         .bank_number = 0,
1475                         .base_address = FLASH_BANK0_BASE_AX,
1476                         .controller_address = 0x400e0a00,
1477                         .flash_wait_states = 6, /* workaround silicon bug */
1478                         .present = 1,
1479                         .size_bytes =  256 * 1024,
1480                         .nsectors   =  16,
1481                         .sector_size = 16384,
1482                         .page_size   = 256,
1483                   },
1484 /*              .bank[1] = { */
1485                   {
1486                         .probed = 0,
1487                         .pChip  = NULL,
1488                         .pBank  = NULL,
1489                         .bank_number = 1,
1490                         .base_address = FLASH_BANK1_BASE_512K_AX,
1491                         .controller_address = 0x400e0c00,
1492                         .flash_wait_states = 6, /* workaround silicon bug */
1493                         .present = 1,
1494                         .size_bytes =  256 * 1024,
1495                         .nsectors   =  16,
1496                         .sector_size = 16384,
1497                         .page_size   = 256,
1498
1499                   },
1500                 },
1501         },
1502         /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1503         {
1504                 .chipid_cidr    = 0x286E0A60,
1505                 .name           = "at91sam3x8h",
1506                 .total_flash_size     = 512 * 1024,
1507                 .total_sram_size      = 96 * 1024,
1508                 .n_gpnvms       = 3,
1509                 .n_banks        = 2,
1510                 {
1511 /*              .bank[0] = { */
1512                   {
1513                         .probed = 0,
1514                         .pChip  = NULL,
1515                         .pBank  = NULL,
1516                         .bank_number = 0,
1517                         .base_address = FLASH_BANK0_BASE_AX,
1518                         .controller_address = 0x400e0a00,
1519                         .flash_wait_states = 6, /* workaround silicon bug */
1520                         .present = 1,
1521                         .size_bytes =  256 * 1024,
1522                         .nsectors   =  16,
1523                         .sector_size = 16384,
1524                         .page_size   = 256,
1525                   },
1526 /*              .bank[1] = { */
1527                   {
1528                         .probed = 0,
1529                         .pChip  = NULL,
1530                         .pBank  = NULL,
1531                         .bank_number = 1,
1532                         .base_address = FLASH_BANK1_BASE_512K_AX,
1533                         .controller_address = 0x400e0c00,
1534                         .flash_wait_states = 6, /* workaround silicon bug */
1535                         .present = 1,
1536                         .size_bytes =  256 * 1024,
1537                         .nsectors   =  16,
1538                         .sector_size = 16384,
1539                         .page_size   = 256,
1540
1541                   },
1542                 },
1543         },
1544         {
1545                 .chipid_cidr    = 0x285E0A60,
1546                 .name           = "at91sam3x8e",
1547                 .total_flash_size     = 512 * 1024,
1548                 .total_sram_size      = 96 * 1024,
1549                 .n_gpnvms       = 3,
1550                 .n_banks        = 2,
1551                 {
1552 /*              .bank[0] = { */
1553                   {
1554                         .probed = 0,
1555                         .pChip  = NULL,
1556                         .pBank  = NULL,
1557                         .bank_number = 0,
1558                         .base_address = FLASH_BANK0_BASE_AX,
1559                         .controller_address = 0x400e0a00,
1560                         .flash_wait_states = 6, /* workaround silicon bug */
1561                         .present = 1,
1562                         .size_bytes =  256 * 1024,
1563                         .nsectors   =  16,
1564                         .sector_size = 16384,
1565                         .page_size   = 256,
1566                   },
1567 /*              .bank[1] = { */
1568                   {
1569                         .probed = 0,
1570                         .pChip  = NULL,
1571                         .pBank  = NULL,
1572                         .bank_number = 1,
1573                         .base_address = FLASH_BANK1_BASE_512K_AX,
1574                         .controller_address = 0x400e0c00,
1575                         .flash_wait_states = 6, /* workaround silicon bug */
1576                         .present = 1,
1577                         .size_bytes =  256 * 1024,
1578                         .nsectors   =  16,
1579                         .sector_size = 16384,
1580                         .page_size   = 256,
1581
1582                   },
1583                 },
1584         },
1585         {
1586                 .chipid_cidr    = 0x284E0A60,
1587                 .name           = "at91sam3x8c",
1588                 .total_flash_size     = 512 * 1024,
1589                 .total_sram_size      = 96 * 1024,
1590                 .n_gpnvms       = 3,
1591                 .n_banks        = 2,
1592                 {
1593 /*              .bank[0] = { */
1594                   {
1595                         .probed = 0,
1596                         .pChip  = NULL,
1597                         .pBank  = NULL,
1598                         .bank_number = 0,
1599                         .base_address = FLASH_BANK0_BASE_AX,
1600                         .controller_address = 0x400e0a00,
1601                         .flash_wait_states = 6, /* workaround silicon bug */
1602                         .present = 1,
1603                         .size_bytes =  256 * 1024,
1604                         .nsectors   =  16,
1605                         .sector_size = 16384,
1606                         .page_size   = 256,
1607                   },
1608 /*              .bank[1] = { */
1609                   {
1610                         .probed = 0,
1611                         .pChip  = NULL,
1612                         .pBank  = NULL,
1613                         .bank_number = 1,
1614                         .base_address = FLASH_BANK1_BASE_512K_AX ,
1615                         .controller_address = 0x400e0c00,
1616                         .flash_wait_states = 6, /* workaround silicon bug */
1617                         .present = 1,
1618                         .size_bytes =  256 * 1024,
1619                         .nsectors   =  16,
1620                         .sector_size = 16384,
1621                         .page_size   = 256,
1622
1623                   },
1624                 },
1625         },
1626         {
1627                 .chipid_cidr    = 0x285B0960,
1628                 .name           = "at91sam3x4e",
1629                 .total_flash_size     = 256 * 1024,
1630                 .total_sram_size      = 64 * 1024,
1631                 .n_gpnvms       = 3,
1632                 .n_banks        = 2,
1633                 {
1634 /*              .bank[0] = { */
1635                   {
1636                         .probed = 0,
1637                         .pChip  = NULL,
1638                         .pBank  = NULL,
1639                         .bank_number = 0,
1640                         .base_address = FLASH_BANK0_BASE_AX,
1641                         .controller_address = 0x400e0a00,
1642                         .flash_wait_states = 6, /* workaround silicon bug */
1643                         .present = 1,
1644                         .size_bytes =  128 * 1024,
1645                         .nsectors   =  8,
1646                         .sector_size = 16384,
1647                         .page_size   = 256,
1648                   },
1649 /*              .bank[1] = { */
1650                   {
1651                         .probed = 0,
1652                         .pChip  = NULL,
1653                         .pBank  = NULL,
1654                         .bank_number = 1,
1655                         .base_address = FLASH_BANK1_BASE_256K_AX,
1656                         .controller_address = 0x400e0c00,
1657                         .flash_wait_states = 6, /* workaround silicon bug */
1658                         .present = 1,
1659                         .size_bytes =  128 * 1024,
1660                         .nsectors   =  8,
1661                         .sector_size = 16384,
1662                         .page_size   = 256,
1663
1664                   },
1665                 },
1666         },
1667         {
1668                 .chipid_cidr    = 0x284B0960,
1669                 .name           = "at91sam3x4c",
1670                 .total_flash_size     = 256 * 1024,
1671                 .total_sram_size      = 64 * 1024,
1672                 .n_gpnvms       = 3,
1673                 .n_banks        = 2,
1674                 {
1675 /*              .bank[0] = { */
1676                   {
1677                         .probed = 0,
1678                         .pChip  = NULL,
1679                         .pBank  = NULL,
1680                         .bank_number = 0,
1681                         .base_address = FLASH_BANK0_BASE_AX,
1682                         .controller_address = 0x400e0a00,
1683                         .flash_wait_states = 6, /* workaround silicon bug */
1684                         .present = 1,
1685                         .size_bytes =  128 * 1024,
1686                         .nsectors   =  8,
1687                         .sector_size = 16384,
1688                         .page_size   = 256,
1689                   },
1690 /*              .bank[1] = { */
1691                   {
1692                         .probed = 0,
1693                         .pChip  = NULL,
1694                         .pBank  = NULL,
1695                         .bank_number = 1,
1696                         .base_address = FLASH_BANK1_BASE_256K_AX,
1697                         .controller_address = 0x400e0c00,
1698                         .flash_wait_states = 6, /* workaround silicon bug */
1699                         .present = 1,
1700                         .size_bytes =  128 * 1024,
1701                         .nsectors   =  8,
1702                         .sector_size = 16384,
1703                         .page_size   = 256,
1704
1705                   },
1706                 },
1707         },
1708         /* terminate */
1709         {
1710                 .chipid_cidr    = 0,
1711                 .name                   = NULL,
1712         }
1713 };
1714
1715 /* Globals above */
1716 /***********************************************************************
1717  **********************************************************************
1718  **********************************************************************
1719  **********************************************************************
1720  **********************************************************************
1721  **********************************************************************/
1722 /* *ATMEL* style code - from the SAM3 driver code */
1723
1724 /**
1725  * Get the current status of the EEFC and
1726  * the value of some status bits (LOCKE, PROGE).
1727  * @param pPrivate - info about the bank
1728  * @param v        - result goes here
1729  */
1730 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
1731 {
1732         int r;
1733         r = target_read_u32(pPrivate->pChip->target,
1734                         pPrivate->controller_address + offset_EFC_FSR,
1735                         v);
1736         LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1737                 (unsigned int)(*v),
1738                 ((unsigned int)((*v >> 2) & 1)),
1739                 ((unsigned int)((*v >> 1) & 1)),
1740                 ((unsigned int)((*v >> 0) & 1)));
1741
1742         return r;
1743 }
1744
1745 /**
1746  * Get the result of the last executed command.
1747  * @param pPrivate - info about the bank
1748  * @param v        - result goes here
1749  */
1750 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
1751 {
1752         int r;
1753         uint32_t rv;
1754         r = target_read_u32(pPrivate->pChip->target,
1755                         pPrivate->controller_address + offset_EFC_FRR,
1756                         &rv);
1757         if (v)
1758                 *v = rv;
1759         LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1760         return r;
1761 }
1762
1763 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
1764         unsigned command, unsigned argument)
1765 {
1766         uint32_t n, v;
1767         int r;
1768         int retry;
1769
1770         retry = 0;
1771 do_retry:
1772
1773         /* Check command & argument */
1774         switch (command) {
1775
1776                 case AT91C_EFC_FCMD_WP:
1777                 case AT91C_EFC_FCMD_WPL:
1778                 case AT91C_EFC_FCMD_EWP:
1779                 case AT91C_EFC_FCMD_EWPL:
1780                 /* case AT91C_EFC_FCMD_EPL: */
1781                 /* case AT91C_EFC_FCMD_EPA: */
1782                 case AT91C_EFC_FCMD_SLB:
1783                 case AT91C_EFC_FCMD_CLB:
1784                         n = (pPrivate->size_bytes / pPrivate->page_size);
1785                         if (argument >= n)
1786                                 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1787                         break;
1788
1789                 case AT91C_EFC_FCMD_SFB:
1790                 case AT91C_EFC_FCMD_CFB:
1791                         if (argument >= pPrivate->pChip->details.n_gpnvms) {
1792                                 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1793                                                 pPrivate->pChip->details.n_gpnvms);
1794                         }
1795                         break;
1796
1797                 case AT91C_EFC_FCMD_GETD:
1798                 case AT91C_EFC_FCMD_EA:
1799                 case AT91C_EFC_FCMD_GLB:
1800                 case AT91C_EFC_FCMD_GFB:
1801                 case AT91C_EFC_FCMD_STUI:
1802                 case AT91C_EFC_FCMD_SPUI:
1803                         if (argument != 0)
1804                                 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1805                         break;
1806                 default:
1807                         LOG_ERROR("Unknown command %d", command);
1808                         break;
1809         }
1810
1811         if (command == AT91C_EFC_FCMD_SPUI) {
1812                 /* this is a very special situation. */
1813                 /* Situation (1) - error/retry - see below */
1814                 /*      And we are being called recursively */
1815                 /* Situation (2) - normal, finished reading unique id */
1816         } else {
1817                 /* it should be "ready" */
1818                 EFC_GetStatus(pPrivate, &v);
1819                 if (v & 1) {
1820                         /* then it is ready */
1821                         /* we go on */
1822                 } else {
1823                         if (retry) {
1824                                 /* we have done this before */
1825                                 /* the controller is not responding. */
1826                                 LOG_ERROR("flash controller(%d) is not ready! Error",
1827                                         pPrivate->bank_number);
1828                                 return ERROR_FAIL;
1829                         } else {
1830                                 retry++;
1831                                 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1832                                         pPrivate->bank_number);
1833                                 /* we do that by issuing the *STOP* command */
1834                                 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1835                                 /* above is recursive, and further recursion is blocked by */
1836                                 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1837                                 goto do_retry;
1838                         }
1839                 }
1840         }
1841
1842         v = (0x5A << 24) | (argument << 8) | command;
1843         LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1844         r = target_write_u32(pPrivate->pBank->target,
1845                         pPrivate->controller_address + offset_EFC_FCR, v);
1846         if (r != ERROR_OK)
1847                 LOG_DEBUG("Error Write failed");
1848         return r;
1849 }
1850
1851 /**
1852  * Performs the given command and wait until its completion (or an error).
1853  * @param pPrivate - info about the bank
1854  * @param command  - Command to perform.
1855  * @param argument - Optional command argument.
1856  * @param status   - put command status bits here
1857  */
1858 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
1859         unsigned command,
1860         unsigned argument,
1861         uint32_t *status)
1862 {
1863
1864         int r;
1865         uint32_t v;
1866         long long ms_now, ms_end;
1867
1868         /* default */
1869         if (status)
1870                 *status = 0;
1871
1872         r = EFC_StartCommand(pPrivate, command, argument);
1873         if (r != ERROR_OK)
1874                 return r;
1875
1876         ms_end = 500 + timeval_ms();
1877
1878         do {
1879                 r = EFC_GetStatus(pPrivate, &v);
1880                 if (r != ERROR_OK)
1881                         return r;
1882                 ms_now = timeval_ms();
1883                 if (ms_now > ms_end) {
1884                         /* error */
1885                         LOG_ERROR("Command timeout");
1886                         return ERROR_FAIL;
1887                 }
1888         } while ((v & 1) == 0);
1889
1890         /* error bits.. */
1891         if (status)
1892                 *status = (v & 0x6);
1893         return ERROR_OK;
1894
1895 }
1896
1897 /**
1898  * Read the unique ID.
1899  * @param pPrivate - info about the bank
1900  * The unique ID is stored in the 'pPrivate' structure.
1901  */
1902 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
1903 {
1904         int r;
1905         uint32_t v;
1906         int x;
1907         /* assume 0 */
1908         pPrivate->pChip->cfg.unique_id[0] = 0;
1909         pPrivate->pChip->cfg.unique_id[1] = 0;
1910         pPrivate->pChip->cfg.unique_id[2] = 0;
1911         pPrivate->pChip->cfg.unique_id[3] = 0;
1912
1913         LOG_DEBUG("Begin");
1914         r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1915         if (r < 0)
1916                 return r;
1917
1918         for (x = 0; x < 4; x++) {
1919                 r = target_read_u32(pPrivate->pChip->target,
1920                                 pPrivate->pBank->base + (x * 4),
1921                                 &v);
1922                 if (r < 0)
1923                         return r;
1924                 pPrivate->pChip->cfg.unique_id[x] = v;
1925         }
1926
1927         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1928         LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1929                 r,
1930                 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1931                 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1932                 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1933                 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1934         return r;
1935
1936 }
1937
1938 /**
1939  * Erases the entire flash.
1940  * @param pPrivate - the info about the bank.
1941  */
1942 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
1943 {
1944         LOG_DEBUG("Here");
1945         return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1946 }
1947
1948 /**
1949  * Gets current GPNVM state.
1950  * @param pPrivate - info about the bank.
1951  * @param gpnvm    -  GPNVM bit index.
1952  * @param puthere  - result stored here.
1953  */
1954 /* ------------------------------------------------------------------------------ */
1955 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1956 {
1957         uint32_t v;
1958         int r;
1959
1960         LOG_DEBUG("Here");
1961         if (pPrivate->bank_number != 0) {
1962                 LOG_ERROR("GPNVM only works with Bank0");
1963                 return ERROR_FAIL;
1964         }
1965
1966         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1967                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1968                         gpnvm, pPrivate->pChip->details.n_gpnvms);
1969                 return ERROR_FAIL;
1970         }
1971
1972         /* Get GPNVMs status */
1973         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1974         if (r != ERROR_OK) {
1975                 LOG_ERROR("Failed");
1976                 return r;
1977         }
1978
1979         r = EFC_GetResult(pPrivate, &v);
1980
1981         if (puthere) {
1982                 /* Check if GPNVM is set */
1983                 /* get the bit and make it a 0/1 */
1984                 *puthere = (v >> gpnvm) & 1;
1985         }
1986
1987         return r;
1988 }
1989
1990 /**
1991  * Clears the selected GPNVM bit.
1992  * @param pPrivate info about the bank
1993  * @param gpnvm GPNVM index.
1994  * @returns 0 if successful; otherwise returns an error code.
1995  */
1996 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1997 {
1998         int r;
1999         unsigned v;
2000
2001         LOG_DEBUG("Here");
2002         if (pPrivate->bank_number != 0) {
2003                 LOG_ERROR("GPNVM only works with Bank0");
2004                 return ERROR_FAIL;
2005         }
2006
2007         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2008                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2009                         gpnvm, pPrivate->pChip->details.n_gpnvms);
2010                 return ERROR_FAIL;
2011         }
2012
2013         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2014         if (r != ERROR_OK) {
2015                 LOG_DEBUG("Failed: %d", r);
2016                 return r;
2017         }
2018         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2019         LOG_DEBUG("End: %d", r);
2020         return r;
2021 }
2022
2023 /**
2024  * Sets the selected GPNVM bit.
2025  * @param pPrivate info about the bank
2026  * @param gpnvm GPNVM index.
2027  */
2028 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2029 {
2030         int r;
2031         unsigned v;
2032
2033         if (pPrivate->bank_number != 0) {
2034                 LOG_ERROR("GPNVM only works with Bank0");
2035                 return ERROR_FAIL;
2036         }
2037
2038         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2039                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2040                         gpnvm, pPrivate->pChip->details.n_gpnvms);
2041                 return ERROR_FAIL;
2042         }
2043
2044         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2045         if (r != ERROR_OK)
2046                 return r;
2047         if (v) {
2048                 /* already set */
2049                 r = ERROR_OK;
2050         } else {
2051                 /* set it */
2052                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2053         }
2054         return r;
2055 }
2056
2057 /**
2058  * Returns a bit field (at most 64) of locked regions within a page.
2059  * @param pPrivate info about the bank
2060  * @param v where to store locked bits
2061  */
2062 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
2063 {
2064         int r;
2065         LOG_DEBUG("Here");
2066         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
2067         if (r == ERROR_OK)
2068                 r = EFC_GetResult(pPrivate, v);
2069         LOG_DEBUG("End: %d", r);
2070         return r;
2071 }
2072
2073 /**
2074  * Unlocks all the regions in the given address range.
2075  * @param pPrivate info about the bank
2076  * @param start_sector first sector to unlock
2077  * @param end_sector last (inclusive) to unlock
2078  */
2079
2080 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
2081         unsigned start_sector,
2082         unsigned end_sector)
2083 {
2084         int r;
2085         uint32_t status;
2086         uint32_t pg;
2087         uint32_t pages_per_sector;
2088
2089         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2090
2091         /* Unlock all pages */
2092         while (start_sector <= end_sector) {
2093                 pg = start_sector * pages_per_sector;
2094
2095                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
2096                 if (r != ERROR_OK)
2097                         return r;
2098                 start_sector++;
2099         }
2100
2101         return ERROR_OK;
2102 }
2103
2104 /**
2105  * Locks regions
2106  * @param pPrivate - info about the bank
2107  * @param start_sector - first sector to lock
2108  * @param end_sector   - last sector (inclusive) to lock
2109  */
2110 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
2111         unsigned start_sector,
2112         unsigned end_sector)
2113 {
2114         uint32_t status;
2115         uint32_t pg;
2116         uint32_t pages_per_sector;
2117         int r;
2118
2119         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2120
2121         /* Lock all pages */
2122         while (start_sector <= end_sector) {
2123                 pg = start_sector * pages_per_sector;
2124
2125                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
2126                 if (r != ERROR_OK)
2127                         return r;
2128                 start_sector++;
2129         }
2130         return ERROR_OK;
2131 }
2132
2133 /****** END SAM3 CODE ********/
2134
2135 /* begin helpful debug code */
2136 /* print the fieldname, the field value, in dec & hex, and return field value */
2137 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
2138         const char *regname,
2139         uint32_t value,
2140         unsigned shift,
2141         unsigned width)
2142 {
2143         uint32_t v;
2144         int hwidth, dwidth;
2145
2146
2147         /* extract the field */
2148         v = value >> shift;
2149         v = v & ((1 << width)-1);
2150         if (width <= 16) {
2151                 hwidth = 4;
2152                 dwidth = 5;
2153         } else {
2154                 hwidth = 8;
2155                 dwidth = 12;
2156         }
2157
2158         /* show the basics */
2159         LOG_USER_N("\t%*s: %*d [0x%0*x] ",
2160                 REG_NAME_WIDTH, regname,
2161                 dwidth, v,
2162                 hwidth, v);
2163         return v;
2164 }
2165
2166 static const char _unknown[] = "unknown";
2167 static const char *const eproc_names[] = {
2168         _unknown,                                       /* 0 */
2169         "arm946es",                                     /* 1 */
2170         "arm7tdmi",                                     /* 2 */
2171         "cortex-m3",                            /* 3 */
2172         "arm920t",                                      /* 4 */
2173         "arm926ejs",                            /* 5 */
2174         _unknown,                                       /* 6 */
2175         _unknown,                                       /* 7 */
2176         _unknown,                                       /* 8 */
2177         _unknown,                                       /* 9 */
2178         _unknown,                                       /* 10 */
2179         _unknown,                                       /* 11 */
2180         _unknown,                                       /* 12 */
2181         _unknown,                                       /* 13 */
2182         _unknown,                                       /* 14 */
2183         _unknown,                                       /* 15 */
2184 };
2185
2186 #define nvpsize2 nvpsize                /* these two tables are identical */
2187 static const char *const nvpsize[] = {
2188         "none",                                         /*  0 */
2189         "8K bytes",                                     /*  1 */
2190         "16K bytes",                            /*  2 */
2191         "32K bytes",                            /*  3 */
2192         _unknown,                                       /*  4 */
2193         "64K bytes",                            /*  5 */
2194         _unknown,                                       /*  6 */
2195         "128K bytes",                           /*  7 */
2196         _unknown,                                       /*  8 */
2197         "256K bytes",                           /*  9 */
2198         "512K bytes",                           /* 10 */
2199         _unknown,                                       /* 11 */
2200         "1024K bytes",                          /* 12 */
2201         _unknown,                                       /* 13 */
2202         "2048K bytes",                          /* 14 */
2203         _unknown,                                       /* 15 */
2204 };
2205
2206 static const char *const sramsize[] = {
2207         "48K Bytes",                            /*  0 */
2208         "1K Bytes",                                     /*  1 */
2209         "2K Bytes",                                     /*  2 */
2210         "6K Bytes",                                     /*  3 */
2211         "112K Bytes",                           /*  4 */
2212         "4K Bytes",                                     /*  5 */
2213         "80K Bytes",                            /*  6 */
2214         "160K Bytes",                           /*  7 */
2215         "8K Bytes",                                     /*  8 */
2216         "16K Bytes",                            /*  9 */
2217         "32K Bytes",                            /* 10 */
2218         "64K Bytes",                            /* 11 */
2219         "128K Bytes",                           /* 12 */
2220         "256K Bytes",                           /* 13 */
2221         "96K Bytes",                            /* 14 */
2222         "512K Bytes",                           /* 15 */
2223
2224 };
2225
2226 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2227         { 0x19,  "AT91SAM9xx Series"                                            },
2228         { 0x29,  "AT91SAM9XExx Series"                                          },
2229         { 0x34,  "AT91x34 Series"                                                       },
2230         { 0x37,  "CAP7 Series"                                                          },
2231         { 0x39,  "CAP9 Series"                                                          },
2232         { 0x3B,  "CAP11 Series"                                                         },
2233         { 0x40,  "AT91x40 Series"                                                       },
2234         { 0x42,  "AT91x42 Series"                                                       },
2235         { 0x55,  "AT91x55 Series"                                                       },
2236         { 0x60,  "AT91SAM7Axx Series"                                           },
2237         { 0x61,  "AT91SAM7AQxx Series"                                          },
2238         { 0x63,  "AT91x63 Series"                                                       },
2239         { 0x70,  "AT91SAM7Sxx Series"                                           },
2240         { 0x71,  "AT91SAM7XCxx Series"                                          },
2241         { 0x72,  "AT91SAM7SExx Series"                                          },
2242         { 0x73,  "AT91SAM7Lxx Series"                                           },
2243         { 0x75,  "AT91SAM7Xxx Series"                                           },
2244         { 0x76,  "AT91SAM7SLxx Series"                                          },
2245         { 0x80,  "ATSAM3UxC Series (100-pin version)"           },
2246         { 0x81,  "ATSAM3UxE Series (144-pin version)"           },
2247         { 0x83,  "ATSAM3AxC Series (100-pin version)"           },
2248         { 0x84,  "ATSAM3XxC Series (100-pin version)"           },
2249         { 0x85,  "ATSAM3XxE Series (144-pin version)"           },
2250         { 0x86,  "ATSAM3XxG Series (208/217-pin version)"       },
2251         { 0x88,  "ATSAM3SxA Series (48-pin version)"            },
2252         { 0x89,  "ATSAM3SxB Series (64-pin version)"            },
2253         { 0x8A,  "ATSAM3SxC Series (100-pin version)"           },
2254         { 0x92,  "AT91x92 Series"                                                       },
2255         { 0x93,  "ATSAM3NxA Series (48-pin version)"            },
2256         { 0x94,  "ATSAM3NxB Series (64-pin version)"            },
2257         { 0x95,  "ATSAM3NxC Series (100-pin version)"           },
2258         { 0x98,  "ATSAM3SDxA Series (48-pin version)"           },
2259         { 0x99,  "ATSAM3SDxB Series (64-pin version)"           },
2260         { 0x9A,  "ATSAM3SDxC Series (100-pin version)"          },
2261         { 0xA5,  "ATSAM5A"                                                              },
2262         { 0xF0,  "AT75Cxx Series"                                                       },
2263         { -1, NULL },
2264 };
2265
2266 static const char *const nvptype[] = {
2267         "rom",  /* 0 */
2268         "romless or onchip flash",      /* 1 */
2269         "embedded flash memory",/* 2 */
2270         "rom(nvpsiz) + embedded flash (nvpsiz2)",       /* 3 */
2271         "sram emulating flash", /* 4 */
2272         _unknown,       /* 5 */
2273         _unknown,       /* 6 */
2274         _unknown,       /* 7 */
2275 };
2276
2277 static const char *_yes_or_no(uint32_t v)
2278 {
2279         if (v)
2280                 return "YES";
2281         else
2282                 return "NO";
2283 }
2284
2285 static const char *const _rc_freq[] = {
2286         "4 MHz", "8 MHz", "12 MHz", "reserved"
2287 };
2288
2289 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
2290 {
2291         uint32_t v;
2292         uint32_t rcen;
2293
2294         v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2295         LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2296         v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2297         LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2298         rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2299         LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2300         v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2301         LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2302
2303         pChip->cfg.rc_freq = 0;
2304         if (rcen) {
2305                 switch (v) {
2306                         default:
2307                                 pChip->cfg.rc_freq = 0;
2308                                 break;
2309                         case 0:
2310                                 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2311                                 break;
2312                         case 1:
2313                                 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2314                                 break;
2315                         case 2:
2316                                 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2317                                 break;
2318                 }
2319         }
2320
2321         v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2322         LOG_USER("(startup clks, time= %f uSecs)",
2323                 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2324         v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2325         LOG_USER("(mainosc source: %s)",
2326                 v ? "external xtal" : "internal RC");
2327
2328         v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2329         LOG_USER("(clock failure enabled: %s)",
2330                 _yes_or_no(v));
2331 }
2332
2333 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
2334 {
2335         int x;
2336         uint32_t v;
2337         const char *cp;
2338
2339         sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2340         LOG_USER_N("\n");
2341
2342         v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2343         LOG_USER("%s", eproc_names[v]);
2344
2345         v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2346         LOG_USER("%s", nvpsize[v]);
2347
2348         v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2349         LOG_USER("%s", nvpsize2[v]);
2350
2351         v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2352         LOG_USER("%s", sramsize[v]);
2353
2354         v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2355         cp = _unknown;
2356         for (x = 0; archnames[x].name; x++) {
2357                 if (v == archnames[x].value) {
2358                         cp = archnames[x].name;
2359                         break;
2360                 }
2361         }
2362
2363         LOG_USER("%s", cp);
2364
2365         v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2366         LOG_USER("%s", nvptype[v]);
2367
2368         v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2369         LOG_USER("(exists: %s)", _yes_or_no(v));
2370 }
2371
2372 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
2373 {
2374         uint32_t v;
2375
2376         v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2377         LOG_USER("(main ready: %s)", _yes_or_no(v));
2378
2379         v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2380
2381         v = (v * pChip->cfg.slow_freq) / 16;
2382         pChip->cfg.mainosc_freq = v;
2383
2384         LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2385                 _tomhz(v),
2386                 pChip->cfg.slow_freq / 1000,
2387                 pChip->cfg.slow_freq % 1000);
2388 }
2389
2390 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
2391 {
2392         uint32_t mula, diva;
2393
2394         diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2395         LOG_USER_N("\n");
2396         mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2397         LOG_USER_N("\n");
2398         pChip->cfg.plla_freq = 0;
2399         if (mula == 0)
2400                 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2401         else if (diva == 0)
2402                 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2403         else if (diva == 1) {
2404                 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
2405                 LOG_USER("\tPLLA Freq: %3.03f MHz",
2406                         _tomhz(pChip->cfg.plla_freq));
2407         }
2408 }
2409
2410 static void sam3_explain_mckr(struct sam3_chip *pChip)
2411 {
2412         uint32_t css, pres, fin = 0;
2413         int pdiv = 0;
2414         const char *cp = NULL;
2415
2416         css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2417         switch (css & 3) {
2418                 case 0:
2419                         fin = pChip->cfg.slow_freq;
2420                         cp = "slowclk";
2421                         break;
2422                 case 1:
2423                         fin = pChip->cfg.mainosc_freq;
2424                         cp  = "mainosc";
2425                         break;
2426                 case 2:
2427                         fin = pChip->cfg.plla_freq;
2428                         cp  = "plla";
2429                         break;
2430                 case 3:
2431                         if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2432                                 fin = 480 * 1000 * 1000;
2433                                 cp = "upll";
2434                         } else {
2435                                 fin = 0;
2436                                 cp  = "upll (*ERROR* UPLL is disabled)";
2437                         }
2438                         break;
2439                 default:
2440                         assert(0);
2441                         break;
2442         }
2443
2444         LOG_USER("%s (%3.03f Mhz)",
2445                 cp,
2446                 _tomhz(fin));
2447         pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2448         switch (pres & 0x07) {
2449                 case 0:
2450                         pdiv = 1;
2451                         cp = "selected clock";
2452                         break;
2453                 case 1:
2454                         pdiv = 2;
2455                         cp = "clock/2";
2456                         break;
2457                 case 2:
2458                         pdiv = 4;
2459                         cp = "clock/4";
2460                         break;
2461                 case 3:
2462                         pdiv = 8;
2463                         cp = "clock/8";
2464                         break;
2465                 case 4:
2466                         pdiv = 16;
2467                         cp = "clock/16";
2468                         break;
2469                 case 5:
2470                         pdiv = 32;
2471                         cp = "clock/32";
2472                         break;
2473                 case 6:
2474                         pdiv = 64;
2475                         cp = "clock/64";
2476                         break;
2477                 case 7:
2478                         pdiv = 6;
2479                         cp = "clock/6";
2480                         break;
2481                 default:
2482                         assert(0);
2483                         break;
2484         }
2485         LOG_USER("(%s)", cp);
2486         fin = fin / pdiv;
2487         /* sam3 has a *SINGLE* clock - */
2488         /* other at91 series parts have divisors for these. */
2489         pChip->cfg.cpu_freq = fin;
2490         pChip->cfg.mclk_freq = fin;
2491         pChip->cfg.fclk_freq = fin;
2492         LOG_USER("\t\tResult CPU Freq: %3.03f",
2493                 _tomhz(fin));
2494 }
2495
2496 #if 0
2497 static struct sam3_chip *target2sam3(struct target *pTarget)
2498 {
2499         struct sam3_chip *pChip;
2500
2501         if (pTarget == NULL)
2502                 return NULL;
2503
2504         pChip = all_sam3_chips;
2505         while (pChip) {
2506                 if (pChip->target == pTarget)
2507                         break;  /* return below */
2508                 else
2509                         pChip = pChip->next;
2510         }
2511         return pChip;
2512 }
2513 #endif
2514
2515 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2516 {
2517         /* this function exists to help */
2518         /* keep funky offsetof() errors */
2519         /* and casting from causing bugs */
2520
2521         /* By using prototypes - we can detect what would */
2522         /* be casting errors. */
2523
2524         return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2525 }
2526
2527
2528 #define SAM3_ENTRY(NAME, FUNC)  { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2529                                                   struct sam3_cfg, \
2530                                                   NAME), # NAME, FUNC }
2531 static const struct sam3_reg_list sam3_all_regs[] = {
2532         SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2533         SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2534         SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2535         SAM3_ENTRY(CKGR_UCKR, NULL),
2536         SAM3_ENTRY(PMC_FSMR, NULL),
2537         SAM3_ENTRY(PMC_FSPR, NULL),
2538         SAM3_ENTRY(PMC_IMR, NULL),
2539         SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2540         SAM3_ENTRY(PMC_PCK0, NULL),
2541         SAM3_ENTRY(PMC_PCK1, NULL),
2542         SAM3_ENTRY(PMC_PCK2, NULL),
2543         SAM3_ENTRY(PMC_PCSR, NULL),
2544         SAM3_ENTRY(PMC_SCSR, NULL),
2545         SAM3_ENTRY(PMC_SR, NULL),
2546         SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2547         SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2548         SAM3_ENTRY(CHIPID_EXID, NULL),
2549         SAM3_ENTRY(CHIPID_EXID2, NULL),
2550         /* TERMINATE THE LIST */
2551         { .name = NULL }
2552 };
2553 #undef SAM3_ENTRY
2554
2555 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2556 {
2557         return (struct sam3_bank_private *)(bank->driver_priv);
2558 }
2559
2560 /**
2561  * Given a pointer to where it goes in the structure,
2562  * determine the register name, address from the all registers table.
2563  */
2564 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2565 {
2566         const struct sam3_reg_list *pReg;
2567
2568         pReg = &(sam3_all_regs[0]);
2569         while (pReg->name) {
2570                 uint32_t *pPossible;
2571
2572                 /* calculate where this one go.. */
2573                 /* it is "possibly" this register. */
2574
2575                 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2576
2577                 /* well? Is it this register */
2578                 if (pPossible == goes_here) {
2579                         /* Jump for joy! */
2580                         return pReg;
2581                 }
2582
2583                 /* next... */
2584                 pReg++;
2585         }
2586         /* This is *TOTAL*PANIC* - we are totally screwed. */
2587         LOG_ERROR("INVALID SAM3 REGISTER");
2588         return NULL;
2589 }
2590
2591 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2592 {
2593         const struct sam3_reg_list *pReg;
2594         int r;
2595
2596         pReg = sam3_GetReg(pChip, goes_here);
2597         if (!pReg)
2598                 return ERROR_FAIL;
2599
2600         r = target_read_u32(pChip->target, pReg->address, goes_here);
2601         if (r != ERROR_OK) {
2602                 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2603                         pReg->name, (unsigned)(pReg->address), r);
2604         }
2605         return r;
2606 }
2607
2608 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2609 {
2610         int r;
2611         const struct sam3_reg_list *pReg;
2612
2613         pReg = &(sam3_all_regs[0]);
2614         while (pReg->name) {
2615                 r = sam3_ReadThisReg(pChip,
2616                                 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2617                 if (r != ERROR_OK) {
2618                         LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
2619                                 pReg->name, ((unsigned)(pReg->address)), r);
2620                         return r;
2621                 }
2622                 pReg++;
2623         }
2624
2625         /* Chip identification register
2626         *
2627         * Unfortunately, the chip identification register is not at
2628         * a constant address across all of the SAM3 series'. As a
2629         * consequence, a simple heuristic is used to find where it's
2630         * at...
2631         *
2632         * If the contents at the first address is zero, then we know
2633         * that the second address is where the chip id register is.
2634         * We can deduce this because for those SAM's that have the
2635         * chip id @ 0x400e0940, the first address, 0x400e0740, is
2636         * located in the memory map of the Power Management Controller
2637         * (PMC). Furthermore, the address is not used by the PMC.
2638         * So when read, the memory controller returns zero.*/
2639         if (pChip->cfg.CHIPID_CIDR == 0)        {
2640                 /*Put the correct CIDR and EXID values in the pChip structure */
2641                 pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
2642                 pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
2643         }
2644         return ERROR_OK;
2645 }
2646
2647 static int sam3_GetInfo(struct sam3_chip *pChip)
2648 {
2649         const struct sam3_reg_list *pReg;
2650         uint32_t regval;
2651
2652         pReg = &(sam3_all_regs[0]);
2653         while (pReg->name) {
2654                 /* display all regs */
2655                 LOG_DEBUG("Start: %s", pReg->name);
2656                 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2657                 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2658                         REG_NAME_WIDTH,
2659                         pReg->name,
2660                         pReg->address,
2661                         regval);
2662                 if (pReg->explain_func)
2663                         (*(pReg->explain_func))(pChip);
2664                 LOG_DEBUG("End: %s", pReg->name);
2665                 pReg++;
2666         }
2667         LOG_USER("   rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2668         LOG_USER("  mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2669         LOG_USER("     plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2670         LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2671         LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2672
2673         LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2674                 pChip->cfg.unique_id[0],
2675                 pChip->cfg.unique_id[1],
2676                 pChip->cfg.unique_id[2],
2677                 pChip->cfg.unique_id[3]);
2678
2679         return ERROR_OK;
2680 }
2681
2682 static int sam3_erase_check(struct flash_bank *bank)
2683 {
2684         int x;
2685
2686         LOG_DEBUG("Here");
2687         if (bank->target->state != TARGET_HALTED) {
2688                 LOG_ERROR("Target not halted");
2689                 return ERROR_TARGET_NOT_HALTED;
2690         }
2691         if (0 == bank->num_sectors) {
2692                 LOG_ERROR("Target: not supported/not probed");
2693                 return ERROR_FAIL;
2694         }
2695
2696         LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2697         for (x = 0; x < bank->num_sectors; x++)
2698                 bank->sectors[x].is_erased = 1;
2699
2700         LOG_DEBUG("Done");
2701         return ERROR_OK;
2702 }
2703
2704 static int sam3_protect_check(struct flash_bank *bank)
2705 {
2706         int r;
2707         uint32_t v = 0;
2708         unsigned x;
2709         struct sam3_bank_private *pPrivate;
2710
2711         LOG_DEBUG("Begin");
2712         if (bank->target->state != TARGET_HALTED) {
2713                 LOG_ERROR("Target not halted");
2714                 return ERROR_TARGET_NOT_HALTED;
2715         }
2716
2717         pPrivate = get_sam3_bank_private(bank);
2718         if (!pPrivate) {
2719                 LOG_ERROR("no private for this bank?");
2720                 return ERROR_FAIL;
2721         }
2722         if (!(pPrivate->probed))
2723                 return ERROR_FLASH_BANK_NOT_PROBED;
2724
2725         r = FLASHD_GetLockBits(pPrivate, &v);
2726         if (r != ERROR_OK) {
2727                 LOG_DEBUG("Failed: %d", r);
2728                 return r;
2729         }
2730
2731         for (x = 0; x < pPrivate->nsectors; x++)
2732                 bank->sectors[x].is_protected = (!!(v & (1 << x)));
2733         LOG_DEBUG("Done");
2734         return ERROR_OK;
2735 }
2736
2737 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2738 {
2739         struct sam3_chip *pChip;
2740
2741         pChip = all_sam3_chips;
2742
2743         /* is this an existing chip? */
2744         while (pChip) {
2745                 if (pChip->target == bank->target)
2746                         break;
2747                 pChip = pChip->next;
2748         }
2749
2750         if (!pChip) {
2751                 /* this is a *NEW* chip */
2752                 pChip = calloc(1, sizeof(struct sam3_chip));
2753                 if (!pChip) {
2754                         LOG_ERROR("NO RAM!");
2755                         return ERROR_FAIL;
2756                 }
2757                 pChip->target = bank->target;
2758                 /* insert at head */
2759                 pChip->next = all_sam3_chips;
2760                 all_sam3_chips = pChip;
2761                 pChip->target = bank->target;
2762                 /* assumption is this runs at 32khz */
2763                 pChip->cfg.slow_freq = 32768;
2764                 pChip->probed = 0;
2765         }
2766
2767         switch (bank->base) {
2768                 default:
2769                         LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2770                         "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2771                         "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
2772                         ((unsigned int)(bank->base)),
2773                         ((unsigned int)(FLASH_BANK0_BASE_U)),
2774                         ((unsigned int)(FLASH_BANK1_BASE_U)),
2775                         ((unsigned int)(FLASH_BANK_BASE_S)),
2776                         ((unsigned int)(FLASH_BANK_BASE_N)),
2777                         ((unsigned int)(FLASH_BANK0_BASE_AX)),
2778                     ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
2779                     ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
2780                         return ERROR_FAIL;
2781                         break;
2782
2783                 /* at91sam3s and at91sam3n series only has bank 0*/
2784                 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
2785                 case FLASH_BANK_BASE_S:
2786                 case FLASH_BANK0_BASE_U:
2787                         bank->driver_priv = &(pChip->details.bank[0]);
2788                         bank->bank_number = 0;
2789                         pChip->details.bank[0].pChip = pChip;
2790                         pChip->details.bank[0].pBank = bank;
2791                         break;
2792
2793                 /* Bank 1 of at91sam3u or at91sam3ax series */
2794                 case FLASH_BANK1_BASE_U:
2795                 case FLASH_BANK1_BASE_256K_AX:
2796                 case FLASH_BANK1_BASE_512K_AX:
2797                         bank->driver_priv = &(pChip->details.bank[1]);
2798                         bank->bank_number = 1;
2799                         pChip->details.bank[1].pChip = pChip;
2800                         pChip->details.bank[1].pBank = bank;
2801                         break;
2802         }
2803
2804         /* we initialize after probing. */
2805         return ERROR_OK;
2806 }
2807
2808 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
2809 {
2810         const struct sam3_chip_details *pDetails;
2811         struct sam3_chip *pChip;
2812         struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
2813         unsigned x;
2814
2815         LOG_DEBUG("Begin");
2816         pDetails = all_sam3_details;
2817         while (pDetails->name) {
2818                 /* Compare cidr without version bits */
2819                 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2820                         break;
2821                 else
2822                         pDetails++;
2823         }
2824         if (pDetails->name == NULL) {
2825                 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2826                         (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2827                 /* Help the victim, print details about the chip */
2828                 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2829                         pPrivate->pChip->cfg.CHIPID_CIDR);
2830                 sam3_explain_chipid_cidr(pPrivate->pChip);
2831                 return ERROR_FAIL;
2832         }
2833
2834         /* DANGER: THERE ARE DRAGONS HERE */
2835
2836         /* get our pChip - it is going */
2837         /* to be over-written shortly */
2838         pChip = pPrivate->pChip;
2839
2840         /* Note that, in reality: */
2841         /*  */
2842         /*     pPrivate = &(pChip->details.bank[0]) */
2843         /* or  pPrivate = &(pChip->details.bank[1]) */
2844         /*  */
2845
2846         /* save the "bank" pointers */
2847         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
2848                 saved_banks[x] = pChip->details.bank[x].pBank;
2849
2850         /* Overwrite the "details" structure. */
2851         memcpy(&(pPrivate->pChip->details),
2852                 pDetails,
2853                 sizeof(pPrivate->pChip->details));
2854
2855         /* now fix the ghosted pointers */
2856         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2857                 pChip->details.bank[x].pChip = pChip;
2858                 pChip->details.bank[x].pBank = saved_banks[x];
2859         }
2860
2861         /* update the *BANK*SIZE* */
2862
2863         LOG_DEBUG("End");
2864         return ERROR_OK;
2865 }
2866
2867 static int _sam3_probe(struct flash_bank *bank, int noise)
2868 {
2869         unsigned x;
2870         int r;
2871         struct sam3_bank_private *pPrivate;
2872
2873
2874         LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2875         if (bank->target->state != TARGET_HALTED) {
2876                 LOG_ERROR("Target not halted");
2877                 return ERROR_TARGET_NOT_HALTED;
2878         }
2879
2880         pPrivate = get_sam3_bank_private(bank);
2881         if (!pPrivate) {
2882                 LOG_ERROR("Invalid/unknown bank number");
2883                 return ERROR_FAIL;
2884         }
2885
2886         r = sam3_ReadAllRegs(pPrivate->pChip);
2887         if (r != ERROR_OK)
2888                 return r;
2889
2890         LOG_DEBUG("Here");
2891         if (pPrivate->pChip->probed)
2892                 r = sam3_GetInfo(pPrivate->pChip);
2893         else
2894                 r = sam3_GetDetails(pPrivate);
2895         if (r != ERROR_OK)
2896                 return r;
2897
2898         /* update the flash bank size */
2899         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2900                 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2901                         bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2902                         break;
2903                 }
2904         }
2905
2906         if (bank->sectors == NULL) {
2907                 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2908                 if (bank->sectors == NULL) {
2909                         LOG_ERROR("No memory!");
2910                         return ERROR_FAIL;
2911                 }
2912                 bank->num_sectors = pPrivate->nsectors;
2913
2914                 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2915                         bank->sectors[x].size = pPrivate->sector_size;
2916                         bank->sectors[x].offset = x * (pPrivate->sector_size);
2917                         /* mark as unknown */
2918                         bank->sectors[x].is_erased = -1;
2919                         bank->sectors[x].is_protected = -1;
2920                 }
2921         }
2922
2923         pPrivate->probed = 1;
2924
2925         r = sam3_protect_check(bank);
2926         if (r != ERROR_OK)
2927                 return r;
2928
2929         LOG_DEBUG("Bank = %d, nbanks = %d",
2930                 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2931         if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2932                 /* read unique id, */
2933                 /* it appears to be associated with the *last* flash bank. */
2934                 FLASHD_ReadUniqueID(pPrivate);
2935         }
2936
2937         return r;
2938 }
2939
2940 static int sam3_probe(struct flash_bank *bank)
2941 {
2942         return _sam3_probe(bank, 1);
2943 }
2944
2945 static int sam3_auto_probe(struct flash_bank *bank)
2946 {
2947         return _sam3_probe(bank, 0);
2948 }
2949
2950 static int sam3_erase(struct flash_bank *bank, int first, int last)
2951 {
2952         struct sam3_bank_private *pPrivate;
2953         int r;
2954
2955         LOG_DEBUG("Here");
2956         if (bank->target->state != TARGET_HALTED) {
2957                 LOG_ERROR("Target not halted");
2958                 return ERROR_TARGET_NOT_HALTED;
2959         }
2960
2961         r = sam3_auto_probe(bank);
2962         if (r != ERROR_OK) {
2963                 LOG_DEBUG("Here,r=%d", r);
2964                 return r;
2965         }
2966
2967         pPrivate = get_sam3_bank_private(bank);
2968         if (!(pPrivate->probed))
2969                 return ERROR_FLASH_BANK_NOT_PROBED;
2970
2971         if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2972                 /* whole chip */
2973                 LOG_DEBUG("Here");
2974                 return FLASHD_EraseEntireBank(pPrivate);
2975         }
2976         LOG_INFO("sam3 auto-erases while programing (request ignored)");
2977         return ERROR_OK;
2978 }
2979
2980 static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
2981 {
2982         struct sam3_bank_private *pPrivate;
2983         int r;
2984
2985         LOG_DEBUG("Here");
2986         if (bank->target->state != TARGET_HALTED) {
2987                 LOG_ERROR("Target not halted");
2988                 return ERROR_TARGET_NOT_HALTED;
2989         }
2990
2991         pPrivate = get_sam3_bank_private(bank);
2992         if (!(pPrivate->probed))
2993                 return ERROR_FLASH_BANK_NOT_PROBED;
2994
2995         if (set)
2996                 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2997         else
2998                 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2999         LOG_DEBUG("End: r=%d", r);
3000
3001         return r;
3002
3003 }
3004
3005 static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)
3006 {
3007         if (bank->target->state != TARGET_HALTED) {
3008                 LOG_ERROR("Target not halted");
3009                 return ERROR_TARGET_NOT_HALTED;
3010         }
3011         buf[0] = 0;
3012         return ERROR_OK;
3013 }
3014
3015 static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3016 {
3017         uint32_t adr;
3018         int r;
3019
3020         adr = pagenum * pPrivate->page_size;
3021         adr += adr + pPrivate->base_address;
3022
3023         r = target_read_memory(pPrivate->pChip->target,
3024                         adr,
3025                         4,                                      /* THIS*MUST*BE* in 32bit values */
3026                         pPrivate->page_size / 4,
3027                         buf);
3028         if (r != ERROR_OK)
3029                 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3030                         (unsigned int)(adr));
3031         return r;
3032 }
3033
3034 /* The code below is basically this: */
3035 /* compiled with */
3036 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
3037 /*  */
3038 /* Only the *CPU* can write to the flash buffer. */
3039 /* the DAP cannot... so - we download this 28byte thing */
3040 /* Run the algorithm - (below) */
3041 /* to program the device */
3042 /*  */
3043 /* ======================================== */
3044 /* #include <stdint.h> */
3045 /*  */
3046 /* struct foo { */
3047 /*   uint32_t *dst; */
3048 /*   const uint32_t *src; */
3049 /*   int   n; */
3050 /*   volatile uint32_t *base; */
3051 /*   uint32_t   cmd; */
3052 /* }; */
3053 /*  */
3054 /*  */
3055 /* uint32_t sam3_function(struct foo *p) */
3056 /* { */
3057 /*   volatile uint32_t *v; */
3058 /*   uint32_t *d; */
3059 /*   const uint32_t *s; */
3060 /*   int   n; */
3061 /*   uint32_t r; */
3062 /*  */
3063 /*   d = p->dst; */
3064 /*   s = p->src; */
3065 /*   n = p->n; */
3066 /*  */
3067 /*   do { */
3068 /*     *d++ = *s++; */
3069 /*   } while (--n) */
3070 /*     ; */
3071 /*  */
3072 /*   v = p->base; */
3073 /*  */
3074 /*   v[ 1 ] = p->cmd; */
3075 /*   do { */
3076 /*     r = v[8/4]; */
3077 /*   } while (!(r&1)) */
3078 /*     ; */
3079 /*   return r; */
3080 /* } */
3081 /* ======================================== */
3082
3083 static const uint8_t
3084         sam3_page_write_opcodes[] = {
3085         /*  24 0000 0446                mov     r4, r0 */
3086         0x04, 0x46,
3087         /*  25 0002 6168                ldr     r1, [r4, #4] */
3088         0x61, 0x68,
3089         /*  26 0004 0068                ldr     r0, [r0, #0] */
3090         0x00, 0x68,
3091         /*  27 0006 A268                ldr     r2, [r4, #8] */
3092         0xa2, 0x68,
3093         /*  28                          @ lr needed for prologue */
3094         /*  29                  .L2: */
3095         /*  30 0008 51F8043B            ldr     r3, [r1], #4 */
3096         0x51, 0xf8, 0x04, 0x3b,
3097         /*  31 000c 12F1FF32            adds    r2, r2, #-1 */
3098         0x12, 0xf1, 0xff, 0x32,
3099         /*  32 0010 40F8043B            str     r3, [r0], #4 */
3100         0x40, 0xf8, 0x04, 0x3b,
3101         /*  33 0014 F8D1                bne     .L2 */
3102         0xf8, 0xd1,
3103         /*  34 0016 E268                ldr     r2, [r4, #12] */
3104         0xe2, 0x68,
3105         /*  35 0018 2369                ldr     r3, [r4, #16] */
3106         0x23, 0x69,
3107         /*  36 001a 5360                str     r3, [r2, #4] */
3108         0x53, 0x60,
3109         /*  37 001c 0832                adds    r2, r2, #8 */
3110         0x08, 0x32,
3111         /*  38                  .L4: */
3112         /*  39 001e 1068                ldr     r0, [r2, #0] */
3113         0x10, 0x68,
3114         /*  40 0020 10F0010F            tst     r0, #1 */
3115         0x10, 0xf0, 0x01, 0x0f,
3116         /*  41 0024 FBD0                beq     .L4 */
3117         0xfb, 0xd0,
3118         0x00, 0xBE                              /* bkpt #0 */
3119 };
3120
3121 static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3122 {
3123         uint32_t adr;
3124         uint32_t status;
3125         uint32_t fmr;   /* EEFC Flash Mode Register */
3126         int r;
3127
3128         adr = pagenum * pPrivate->page_size;
3129         adr += (adr + pPrivate->base_address);
3130
3131         /* Get flash mode register value */
3132         r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
3133         if (r != ERROR_OK)
3134                 LOG_DEBUG("Error Read failed: read flash mode register");
3135
3136         /* Clear flash wait state field */
3137         fmr &= 0xfffff0ff;
3138
3139         /* set FWS (flash wait states) field in the FMR (flash mode register) */
3140         fmr |= (pPrivate->flash_wait_states << 8);
3141
3142         LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3143         r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
3144         if (r != ERROR_OK)
3145                 LOG_DEBUG("Error Write failed: set flash mode register");
3146
3147         LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3148         r = target_write_memory(pPrivate->pChip->target,
3149                         adr,
3150                         4,                                      /* THIS*MUST*BE* in 32bit values */
3151                         pPrivate->page_size / 4,
3152                         buf);
3153         if (r != ERROR_OK) {
3154                 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3155                         (unsigned int)(adr));
3156                 return r;
3157         }
3158
3159         r = EFC_PerformCommand(pPrivate,
3160                         /* send Erase & Write Page */
3161                         AT91C_EFC_FCMD_EWP,
3162                         pagenum,
3163                         &status);
3164
3165         if (r != ERROR_OK)
3166                 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3167                         (unsigned int)(adr));
3168         if (status & (1 << 2)) {
3169                 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3170                 return ERROR_FAIL;
3171         }
3172         if (status & (1 << 1)) {
3173                 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3174                 return ERROR_FAIL;
3175         }
3176         return ERROR_OK;
3177 }
3178
3179 static int sam3_write(struct flash_bank *bank,
3180         uint8_t *buffer,
3181         uint32_t offset,
3182         uint32_t count)
3183 {
3184         int n;
3185         unsigned page_cur;
3186         unsigned page_end;
3187         int r;
3188         unsigned page_offset;
3189         struct sam3_bank_private *pPrivate;
3190         uint8_t *pagebuffer;
3191
3192         /* incase we bail further below, set this to null */
3193         pagebuffer = NULL;
3194
3195         /* ignore dumb requests */
3196         if (count == 0) {
3197                 r = ERROR_OK;
3198                 goto done;
3199         }
3200
3201         if (bank->target->state != TARGET_HALTED) {
3202                 LOG_ERROR("Target not halted");
3203                 r = ERROR_TARGET_NOT_HALTED;
3204                 goto done;
3205         }
3206
3207         pPrivate = get_sam3_bank_private(bank);
3208         if (!(pPrivate->probed)) {
3209                 r = ERROR_FLASH_BANK_NOT_PROBED;
3210                 goto done;
3211         }
3212
3213         if ((offset + count) > pPrivate->size_bytes) {
3214                 LOG_ERROR("Flash write error - past end of bank");
3215                 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3216                         (unsigned int)(offset),
3217                         (unsigned int)(count),
3218                         (unsigned int)(pPrivate->size_bytes));
3219                 r = ERROR_FAIL;
3220                 goto done;
3221         }
3222
3223         pagebuffer = malloc(pPrivate->page_size);
3224         if (!pagebuffer) {
3225                 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
3226                 r = ERROR_FAIL;
3227                 goto done;
3228         }
3229
3230         /* what page do we start & end in? */
3231         page_cur = offset / pPrivate->page_size;
3232         page_end = (offset + count - 1) / pPrivate->page_size;
3233
3234         LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3235         LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3236
3237         /* Special case: all one page */
3238         /*  */
3239         /* Otherwise: */
3240         /*    (1) non-aligned start */
3241         /*    (2) body pages */
3242         /*    (3) non-aligned end. */
3243
3244         /* Handle special case - all one page. */
3245         if (page_cur == page_end) {
3246                 LOG_DEBUG("Special case, all in one page");
3247                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3248                 if (r != ERROR_OK)
3249                         goto done;
3250
3251                 page_offset = (offset & (pPrivate->page_size-1));
3252                 memcpy(pagebuffer + page_offset,
3253                         buffer,
3254                         count);
3255
3256                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3257                 if (r != ERROR_OK)
3258                         goto done;
3259                 r = ERROR_OK;
3260                 goto done;
3261         }
3262
3263         /* non-aligned start */
3264         page_offset = offset & (pPrivate->page_size - 1);
3265         if (page_offset) {
3266                 LOG_DEBUG("Not-Aligned start");
3267                 /* read the partial */
3268                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3269                 if (r != ERROR_OK)
3270                         goto done;
3271
3272                 /* over-write with new data */
3273                 n = (pPrivate->page_size - page_offset);
3274                 memcpy(pagebuffer + page_offset,
3275                         buffer,
3276                         n);
3277
3278                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3279                 if (r != ERROR_OK)
3280                         goto done;
3281
3282                 count  -= n;
3283                 offset += n;
3284                 buffer += n;
3285                 page_cur++;
3286         }
3287
3288         /* By checking that offset is correct here, we also
3289         fix a clang warning */
3290         assert(offset % pPrivate->page_size == 0);
3291
3292         /* intermediate large pages */
3293         /* also - the final *terminal* */
3294         /* if that terminal page is a full page */
3295         LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3296                 (int)page_cur, (int)page_end, (unsigned int)(count));
3297
3298         while ((page_cur < page_end) &&
3299                         (count >= pPrivate->page_size)) {
3300                 r = sam3_page_write(pPrivate, page_cur, buffer);
3301                 if (r != ERROR_OK)
3302                         goto done;
3303                 count -= pPrivate->page_size;
3304                 buffer += pPrivate->page_size;
3305                 page_cur += 1;
3306         }
3307
3308         /* terminal partial page? */
3309         if (count) {
3310                 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3311                 /* we have a partial page */
3312                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3313                 if (r != ERROR_OK)
3314                         goto done;
3315                                         /* data goes at start */
3316                 memcpy(pagebuffer, buffer, count);
3317                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3318                 if (r != ERROR_OK)
3319                         goto done;
3320         }
3321         LOG_DEBUG("Done!");
3322         r = ERROR_OK;
3323 done:
3324         if (pagebuffer)
3325                 free(pagebuffer);
3326         return r;
3327 }
3328
3329 COMMAND_HANDLER(sam3_handle_info_command)
3330 {
3331         struct sam3_chip *pChip;
3332         pChip = get_current_sam3(CMD_CTX);
3333         if (!pChip)
3334                 return ERROR_OK;
3335
3336         unsigned x;
3337         int r;
3338
3339         /* bank0 must exist before we can do anything */
3340         if (pChip->details.bank[0].pBank == NULL) {
3341                 x = 0;
3342 need_define:
3343                 command_print(CMD_CTX,
3344                         "Please define bank %d via command: flash bank %s ... ",
3345                         x,
3346                         at91sam3_flash.name);
3347                 return ERROR_FAIL;
3348         }
3349
3350         /* if bank 0 is not probed, then probe it */
3351         if (!(pChip->details.bank[0].probed)) {
3352                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3353                 if (r != ERROR_OK)
3354                         return ERROR_FAIL;
3355         }
3356         /* above guarantees the "chip details" structure is valid */
3357         /* and thus, bank private areas are valid */
3358         /* and we have a SAM3 chip, what a concept! */
3359
3360         /* auto-probe other banks, 0 done above */
3361         for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3362                 /* skip banks not present */
3363                 if (!(pChip->details.bank[x].present))
3364                         continue;
3365
3366                 if (pChip->details.bank[x].pBank == NULL)
3367                         goto need_define;
3368
3369                 if (pChip->details.bank[x].probed)
3370                         continue;
3371
3372                 r = sam3_auto_probe(pChip->details.bank[x].pBank);
3373                 if (r != ERROR_OK)
3374                         return r;
3375         }
3376
3377         r = sam3_GetInfo(pChip);
3378         if (r != ERROR_OK) {
3379                 LOG_DEBUG("Sam3Info, Failed %d", r);
3380                 return r;
3381         }
3382
3383         return ERROR_OK;
3384 }
3385
3386 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3387 {
3388         unsigned x, v;
3389         int r, who;
3390         struct sam3_chip *pChip;
3391
3392         pChip = get_current_sam3(CMD_CTX);
3393         if (!pChip)
3394                 return ERROR_OK;
3395
3396         if (pChip->target->state != TARGET_HALTED) {
3397                 LOG_ERROR("sam3 - target not halted");
3398                 return ERROR_TARGET_NOT_HALTED;
3399         }
3400
3401         if (pChip->details.bank[0].pBank == NULL) {
3402                 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3403                         at91sam3_flash.name);
3404                 return ERROR_FAIL;
3405         }
3406         if (!pChip->details.bank[0].probed) {
3407                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3408                 if (r != ERROR_OK)
3409                         return r;
3410         }
3411
3412         switch (CMD_ARGC) {
3413                 default:
3414                         return ERROR_COMMAND_SYNTAX_ERROR;
3415                         break;
3416                 case 0:
3417                         goto showall;
3418                         break;
3419                 case 1:
3420                         who = -1;
3421                         break;
3422                 case 2:
3423                         if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3424                                 who = -1;
3425                         else {
3426                                 uint32_t v32;
3427                                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3428                                 who = v32;
3429                         }
3430                         break;
3431         }
3432
3433         if (0 == strcmp("show", CMD_ARGV[0])) {
3434                 if (who == -1) {
3435 showall:
3436                         r = ERROR_OK;
3437                         for (x = 0; x < pChip->details.n_gpnvms; x++) {
3438                                 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3439                                 if (r != ERROR_OK)
3440                                         break;
3441                                 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
3442                         }
3443                         return r;
3444                 }
3445                 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3446                         r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3447                         command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
3448                         return r;
3449                 } else {
3450                         command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
3451                         return ERROR_COMMAND_SYNTAX_ERROR;
3452                 }
3453         }
3454
3455         if (who == -1) {
3456                 command_print(CMD_CTX, "Missing GPNVM number");
3457                 return ERROR_COMMAND_SYNTAX_ERROR;
3458         }
3459
3460         if (0 == strcmp("set", CMD_ARGV[0]))
3461                 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3462         else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3463                  (0 == strcmp("clear", CMD_ARGV[0])))                   /* quietly accept both */
3464                 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3465         else {
3466                 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3467                 r = ERROR_COMMAND_SYNTAX_ERROR;
3468         }
3469         return r;
3470 }
3471
3472 COMMAND_HANDLER(sam3_handle_slowclk_command)
3473 {
3474         struct sam3_chip *pChip;
3475
3476         pChip = get_current_sam3(CMD_CTX);
3477         if (!pChip)
3478                 return ERROR_OK;
3479
3480         switch (CMD_ARGC) {
3481                 case 0:
3482                         /* show */
3483                         break;
3484                 case 1:
3485                 {
3486                         /* set */
3487                         uint32_t v;
3488                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3489                         if (v > 200000) {
3490                                 /* absurd slow clock of 200Khz? */
3491                                 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3492                                 return ERROR_COMMAND_SYNTAX_ERROR;
3493                         }
3494                         pChip->cfg.slow_freq = v;
3495                         break;
3496                 }
3497                 default:
3498                         /* error */
3499                         command_print(CMD_CTX, "Too many parameters");
3500                         return ERROR_COMMAND_SYNTAX_ERROR;
3501                         break;
3502         }
3503         command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3504                 (int)(pChip->cfg.slow_freq / 1000),
3505                 (int)(pChip->cfg.slow_freq % 1000));
3506         return ERROR_OK;
3507 }
3508
3509 static const struct command_registration at91sam3_exec_command_handlers[] = {
3510         {
3511                 .name = "gpnvm",
3512                 .handler = sam3_handle_gpnvm_command,
3513                 .mode = COMMAND_EXEC,
3514                 .usage = "[('clr'|'set'|'show') bitnum]",
3515                 .help = "Without arguments, shows all bits in the gpnvm "
3516                         "register.  Otherwise, clears, sets, or shows one "
3517                         "General Purpose Non-Volatile Memory (gpnvm) bit.",
3518         },
3519         {
3520                 .name = "info",
3521                 .handler = sam3_handle_info_command,
3522                 .mode = COMMAND_EXEC,
3523                 .help = "Print information about the current at91sam3 chip"
3524                         "and its flash configuration.",
3525         },
3526         {
3527                 .name = "slowclk",
3528                 .handler = sam3_handle_slowclk_command,
3529                 .mode = COMMAND_EXEC,
3530                 .usage = "[clock_hz]",
3531                 .help = "Display or set the slowclock frequency "
3532                         "(default 32768 Hz).",
3533         },
3534         COMMAND_REGISTRATION_DONE
3535 };
3536 static const struct command_registration at91sam3_command_handlers[] = {
3537         {
3538                 .name = "at91sam3",
3539                 .mode = COMMAND_ANY,
3540                 .help = "at91sam3 flash command group",
3541                 .usage = "",
3542                 .chain = at91sam3_exec_command_handlers,
3543         },
3544         COMMAND_REGISTRATION_DONE
3545 };
3546
3547 struct flash_driver at91sam3_flash = {
3548         .name = "at91sam3",
3549         .commands = at91sam3_command_handlers,
3550         .flash_bank_command = sam3_flash_bank_command,
3551         .erase = sam3_erase,
3552         .protect = sam3_protect,
3553         .write = sam3_write,
3554         .read = default_flash_read,
3555         .probe = sam3_probe,
3556         .auto_probe = sam3_auto_probe,
3557         .erase_check = sam3_erase_check,
3558         .protect_check = sam3_protect_check,
3559         .info = sam3_info,
3560 };