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   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3
   4 /***************************************************************************
   5  *   Copyright (C) 2009 by Alexei Babich                                   *
   6  *   Rezonans plc., Chelyabinsk, Russia                                    *
   7  *   impatt@mail.ru                                                        *
   8  ***************************************************************************/
   9
  10 /*
  11  * Freescale iMX3* OpenOCD NAND Flash controller support.
  12  *
  13  * Many thanks to Ben Dooks for writing s3c24xx driver.
  14  */
  15
  16 /*
  17 driver tested with STMicro NAND512W3A @imx31
  18 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
  19 get_next_halfword_from_sram_buffer() not tested
  20 */
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "imp.h"
  26 #include "mx3.h"
  27 #include <target/target.h>
  28
  29 static const char target_not_halted_err_msg[] =
  30                 "target must be halted to use mx3 NAND flash controller";
  31 static const char data_block_size_err_msg[] =
  32                 "minimal granularity is one half-word, %" PRIu32 " is incorrect";
  33 static const char sram_buffer_bounds_err_msg[] =
  34                 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  35 static const char get_status_register_err_msg[] = "can't get NAND status";
  36 static uint32_t in_sram_address;
  37 static unsigned char sign_of_sequental_byte_read;
  38
  39 static int test_iomux_settings(struct target *target, uint32_t value,
  40                 uint32_t mask, const char *text);
  41 static int initialize_nf_controller(struct nand_device *nand);
  42 static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value);
  43 static int get_next_halfword_from_sram_buffer(struct target *target,
  44                 uint16_t *value);
  45 static int poll_for_complete_op(struct target *target, const char *text);
  46 static int validate_target_state(struct nand_device *nand);
  47 static int do_data_output(struct nand_device *nand);
  48
  49 static int imx31_command(struct nand_device *nand, uint8_t command);
  50 static int imx31_address(struct nand_device *nand, uint8_t address);
  51
  52 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
  53 {
  54         struct mx3_nf_controller *mx3_nf_info;
  55         mx3_nf_info = malloc(sizeof(struct mx3_nf_controller));
  56         if (!mx3_nf_info) {
  57                 LOG_ERROR("no memory for nand controller");
  58                 return ERROR_FAIL;
  59         }
  60
  61         nand->controller_priv = mx3_nf_info;
  62
  63         if (CMD_ARGC < 3)
  64                 return ERROR_COMMAND_SYNTAX_ERROR;
  65         /*
  66         * check hwecc requirements
  67         */
  68         {
  69                 int hwecc_needed;
  70                 hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
  71                 if (hwecc_needed == 0)
  72                         mx3_nf_info->flags.hw_ecc_enabled = 1;
  73                 else
  74                         mx3_nf_info->flags.hw_ecc_enabled = 0;
  75         }
  76
  77         mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
  78         mx3_nf_info->fin = MX3_NF_FIN_NONE;
  79         mx3_nf_info->flags.target_little_endian =
  80                         (nand->target->endianness == TARGET_LITTLE_ENDIAN);
  81
  82         return ERROR_OK;
  83 }
  84
  85 static int imx31_init(struct nand_device *nand)
  86 {
  87         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
  88         struct target *target = nand->target;
  89
  90         {
  91                 /*
  92                  * validate target state
  93                  */
  94                 int validate_target_result;
  95                 validate_target_result = validate_target_state(nand);
  96                 if (validate_target_result != ERROR_OK)
  97                         return validate_target_result;
  98         }
  99
 100         {
 101                 uint16_t buffsize_register_content;
 102                 target_read_u16(target, MX3_NF_BUFSIZ, &buffsize_register_content);
 103                 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 104         }
 105
 106         {
 107                 uint32_t pcsr_register_content;
 108                 target_read_u32(target, MX3_PCSR, &pcsr_register_content);
 109                 if (!nand->bus_width) {
 110                         nand->bus_width = (pcsr_register_content & 0x80000000) ? 16 : 8;
 111                 } else {
 112                         pcsr_register_content |= ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
 113                         target_write_u32(target, MX3_PCSR, pcsr_register_content);
 114                 }
 115
 116                 if (!nand->page_size) {
 117                         nand->page_size = (pcsr_register_content & 0x40000000) ? 2048 : 512;
 118                 } else {
 119                         pcsr_register_content |= ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
 120                         target_write_u32(target, MX3_PCSR, pcsr_register_content);
 121                 }
 122                 if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
 123                         LOG_ERROR("NAND controller have only 1 kb SRAM, "
 124                                         "so pagesize 2048 is incompatible with it");
 125                 }
 126         }
 127
 128         {
 129                 uint32_t cgr_register_content;
 130                 target_read_u32(target, MX3_CCM_CGR2, &cgr_register_content);
 131                 if (!(cgr_register_content & 0x00000300)) {
 132                         LOG_ERROR("clock gating to EMI disabled");
 133                         return ERROR_FAIL;
 134                 }
 135         }
 136
 137         {
 138                 uint32_t gpr_register_content;
 139                 target_read_u32(target, MX3_GPR, &gpr_register_content);
 140                 if (gpr_register_content & 0x00000060) {
 141                         LOG_ERROR("pins mode overridden by GPR");
 142                         return ERROR_FAIL;
 143                 }
 144         }
 145
 146         {
 147                 /*
 148                  * testing IOMUX settings; must be in "functional-mode output and
 149                  * functional-mode input" mode
 150                  */
 151                 int test_iomux;
 152                 test_iomux = ERROR_OK;
 153                 test_iomux |= test_iomux_settings(target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
 154                 test_iomux |= test_iomux_settings(target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
 155                 test_iomux |= test_iomux_settings(target, 0x43fac0c8, 0x0000007f, "d7");
 156                 if (nand->bus_width == 16) {
 157                         test_iomux |= test_iomux_settings(target, 0x43fac0c8, 0x7f7f7f00, "d8,d9,d10");
 158                         test_iomux |= test_iomux_settings(target, 0x43fac0cc, 0x7f7f7f7f, "d11,d12,d13,d14");
 159                         test_iomux |= test_iomux_settings(target, 0x43fac0d0, 0x0000007f, "d15");
 160                 }
 161                 test_iomux |= test_iomux_settings(target, 0x43fac0d0, 0x7f7f7f00, "nfwp,nfce,nfrb");
 162                 test_iomux |= test_iomux_settings(target, 0x43fac0d4, 0x7f7f7f7f,
 163                                 "nfwe,nfre,nfale,nfcle");
 164                 if (test_iomux != ERROR_OK)
 165                         return ERROR_FAIL;
 166         }
 167
 168         initialize_nf_controller(nand);
 169
 170         {
 171                 int retval;
 172                 uint16_t nand_status_content;
 173                 retval = ERROR_OK;
 174                 retval |= imx31_command(nand, NAND_CMD_STATUS);
 175                 retval |= imx31_address(nand, 0x00);
 176                 retval |= do_data_output(nand);
 177                 if (retval != ERROR_OK) {
 178                         LOG_ERROR(get_status_register_err_msg);
 179                         return ERROR_FAIL;
 180                 }
 181                 target_read_u16(target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
 182                 if (!(nand_status_content & 0x0080)) {
 183                         /*
 184                          * is host-big-endian correctly ??
 185                          */
 186                         LOG_INFO("NAND read-only");
 187                         mx3_nf_info->flags.nand_readonly = 1;
 188                 } else
 189                         mx3_nf_info->flags.nand_readonly = 0;
 190         }
 191         return ERROR_OK;
 192 }
 193
 194 static int imx31_read_data(struct nand_device *nand, void *data)
 195 {
 196         struct target *target = nand->target;
 197         {
 198                 /*
 199                  * validate target state
 200                  */
 201                 int validate_target_result;
 202                 validate_target_result = validate_target_state(nand);
 203                 if (validate_target_result != ERROR_OK)
 204                         return validate_target_result;
 205         }
 206
 207         {
 208                 /*
 209                  * get data from nand chip
 210                  */
 211                 int try_data_output_from_nand_chip;
 212                 try_data_output_from_nand_chip = do_data_output(nand);
 213                 if (try_data_output_from_nand_chip != ERROR_OK)
 214                         return try_data_output_from_nand_chip;
 215         }
 216
 217         if (nand->bus_width == 16)
 218                 get_next_halfword_from_sram_buffer(target, data);
 219         else
 220                 get_next_byte_from_sram_buffer(target, data);
 221
 222         return ERROR_OK;
 223 }
 224
 225 static int imx31_write_data(struct nand_device *nand, uint16_t data)
 226 {
 227         LOG_ERROR("write_data() not implemented");
 228         return ERROR_NAND_OPERATION_FAILED;
 229 }
 230
 231 static int imx31_reset(struct nand_device *nand)
 232 {
 233         /*
 234         * validate target state
 235         */
 236         int validate_target_result;
 237         validate_target_result = validate_target_state(nand);
 238         if (validate_target_result != ERROR_OK)
 239                 return validate_target_result;
 240         initialize_nf_controller(nand);
 241         return ERROR_OK;
 242 }
 243
 244 static int imx31_command(struct nand_device *nand, uint8_t command)
 245 {
 246         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 247         struct target *target = nand->target;
 248         {
 249                 /*
 250                  * validate target state
 251                  */
 252                 int validate_target_result;
 253                 validate_target_result = validate_target_state(nand);
 254                 if (validate_target_result != ERROR_OK)
 255                         return validate_target_result;
 256         }
 257
 258         switch (command) {
 259                 case NAND_CMD_READOOB:
 260                         command = NAND_CMD_READ0;
 261                         in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
 262                                                                 * data_read() and
 263                                                                 * read_block_data() to
 264                                                                 * spare area in SRAM
 265                                                                 * buffer */
 266                         break;
 267                 case NAND_CMD_READ1:
 268                         command = NAND_CMD_READ0;
 269                         /*
 270                          * offset == one half of page size
 271                          */
 272                         in_sram_address = MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 273                         break;
 274                 default:
 275                         in_sram_address = MX3_NF_MAIN_BUFFER0;
 276         }
 277
 278         target_write_u16(target, MX3_NF_FCMD, command);
 279         /*
 280         * start command input operation (set MX3_NF_BIT_OP_DONE==0)
 281         */
 282         target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
 283         {
 284                 int poll_result;
 285                 poll_result = poll_for_complete_op(target, "command");
 286                 if (poll_result != ERROR_OK)
 287                         return poll_result;
 288         }
 289         /*
 290         * reset cursor to begin of the buffer
 291         */
 292         sign_of_sequental_byte_read = 0;
 293         switch (command) {
 294                 case NAND_CMD_READID:
 295                         mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
 296                         mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 297                         break;
 298                 case NAND_CMD_STATUS:
 299                         mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
 300                         mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 301                         break;
 302                 case NAND_CMD_READ0:
 303                         mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 304                         mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
 305                         break;
 306                 default:
 307                         mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
 308         }
 309         return ERROR_OK;
 310 }
 311
 312 static int imx31_address(struct nand_device *nand, uint8_t address)
 313 {
 314         struct target *target = nand->target;
 315         {
 316                 /*
 317                  * validate target state
 318                  */
 319                 int validate_target_result;
 320                 validate_target_result = validate_target_state(nand);
 321                 if (validate_target_result != ERROR_OK)
 322                         return validate_target_result;
 323         }
 324
 325         target_write_u16(target, MX3_NF_FADDR, address);
 326         /*
 327         * start address input operation (set MX3_NF_BIT_OP_DONE==0)
 328         */
 329         target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
 330         {
 331                 int poll_result;
 332                 poll_result = poll_for_complete_op(target, "address");
 333                 if (poll_result != ERROR_OK)
 334                         return poll_result;
 335         }
 336         return ERROR_OK;
 337 }
 338
 339 static int imx31_nand_ready(struct nand_device *nand, int tout)
 340 {
 341         uint16_t poll_complete_status;
 342         struct target *target = nand->target;
 343
 344         {
 345                 /*
 346                  * validate target state
 347                  */
 348                 int validate_target_result;
 349                 validate_target_result = validate_target_state(nand);
 350                 if (validate_target_result != ERROR_OK)
 351                         return validate_target_result;
 352         }
 353
 354         do {
 355                 target_read_u16(target, MX3_NF_CFG2, &poll_complete_status);
 356                 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
 357                         return tout;
 358                 alive_sleep(1);
 359         } while (tout-- > 0);
 360         return tout;
 361 }
 362
 363 static int imx31_write_page(struct nand_device *nand, uint32_t page,
 364                 uint8_t *data, uint32_t data_size, uint8_t *oob,
 365                 uint32_t oob_size)
 366 {
 367         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 368         struct target *target = nand->target;
 369
 370         if (data_size % 2) {
 371                 LOG_ERROR(data_block_size_err_msg, data_size);
 372                 return ERROR_NAND_OPERATION_FAILED;
 373         }
 374         if (oob_size % 2) {
 375                 LOG_ERROR(data_block_size_err_msg, oob_size);
 376                 return ERROR_NAND_OPERATION_FAILED;
 377         }
 378         if (!data) {
 379                 LOG_ERROR("nothing to program");
 380                 return ERROR_NAND_OPERATION_FAILED;
 381         }
 382         {
 383                 /*
 384                  * validate target state
 385                  */
 386                 int retval;
 387                 retval = validate_target_state(nand);
 388                 if (retval != ERROR_OK)
 389                         return retval;
 390         }
 391         {
 392                 int retval = ERROR_OK;
 393                 retval |= imx31_command(nand, NAND_CMD_SEQIN);
 394                 retval |= imx31_address(nand, 0x00);
 395                 retval |= imx31_address(nand, page & 0xff);
 396                 retval |= imx31_address(nand, (page >> 8) & 0xff);
 397                 if (nand->address_cycles >= 4) {
 398                         retval |= imx31_address(nand, (page >> 16) & 0xff);
 399                         if (nand->address_cycles >= 5)
 400                                 retval |= imx31_address(nand, (page >> 24) & 0xff);
 401                 }
 402                 target_write_buffer(target, MX3_NF_MAIN_BUFFER0, data_size, data);
 403                 if (oob) {
 404                         if (mx3_nf_info->flags.hw_ecc_enabled) {
 405                                 /*
 406                                  * part of spare block will be overridden by hardware
 407                                  * ECC generator
 408                                  */
 409                                 LOG_DEBUG("part of spare block will be overridden by hardware ECC generator");
 410                         }
 411                         target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
 412                 }
 413                 /*
 414                  * start data input operation (set MX3_NF_BIT_OP_DONE==0)
 415                  */
 416                 target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
 417                 {
 418                         int poll_result;
 419                         poll_result = poll_for_complete_op(target, "data input");
 420                         if (poll_result != ERROR_OK)
 421                                 return poll_result;
 422                 }
 423                 retval |= imx31_command(nand, NAND_CMD_PAGEPROG);
 424                 if (retval != ERROR_OK)
 425                         return retval;
 426
 427                 /*
 428                  * check status register
 429                  */
 430                 {
 431                         uint16_t nand_status_content;
 432                         retval = ERROR_OK;
 433                         retval |= imx31_command(nand, NAND_CMD_STATUS);
 434                         retval |= imx31_address(nand, 0x00);
 435                         retval |= do_data_output(nand);
 436                         if (retval != ERROR_OK) {
 437                                 LOG_ERROR(get_status_register_err_msg);
 438                                 return retval;
 439                         }
 440                         target_read_u16(target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
 441                         if (nand_status_content & 0x0001) {
 442                                 /*
 443                                  * is host-big-endian correctly ??
 444                                  */
 445                                 return ERROR_NAND_OPERATION_FAILED;
 446                         }
 447                 }
 448         }
 449         return ERROR_OK;
 450 }
 451
 452 static int imx31_read_page(struct nand_device *nand, uint32_t page,
 453                 uint8_t *data, uint32_t data_size, uint8_t *oob,
 454                 uint32_t oob_size)
 455 {
 456         struct target *target = nand->target;
 457
 458         if (data_size % 2) {
 459                 LOG_ERROR(data_block_size_err_msg, data_size);
 460                 return ERROR_NAND_OPERATION_FAILED;
 461         }
 462         if (oob_size % 2) {
 463                 LOG_ERROR(data_block_size_err_msg, oob_size);
 464                 return ERROR_NAND_OPERATION_FAILED;
 465         }
 466
 467         {
 468                 /*
 469                  * validate target state
 470                  */
 471                 int retval;
 472                 retval = validate_target_state(nand);
 473                 if (retval != ERROR_OK)
 474                         return retval;
 475         }
 476         {
 477                 int retval = ERROR_OK;
 478                 retval |= imx31_command(nand, NAND_CMD_READ0);
 479                 retval |= imx31_address(nand, 0x00);
 480                 retval |= imx31_address(nand, page & 0xff);
 481                 retval |= imx31_address(nand, (page >> 8) & 0xff);
 482                 if (nand->address_cycles >= 4) {
 483                         retval |= imx31_address(nand, (page >> 16) & 0xff);
 484                         if (nand->address_cycles >= 5) {
 485                                 retval |= imx31_address(nand, (page >> 24) & 0xff);
 486                                 retval |= imx31_command(nand, NAND_CMD_READSTART);
 487                         }
 488                 }
 489                 retval |= do_data_output(nand);
 490                 if (retval != ERROR_OK)
 491                         return retval;
 492
 493                 if (data) {
 494                         target_read_buffer(target, MX3_NF_MAIN_BUFFER0, data_size,
 495                                 data);
 496                 }
 497                 if (oob) {
 498                         target_read_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size,
 499                                 oob);
 500                 }
 501         }
 502         return ERROR_OK;
 503 }
 504
 505 static int test_iomux_settings(struct target *target, uint32_t address,
 506                 uint32_t mask, const char *text)
 507 {
 508         uint32_t register_content;
 509         target_read_u32(target, address, &register_content);
 510         if ((register_content & mask) != (0x12121212 & mask)) {
 511                 LOG_ERROR("IOMUX for {%s} is bad", text);
 512                 return ERROR_FAIL;
 513         }
 514         return ERROR_OK;
 515 }
 516
 517 static int initialize_nf_controller(struct nand_device *nand)
 518 {
 519         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 520         struct target *target = nand->target;
 521         /*
 522         * resets NAND flash controller in zero time ? I don't know.
 523         */
 524         target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
 525         {
 526                 uint16_t work_mode;
 527                 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
 528                 if (target->endianness == TARGET_BIG_ENDIAN)
 529                         work_mode |= MX3_NF_BIT_BE_EN;
 530                 if (mx3_nf_info->flags.hw_ecc_enabled)
 531                         work_mode |= MX3_NF_BIT_ECC_EN;
 532                 target_write_u16(target, MX3_NF_CFG1, work_mode);
 533         }
 534         /*
 535         * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 536         */
 537         target_write_u16(target, MX3_NF_BUFCFG, 2);
 538         {
 539                 uint16_t temp;
 540                 target_read_u16(target, MX3_NF_FWP, &temp);
 541                 if ((temp & 0x0007) == 1) {
 542                         LOG_ERROR("NAND flash is tight-locked, reset needed");
 543                         return ERROR_FAIL;
 544                 }
 545
 546         }
 547         /*
 548         * unlock NAND flash for write
 549         */
 550         target_write_u16(target, MX3_NF_FWP, 4);
 551         target_write_u16(target, MX3_NF_LOCKSTART, 0x0000);
 552         target_write_u16(target, MX3_NF_LOCKEND, 0xFFFF);
 553         /*
 554         * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
 555         */
 556         target_write_u16(target, MX3_NF_BUFADDR, 0x0000);
 557         /*
 558         * address of SRAM buffer
 559         */
 560         in_sram_address = MX3_NF_MAIN_BUFFER0;
 561         sign_of_sequental_byte_read = 0;
 562         return ERROR_OK;
 563 }
 564
 565 static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value)
 566 {
 567         static uint8_t even_byte;
 568         /*
 569         * host-big_endian ??
 570         */
 571         if (sign_of_sequental_byte_read == 0)
 572                 even_byte = 0;
 573         if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) {
 574                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 575                 *value = 0;
 576                 sign_of_sequental_byte_read = 0;
 577                 even_byte = 0;
 578                 return ERROR_NAND_OPERATION_FAILED;
 579         } else {
 580                 uint16_t temp;
 581                 target_read_u16(target, in_sram_address, &temp);
 582                 if (even_byte) {
 583                         *value = temp >> 8;
 584                         even_byte = 0;
 585                         in_sram_address += 2;
 586                 } else {
 587                         *value = temp & 0xff;
 588                         even_byte = 1;
 589                 }
 590         }
 591         sign_of_sequental_byte_read = 1;
 592         return ERROR_OK;
 593 }
 594
 595 static int get_next_halfword_from_sram_buffer(struct target *target,
 596                 uint16_t *value)
 597 {
 598         if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) {
 599                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 600                 *value = 0;
 601                 return ERROR_NAND_OPERATION_FAILED;
 602         } else {
 603                 target_read_u16(target, in_sram_address, value);
 604                 in_sram_address += 2;
 605         }
 606         return ERROR_OK;
 607 }
 608
 609 static int poll_for_complete_op(struct target *target, const char *text)
 610 {
 611         uint16_t poll_complete_status;
 612         for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
 613                 usleep(25);
 614                 target_read_u16(target, MX3_NF_CFG2, &poll_complete_status);
 615                 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
 616                         break;
 617         }
 618         if (!(poll_complete_status & MX3_NF_BIT_OP_DONE)) {
 619                 LOG_ERROR("%s sending timeout", text);
 620                 return ERROR_NAND_OPERATION_FAILED;
 621         }
 622         return ERROR_OK;
 623 }
 624
 625 static int validate_target_state(struct nand_device *nand)
 626 {
 627         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 628         struct target *target = nand->target;
 629
 630         if (target->state != TARGET_HALTED) {
 631                 LOG_ERROR(target_not_halted_err_msg);
 632                 return ERROR_NAND_OPERATION_FAILED;
 633         }
 634
 635         if (mx3_nf_info->flags.target_little_endian !=
 636                         (target->endianness == TARGET_LITTLE_ENDIAN)) {
 637                 /*
 638                  * endianness changed after NAND controller probed
 639                  */
 640                 return ERROR_NAND_OPERATION_FAILED;
 641         }
 642         return ERROR_OK;
 643 }
 644
 645 static int do_data_output(struct nand_device *nand)
 646 {
 647         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 648         struct target *target = nand->target;
 649         switch (mx3_nf_info->fin) {
 650                 case MX3_NF_FIN_DATAOUT:
 651                         /*
 652                          * start data output operation (set MX3_NF_BIT_OP_DONE==0)
 653                          */
 654                         target_write_u16 (target, MX3_NF_CFG2,
 655                                         MX3_NF_BIT_DATAOUT_TYPE(mx3_nf_info->optype));
 656                         {
 657                                 int poll_result;
 658                                 poll_result = poll_for_complete_op(target, "data output");
 659                                 if (poll_result != ERROR_OK)
 660                                         return poll_result;
 661                         }
 662                         mx3_nf_info->fin = MX3_NF_FIN_NONE;
 663                         /*
 664                          * ECC stuff
 665                          */
 666                         if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
 667                                         && mx3_nf_info->flags.hw_ecc_enabled) {
 668                                 uint16_t ecc_status;
 669                                 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
 670                                 switch (ecc_status & 0x000c) {
 671                                 case 1 << 2:
 672                                         LOG_DEBUG("main area read with 1 (correctable) error");
 673                                         break;
 674                                 case 2 << 2:
 675                                         LOG_DEBUG("main area read with more than 1 (incorrectable) error");
 676                                         return ERROR_NAND_OPERATION_FAILED;
 677                                 }
 678                                 switch (ecc_status & 0x0003) {
 679                                 case 1:
 680                                         LOG_DEBUG("spare area read with 1 (correctable) error");
 681                                         break;
 682                                 case 2:
 683                                         LOG_DEBUG("main area read with more than 1 (incorrectable) error");
 684                                         return ERROR_NAND_OPERATION_FAILED;
 685                                 }
 686                         }
 687                         break;
 688                 case MX3_NF_FIN_NONE:
 689                         break;
 690         }
 691         return ERROR_OK;
 692 }
 693
 694 struct nand_flash_controller imx31_nand_flash_controller = {
 695         .name = "imx31",
 696         .usage = "nand device imx31 target noecc|hwecc",
 697         .nand_device_command = &imx31_nand_device_command,
 698         .init = &imx31_init,
 699         .reset = &imx31_reset,
 700         .command = &imx31_command,
 701         .address = &imx31_address,
 702         .write_data = &imx31_write_data,
 703         .read_data = &imx31_read_data,
 704         .write_page = &imx31_write_page,
 705         .read_page = &imx31_read_page,
 706         .nand_ready = &imx31_nand_ready,
 707 };