git.gag.com Git - fw/openocd/blob - src/flash/nand/lpc32xx.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2007 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2011 Bjarne Steinsbo <bsteinsbo@gmail.com>              *
   8  *   Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com>                *
   9  *   Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com>            *
  10  *                                                                         *
  11  *   Based on a combination of the lpc3180 driver and code from            *
  12  *   uboot-2009.03-lpc32xx by Kevin Wells.                                 *
  13  *   Any bugs are mine. --BSt                                              *
  14  ***************************************************************************/
  15
  16 #ifdef HAVE_CONFIG_H
  17 #include "config.h"
  18 #endif
  19
  20 #include "imp.h"
  21 #include "lpc32xx.h"
  22 #include <target/target.h>
  23
  24 static int lpc32xx_reset(struct nand_device *nand);
  25 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout);
  26 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout);
  27 extern int nand_correct_data(struct nand_device *nand, u_char *dat,
  28                 u_char *read_ecc, u_char *calc_ecc);
  29
  30 /* These are offset with the working area in IRAM when using DMA to
  31  * read/write data to the SLC controller.
  32  * - DMA descriptors will be put at start of working area,
  33  * - Hardware generated ECC will be stored at ECC_OFFS
  34  * - OOB will be read/written from/to SPARE_OFFS
  35  * - Actual page data will be read from/to DATA_OFFS
  36  * There are unused holes between the used areas.
  37  */
  38 #define ECC_OFFS   0x120
  39 #define SPARE_OFFS 0x140
  40 #define DATA_OFFS  0x200
  41
  42 static const int sp_ooblayout[] = {
  43         10, 11, 12, 13, 14, 15
  44 };
  45 static const int lp_ooblayout[] = {
  46         40, 41, 42, 43, 44, 45,
  47         46, 47, 48, 49, 50, 51,
  48         52, 53, 54, 55, 56, 57,
  49         58, 59, 60, 61, 62, 63
  50 };
  51
  52 struct dmac_ll {
  53         volatile uint32_t dma_src;
  54         volatile uint32_t dma_dest;
  55         volatile uint32_t next_lli;
  56         volatile uint32_t next_ctrl;
  57 };
  58
  59 static struct dmac_ll dmalist[(2048/256) * 2 + 1];
  60
  61 /* nand device lpc32xx <target#> <oscillator_frequency>
  62  */
  63 NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
  64 {
  65         if (CMD_ARGC < 3)
  66                 return ERROR_COMMAND_SYNTAX_ERROR;
  67
  68         uint32_t osc_freq;
  69         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
  70
  71         struct lpc32xx_nand_controller *lpc32xx_info;
  72         lpc32xx_info = malloc(sizeof(struct lpc32xx_nand_controller));
  73         nand->controller_priv = lpc32xx_info;
  74
  75         lpc32xx_info->osc_freq = osc_freq;
  76
  77         if ((lpc32xx_info->osc_freq < 1000) || (lpc32xx_info->osc_freq > 20000))
  78                 LOG_WARNING("LPC32xx oscillator frequency should be between "
  79                         "1000 and 20000 kHz, was %i",
  80                         lpc32xx_info->osc_freq);
  81
  82         lpc32xx_info->selected_controller = LPC32XX_NO_CONTROLLER;
  83         lpc32xx_info->sw_write_protection = 0;
  84         lpc32xx_info->sw_wp_lower_bound = 0x0;
  85         lpc32xx_info->sw_wp_upper_bound = 0x0;
  86
  87         return ERROR_OK;
  88 }
  89
  90 static int lpc32xx_pll(int fclkin, uint32_t pll_ctrl)
  91 {
  92         int bypass = (pll_ctrl & 0x8000) >> 15;
  93         int direct = (pll_ctrl & 0x4000) >> 14;
  94         int feedback = (pll_ctrl & 0x2000) >> 13;
  95         int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
  96         int n = ((pll_ctrl & 0x0600) >> 9) + 1;
  97         int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
  98         int lock = (pll_ctrl & 0x1);
  99
 100         if (!lock)
 101                 LOG_WARNING("PLL is not locked");
 102
 103         if (!bypass && direct)  /* direct mode */
 104                 return (m * fclkin) / n;
 105
 106         if (bypass && !direct)  /* bypass mode */
 107                 return fclkin / (2 * p);
 108
 109         if (bypass & direct)    /* direct bypass mode */
 110                 return fclkin;
 111
 112         if (feedback)   /* integer mode */
 113                 return m * (fclkin / n);
 114         else    /* non-integer mode */
 115                 return (m / (2 * p)) * (fclkin / n);
 116 }
 117
 118 static float lpc32xx_cycle_time(struct nand_device *nand)
 119 {
 120         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 121         struct target *target = nand->target;
 122         uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
 123         int sysclk;
 124         int hclk;
 125         int hclk_pll;
 126         float cycle;
 127         int retval;
 128
 129         /* calculate timings */
 130
 131         /* determine current SYSCLK (13'MHz or main oscillator) */
 132         retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
 133         if (retval != ERROR_OK) {
 134                 LOG_ERROR("could not read SYSCLK_CTRL");
 135                 return ERROR_NAND_OPERATION_FAILED;
 136         }
 137
 138         if ((sysclk_ctrl & 1) == 0)
 139                 sysclk = lpc32xx_info->osc_freq;
 140         else
 141                 sysclk = 13000;
 142
 143         /* determine selected HCLK source */
 144         retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
 145         if (retval != ERROR_OK) {
 146                 LOG_ERROR("could not read HCLK_CTRL");
 147                 return ERROR_NAND_OPERATION_FAILED;
 148         }
 149
 150         if ((pwr_ctrl & (1 << 2)) == 0)         /* DIRECT RUN mode */
 151                 hclk = sysclk;
 152         else {
 153                 retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
 154                 if (retval != ERROR_OK) {
 155                         LOG_ERROR("could not read HCLKPLL_CTRL");
 156                         return ERROR_NAND_OPERATION_FAILED;
 157                 }
 158                 hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl);
 159
 160                 retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
 161                 if (retval != ERROR_OK) {
 162                         LOG_ERROR("could not read CLKDIV_CTRL");
 163                         return ERROR_NAND_OPERATION_FAILED;
 164                 }
 165
 166                 if (pwr_ctrl & (1 << 10))       /* ARM_CLK and HCLK use PERIPH_CLK */
 167                         hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
 168                 else    /* HCLK uses HCLK_PLL */
 169                         hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
 170         }
 171
 172         LOG_DEBUG("LPC32xx HCLK currently clocked at %i kHz", hclk);
 173
 174         cycle = (1.0 / hclk) * 1000000.0;
 175
 176         return cycle;
 177 }
 178
 179 static int lpc32xx_init(struct nand_device *nand)
 180 {
 181         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 182         struct target *target = nand->target;
 183         int bus_width = nand->bus_width ? nand->bus_width : 8;
 184         int address_cycles = nand->address_cycles ? nand->address_cycles : 3;
 185         int page_size = nand->page_size ? nand->page_size : 512;
 186         int retval;
 187
 188         if (target->state != TARGET_HALTED) {
 189                 LOG_ERROR("target must be halted to use LPC32xx "
 190                         "NAND flash controller");
 191                 return ERROR_NAND_OPERATION_FAILED;
 192         }
 193
 194         /* sanitize arguments */
 195         if (bus_width != 8) {
 196                 LOG_ERROR("LPC32xx doesn't support %i", bus_width);
 197                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 198         }
 199
 200         /* inform calling code about selected bus width */
 201         nand->bus_width = bus_width;
 202
 203         if ((address_cycles < 3) || (address_cycles > 5)) {
 204                 LOG_ERROR("LPC32xx driver doesn't support %i address cycles", address_cycles);
 205                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 206         }
 207
 208         if ((page_size != 512) && (page_size != 2048)) {
 209                 LOG_ERROR("LPC32xx doesn't support page size %i", page_size);
 210                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 211         }
 212
 213         /* select MLC controller if none is currently selected */
 214         if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
 215                 LOG_DEBUG("no LPC32xx NAND flash controller selected, "
 216                         "using default 'slc'");
 217                 lpc32xx_info->selected_controller = LPC32XX_SLC_CONTROLLER;
 218         }
 219
 220         if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
 221                 uint32_t mlc_icr_value = 0x0;
 222                 float cycle;
 223                 int twp, twh, trp, treh, trhz, trbwb, tcea;
 224
 225                 /* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */
 226                 retval = target_write_u32(target, 0x400040c8, 0x22);
 227                 if (retval != ERROR_OK) {
 228                         LOG_ERROR("could not set FLASHCLK_CTRL");
 229                         return ERROR_NAND_OPERATION_FAILED;
 230                 }
 231
 232                 /* MLC_CEH = 0x0 (Force nCE assert) */
 233                 retval = target_write_u32(target, 0x200b804c, 0x0);
 234                 if (retval != ERROR_OK) {
 235                         LOG_ERROR("could not set MLC_CEH");
 236                         return ERROR_NAND_OPERATION_FAILED;
 237                 }
 238
 239                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 240                 retval = target_write_u32(target, 0x200b8044, 0xa25e);
 241                 if (retval != ERROR_OK) {
 242                         LOG_ERROR("could not set MLC_LOCK");
 243                         return ERROR_NAND_OPERATION_FAILED;
 244                 }
 245
 246                 /* MLC_ICR = configuration */
 247                 if (lpc32xx_info->sw_write_protection)
 248                         mlc_icr_value |= 0x8;
 249                 if (page_size == 2048)
 250                         mlc_icr_value |= 0x4;
 251                 if (address_cycles == 4)
 252                         mlc_icr_value |= 0x2;
 253                 if (bus_width == 16)
 254                         mlc_icr_value |= 0x1;
 255                 retval = target_write_u32(target, 0x200b8030, mlc_icr_value);
 256                 if (retval != ERROR_OK) {
 257                         LOG_ERROR("could not set MLC_ICR");
 258                         return ERROR_NAND_OPERATION_FAILED;
 259                 }
 260
 261                 /* calculate NAND controller timings */
 262                 cycle = lpc32xx_cycle_time(nand);
 263
 264                 twp = ((40 / cycle) + 1);
 265                 twh = ((20 / cycle) + 1);
 266                 trp = ((30 / cycle) + 1);
 267                 treh = ((15 / cycle) + 1);
 268                 trhz = ((30 / cycle) + 1);
 269                 trbwb = ((100 / cycle) + 1);
 270                 tcea = ((45 / cycle) + 1);
 271
 272                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 273                 retval = target_write_u32(target, 0x200b8044, 0xa25e);
 274                 if (retval != ERROR_OK) {
 275                         LOG_ERROR("could not set MLC_LOCK");
 276                         return ERROR_NAND_OPERATION_FAILED;
 277                 }
 278
 279                 /* MLC_TIME_REG */
 280                 retval = target_write_u32(target, 0x200b8034,
 281                                 (twp & 0xf)
 282                                 | ((twh & 0xf) << 4)
 283                                 | ((trp & 0xf) << 8)
 284                                 | ((treh & 0xf) << 12)
 285                                 | ((trhz & 0x7) << 16)
 286                                 | ((trbwb & 0x1f) << 19)
 287                                 | ((tcea & 0x3) << 24));
 288                 if (retval != ERROR_OK) {
 289                         LOG_ERROR("could not set MLC_TIME_REG");
 290                         return ERROR_NAND_OPERATION_FAILED;
 291                 }
 292
 293                 retval = lpc32xx_reset(nand);
 294                 if (retval != ERROR_OK)
 295                         return ERROR_NAND_OPERATION_FAILED;
 296         } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
 297                 float cycle;
 298                 int r_setup, r_hold, r_width, r_rdy;
 299                 int w_setup, w_hold, w_width, w_rdy;
 300
 301                 /* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */
 302                 retval = target_write_u32(target, 0x400040c8, 0x05);
 303                 if (retval != ERROR_OK) {
 304                         LOG_ERROR("could not set FLASHCLK_CTRL");
 305                         return ERROR_NAND_OPERATION_FAILED;
 306                 }
 307
 308                 /* after reset set other registers of SLC,
 309                  * so reset calling is here at the beginning
 310                  */
 311                 retval = lpc32xx_reset(nand);
 312                 if (retval != ERROR_OK)
 313                         return ERROR_NAND_OPERATION_FAILED;
 314
 315                 /* SLC_CFG =
 316                         Force nCE assert,
 317                         DMA ECC enabled,
 318                         ECC enabled,
 319                         DMA burst enabled,
 320                         DMA read from SLC,
 321                         WIDTH = bus_width)
 322                 */
 323                 retval = target_write_u32(target, 0x20020014,
 324                                 0x3e | ((bus_width == 16) ? 1 : 0));
 325                 if (retval != ERROR_OK) {
 326                         LOG_ERROR("could not set SLC_CFG");
 327                         return ERROR_NAND_OPERATION_FAILED;
 328                 }
 329
 330                 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
 331                 retval = target_write_u32(target, 0x20020020, 0x03);
 332                 if (retval != ERROR_OK) {
 333                         LOG_ERROR("could not set SLC_IEN");
 334                         return ERROR_NAND_OPERATION_FAILED;
 335                 }
 336
 337                 /* DMA configuration */
 338
 339                 /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
 340                 retval = target_write_u32(target, 0x400040e8, 0x01);
 341                 if (retval != ERROR_OK) {
 342                         LOG_ERROR("could not set DMACLK_CTRL");
 343                         return ERROR_NAND_OPERATION_FAILED;
 344                 }
 345
 346                 /* DMACConfig = DMA enabled*/
 347                 retval = target_write_u32(target, 0x31000030, 0x01);
 348                 if (retval != ERROR_OK) {
 349                         LOG_ERROR("could not set DMACConfig");
 350                         return ERROR_NAND_OPERATION_FAILED;
 351                 }
 352
 353                 /* calculate NAND controller timings */
 354                 cycle = lpc32xx_cycle_time(nand);
 355
 356                 r_setup = w_setup = 0;
 357                 r_hold = w_hold = 10 / cycle;
 358                 r_width = 30 / cycle;
 359                 w_width = 40 / cycle;
 360                 r_rdy = w_rdy = 100 / cycle;
 361
 362                 /* SLC_TAC: SLC timing arcs register */
 363                 retval = target_write_u32(target, 0x2002002c,
 364                                 (r_setup & 0xf)
 365                                 | ((r_hold & 0xf) << 4)
 366                                 | ((r_width & 0xf) << 8)
 367                                 | ((r_rdy & 0xf) << 12)
 368                                 | ((w_setup & 0xf) << 16)
 369                                 | ((w_hold & 0xf) << 20)
 370                                 | ((w_width & 0xf) << 24)
 371                                 | ((w_rdy & 0xf) << 28));
 372                 if (retval != ERROR_OK) {
 373                         LOG_ERROR("could not set SLC_TAC");
 374                         return ERROR_NAND_OPERATION_FAILED;
 375                 }
 376         }
 377
 378         return ERROR_OK;
 379 }
 380
 381 static int lpc32xx_reset(struct nand_device *nand)
 382 {
 383         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 384         struct target *target = nand->target;
 385         int retval;
 386
 387         if (target->state != TARGET_HALTED) {
 388                 LOG_ERROR("target must be halted to use "
 389                         "LPC32xx NAND flash controller");
 390                 return ERROR_NAND_OPERATION_FAILED;
 391         }
 392
 393         if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
 394                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
 395                 return ERROR_NAND_OPERATION_FAILED;
 396         } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
 397                 /* MLC_CMD = 0xff (reset controller and NAND device) */
 398                 retval = target_write_u32(target, 0x200b8000, 0xff);
 399                 if (retval != ERROR_OK) {
 400                         LOG_ERROR("could not set MLC_CMD");
 401                         return ERROR_NAND_OPERATION_FAILED;
 402                 }
 403
 404                 if (!lpc32xx_controller_ready(nand, 100)) {
 405                         LOG_ERROR("LPC32xx MLC NAND controller timed out "
 406                                 "after reset");
 407                         return ERROR_NAND_OPERATION_TIMEOUT;
 408                 }
 409         } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
 410                 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
 411                 retval = target_write_u32(target, 0x20020010, 0x6);
 412                 if (retval != ERROR_OK) {
 413                         LOG_ERROR("could not set SLC_CTRL");
 414                         return ERROR_NAND_OPERATION_FAILED;
 415                 }
 416
 417                 if (!lpc32xx_controller_ready(nand, 100)) {
 418                         LOG_ERROR("LPC32xx SLC NAND controller timed out "
 419                                 "after reset");
 420                         return ERROR_NAND_OPERATION_TIMEOUT;
 421                 }
 422         }
 423
 424         return ERROR_OK;
 425 }
 426
 427 static int lpc32xx_command(struct nand_device *nand, uint8_t command)
 428 {
 429         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 430         struct target *target = nand->target;
 431         int retval;
 432
 433         if (target->state != TARGET_HALTED) {
 434                 LOG_ERROR("target must be halted to use "
 435                         "LPC32xx NAND flash controller");
 436                 return ERROR_NAND_OPERATION_FAILED;
 437         }
 438
 439         if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
 440                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
 441                 return ERROR_NAND_OPERATION_FAILED;
 442         } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
 443                 /* MLC_CMD = command */
 444                 retval = target_write_u32(target, 0x200b8000, command);
 445                 if (retval != ERROR_OK) {
 446                         LOG_ERROR("could not set MLC_CMD");
 447                         return ERROR_NAND_OPERATION_FAILED;
 448                 }
 449         } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
 450                 /* SLC_CMD = command */
 451                 retval = target_write_u32(target, 0x20020008, command);
 452                 if (retval != ERROR_OK) {
 453                         LOG_ERROR("could not set SLC_CMD");
 454                         return ERROR_NAND_OPERATION_FAILED;
 455                 }
 456         }
 457
 458         return ERROR_OK;
 459 }
 460
 461 static int lpc32xx_address(struct nand_device *nand, uint8_t address)
 462 {
 463         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 464         struct target *target = nand->target;
 465         int retval;
 466
 467         if (target->state != TARGET_HALTED) {
 468                 LOG_ERROR("target must be halted to use "
 469                         "LPC32xx NAND flash controller");
 470                 return ERROR_NAND_OPERATION_FAILED;
 471         }
 472
 473         if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
 474                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
 475                 return ERROR_NAND_OPERATION_FAILED;
 476         } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
 477                 /* MLC_ADDR = address */
 478                 retval = target_write_u32(target, 0x200b8004, address);
 479                 if (retval != ERROR_OK) {
 480                         LOG_ERROR("could not set MLC_ADDR");
 481                         return ERROR_NAND_OPERATION_FAILED;
 482                 }
 483         } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
 484                 /* SLC_ADDR = address */
 485                 retval = target_write_u32(target, 0x20020004, address);
 486                 if (retval != ERROR_OK) {
 487                         LOG_ERROR("could not set SLC_ADDR");
 488                         return ERROR_NAND_OPERATION_FAILED;
 489                 }
 490         }
 491
 492         return ERROR_OK;
 493 }
 494
 495 static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
 496 {
 497         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 498         struct target *target = nand->target;
 499         int retval;
 500
 501         if (target->state != TARGET_HALTED) {
 502                 LOG_ERROR("target must be halted to use "
 503                         "LPC32xx NAND flash controller");
 504                 return ERROR_NAND_OPERATION_FAILED;
 505         }
 506
 507         if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
 508                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
 509                 return ERROR_NAND_OPERATION_FAILED;
 510         } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
 511                 /* MLC_DATA = data */
 512                 retval = target_write_u32(target, 0x200b0000, data);
 513                 if (retval != ERROR_OK) {
 514                         LOG_ERROR("could not set MLC_DATA");
 515                         return ERROR_NAND_OPERATION_FAILED;
 516                 }
 517         } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
 518                 /* SLC_DATA = data */
 519                 retval = target_write_u32(target, 0x20020000, data);
 520                 if (retval != ERROR_OK) {
 521                         LOG_ERROR("could not set SLC_DATA");
 522                         return ERROR_NAND_OPERATION_FAILED;
 523                 }
 524         }
 525
 526         return ERROR_OK;
 527 }
 528
 529 static int lpc32xx_read_data(struct nand_device *nand, void *data)
 530 {
 531         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 532         struct target *target = nand->target;
 533         int retval;
 534
 535         if (target->state != TARGET_HALTED) {
 536                 LOG_ERROR("target must be halted to use LPC32xx "
 537                         "NAND flash controller");
 538                 return ERROR_NAND_OPERATION_FAILED;
 539         }
 540
 541         if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
 542                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
 543                 return ERROR_NAND_OPERATION_FAILED;
 544         } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
 545                 /* data = MLC_DATA, use sized access */
 546                 if (nand->bus_width == 8) {
 547                         uint8_t *data8 = data;
 548                         retval = target_read_u8(target, 0x200b0000, data8);
 549                 } else {
 550                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 551                         return ERROR_NAND_OPERATION_FAILED;
 552                 }
 553                 if (retval != ERROR_OK) {
 554                         LOG_ERROR("could not read MLC_DATA");
 555                         return ERROR_NAND_OPERATION_FAILED;
 556                 }
 557         } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
 558                 uint32_t data32;
 559
 560                 /* data = SLC_DATA, must use 32-bit access */
 561                 retval = target_read_u32(target, 0x20020000, &data32);
 562                 if (retval != ERROR_OK) {
 563                         LOG_ERROR("could not read SLC_DATA");
 564                         return ERROR_NAND_OPERATION_FAILED;
 565                 }
 566
 567                 if (nand->bus_width == 8) {
 568                         uint8_t *data8 = data;
 569                         *data8 = data32 & 0xff;
 570                 } else {
 571                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 572                         return ERROR_NAND_OPERATION_FAILED;
 573                 }
 574         }
 575
 576         return ERROR_OK;
 577 }
 578
 579 static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
 580         uint8_t *data, uint32_t data_size,
 581         uint8_t *oob, uint32_t oob_size)
 582 {
 583         struct target *target = nand->target;
 584         int retval;
 585         uint8_t status;
 586         static uint8_t page_buffer[512];
 587         static uint8_t oob_buffer[6];
 588         int quarter, num_quarters;
 589
 590         /* MLC_CMD = sequential input */
 591         retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
 592         if (retval != ERROR_OK) {
 593                 LOG_ERROR("could not set MLC_CMD");
 594                 return ERROR_NAND_OPERATION_FAILED;
 595         }
 596
 597         if (nand->page_size == 512) {
 598                 /* MLC_ADDR = 0x0 (one column cycle) */
 599                 retval = target_write_u32(target, 0x200b8004, 0x0);
 600                 if (retval != ERROR_OK) {
 601                         LOG_ERROR("could not set MLC_ADDR");
 602                         return ERROR_NAND_OPERATION_FAILED;
 603                 }
 604
 605                 /* MLC_ADDR = row */
 606                 retval = target_write_u32(target, 0x200b8004, page & 0xff);
 607                 if (retval != ERROR_OK) {
 608                         LOG_ERROR("could not set MLC_ADDR");
 609                         return ERROR_NAND_OPERATION_FAILED;
 610                 }
 611                 retval = target_write_u32(target, 0x200b8004,
 612                                 (page >> 8) & 0xff);
 613                 if (retval != ERROR_OK) {
 614                         LOG_ERROR("could not set MLC_ADDR");
 615                         return ERROR_NAND_OPERATION_FAILED;
 616                 }
 617
 618                 if (nand->address_cycles == 4) {
 619                         retval = target_write_u32(target, 0x200b8004,
 620                                         (page >> 16) & 0xff);
 621                         if (retval != ERROR_OK) {
 622                                 LOG_ERROR("could not set MLC_ADDR");
 623                                 return ERROR_NAND_OPERATION_FAILED;
 624                         }
 625                 }
 626         } else {
 627                 /* MLC_ADDR = 0x0 (two column cycles) */
 628                 retval = target_write_u32(target, 0x200b8004, 0x0);
 629                 if (retval != ERROR_OK) {
 630                         LOG_ERROR("could not set MLC_ADDR");
 631                         return ERROR_NAND_OPERATION_FAILED;
 632                 }
 633                 retval = target_write_u32(target, 0x200b8004, 0x0);
 634                 if (retval != ERROR_OK) {
 635                         LOG_ERROR("could not set MLC_ADDR");
 636                         return ERROR_NAND_OPERATION_FAILED;
 637                 }
 638
 639                 /* MLC_ADDR = row */
 640                 retval = target_write_u32(target, 0x200b8004, page & 0xff);
 641                 if (retval != ERROR_OK) {
 642                         LOG_ERROR("could not set MLC_ADDR");
 643                         return ERROR_NAND_OPERATION_FAILED;
 644                 }
 645                 retval = target_write_u32(target, 0x200b8004,
 646                                 (page >> 8) & 0xff);
 647                 if (retval != ERROR_OK) {
 648                         LOG_ERROR("could not set MLC_ADDR");
 649                         return ERROR_NAND_OPERATION_FAILED;
 650                 }
 651         }
 652
 653         /* when using the MLC controller, we have to treat a large page device
 654          * as being made out of four quarters, each the size of a small page
 655          * device
 656          */
 657         num_quarters = (nand->page_size == 2048) ? 4 : 1;
 658
 659         for (quarter = 0; quarter < num_quarters; quarter++) {
 660                 int thisrun_data_size = (data_size > 512) ? 512 : data_size;
 661                 int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
 662
 663                 memset(page_buffer, 0xff, 512);
 664                 if (data) {
 665                         memcpy(page_buffer, data, thisrun_data_size);
 666                         data_size -= thisrun_data_size;
 667                         data += thisrun_data_size;
 668                 }
 669
 670                 memset(oob_buffer, 0xff, 6);
 671                 if (oob) {
 672                         memcpy(oob_buffer, oob, thisrun_oob_size);
 673                         oob_size -= thisrun_oob_size;
 674                         oob += thisrun_oob_size;
 675                 }
 676
 677                 /* write MLC_ECC_ENC_REG to start encode cycle */
 678                 retval = target_write_u32(target, 0x200b8008, 0x0);
 679                 if (retval != ERROR_OK) {
 680                         LOG_ERROR("could not set MLC_ECC_ENC_REG");
 681                         return ERROR_NAND_OPERATION_FAILED;
 682                 }
 683
 684                 retval = target_write_memory(target, 0x200a8000,
 685                                 4, 128, page_buffer);
 686                 if (retval != ERROR_OK) {
 687                         LOG_ERROR("could not set MLC_BUF (data)");
 688                         return ERROR_NAND_OPERATION_FAILED;
 689                 }
 690                 retval = target_write_memory(target, 0x200a8000,
 691                                 1, 6, oob_buffer);
 692                 if (retval != ERROR_OK) {
 693                         LOG_ERROR("could not set MLC_BUF (oob)");
 694                         return ERROR_NAND_OPERATION_FAILED;
 695                 }
 696
 697                 /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
 698                 retval = target_write_u32(target, 0x200b8010, 0x0);
 699                 if (retval != ERROR_OK) {
 700                         LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG");
 701                         return ERROR_NAND_OPERATION_FAILED;
 702                 }
 703
 704                 if (!lpc32xx_controller_ready(nand, 1000)) {
 705                         LOG_ERROR("timeout while waiting for "
 706                                 "completion of auto encode cycle");
 707                         return ERROR_NAND_OPERATION_FAILED;
 708                 }
 709         }
 710
 711         /* MLC_CMD = auto program command */
 712         retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
 713         if (retval != ERROR_OK) {
 714                 LOG_ERROR("could not set MLC_CMD");
 715                 return ERROR_NAND_OPERATION_FAILED;
 716         }
 717
 718         retval = nand_read_status(nand, &status);
 719         if (retval != ERROR_OK) {
 720                 LOG_ERROR("couldn't read status");
 721                 return ERROR_NAND_OPERATION_FAILED;
 722         }
 723
 724         if (status & NAND_STATUS_FAIL) {
 725                 LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
 726                         status);
 727                 return ERROR_NAND_OPERATION_FAILED;
 728         }
 729
 730         return ERROR_OK;
 731 }
 732
 733 /* SLC controller in !raw mode will use target cpu to read/write nand from/to
 734  * target internal memory.  The transfer to/from flash is done by DMA.  This
 735  * function sets up the dma linked list in host memory for later transfer to
 736  * target.
 737  */
 738 static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 739         int do_read)
 740 {
 741         uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
 742
 743         /* DMACCxControl =
 744                 TransferSize =64,
 745                 Source burst size =16,
 746                 Destination burst size = 16,
 747                 Source transfer width = 32 bit,
 748                 Destination transfer width = 32 bit,
 749                 Source AHB master select = M0,
 750                 Destination AHB master select = M0,
 751                 Source increment = 0, // set later
 752                 Destination increment = 0, // set later
 753                 Terminal count interrupt enable bit = 0 // set on last
 754         */                      /*
 755          * Write Operation Sequence for Small Block NAND
 756          * ----------------------------------------------------------
 757          * 1. X'fer 256 bytes of data from Memory to Flash.
 758          * 2. Copy generated ECC data from Register to Spare Area
 759          * 3. X'fer next 256 bytes of data from Memory to Flash.
 760          * 4. Copy generated ECC data from Register to Spare Area.
 761          * 5. X'fer 16 bytes of Spare area from Memory to Flash.
 762          * Read Operation Sequence for Small Block NAND
 763          * ----------------------------------------------------------
 764          * 1. X'fer 256 bytes of data from Flash to Memory.
 765          * 2. Copy generated ECC data from Register to ECC calc Buffer.
 766          * 3. X'fer next 256 bytes of data from Flash to Memory.
 767          * 4. Copy generated ECC data from Register to ECC calc Buffer.
 768          * 5. X'fer 16 bytes of Spare area from Flash to Memory.
 769          * Write Operation Sequence for Large Block NAND
 770          * ----------------------------------------------------------
 771          * 1. Steps(1-4) of Write Operations repeated for four times
 772          * which generates 16 DMA descriptors to X'fer 2048 bytes of
 773          * data & 32 bytes of ECC data.
 774          * 2. X'fer 64 bytes of Spare area from Memory to Flash.
 775          * Read Operation Sequence for Large Block NAND
 776          * ----------------------------------------------------------
 777          * 1. Steps(1-4) of Read Operations repeated for four times
 778          * which generates 16 DMA descriptors to X'fer 2048 bytes of
 779          * data & 32 bytes of ECC data.
 780          * 2. X'fer 64 bytes of Spare area from Flash to Memory.
 781          */
 782
 783         ctrl = (0x40 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
 784                 | 0 << 25 | 0 << 26 | 0 << 27 | 0 << 31);
 785
 786         /* DMACCxControl =
 787                 TransferSize =1,
 788                 Source burst size =4,
 789                 Destination burst size = 4,
 790                 Source transfer width = 32 bit,
 791                 Destination transfer width = 32 bit,
 792                 Source AHB master select = M0,
 793                 Destination AHB master select = M0,
 794                 Source increment = 0,
 795                 Destination increment = 1,
 796                 Terminal count interrupt enable bit = 0
 797          */
 798         ecc_ctrl = 0x01 | 1 << 12 | 1 << 15 | 2 << 18 | 2 << 21 | 0 << 24
 799                 | 0 << 25 | 0 << 26 | 1 << 27 | 0 << 31;
 800
 801         /* DMACCxControl =
 802                 TransferSize =16 for lp or 4 for sp,
 803                 Source burst size =16,
 804                 Destination burst size = 16,
 805                 Source transfer width = 32 bit,
 806                 Destination transfer width = 32 bit,
 807                 Source AHB master select = M0,
 808                 Destination AHB master select = M0,
 809                 Source increment = 0, // set later
 810                 Destination increment = 0, // set later
 811                 Terminal count interrupt enable bit = 1 // set on last
 812          */
 813         oob_ctrl = (page_size == 2048 ? 0x10 : 0x04)
 814                 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
 815                 | 0 << 25 | 0 << 26 | 0 << 27 | 1 << 31;
 816         if (do_read) {
 817                 ctrl |= 1 << 27;/* Destination increment = 1 */
 818                 oob_ctrl |= 1 << 27;    /* Destination increment = 1 */
 819                 dmasrc = 0x20020038;    /* SLC_DMA_DATA */
 820                 dmadst = target_mem_base + DATA_OFFS;
 821         } else {
 822                 ctrl |= 1 << 26;/* Source increment = 1 */
 823                 oob_ctrl |= 1 << 26;    /* Source increment = 1 */
 824                 dmasrc = target_mem_base + DATA_OFFS;
 825                 dmadst = 0x20020038;    /* SLC_DMA_DATA */
 826         }
 827         /*
 828          * Write Operation Sequence for Small Block NAND
 829          * ----------------------------------------------------------
 830          * 1. X'fer 256 bytes of data from Memory to Flash.
 831          * 2. Copy generated ECC data from Register to Spare Area
 832          * 3. X'fer next 256 bytes of data from Memory to Flash.
 833          * 4. Copy generated ECC data from Register to Spare Area.
 834          * 5. X'fer 16 bytes of Spare area from Memory to Flash.
 835          * Read Operation Sequence for Small Block NAND
 836          * ----------------------------------------------------------
 837          * 1. X'fer 256 bytes of data from Flash to Memory.
 838          * 2. Copy generated ECC data from Register to ECC calc Buffer.
 839          * 3. X'fer next 256 bytes of data from Flash to Memory.
 840          * 4. Copy generated ECC data from Register to ECC calc Buffer.
 841          * 5. X'fer 16 bytes of Spare area from Flash to Memory.
 842          * Write Operation Sequence for Large Block NAND
 843          * ----------------------------------------------------------
 844          * 1. Steps(1-4) of Write Operations repeated for four times
 845          * which generates 16 DMA descriptors to X'fer 2048 bytes of
 846          * data & 32 bytes of ECC data.
 847          * 2. X'fer 64 bytes of Spare area from Memory to Flash.
 848          * Read Operation Sequence for Large Block NAND
 849          * ----------------------------------------------------------
 850          * 1. Steps(1-4) of Read Operations repeated for four times
 851          * which generates 16 DMA descriptors to X'fer 2048 bytes of
 852          * data & 32 bytes of ECC data.
 853          * 2. X'fer 64 bytes of Spare area from Flash to Memory.
 854          */
 855         for (i = 0; i < page_size/0x100; i++) {
 856                 dmalist[i*2].dma_src = (do_read ? dmasrc : (dmasrc + i * 256));
 857                 dmalist[i*2].dma_dest = (do_read ? (dmadst + i * 256) : dmadst);
 858                 dmalist[i*2].next_lli =
 859                         target_mem_base + (i*2 + 1) * sizeof(struct dmac_ll);
 860                 dmalist[i*2].next_ctrl = ctrl;
 861
 862                 dmalist[(i*2) + 1].dma_src = 0x20020034;/* SLC_ECC */
 863                 dmalist[(i*2) + 1].dma_dest =
 864                         target_mem_base + ECC_OFFS + i * 4;
 865                 dmalist[(i*2) + 1].next_lli =
 866                         target_mem_base + (i*2 + 2) * sizeof(struct dmac_ll);
 867                 dmalist[(i*2) + 1].next_ctrl = ecc_ctrl;
 868
 869         }
 870         if (do_read)
 871                 dmadst = target_mem_base + SPARE_OFFS;
 872         else {
 873                 dmasrc = target_mem_base + SPARE_OFFS;
 874                 dmalist[(i*2) - 1].next_lli = 0;/* last link = null on write */
 875                 dmalist[(i*2) - 1].next_ctrl |= (1 << 31);      /* Set TC enable */
 876         }
 877         dmalist[i*2].dma_src = dmasrc;
 878         dmalist[i*2].dma_dest = dmadst;
 879         dmalist[i*2].next_lli = 0;
 880         dmalist[i*2].next_ctrl = oob_ctrl;
 881
 882         return i * 2 + 1;       /* Number of descriptors */
 883 }
 884
 885 static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count,
 886         int do_wait)
 887 {
 888         struct target *target = nand->target;
 889         int retval;
 890
 891         /* DMACIntTCClear = ch0 */
 892         retval = target_write_u32(target, 0x31000008, 1);
 893         if (retval != ERROR_OK) {
 894                 LOG_ERROR("Could not set DMACIntTCClear");
 895                 return retval;
 896         }
 897
 898         /* DMACIntErrClear = ch0 */
 899         retval = target_write_u32(target, 0x31000010, 1);
 900         if (retval != ERROR_OK) {
 901                 LOG_ERROR("Could not set DMACIntErrClear");
 902                 return retval;
 903         }
 904
 905         /* DMACCxConfig=
 906                 E=1,
 907                 SrcPeripheral = 1 (SLC),
 908                 DestPeripheral = 1 (SLC),
 909                 FlowCntrl = 2 (Pher -> Mem, DMA),
 910                 IE = 0,
 911                 ITC = 0,
 912                 L= 0,
 913                 H=0
 914         */
 915         retval = target_write_u32(target, 0x31000110,
 916                         1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
 917                         | 0<<15 | 0<<16 | 0<<18);
 918         if (retval != ERROR_OK) {
 919                 LOG_ERROR("Could not set DMACC0Config");
 920                 return retval;
 921         }
 922
 923         /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
 924         retval = target_write_u32(target, 0x20020010, 0x3);
 925         if (retval != ERROR_OK) {
 926                 LOG_ERROR("Could not set SLC_CTRL");
 927                 return retval;
 928         }
 929
 930         /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
 931         retval = target_write_u32(target, 0x20020028, 2);
 932         if (retval != ERROR_OK) {
 933                 LOG_ERROR("Could not set SLC_ICR");
 934                 return retval;
 935         }
 936
 937         /* SLC_TC */
 938         retval = target_write_u32(target, 0x20020030, count);
 939         if (retval != ERROR_OK) {
 940                 LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC");
 941                 return retval;
 942         }
 943
 944         /* Wait finish */
 945         if (do_wait && !lpc32xx_tc_ready(nand, 100)) {
 946                 LOG_ERROR("timeout while waiting for completion of DMA");
 947                 return ERROR_NAND_OPERATION_FAILED;
 948         }
 949
 950         return retval;
 951 }
 952
 953 static int lpc32xx_dma_ready(struct nand_device *nand, int timeout)
 954 {
 955         struct target *target = nand->target;
 956
 957         LOG_DEBUG("lpc32xx_dma_ready count start=%d", timeout);
 958
 959         do {
 960                 uint32_t tc_stat;
 961                 uint32_t err_stat;
 962                 int retval;
 963
 964                 /* Read DMACRawIntTCStat */
 965                 retval = target_read_u32(target, 0x31000014, &tc_stat);
 966                 if (retval != ERROR_OK) {
 967                         LOG_ERROR("Could not read DMACRawIntTCStat");
 968                         return 0;
 969                 }
 970                 /* Read DMACRawIntErrStat */
 971                 retval = target_read_u32(target, 0x31000018, &err_stat);
 972                 if (retval != ERROR_OK) {
 973                         LOG_ERROR("Could not read DMACRawIntErrStat");
 974                         return 0;
 975                 }
 976                 if ((tc_stat | err_stat) & 1) {
 977                         LOG_DEBUG("lpc32xx_dma_ready count=%d",
 978                                 timeout);
 979                         if (err_stat & 1) {
 980                                 LOG_ERROR("lpc32xx_dma_ready "
 981                                         "DMA error, aborted");
 982                                 return 0;
 983                         } else
 984                                 return 1;
 985                 }
 986
 987                 alive_sleep(1);
 988         } while (timeout-- > 0);
 989
 990         return 0;
 991 }
 992
 993 static uint32_t slc_ecc_copy_to_buffer(uint8_t *spare,
 994         const uint32_t *ecc, int count)
 995 {
 996         int i;
 997         for (i = 0; i < (count * 3); i += 3) {
 998                 uint32_t ce = ecc[i/3];
 999                 ce = ~(ce << 2) & 0xFFFFFF;
1000                 spare[i+2] = (uint8_t)(ce & 0xFF); ce >>= 8;
1001                 spare[i+1] = (uint8_t)(ce & 0xFF); ce >>= 8;
1002                 spare[i]   = (uint8_t)(ce & 0xFF);
1003         }
1004         return 0;
1005 }
1006
1007 static void lpc32xx_dump_oob(uint8_t *oob, uint32_t oob_size)
1008 {
1009         int addr = 0;
1010         while (oob_size > 0) {
1011                 LOG_DEBUG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x", addr,
1012                         oob[0], oob[1], oob[2], oob[3],
1013                         oob[4], oob[5], oob[6], oob[7]);
1014                 oob += 8;
1015                 addr += 8;
1016                 oob_size -= 8;
1017         }
1018 }
1019
1020 static int lpc32xx_write_page_slc(struct nand_device *nand,
1021         struct working_area *pworking_area,
1022         uint32_t page, uint8_t *data,
1023         uint32_t data_size, uint8_t *oob,
1024         uint32_t oob_size)
1025 {
1026         struct target *target = nand->target;
1027         int retval;
1028         uint32_t target_mem_base;
1029
1030         LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, "
1031                 "data_size=%" PRIu32 ", oob_size=%" PRIu32,
1032                 page, data != 0, oob != 0, data_size, oob_size);
1033
1034         target_mem_base = pworking_area->address;
1035         /*
1036          * Skip writing page which has all 0xFF data as this will
1037          * generate 0x0 value.
1038          */
1039         if (data && !oob) {
1040                 uint32_t i, all_ff = 1;
1041                 for (i = 0; i < data_size; i++)
1042                         if (data[i] != 0xFF) {
1043                                 all_ff = 0;
1044                                 break;
1045                         }
1046                 if (all_ff)
1047                         return ERROR_OK;
1048         }
1049         /* Make the dma descriptors in local memory */
1050         int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 0);
1051         /* Write them to target.
1052            XXX: Assumes host and target have same byte sex.
1053         */
1054         retval = target_write_memory(target, target_mem_base, 4,
1055                         nll * sizeof(struct dmac_ll) / 4,
1056                         (uint8_t *)dmalist);
1057         if (retval != ERROR_OK) {
1058                 LOG_ERROR("Could not write DMA descriptors to IRAM");
1059                 return retval;
1060         }
1061
1062         retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
1063         if (retval != ERROR_OK) {
1064                 LOG_ERROR("NAND_CMD_SEQIN failed");
1065                 return retval;
1066         }
1067
1068         /* SLC_CFG =
1069                Force nCE assert,
1070                DMA ECC enabled,
1071                ECC enabled,
1072                DMA burst enabled,
1073                DMA write to SLC,
1074                WIDTH = bus_width
1075         */
1076         retval = target_write_u32(target, 0x20020014, 0x3c);
1077         if (retval != ERROR_OK) {
1078                 LOG_ERROR("Could not set SLC_CFG");
1079                 return retval;
1080         }
1081         if (data) {
1082                 /* Write data to target */
1083                 static uint8_t fdata[2048];
1084                 memset(fdata, 0xFF, nand->page_size);
1085                 memcpy(fdata, data, data_size);
1086                 retval = target_write_memory(target,
1087                                 target_mem_base + DATA_OFFS,
1088                                 4, nand->page_size/4, fdata);
1089                 if (retval != ERROR_OK) {
1090                         LOG_ERROR("Could not write data to IRAM");
1091                         return retval;
1092                 }
1093
1094                 /* Write first descriptor to DMA controller */
1095                 retval = target_write_memory(target, 0x31000100, 4,
1096                                 sizeof(struct dmac_ll) / 4,
1097                                 (uint8_t *)dmalist);
1098                 if (retval != ERROR_OK) {
1099                         LOG_ERROR("Could not write DMA descriptor to DMAC");
1100                         return retval;
1101                 }
1102
1103                 /* Start xfer of data from iram to flash using DMA */
1104                 int tot_size = nand->page_size;
1105                 tot_size += tot_size == 2048 ? 64 : 16;
1106                 retval = lpc32xx_start_slc_dma(nand, tot_size, 0);
1107                 if (retval != ERROR_OK) {
1108                         LOG_ERROR("DMA failed");
1109                         return retval;
1110                 }
1111
1112                 /* Wait for DMA to finish.  SLC is not finished at this stage */
1113                 if (!lpc32xx_dma_ready(nand, 100)) {
1114                         LOG_ERROR("Data DMA failed during write");
1115                         return ERROR_FLASH_OPERATION_FAILED;
1116                 }
1117         }       /* data xfer */
1118
1119         /* Copy OOB to iram */
1120         static uint8_t foob[64];
1121         int foob_size = nand->page_size == 2048 ? 64 : 16;
1122         memset(foob, 0xFF, foob_size);
1123         if (oob)        /* Raw mode */
1124                 memcpy(foob, oob, oob_size);
1125         else {
1126                 /* Get HW generated ECC, made while writing data */
1127                 int ecc_count = nand->page_size == 2048 ? 8 : 2;
1128                 static uint32_t hw_ecc[8];
1129                 retval = target_read_memory(target, target_mem_base + ECC_OFFS,
1130                                 4, ecc_count, (uint8_t *)hw_ecc);
1131                 if (retval != ERROR_OK) {
1132                         LOG_ERROR("Reading hw generated ECC from IRAM failed");
1133                         return retval;
1134                 }
1135                 /* Copy to oob, at correct offsets */
1136                 static uint8_t ecc[24];
1137                 slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1138                 const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1139                 int i;
1140                 for (i = 0; i < ecc_count * 3; i++)
1141                         foob[layout[i]] = ecc[i];
1142                 lpc32xx_dump_oob(foob, foob_size);
1143         }
1144         retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
1145                         foob_size / 4, foob);
1146         if (retval != ERROR_OK) {
1147                 LOG_ERROR("Writing OOB to IRAM failed");
1148                 return retval;
1149         }
1150
1151         /* Write OOB descriptor to DMA controller */
1152         retval = target_write_memory(target, 0x31000100, 4,
1153                         sizeof(struct dmac_ll) / 4,
1154                         (uint8_t *)(&dmalist[nll-1]));
1155         if (retval != ERROR_OK) {
1156                 LOG_ERROR("Could not write OOB DMA descriptor to DMAC");
1157                 return retval;
1158         }
1159         if (data) {
1160                 /* Only restart DMA with last descriptor,
1161                  * don't setup SLC again */
1162
1163                 /* DMACIntTCClear = ch0 */
1164                 retval = target_write_u32(target, 0x31000008, 1);
1165                 if (retval != ERROR_OK) {
1166                         LOG_ERROR("Could not set DMACIntTCClear");
1167                         return retval;
1168                 }
1169                 /* DMACCxConfig=
1170                  * E=1,
1171                  * SrcPeripheral = 1 (SLC),
1172                  * DestPeripheral = 1 (SLC),
1173                  * FlowCntrl = 2 (Pher -> Mem, DMA),
1174                  * IE = 0,
1175                  * ITC = 0,
1176                  * L= 0,
1177                  * H=0
1178                 */
1179                 retval = target_write_u32(target, 0x31000110,
1180                                 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
1181                                 | 0<<15 | 0<<16 | 0<<18);
1182                 if (retval != ERROR_OK) {
1183                         LOG_ERROR("Could not set DMACC0Config");
1184                         return retval;
1185                 }
1186                 /* Wait finish */
1187                 if (!lpc32xx_tc_ready(nand, 100)) {
1188                         LOG_ERROR("timeout while waiting for "
1189                                 "completion of DMA");
1190                         return ERROR_NAND_OPERATION_FAILED;
1191                 }
1192         } else {
1193                 /* Start xfer of data from iram to flash using DMA */
1194                 retval = lpc32xx_start_slc_dma(nand, foob_size, 1);
1195                 if (retval != ERROR_OK) {
1196                         LOG_ERROR("DMA OOB failed");
1197                         return retval;
1198                 }
1199         }
1200
1201         /* Let NAND start actual writing */
1202         retval = nand_write_finish(nand);
1203         if (retval != ERROR_OK) {
1204                 LOG_ERROR("nand_write_finish failed");
1205                 return retval;
1206         }
1207
1208         return ERROR_OK;
1209 }
1210
1211 static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
1212         uint8_t *data, uint32_t data_size,
1213         uint8_t *oob, uint32_t oob_size)
1214 {
1215         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1216         struct target *target = nand->target;
1217         int retval = ERROR_OK;
1218
1219         if (target->state != TARGET_HALTED) {
1220                 LOG_ERROR("target must be halted to use LPC32xx "
1221                         "NAND flash controller");
1222                 return ERROR_NAND_OPERATION_FAILED;
1223         }
1224
1225         if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
1226                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1227                 return ERROR_NAND_OPERATION_FAILED;
1228         } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
1229                 if (!data && oob) {
1230                         LOG_ERROR("LPC32xx MLC controller can't write "
1231                                 "OOB data only");
1232                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1233                 }
1234
1235                 if (oob && (oob_size > 24)) {
1236                         LOG_ERROR("LPC32xx MLC controller can't write more "
1237                                 "than 6 bytes for each quarter's OOB data");
1238                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1239                 }
1240
1241                 if (data_size > (uint32_t)nand->page_size) {
1242                         LOG_ERROR("data size exceeds page size");
1243                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1244                 }
1245
1246                 retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
1247                                 oob, oob_size);
1248         } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
1249                 struct working_area *pworking_area;
1250                 if (!data && oob) {
1251                         /*
1252                          * if oob only mode is active original method is used
1253                          * as SLC controller hangs during DMA interworking. (?)
1254                          * Anyway the code supports the oob only mode below.
1255                          */
1256                         return nand_write_page_raw(nand, page, data,
1257                                 data_size, oob, oob_size);
1258                 }
1259                 retval = target_alloc_working_area(target,
1260                                 nand->page_size + DATA_OFFS,
1261                                 &pworking_area);
1262                 if (retval != ERROR_OK) {
1263                         LOG_ERROR("Can't allocate working area in "
1264                                 "LPC internal RAM");
1265                         return ERROR_FLASH_OPERATION_FAILED;
1266                 }
1267                 retval = lpc32xx_write_page_slc(nand, pworking_area, page,
1268                                 data, data_size, oob, oob_size);
1269                 target_free_working_area(target, pworking_area);
1270         }
1271
1272         return retval;
1273 }
1274
1275 static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page,
1276         uint8_t *data, uint32_t data_size,
1277         uint8_t *oob, uint32_t oob_size)
1278 {
1279         struct target *target = nand->target;
1280         static uint8_t page_buffer[2048];
1281         static uint8_t oob_buffer[64];
1282         uint32_t page_bytes_done = 0;
1283         uint32_t oob_bytes_done = 0;
1284         uint32_t mlc_isr;
1285         int retval;
1286
1287         if (!data && oob) {
1288                 /* MLC_CMD = Read OOB
1289                  * we can use the READOOB command on both small and large page
1290                  * devices, as the controller translates the 0x50 command to
1291                  * a 0x0 with appropriate positioning of the serial buffer
1292                  * read pointer
1293                  */
1294                 retval = target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
1295         } else {
1296                 /* MLC_CMD = Read0 */
1297                 retval = target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
1298         }
1299         if (retval != ERROR_OK) {
1300                 LOG_ERROR("could not set MLC_CMD");
1301                 return ERROR_NAND_OPERATION_FAILED;
1302         }
1303         if (nand->page_size == 512) {
1304                 /* small page device
1305                  * MLC_ADDR = 0x0 (one column cycle) */
1306                 retval = target_write_u32(target, 0x200b8004, 0x0);
1307                 if (retval != ERROR_OK) {
1308                         LOG_ERROR("could not set MLC_ADDR");
1309                         return ERROR_NAND_OPERATION_FAILED;
1310                 }
1311
1312                 /* MLC_ADDR = row */
1313                 retval = target_write_u32(target, 0x200b8004, page & 0xff);
1314                 if (retval != ERROR_OK) {
1315                         LOG_ERROR("could not set MLC_ADDR");
1316                         return ERROR_NAND_OPERATION_FAILED;
1317                 }
1318                 retval = target_write_u32(target, 0x200b8004,
1319                                 (page >> 8) & 0xff);
1320                 if (retval != ERROR_OK) {
1321                         LOG_ERROR("could not set MLC_ADDR");
1322                         return ERROR_NAND_OPERATION_FAILED;
1323                 }
1324
1325                 if (nand->address_cycles == 4) {
1326                         retval = target_write_u32(target, 0x200b8004,
1327                                         (page >> 16) & 0xff);
1328                         if (retval != ERROR_OK) {
1329                                 LOG_ERROR("could not set MLC_ADDR");
1330                                 return ERROR_NAND_OPERATION_FAILED;
1331                         }
1332                 }
1333         } else {
1334                 /* large page device
1335                  * MLC_ADDR = 0x0 (two column cycles) */
1336                 retval = target_write_u32(target, 0x200b8004, 0x0);
1337                 if (retval != ERROR_OK) {
1338                         LOG_ERROR("could not set MLC_ADDR");
1339                         return ERROR_NAND_OPERATION_FAILED;
1340                 }
1341                 retval = target_write_u32(target, 0x200b8004, 0x0);
1342                 if (retval != ERROR_OK) {
1343                         LOG_ERROR("could not set MLC_ADDR");
1344                         return ERROR_NAND_OPERATION_FAILED;
1345                 }
1346
1347                 /* MLC_ADDR = row */
1348                 retval = target_write_u32(target, 0x200b8004, page & 0xff);
1349                 if (retval != ERROR_OK) {
1350                         LOG_ERROR("could not set MLC_ADDR");
1351                         return ERROR_NAND_OPERATION_FAILED;
1352                 }
1353                 retval = target_write_u32(target, 0x200b8004,
1354                                 (page >> 8) & 0xff);
1355                 if (retval != ERROR_OK) {
1356                         LOG_ERROR("could not set MLC_ADDR");
1357                         return ERROR_NAND_OPERATION_FAILED;
1358                 }
1359
1360                 /* MLC_CMD = Read Start */
1361                 retval = target_write_u32(target, 0x200b8000,
1362                                 NAND_CMD_READSTART);
1363                 if (retval != ERROR_OK) {
1364                         LOG_ERROR("could not set MLC_CMD");
1365                         return ERROR_NAND_OPERATION_FAILED;
1366                 }
1367         }
1368
1369         while (page_bytes_done < (uint32_t)nand->page_size) {
1370                 /* MLC_ECC_AUTO_DEC_REG = dummy */
1371                 retval = target_write_u32(target, 0x200b8014, 0xaa55aa55);
1372                 if (retval != ERROR_OK) {
1373                         LOG_ERROR("could not set MLC_ECC_AUTO_DEC_REG");
1374                         return ERROR_NAND_OPERATION_FAILED;
1375                 }
1376
1377                 if (!lpc32xx_controller_ready(nand, 1000)) {
1378                         LOG_ERROR("timeout while waiting for "
1379                                 "completion of auto decode cycle");
1380                         return ERROR_NAND_OPERATION_FAILED;
1381                 }
1382
1383                 retval = target_read_u32(target, 0x200b8048, &mlc_isr);
1384                 if (retval != ERROR_OK) {
1385                         LOG_ERROR("could not read MLC_ISR");
1386                         return ERROR_NAND_OPERATION_FAILED;
1387                 }
1388
1389                 if (mlc_isr & 0x8) {
1390                         if (mlc_isr & 0x40) {
1391                                 LOG_ERROR("uncorrectable error detected: "
1392                                         "0x%2.2x", (unsigned)mlc_isr);
1393                                 return ERROR_NAND_OPERATION_FAILED;
1394                         }
1395
1396                         LOG_WARNING("%i symbol error detected and corrected",
1397                                 ((int)(((mlc_isr & 0x30) >> 4) + 1)));
1398                 }
1399
1400                 if (data) {
1401                         retval = target_read_memory(target, 0x200a8000, 4, 128,
1402                                         page_buffer + page_bytes_done);
1403                         if (retval != ERROR_OK) {
1404                                 LOG_ERROR("could not read MLC_BUF (data)");
1405                                 return ERROR_NAND_OPERATION_FAILED;
1406                         }
1407                 }
1408
1409                 if (oob) {
1410                         retval = target_read_memory(target, 0x200a8000, 4, 4,
1411                                         oob_buffer + oob_bytes_done);
1412                         if (retval != ERROR_OK) {
1413                                 LOG_ERROR("could not read MLC_BUF (oob)");
1414                                 return ERROR_NAND_OPERATION_FAILED;
1415                         }
1416                 }
1417
1418                 page_bytes_done += 512;
1419                 oob_bytes_done += 16;
1420         }
1421
1422         if (data)
1423                 memcpy(data, page_buffer, data_size);
1424
1425         if (oob)
1426                 memcpy(oob, oob_buffer, oob_size);
1427
1428         return ERROR_OK;
1429 }
1430
1431 static int lpc32xx_read_page_slc(struct nand_device *nand,
1432         struct working_area *pworking_area,
1433         uint32_t page, uint8_t *data,
1434         uint32_t data_size, uint8_t *oob,
1435         uint32_t oob_size)
1436 {
1437         struct target *target = nand->target;
1438         int retval;
1439         uint32_t target_mem_base;
1440
1441         LOG_DEBUG("SLC read page %" PRIx32 " data=%" PRIu32 ", oob=%" PRIu32,
1442                 page, data_size, oob_size);
1443
1444         target_mem_base = pworking_area->address;
1445
1446         /* Make the dma descriptors in local memory */
1447         int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 1);
1448         /* Write them to target.
1449            XXX: Assumes host and target have same byte sex.
1450         */
1451         retval = target_write_memory(target, target_mem_base, 4,
1452                         nll * sizeof(struct dmac_ll) / 4,
1453                         (uint8_t *)dmalist);
1454         if (retval != ERROR_OK) {
1455                 LOG_ERROR("Could not write DMA descriptors to IRAM");
1456                 return retval;
1457         }
1458
1459         retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
1460         if (retval != ERROR_OK) {
1461                 LOG_ERROR("lpc32xx_read_page_slc: NAND_CMD_READ0 failed");
1462                 return retval;
1463         }
1464
1465         /* SLC_CFG =
1466                Force nCE assert,
1467                DMA ECC enabled,
1468                ECC enabled,
1469                DMA burst enabled,
1470                DMA read from SLC,
1471                WIDTH = bus_width
1472         */
1473         retval = target_write_u32(target, 0x20020014, 0x3e);
1474         if (retval != ERROR_OK) {
1475                 LOG_ERROR("lpc32xx_read_page_slc: Could not set SLC_CFG");
1476                 return retval;
1477         }
1478
1479         /* Write first descriptor to DMA controller */
1480         retval = target_write_memory(target, 0x31000100, 4,
1481                         sizeof(struct dmac_ll) / 4, (uint8_t *)dmalist);
1482         if (retval != ERROR_OK) {
1483                 LOG_ERROR("Could not write DMA descriptor to DMAC");
1484                 return retval;
1485         }
1486
1487         /* Start xfer of data from flash to iram using DMA */
1488         int tot_size = nand->page_size;
1489         tot_size += nand->page_size == 2048 ? 64 : 16;
1490         retval = lpc32xx_start_slc_dma(nand, tot_size, 1);
1491         if (retval != ERROR_OK) {
1492                 LOG_ERROR("lpc32xx_read_page_slc: DMA read failed");
1493                 return retval;
1494         }
1495
1496         /* Copy data from iram */
1497         if (data) {
1498                 retval = target_read_memory(target, target_mem_base + DATA_OFFS,
1499                                 4, data_size/4, data);
1500                 if (retval != ERROR_OK) {
1501                         LOG_ERROR("Could not read data from IRAM");
1502                         return retval;
1503                 }
1504         }
1505         if (oob) {
1506                 /* No error correction, just return data as read from flash */
1507                 retval = target_read_memory(target,
1508                                 target_mem_base + SPARE_OFFS, 4,
1509                                 oob_size/4, oob);
1510                 if (retval != ERROR_OK) {
1511                         LOG_ERROR("Could not read OOB from IRAM");
1512                         return retval;
1513                 }
1514                 return ERROR_OK;
1515         }
1516
1517         /* Copy OOB from flash, stored in IRAM */
1518         static uint8_t foob[64];
1519         retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
1520                         4, nand->page_size == 2048 ? 16 : 4, foob);
1521         lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
1522         if (retval != ERROR_OK) {
1523                 LOG_ERROR("Could not read OOB from IRAM");
1524                 return retval;
1525         }
1526         /* Copy ECC from HW, generated while reading */
1527         int ecc_count = nand->page_size == 2048 ? 8 : 2;
1528         static uint32_t hw_ecc[8];      /* max size */
1529         retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
1530                         ecc_count, (uint8_t *)hw_ecc);
1531         if (retval != ERROR_OK) {
1532                 LOG_ERROR("Could not read hw generated ECC from IRAM");
1533                 return retval;
1534         }
1535         static uint8_t ecc[24];
1536         slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1537         /* Copy ECC from flash using correct layout */
1538         static uint8_t fecc[24];/* max size */
1539         const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1540         int i;
1541         for (i = 0; i < ecc_count * 3; i++)
1542                 fecc[i] = foob[layout[i]];
1543         /* Compare ECC and possibly correct data */
1544         for (i = 0; i < ecc_count; i++) {
1545                 retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3],
1546                                 &ecc[i * 3]);
1547                 if (retval > 0)
1548                         LOG_WARNING("error detected and corrected: %" PRIu32 "/%d",
1549                                 page, i);
1550                 if (retval < 0)
1551                         break;
1552         }
1553         if (i == ecc_count)
1554                 retval = ERROR_OK;
1555         else {
1556                 LOG_ERROR("uncorrectable error detected: %" PRIu32 "/%d", page, i);
1557                 retval = ERROR_NAND_OPERATION_FAILED;
1558         }
1559         return retval;
1560 }
1561
1562 static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
1563         uint8_t *data, uint32_t data_size,
1564         uint8_t *oob, uint32_t oob_size)
1565 {
1566         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1567         struct target *target = nand->target;
1568         int retval = ERROR_OK;
1569
1570         if (target->state != TARGET_HALTED) {
1571                 LOG_ERROR("target must be halted to use LPC32xx "
1572                         "NAND flash controller");
1573                 return ERROR_NAND_OPERATION_FAILED;
1574         }
1575
1576         if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
1577                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1578                 return ERROR_NAND_OPERATION_FAILED;
1579         } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
1580                 if (data_size > (uint32_t)nand->page_size) {
1581                         LOG_ERROR("data size exceeds page size");
1582                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1583                 }
1584                 retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
1585                                 oob, oob_size);
1586         } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
1587                 struct working_area *pworking_area;
1588
1589                 retval = target_alloc_working_area(target,
1590                                 nand->page_size + 0x200,
1591                                 &pworking_area);
1592                 if (retval != ERROR_OK) {
1593                         LOG_ERROR("Can't allocate working area in "
1594                                 "LPC internal RAM");
1595                         return ERROR_FLASH_OPERATION_FAILED;
1596                 }
1597                 retval = lpc32xx_read_page_slc(nand, pworking_area, page,
1598                                 data, data_size, oob, oob_size);
1599                 target_free_working_area(target, pworking_area);
1600         }
1601
1602         return retval;
1603 }
1604
1605 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
1606 {
1607         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1608         struct target *target = nand->target;
1609         int retval;
1610
1611         if (target->state != TARGET_HALTED) {
1612                 LOG_ERROR("target must be halted to use LPC32xx "
1613                         "NAND flash controller");
1614                 return ERROR_NAND_OPERATION_FAILED;
1615         }
1616
1617         LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
1618
1619         do {
1620                 if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
1621                         uint8_t status;
1622
1623                         /* Read MLC_ISR, wait for controller to become ready */
1624                         retval = target_read_u8(target, 0x200b8048, &status);
1625                         if (retval != ERROR_OK) {
1626                                 LOG_ERROR("could not set MLC_STAT");
1627                                 return ERROR_NAND_OPERATION_FAILED;
1628                         }
1629
1630                         if (status & 2) {
1631                                 LOG_DEBUG("lpc32xx_controller_ready count=%d",
1632                                         timeout);
1633                                 return 1;
1634                         }
1635                 } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
1636                         uint32_t status;
1637
1638                         /* Read SLC_STAT and check READY bit */
1639                         retval = target_read_u32(target, 0x20020018, &status);
1640                         if (retval != ERROR_OK) {
1641                                 LOG_ERROR("could not set SLC_STAT");
1642                                 return ERROR_NAND_OPERATION_FAILED;
1643                         }
1644
1645                         if (status & 1) {
1646                                 LOG_DEBUG("lpc32xx_controller_ready count=%d",
1647                                         timeout);
1648                                 return 1;
1649                         }
1650                 }
1651
1652                 alive_sleep(1);
1653         } while (timeout-- > 0);
1654
1655         return 0;
1656 }
1657
1658 static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
1659 {
1660         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1661         struct target *target = nand->target;
1662         int retval;
1663
1664         if (target->state != TARGET_HALTED) {
1665                 LOG_ERROR("target must be halted to use LPC32xx "
1666                         "NAND flash controller");
1667                 return ERROR_NAND_OPERATION_FAILED;
1668         }
1669
1670         LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
1671
1672         do {
1673                 if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
1674                         uint8_t status = 0x0;
1675
1676                         /* Read MLC_ISR, wait for NAND flash device to
1677                          * become ready */
1678                         retval = target_read_u8(target, 0x200b8048, &status);
1679                         if (retval != ERROR_OK) {
1680                                 LOG_ERROR("could not read MLC_ISR");
1681                                 return ERROR_NAND_OPERATION_FAILED;
1682                         }
1683
1684                         if (status & 1) {
1685                                 LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1686                                         timeout);
1687                                 return 1;
1688                         }
1689                 } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
1690                         uint32_t status = 0x0;
1691
1692                         /* Read SLC_STAT and check READY bit */
1693                         retval = target_read_u32(target, 0x20020018, &status);
1694                         if (retval != ERROR_OK) {
1695                                 LOG_ERROR("could not read SLC_STAT");
1696                                 return ERROR_NAND_OPERATION_FAILED;
1697                         }
1698
1699                         if (status & 1) {
1700                                 LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1701                                         timeout);
1702                                 return 1;
1703                         }
1704                 }
1705
1706                 alive_sleep(1);
1707         } while (timeout-- > 0);
1708
1709         return 0;
1710 }
1711
1712 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout)
1713 {
1714         struct target *target = nand->target;
1715
1716         LOG_DEBUG("lpc32xx_tc_ready count start=%d", timeout);
1717
1718         do {
1719                 uint32_t status = 0x0;
1720                 int retval;
1721                 /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1722                 retval = target_read_u32(target, 0x2002001c, &status);
1723                 if (retval != ERROR_OK) {
1724                         LOG_ERROR("Could not read SLC_INT_STAT");
1725                         return 0;
1726                 }
1727                 if (status & 2) {
1728                         LOG_DEBUG("lpc32xx_tc_ready count=%d", timeout);
1729                         return 1;
1730                 }
1731
1732                 alive_sleep(1);
1733         } while (timeout-- > 0);
1734
1735         return 0;
1736 }
1737
1738 COMMAND_HANDLER(handle_lpc32xx_select_command)
1739 {
1740         struct lpc32xx_nand_controller *lpc32xx_info = NULL;
1741         char *selected[] = {
1742                 "no", "mlc", "slc"
1743         };
1744
1745         if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
1746                 return ERROR_COMMAND_SYNTAX_ERROR;
1747
1748         unsigned num;
1749         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1750         struct nand_device *nand = get_nand_device_by_num(num);
1751         if (!nand) {
1752                 command_print(CMD, "nand device '#%s' is out of bounds",
1753                         CMD_ARGV[0]);
1754                 return ERROR_OK;
1755         }
1756
1757         lpc32xx_info = nand->controller_priv;
1758
1759         if (CMD_ARGC >= 2) {
1760                 if (strcmp(CMD_ARGV[1], "mlc") == 0) {
1761                         lpc32xx_info->selected_controller =
1762                                 LPC32XX_MLC_CONTROLLER;
1763                 } else if (strcmp(CMD_ARGV[1], "slc") == 0) {
1764                         lpc32xx_info->selected_controller =
1765                                 LPC32XX_SLC_CONTROLLER;
1766                 } else
1767                         return ERROR_COMMAND_SYNTAX_ERROR;
1768         }
1769
1770         command_print(CMD, "%s controller selected",
1771                 selected[lpc32xx_info->selected_controller]);
1772
1773         return ERROR_OK;
1774 }
1775
1776 static const struct command_registration lpc32xx_exec_command_handlers[] = {
1777         {
1778                 .name = "select",
1779                 .handler = handle_lpc32xx_select_command,
1780                 .mode = COMMAND_EXEC,
1781                 .help = "select MLC or SLC controller (default is MLC)",
1782                 .usage = "bank_id ['mlc'|'slc' ]",
1783         },
1784         COMMAND_REGISTRATION_DONE
1785 };
1786 static const struct command_registration lpc32xx_command_handler[] = {
1787         {
1788                 .name = "lpc32xx",
1789                 .mode = COMMAND_ANY,
1790                 .help = "LPC32xx NAND flash controller commands",
1791                 .usage = "",
1792                 .chain = lpc32xx_exec_command_handlers,
1793         },
1794         COMMAND_REGISTRATION_DONE
1795 };
1796
1797 struct nand_flash_controller lpc32xx_nand_controller = {
1798         .name = "lpc32xx",
1799         .commands = lpc32xx_command_handler,
1800         .nand_device_command = lpc32xx_nand_device_command,
1801         .init = lpc32xx_init,
1802         .reset = lpc32xx_reset,
1803         .command = lpc32xx_command,
1804         .address = lpc32xx_address,
1805         .write_data = lpc32xx_write_data,
1806         .read_data = lpc32xx_read_data,
1807         .write_page = lpc32xx_write_page,
1808         .read_page = lpc32xx_read_page,
1809         .nand_ready = lpc32xx_nand_ready,
1810 };