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   1
   2 /***************************************************************************
   3  *   Copyright (C) 2009 by Alexei Babich                                   *
   4  *   Rezonans plc., Chelyabinsk, Russia                                    *
   5  *   impatt@mail.ru                                                        *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 /*
  24  * Freescale iMX3* OpenOCD NAND Flash controller support.
  25  *
  26  * Many thanks to Ben Dooks for writing s3c24xx driver.
  27  */
  28
  29 /*
  30 driver tested with STMicro NAND512W3A @imx31
  31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
  32 get_next_halfword_from_sram_buffer() not tested
  33 */
  34 #ifdef HAVE_CONFIG_H
  35 #include "config.h"
  36 #endif
  37
  38 #include "mx3_nand.h"
  39
  40 static const char target_not_halted_err_msg[] =
  41         "target must be halted to use mx3 NAND flash controller";
  42 static const char data_block_size_err_msg[] =
  43         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  44 static const char sram_buffer_bounds_err_msg[] =
  45         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  46 static const char get_status_register_err_msg[] = "can't get NAND status";
  47 static uint32_t in_sram_address;
  48 unsigned char sign_of_sequental_byte_read;
  49
  50 static int test_iomux_settings (struct target * target, uint32_t value,
  51                                 uint32_t mask, const char *text);
  52 static int initialize_nf_controller (struct nand_device *nand);
  53 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value);
  54 static int get_next_halfword_from_sram_buffer (struct target * target,
  55                                                uint16_t * value);
  56 static int poll_for_complete_op (struct target * target, const char *text);
  57 static int validate_target_state (struct nand_device *nand);
  58 static int do_data_output (struct nand_device *nand);
  59
  60 static int imx31_command (struct nand_device *nand, uint8_t command);
  61 static int imx31_address (struct nand_device *nand, uint8_t address);
  62 static int imx31_controller_ready (struct nand_device *nand, int tout);
  63
  64 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
  65 {
  66         struct mx3_nf_controller *mx3_nf_info;
  67         mx3_nf_info = malloc (sizeof (struct mx3_nf_controller));
  68         if (mx3_nf_info == NULL)
  69         {
  70             LOG_ERROR ("no memory for nand controller");
  71             return ERROR_FAIL;
  72         }
  73
  74         nand->controller_priv = mx3_nf_info;
  75
  76         mx3_nf_info->target = get_target (args[1]);
  77         if (mx3_nf_info->target == NULL)
  78         {
  79             LOG_ERROR ("target '%s' not defined", args[1]);
  80             return ERROR_FAIL;
  81         }
  82         if (argc < 3)
  83         {
  84             LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
  85             return ERROR_FAIL;
  86         }
  87         /*
  88         * check hwecc requirements
  89         */
  90         {
  91         int hwecc_needed;
  92         hwecc_needed = strcmp (args[2], "hwecc");
  93         if (hwecc_needed == 0)
  94             {
  95                 mx3_nf_info->flags.hw_ecc_enabled = 1;
  96             }
  97         else
  98             {
  99                 mx3_nf_info->flags.hw_ecc_enabled = 0;
 100             }
 101         }
 102
 103         mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
 104         mx3_nf_info->fin = MX3_NF_FIN_NONE;
 105         mx3_nf_info->flags.target_little_endian =
 106         (mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
 107         /*
 108         * testing host endianess
 109         */
 110         {
 111         int x = 1;
 112         if (*(char *) &x == 1)
 113             {
 114                 mx3_nf_info->flags.host_little_endian = 1;
 115             }
 116         else
 117             {
 118                 mx3_nf_info->flags.host_little_endian = 0;
 119             }
 120         }
 121         return ERROR_OK;
 122 }
 123
 124 static int imx31_init (struct nand_device *nand)
 125 {
 126         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 127         struct target *target = mx3_nf_info->target;
 128
 129         {
 130         /*
 131          * validate target state
 132          */
 133         int validate_target_result;
 134         validate_target_result = validate_target_state(nand);
 135         if (validate_target_result != ERROR_OK)
 136             {
 137                 return validate_target_result;
 138             }
 139         }
 140
 141         {
 142         uint16_t buffsize_register_content;
 143         target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
 144         mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 145         }
 146
 147         {
 148         uint32_t pcsr_register_content;
 149         target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
 150         if (!nand->bus_width)
 151             {
 152                 nand->bus_width =
 153                     (pcsr_register_content & 0x80000000) ? 16 : 8;
 154             }
 155         else
 156             {
 157                 pcsr_register_content |=
 158                     ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
 159                 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
 160             }
 161
 162         if (!nand->page_size)
 163             {
 164                 nand->page_size =
 165                     (pcsr_register_content & 0x40000000) ? 2048 : 512;
 166             }
 167         else
 168             {
 169                 pcsr_register_content |=
 170                     ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
 171                 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
 172             }
 173         if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048))
 174             {
 175                 LOG_ERROR
 176                     ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
 177             }
 178         }
 179
 180         {
 181         uint32_t cgr_register_content;
 182         target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
 183         if (!(cgr_register_content & 0x00000300))
 184             {
 185                 LOG_ERROR ("clock gating to EMI disabled");
 186                 return ERROR_FAIL;
 187             }
 188         }
 189
 190         {
 191         uint32_t gpr_register_content;
 192         target_read_u32 (target, MX3_GPR, &gpr_register_content);
 193         if (gpr_register_content & 0x00000060)
 194             {
 195                 LOG_ERROR ("pins mode overrided by GPR");
 196                 return ERROR_FAIL;
 197             }
 198         }
 199
 200         {
 201         /*
 202          * testing IOMUX settings; must be in "functional-mode output and
 203          * functional-mode input" mode
 204          */
 205         int test_iomux;
 206         test_iomux = ERROR_OK;
 207         test_iomux |=
 208             test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
 209         test_iomux |=
 210             test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
 211         test_iomux |=
 212             test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
 213         if (nand->bus_width == 16)
 214             {
 215                 test_iomux |=
 216                     test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
 217                                          "d8,d9,d10");
 218                 test_iomux |=
 219                     test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
 220                                          "d11,d12,d13,d14");
 221                 test_iomux |=
 222                     test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
 223             }
 224         test_iomux |=
 225             test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
 226                                  "nfwp,nfce,nfrb");
 227         test_iomux |=
 228             test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
 229                                  "nfwe,nfre,nfale,nfcle");
 230         if (test_iomux != ERROR_OK)
 231             {
 232                 return ERROR_FAIL;
 233             }
 234         }
 235
 236         initialize_nf_controller (nand);
 237
 238         {
 239         int retval;
 240         uint16_t nand_status_content;
 241         retval = ERROR_OK;
 242         retval |= imx31_command (nand, NAND_CMD_STATUS);
 243         retval |= imx31_address (nand, 0x00);
 244         retval |= do_data_output (nand);
 245         if (retval != ERROR_OK)
 246             {
 247                 LOG_ERROR (get_status_register_err_msg);
 248                 return ERROR_FAIL;
 249             }
 250         target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
 251         if (!(nand_status_content & 0x0080))
 252             {
 253                 /*
 254                  * is host-big-endian correctly ??
 255                  */
 256                 LOG_INFO ("NAND read-only");
 257                 mx3_nf_info->flags.nand_readonly = 1;
 258             }
 259         else
 260             {
 261                 mx3_nf_info->flags.nand_readonly = 0;
 262             }
 263         }
 264         return ERROR_OK;
 265 }
 266
 267 static int imx31_read_data (struct nand_device *nand, void *data)
 268 {
 269         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 270         struct target *target = mx3_nf_info->target;
 271         {
 272         /*
 273          * validate target state
 274          */
 275         int validate_target_result;
 276         validate_target_result = validate_target_state (nand);
 277         if (validate_target_result != ERROR_OK)
 278             {
 279                 return validate_target_result;
 280             }
 281         }
 282
 283         {
 284         /*
 285          * get data from nand chip
 286          */
 287         int try_data_output_from_nand_chip;
 288         try_data_output_from_nand_chip = do_data_output (nand);
 289         if (try_data_output_from_nand_chip != ERROR_OK)
 290             {
 291                 return try_data_output_from_nand_chip;
 292             }
 293         }
 294
 295         if (nand->bus_width == 16)
 296         {
 297             get_next_halfword_from_sram_buffer (target, data);
 298         }
 299         else
 300         {
 301             get_next_byte_from_sram_buffer (target, data);
 302         }
 303
 304         return ERROR_OK;
 305 }
 306
 307 static int imx31_write_data (struct nand_device *nand, uint16_t data)
 308 {
 309         LOG_ERROR ("write_data() not implemented");
 310         return ERROR_NAND_OPERATION_FAILED;
 311 }
 312
 313 static int imx31_nand_ready (struct nand_device *nand, int timeout)
 314 {
 315         return imx31_controller_ready (nand, timeout);
 316 }
 317
 318 static int imx31_register_commands (struct command_context_s *cmd_ctx)
 319 {
 320         return ERROR_OK;
 321 }
 322
 323 static int imx31_reset (struct nand_device *nand)
 324 {
 325         /*
 326         * validate target state
 327         */
 328         int validate_target_result;
 329         validate_target_result = validate_target_state (nand);
 330         if (validate_target_result != ERROR_OK)
 331         {
 332             return validate_target_result;
 333         }
 334         initialize_nf_controller (nand);
 335         return ERROR_OK;
 336 }
 337
 338 static int imx31_command (struct nand_device *nand, uint8_t command)
 339 {
 340         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 341         struct target *target = mx3_nf_info->target;
 342         {
 343         /*
 344          * validate target state
 345          */
 346         int validate_target_result;
 347         validate_target_result = validate_target_state (nand);
 348         if (validate_target_result != ERROR_OK)
 349             {
 350                 return validate_target_result;
 351             }
 352         }
 353
 354         switch (command)
 355         {
 356             case NAND_CMD_READOOB:
 357                 command = NAND_CMD_READ0;
 358                 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
 359                                                          * data_read() and
 360                                                          * read_block_data() to
 361                                                          * spare area in SRAM
 362                                                          * buffer */
 363                 break;
 364             case NAND_CMD_READ1:
 365                 command = NAND_CMD_READ0;
 366                 /*
 367                  * offset == one half of page size
 368                  */
 369                 in_sram_address =
 370                     MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 371             default:
 372                 in_sram_address = MX3_NF_MAIN_BUFFER0;
 373         }
 374
 375         target_write_u16 (target, MX3_NF_FCMD, command);
 376         /*
 377         * start command input operation (set MX3_NF_BIT_OP_DONE==0)
 378         */
 379         target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
 380         {
 381         int poll_result;
 382         poll_result = poll_for_complete_op (target, "command");
 383         if (poll_result != ERROR_OK)
 384             {
 385                 return poll_result;
 386             }
 387         }
 388         /*
 389         * reset cursor to begin of the buffer
 390         */
 391         sign_of_sequental_byte_read = 0;
 392         switch (command)
 393         {
 394             case NAND_CMD_READID:
 395                 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
 396                 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 397                 break;
 398             case NAND_CMD_STATUS:
 399                 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
 400                 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 401                 break;
 402             case NAND_CMD_READ0:
 403                 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 404                 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
 405                 break;
 406             default:
 407                 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
 408         }
 409         return ERROR_OK;
 410 }
 411
 412 static int imx31_address (struct nand_device *nand, uint8_t address)
 413 {
 414         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 415         struct target *target = mx3_nf_info->target;
 416         {
 417         /*
 418          * validate target state
 419          */
 420         int validate_target_result;
 421         validate_target_result = validate_target_state (nand);
 422         if (validate_target_result != ERROR_OK)
 423             {
 424                 return validate_target_result;
 425             }
 426         }
 427
 428         target_write_u16 (target, MX3_NF_FADDR, address);
 429         /*
 430         * start address input operation (set MX3_NF_BIT_OP_DONE==0)
 431         */
 432         target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
 433         {
 434         int poll_result;
 435         poll_result = poll_for_complete_op (target, "address");
 436         if (poll_result != ERROR_OK)
 437             {
 438                 return poll_result;
 439             }
 440         }
 441         return ERROR_OK;
 442 }
 443
 444 static int imx31_controller_ready (struct nand_device *nand, int tout)
 445 {
 446         uint16_t poll_complete_status;
 447         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 448         struct target *target = mx3_nf_info->target;
 449
 450         {
 451         /*
 452          * validate target state
 453          */
 454         int validate_target_result;
 455         validate_target_result = validate_target_state (nand);
 456         if (validate_target_result != ERROR_OK)
 457             {
 458                 return validate_target_result;
 459             }
 460         }
 461
 462         do
 463         {
 464             target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
 465             if (poll_complete_status & MX3_NF_BIT_OP_DONE)
 466                 {
 467                     return tout;
 468                 }
 469             alive_sleep (1);
 470         }
 471         while (tout-- > 0);
 472         return tout;
 473 }
 474
 475 static int imx31_write_page (struct nand_device *nand, uint32_t page,
 476                              uint8_t * data, uint32_t data_size, uint8_t * oob,
 477                              uint32_t oob_size)
 478 {
 479         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 480         struct target *target = mx3_nf_info->target;
 481
 482         if (data_size % 2)
 483         {
 484             LOG_ERROR (data_block_size_err_msg, data_size);
 485             return ERROR_NAND_OPERATION_FAILED;
 486         }
 487         if (oob_size % 2)
 488         {
 489             LOG_ERROR (data_block_size_err_msg, oob_size);
 490             return ERROR_NAND_OPERATION_FAILED;
 491         }
 492         if (!data)
 493         {
 494             LOG_ERROR ("nothing to program");
 495             return ERROR_NAND_OPERATION_FAILED;
 496         }
 497         {
 498         /*
 499          * validate target state
 500          */
 501         int retval;
 502         retval = validate_target_state (nand);
 503         if (retval != ERROR_OK)
 504             {
 505                 return retval;
 506             }
 507         }
 508         {
 509         int retval = ERROR_OK;
 510         retval |= imx31_command(nand, NAND_CMD_SEQIN);
 511         retval |= imx31_address(nand, 0x00);
 512         retval |= imx31_address(nand, page & 0xff);
 513         retval |= imx31_address(nand, (page >> 8) & 0xff);
 514         if (nand->address_cycles >= 4)
 515             {
 516                 retval |= imx31_address (nand, (page >> 16) & 0xff);
 517                 if (nand->address_cycles >= 5)
 518                     {
 519                         retval |= imx31_address (nand, (page >> 24) & 0xff);
 520                     }
 521             }
 522         target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
 523         if (oob)
 524             {
 525                 if (mx3_nf_info->flags.hw_ecc_enabled)
 526                     {
 527                         /*
 528                          * part of spare block will be overrided by hardware
 529                          * ECC generator
 530                          */
 531                         LOG_DEBUG
 532                             ("part of spare block will be overrided by hardware ECC generator");
 533                     }
 534                 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
 535                                      oob);
 536             }
 537         /*
 538          * start data input operation (set MX3_NF_BIT_OP_DONE==0)
 539          */
 540         target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
 541         {
 542             int poll_result;
 543             poll_result = poll_for_complete_op (target, "data input");
 544             if (poll_result != ERROR_OK)
 545                 {
 546                     return poll_result;
 547                 }
 548         }
 549         retval |= imx31_command (nand, NAND_CMD_PAGEPROG);
 550         if (retval != ERROR_OK)
 551             {
 552                 return retval;
 553             }
 554
 555         /*
 556          * check status register
 557          */
 558         {
 559             uint16_t nand_status_content;
 560             retval = ERROR_OK;
 561             retval |= imx31_command(nand, NAND_CMD_STATUS);
 562             retval |= imx31_address(nand, 0x00);
 563             retval |= do_data_output(nand);
 564             if (retval != ERROR_OK)
 565                 {
 566                     LOG_ERROR (get_status_register_err_msg);
 567                     return retval;
 568                 }
 569             target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
 570             if (nand_status_content & 0x0001)
 571                 {
 572                     /*
 573                      * is host-big-endian correctly ??
 574                      */
 575                     return ERROR_NAND_OPERATION_FAILED;
 576                 }
 577         }
 578         }
 579         return ERROR_OK;
 580 }
 581
 582 static int imx31_read_page (struct nand_device *nand, uint32_t page,
 583                             uint8_t * data, uint32_t data_size, uint8_t * oob,
 584                             uint32_t oob_size)
 585 {
 586         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 587         struct target *target = mx3_nf_info->target;
 588
 589         if (data_size % 2)
 590         {
 591             LOG_ERROR (data_block_size_err_msg, data_size);
 592             return ERROR_NAND_OPERATION_FAILED;
 593         }
 594         if (oob_size % 2)
 595         {
 596             LOG_ERROR (data_block_size_err_msg, oob_size);
 597             return ERROR_NAND_OPERATION_FAILED;
 598         }
 599
 600         {
 601         /*
 602          * validate target state
 603          */
 604         int retval;
 605         retval = validate_target_state(nand);
 606         if (retval != ERROR_OK)
 607             {
 608                 return retval;
 609             }
 610         }
 611         {
 612         int retval = ERROR_OK;
 613         retval |= imx31_command(nand, NAND_CMD_READ0);
 614         retval |= imx31_address(nand, 0x00);
 615         retval |= imx31_address(nand, page & 0xff);
 616         retval |= imx31_address(nand, (page >> 8) & 0xff);
 617         if (nand->address_cycles >= 4)
 618             {
 619                 retval |= imx31_address(nand, (page >> 16) & 0xff);
 620                 if (nand->address_cycles >= 5)
 621                     {
 622                         retval |= imx31_address(nand, (page >> 24) & 0xff);
 623                         retval |= imx31_command(nand, NAND_CMD_READSTART);
 624                     }
 625             }
 626         retval |= do_data_output (nand);
 627         if (retval != ERROR_OK)
 628             {
 629                 return retval;
 630             }
 631
 632         if (data)
 633             {
 634                 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
 635                                     data);
 636             }
 637         if (oob)
 638             {
 639                 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
 640                                     oob);
 641             }
 642         }
 643         return ERROR_OK;
 644 }
 645
 646 static int test_iomux_settings (struct target * target, uint32_t address,
 647                                 uint32_t mask, const char *text)
 648 {
 649         uint32_t register_content;
 650         target_read_u32 (target, address, &register_content);
 651         if ((register_content & mask) != (0x12121212 & mask))
 652         {
 653             LOG_ERROR ("IOMUX for {%s} is bad", text);
 654             return ERROR_FAIL;
 655         }
 656         return ERROR_OK;
 657 }
 658
 659 static int initialize_nf_controller (struct nand_device *nand)
 660 {
 661         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 662         struct target *target = mx3_nf_info->target;
 663         /*
 664         * resets NAND flash controller in zero time ? I dont know.
 665         */
 666         target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
 667         {
 668         uint16_t work_mode;
 669         work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
 670         if (target->endianness == TARGET_BIG_ENDIAN)
 671             {
 672                 work_mode |= MX3_NF_BIT_BE_EN;
 673             }
 674         if (mx3_nf_info->flags.hw_ecc_enabled)
 675             {
 676                 work_mode |= MX3_NF_BIT_ECC_EN;
 677             }
 678         target_write_u16 (target, MX3_NF_CFG1, work_mode);
 679         }
 680         /*
 681         * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 682         */
 683         target_write_u16 (target, MX3_NF_BUFCFG, 2);
 684         {
 685         uint16_t temp;
 686         target_read_u16 (target, MX3_NF_FWP, &temp);
 687         if ((temp & 0x0007) == 1)
 688             {
 689                 LOG_ERROR ("NAND flash is tight-locked, reset needed");
 690                 return ERROR_FAIL;
 691             }
 692
 693         }
 694         /*
 695         * unlock NAND flash for write
 696         */
 697         target_write_u16 (target, MX3_NF_FWP, 4);
 698         target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
 699         target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
 700         /*
 701         * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
 702         */
 703         target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
 704         /*
 705         * address of SRAM buffer
 706         */
 707         in_sram_address = MX3_NF_MAIN_BUFFER0;
 708         sign_of_sequental_byte_read = 0;
 709         return ERROR_OK;
 710 }
 711
 712 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value)
 713 {
 714         static uint8_t even_byte = 0;
 715         /*
 716         * host-big_endian ??
 717         */
 718         if (sign_of_sequental_byte_read == 0)
 719         {
 720             even_byte = 0;
 721         }
 722         if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
 723         {
 724             LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
 725             *value = 0;
 726             sign_of_sequental_byte_read = 0;
 727             even_byte = 0;
 728             return ERROR_NAND_OPERATION_FAILED;
 729         }
 730         else
 731         {
 732             uint16_t temp;
 733             target_read_u16 (target, in_sram_address, &temp);
 734             if (even_byte)
 735                 {
 736                     *value = temp >> 8;
 737                     even_byte = 0;
 738                     in_sram_address += 2;
 739                 }
 740             else
 741                 {
 742                     *value = temp & 0xff;
 743                     even_byte = 1;
 744                 }
 745         }
 746         sign_of_sequental_byte_read = 1;
 747         return ERROR_OK;
 748 }
 749
 750 static int get_next_halfword_from_sram_buffer (struct target * target,
 751                                                uint16_t * value)
 752 {
 753         if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
 754         {
 755             LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
 756             *value = 0;
 757             return ERROR_NAND_OPERATION_FAILED;
 758         }
 759         else
 760         {
 761             target_read_u16 (target, in_sram_address, value);
 762             in_sram_address += 2;
 763         }
 764         return ERROR_OK;
 765 }
 766
 767 static int poll_for_complete_op (struct target * target, const char *text)
 768 {
 769         uint16_t poll_complete_status;
 770         for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
 771         {
 772             usleep (25);
 773             target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
 774             if (poll_complete_status & MX3_NF_BIT_OP_DONE)
 775                 {
 776                     break;
 777                 }
 778         }
 779         if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
 780         {
 781             LOG_ERROR ("%s sending timeout", text);
 782             return ERROR_NAND_OPERATION_FAILED;
 783         }
 784         return ERROR_OK;
 785 }
 786
 787 static int validate_target_state (struct nand_device *nand)
 788 {
 789         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 790         struct target *target = mx3_nf_info->target;
 791
 792         if (target->state != TARGET_HALTED)
 793         {
 794             LOG_ERROR (target_not_halted_err_msg);
 795             return ERROR_NAND_OPERATION_FAILED;
 796         }
 797
 798         if (mx3_nf_info->flags.target_little_endian !=
 799         (target->endianness == TARGET_LITTLE_ENDIAN))
 800         {
 801             /*
 802              * endianness changed after NAND controller probed
 803              */
 804             return ERROR_NAND_OPERATION_FAILED;
 805         }
 806         return ERROR_OK;
 807 }
 808
 809 static int do_data_output (struct nand_device *nand)
 810 {
 811         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 812         struct target *target = mx3_nf_info->target;
 813         switch (mx3_nf_info->fin)
 814         {
 815             case MX3_NF_FIN_DATAOUT:
 816                 /*
 817                  * start data output operation (set MX3_NF_BIT_OP_DONE==0)
 818                  */
 819                 target_write_u16 (target, MX3_NF_CFG2,
 820                                   MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
 821                                                            optype));
 822                 {
 823                     int poll_result;
 824                     poll_result = poll_for_complete_op (target, "data output");
 825                     if (poll_result != ERROR_OK)
 826                         {
 827                             return poll_result;
 828                         }
 829                 }
 830                 mx3_nf_info->fin = MX3_NF_FIN_NONE;
 831                 /*
 832                  * ECC stuff
 833                  */
 834                 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
 835                     && mx3_nf_info->flags.hw_ecc_enabled)
 836                     {
 837                         uint16_t ecc_status;
 838                         target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
 839                         switch (ecc_status & 0x000c)
 840                             {
 841                                 case 1 << 2:
 842                                     LOG_DEBUG
 843                                         ("main area readed with 1 (correctable) error");
 844                                     break;
 845                                 case 2 << 2:
 846                                     LOG_DEBUG
 847                                         ("main area readed with more than 1 (incorrectable) error");
 848                                     return ERROR_NAND_OPERATION_FAILED;
 849                                     break;
 850                             }
 851                         switch (ecc_status & 0x0003)
 852                             {
 853                                 case 1:
 854                                     LOG_DEBUG
 855                                         ("spare area readed with 1 (correctable) error");
 856                                     break;
 857                                 case 2:
 858                                     LOG_DEBUG
 859                                         ("main area readed with more than 1 (incorrectable) error");
 860                                     return ERROR_NAND_OPERATION_FAILED;
 861                                     break;
 862                             }
 863                     }
 864                 break;
 865             case MX3_NF_FIN_NONE:
 866                 break;
 867         }
 868         return ERROR_OK;
 869 }
 870
 871 struct nand_flash_controller imx31_nand_flash_controller = {
 872                 .name = "imx31",
 873                 .nand_device_command = &imx31_nand_device_command,
 874                 .register_commands = &imx31_register_commands,
 875                 .init = &imx31_init,
 876                 .reset = &imx31_reset,
 877                 .command = &imx31_command,
 878                 .address = &imx31_address,
 879                 .write_data = &imx31_write_data,
 880                 .read_data = &imx31_read_data,
 881                 .write_page = &imx31_write_page,
 882                 .read_page = &imx31_read_page,
 883                 .controller_ready = &imx31_controller_ready,
 884                 .nand_ready = &imx31_nand_ready,
 885         };