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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "replacements.h"
  27
  28 #include "cfi.h"
  29 #include "non_cfi.h"
  30
  31 #include "flash.h"
  32 #include "target.h"
  33 #include "log.h"
  34 #include "armv4_5.h"
  35 #include "algorithm.h"
  36 #include "binarybuffer.h"
  37 #include "types.h"
  38
  39 #include <stdlib.h>
  40 #include <string.h>
  41 #include <unistd.h>
  42
  43 static int cfi_register_commands(struct command_context_s *cmd_ctx);
  44 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  45 static int cfi_erase(struct flash_bank_s *bank, int first, int last);
  46 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
  47 static int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  48 static int cfi_probe(struct flash_bank_s *bank);
  49 static int cfi_auto_probe(struct flash_bank_s *bank);
  50 static int cfi_protect_check(struct flash_bank_s *bank);
  51 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
  52
  53 //static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54
  55 #define CFI_MAX_BUS_WIDTH       4
  56 #define CFI_MAX_CHIP_WIDTH      4
  57
  58 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  59 #define CFI_MAX_INTEL_CODESIZE 256
  60
  61 flash_driver_t cfi_flash =
  62 {
  63         .name = "cfi",
  64         .register_commands = cfi_register_commands,
  65         .flash_bank_command = cfi_flash_bank_command,
  66         .erase = cfi_erase,
  67         .protect = cfi_protect,
  68         .write = cfi_write,
  69         .probe = cfi_probe,
  70         .auto_probe = cfi_auto_probe,
  71         .erase_check = default_flash_blank_check,
  72         .protect_check = cfi_protect_check,
  73         .info = cfi_info
  74 };
  75
  76 static cfi_unlock_addresses_t cfi_unlock_addresses[] =
  77 {
  78         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  79         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  80 };
  81
  82 /* CFI fixups foward declarations */
  83 static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  84 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  85 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  86
  87 /* fixup after reading cmdset 0002 primary query table */
  88 static cfi_fixup_t cfi_0002_fixups[] = {
  89         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  90         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  91         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  92         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  93         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  94         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  95         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  96         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  97         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  98         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  99         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
 100         {0, 0, NULL, NULL}
 101 };
 102
 103 /* fixup after reading cmdset 0001 primary query table */
 104 static cfi_fixup_t cfi_0001_fixups[] = {
 105         {0, 0, NULL, NULL}
 106 };
 107
 108 static void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
 109 {
 110         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 111         cfi_fixup_t *f;
 112
 113         for (f = fixups; f->fixup; f++)
 114         {
 115                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
 116                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
 117                 {
 118                         f->fixup(bank, f->param);
 119                 }
 120         }
 121 }
 122
 123 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
 124 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
 125 {
 126         /* while the sector list isn't built, only accesses to sector 0 work */
 127         if (sector == 0)
 128                 return bank->base + offset * bank->bus_width;
 129         else
 130         {
 131                 if (!bank->sectors)
 132                 {
 133                         LOG_ERROR("BUG: sector list not yet built");
 134                         exit(-1);
 135                 }
 136                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 137         }
 138
 139 }
 140
 141 static void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
 142 {
 143         int i;
 144
 145         /* clear whole buffer, to ensure bits that exceed the bus_width
 146          * are set to zero
 147          */
 148         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 149                 cmd_buf[i] = 0;
 150
 151         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 152         {
 153                 for (i = bank->bus_width; i > 0; i--)
 154                 {
 155                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 156                 }
 157         }
 158         else
 159         {
 160                 for (i = 1; i <= bank->bus_width; i++)
 161                 {
 162                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 163                 }
 164         }
 165 }
 166
 167 /* read unsigned 8-bit value from the bank
 168  * flash banks are expected to be made of similar chips
 169  * the query result should be the same for all
 170  */
 171 static u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
 172 {
 173         target_t *target = bank->target;
 174         u8 data[CFI_MAX_BUS_WIDTH];
 175
 176         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 177
 178         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 179                 return data[0];
 180         else
 181                 return data[bank->bus_width - 1];
 182 }
 183
 184 /* read unsigned 8-bit value from the bank
 185  * in case of a bank made of multiple chips,
 186  * the individual values are ORed
 187  */
 188 static u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
 189 {
 190         target_t *target = bank->target;
 191         u8 data[CFI_MAX_BUS_WIDTH];
 192         int i;
 193
 194         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 195
 196         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 197         {
 198                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 199                         data[0] |= data[i];
 200
 201                 return data[0];
 202         }
 203         else
 204         {
 205                 u8 value = 0;
 206                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 207                         value |= data[bank->bus_width - 1 - i];
 208
 209                 return value;
 210         }
 211 }
 212
 213 static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
 214 {
 215         target_t *target = bank->target;
 216         u8 data[CFI_MAX_BUS_WIDTH * 2];
 217
 218         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 219
 220         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 221                 return data[0] | data[bank->bus_width] << 8;
 222         else
 223                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 224 }
 225
 226 static u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
 227 {
 228         target_t *target = bank->target;
 229         u8 data[CFI_MAX_BUS_WIDTH * 4];
 230
 231         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 232
 233         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 234                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 235         else
 236                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 237                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 238 }
 239
 240 static void cfi_intel_clear_status_register(flash_bank_t *bank)
 241 {
 242         target_t *target = bank->target;
 243         u8 command[8];
 244
 245         if (target->state != TARGET_HALTED)
 246         {
 247                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 248                 exit(-1);
 249         }
 250
 251         cfi_command(bank, 0x50, command);
 252         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 253 }
 254
 255 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 256 {
 257         u8 status;
 258
 259         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 260         {
 261                 LOG_DEBUG("status: 0x%x", status);
 262                 alive_sleep(1);
 263         }
 264
 265         /* mask out bit 0 (reserved) */
 266         status = status & 0xfe;
 267
 268         LOG_DEBUG("status: 0x%x", status);
 269
 270         if ((status & 0x80) != 0x80)
 271         {
 272                 LOG_ERROR("timeout while waiting for WSM to become ready");
 273         }
 274         else if (status != 0x80)
 275         {
 276                 LOG_ERROR("status register: 0x%x", status);
 277                 if (status & 0x2)
 278                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 279                 if (status & 0x4)
 280                         LOG_ERROR("Program suspended");
 281                 if (status & 0x8)
 282                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 283                 if (status & 0x10)
 284                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 285                 if (status & 0x20)
 286                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 287                 if (status & 0x40)
 288                         LOG_ERROR("Block Erase Suspended");
 289
 290                 cfi_intel_clear_status_register(bank);
 291         }
 292
 293         return status;
 294 }
 295
 296 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 297 {
 298         u8 status, oldstatus;
 299         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 300
 301         oldstatus = cfi_get_u8(bank, 0, 0x0);
 302
 303         do {
 304                 status = cfi_get_u8(bank, 0, 0x0);
 305                 if ((status ^ oldstatus) & 0x40) {
 306                         if (status & cfi_info->status_poll_mask & 0x20) {
 307                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 308                                 status = cfi_get_u8(bank, 0, 0x0);
 309                                 if ((status ^ oldstatus) & 0x40) {
 310                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 311                                         return(ERROR_FLASH_OPERATION_FAILED);
 312                                 } else {
 313                                         LOG_DEBUG("status: 0x%x", status);
 314                                         return(ERROR_OK);
 315                                 }
 316                         }
 317                 } else { /* no toggle: finished, OK */
 318                         LOG_DEBUG("status: 0x%x", status);
 319                         return(ERROR_OK);
 320                 }
 321
 322                 oldstatus = status;
 323                 alive_sleep(1);
 324         } while (timeout-- > 0);
 325
 326         LOG_ERROR("timeout, status: 0x%x", status);
 327
 328         return(ERROR_FLASH_BUSY);
 329 }
 330
 331 static int cfi_read_intel_pri_ext(flash_bank_t *bank)
 332 {
 333         int retval;
 334         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 335         cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
 336         target_t *target = bank->target;
 337         u8 command[8];
 338
 339         cfi_info->pri_ext = pri_ext;
 340
 341         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 342         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 343         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 344
 345         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 346         {
 347                 cfi_command(bank, 0xf0, command);
 348                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 349                 {
 350                         return retval;
 351                 }
 352                 cfi_command(bank, 0xff, command);
 353                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 354                 {
 355                         return retval;
 356                 }
 357                 LOG_ERROR("Could not read bank flash bank information");
 358                 return ERROR_FLASH_BANK_INVALID;
 359         }
 360
 361         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 362         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 363
 364         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 365
 366         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 367         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 368         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 369
 370         LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 371
 372         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 373         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 374
 375         LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 376                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 377                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 378
 379         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 380         if (pri_ext->num_protection_fields != 1)
 381         {
 382                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 383         }
 384
 385         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 386         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 387         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 388
 389         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 390
 391         return ERROR_OK;
 392 }
 393
 394 static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 395 {
 396         int retval;
 397         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 398         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 399         target_t *target = bank->target;
 400         u8 command[8];
 401
 402         cfi_info->pri_ext = pri_ext;
 403
 404         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 405         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 406         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 407
 408         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 409         {
 410                 cfi_command(bank, 0xf0, command);
 411                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 412                 {
 413                         return retval;
 414                 }
 415                 LOG_ERROR("Could not read spansion bank information");
 416                 return ERROR_FLASH_BANK_INVALID;
 417         }
 418
 419         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 420         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 421
 422         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 423
 424         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 425         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 426         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 427         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 428         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 429         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 430         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 431         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 432         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 433         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 434         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 435
 436         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 437               pri_ext->EraseSuspend, pri_ext->BlkProt);
 438
 439         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 440               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 441
 442         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 443
 444
 445         LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 446                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 447                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 448
 449         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 450
 451         /* default values for implementation specific workarounds */
 452         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 453         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 454         pri_ext->_reversed_geometry = 0;
 455
 456         return ERROR_OK;
 457 }
 458
 459 static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 460 {
 461         int retval;
 462         cfi_atmel_pri_ext_t atmel_pri_ext;
 463         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 464         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 465         target_t *target = bank->target;
 466         u8 command[8];
 467
 468         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 469          * but a different primary extended query table.
 470          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 471          */
 472
 473         memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
 474
 475         cfi_info->pri_ext = pri_ext;
 476
 477         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 478         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 479         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 480
 481         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 482         {
 483                 cfi_command(bank, 0xf0, command);
 484                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 485                 {
 486                         return retval;
 487                 }
 488                 LOG_ERROR("Could not read atmel bank information");
 489                 return ERROR_FLASH_BANK_INVALID;
 490         }
 491
 492         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 493         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 494         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 495
 496         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 497         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 498
 499         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 500
 501         pri_ext->major_version = atmel_pri_ext.major_version;
 502         pri_ext->minor_version = atmel_pri_ext.minor_version;
 503
 504         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 505         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 506         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 507         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 508
 509         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 510                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 511
 512         if (atmel_pri_ext.features & 0x02)
 513                 pri_ext->EraseSuspend = 2;
 514
 515         if (atmel_pri_ext.bottom_boot)
 516                 pri_ext->TopBottom = 2;
 517         else
 518                 pri_ext->TopBottom = 3;
 519
 520         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 521         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 522
 523         return ERROR_OK;
 524 }
 525
 526 static int cfi_read_0002_pri_ext(flash_bank_t *bank)
 527 {
 528         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 529
 530         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 531         {
 532                 return cfi_read_atmel_pri_ext(bank);
 533         }
 534         else
 535         {
 536                 return cfi_read_spansion_pri_ext(bank);
 537         }
 538 }
 539
 540 static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 541 {
 542         int printed;
 543         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 544         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 545
 546         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 547         buf += printed;
 548         buf_size -= printed;
 549
 550         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 551                            pri_ext->pri[1], pri_ext->pri[2],
 552                            pri_ext->major_version, pri_ext->minor_version);
 553         buf += printed;
 554         buf_size -= printed;
 555
 556         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 557                            (pri_ext->SiliconRevision) >> 2,
 558                            (pri_ext->SiliconRevision) & 0x03);
 559         buf += printed;
 560         buf_size -= printed;
 561
 562         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 563                            pri_ext->EraseSuspend,
 564                            pri_ext->BlkProt);
 565         buf += printed;
 566         buf_size -= printed;
 567
 568         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 569                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 570                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 571
 572         return ERROR_OK;
 573 }
 574
 575 static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 576 {
 577         int printed;
 578         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 579         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 580
 581         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 582         buf += printed;
 583         buf_size -= printed;
 584
 585         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 586         buf += printed;
 587         buf_size -= printed;
 588
 589         printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 590         buf += printed;
 591         buf_size -= printed;
 592
 593         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 594                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 595                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 596         buf += printed;
 597         buf_size -= printed;
 598
 599         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 600
 601         return ERROR_OK;
 602 }
 603
 604 static int cfi_register_commands(struct command_context_s *cmd_ctx)
 605 {
 606         /*command_t *cfi_cmd = */
 607         register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
 608         /*
 609         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 610                                          "print part id of cfi flash bank <num>");
 611         */
 612         return ERROR_OK;
 613 }
 614
 615 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 616  */
 617 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 618 {
 619         cfi_flash_bank_t *cfi_info;
 620         int i;
 621         (void) cmd_ctx;
 622         (void) cmd;
 623
 624         if (argc < 6)
 625         {
 626                 LOG_WARNING("incomplete flash_bank cfi configuration");
 627                 return ERROR_FLASH_BANK_INVALID;
 628         }
 629
 630         if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
 631                 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
 632         {
 633                 LOG_ERROR("chip and bus width have to specified in bytes");
 634                 return ERROR_FLASH_BANK_INVALID;
 635         }
 636
 637         cfi_info = malloc(sizeof(cfi_flash_bank_t));
 638         cfi_info->probed = 0;
 639         bank->driver_priv = cfi_info;
 640
 641         cfi_info->write_algorithm = NULL;
 642
 643         cfi_info->x16_as_x8 = 0;
 644         cfi_info->jedec_probe = 0;
 645         cfi_info->not_cfi = 0;
 646
 647         for (i = 6; i < argc; i++)
 648         {
 649                 if (strcmp(args[i], "x16_as_x8") == 0)
 650                 {
 651                         cfi_info->x16_as_x8 = 1;
 652                 }
 653                 else if (strcmp(args[i], "jedec_probe") == 0)
 654                 {
 655                         cfi_info->jedec_probe = 1;
 656                 }
 657         }
 658
 659         cfi_info->write_algorithm = NULL;
 660
 661         /* bank wasn't probed yet */
 662         cfi_info->qry[0] = -1;
 663
 664         return ERROR_OK;
 665 }
 666
 667 static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 668 {
 669         int retval;
 670         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 671         target_t *target = bank->target;
 672         u8 command[8];
 673         int i;
 674
 675         cfi_intel_clear_status_register(bank);
 676
 677         for (i = first; i <= last; i++)
 678         {
 679                 cfi_command(bank, 0x20, command);
 680                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 681                 {
 682                         return retval;
 683                 }
 684
 685                 cfi_command(bank, 0xd0, command);
 686                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 687                 {
 688                         return retval;
 689                 }
 690
 691                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 692                         bank->sectors[i].is_erased = 1;
 693                 else
 694                 {
 695                         cfi_command(bank, 0xff, command);
 696                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 697                         {
 698                                 return retval;
 699                         }
 700
 701                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 702                         return ERROR_FLASH_OPERATION_FAILED;
 703                 }
 704         }
 705
 706         cfi_command(bank, 0xff, command);
 707         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 708
 709 }
 710
 711 static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 712 {
 713         int retval;
 714         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 715         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 716         target_t *target = bank->target;
 717         u8 command[8];
 718         int i;
 719
 720         for (i = first; i <= last; i++)
 721         {
 722                 cfi_command(bank, 0xaa, command);
 723                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 724                 {
 725                         return retval;
 726                 }
 727
 728                 cfi_command(bank, 0x55, command);
 729                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 730                 {
 731                         return retval;
 732                 }
 733
 734                 cfi_command(bank, 0x80, command);
 735                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 736                 {
 737                         return retval;
 738                 }
 739
 740                 cfi_command(bank, 0xaa, command);
 741                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 742                 {
 743                         return retval;
 744                 }
 745
 746                 cfi_command(bank, 0x55, command);
 747                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 748                 {
 749                         return retval;
 750                 }
 751
 752                 cfi_command(bank, 0x30, command);
 753                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 754                 {
 755                         return retval;
 756                 }
 757
 758                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 759                         bank->sectors[i].is_erased = 1;
 760                 else
 761                 {
 762                         cfi_command(bank, 0xf0, command);
 763                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 764                         {
 765                                 return retval;
 766                         }
 767
 768                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 769                         return ERROR_FLASH_OPERATION_FAILED;
 770                 }
 771         }
 772
 773         cfi_command(bank, 0xf0, command);
 774         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 775 }
 776
 777 static int cfi_erase(struct flash_bank_s *bank, int first, int last)
 778 {
 779         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 780
 781         if (bank->target->state != TARGET_HALTED)
 782         {
 783                 LOG_ERROR("Target not halted");
 784                 return ERROR_TARGET_NOT_HALTED;
 785         }
 786
 787         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 788         {
 789                 return ERROR_FLASH_SECTOR_INVALID;
 790         }
 791
 792         if (cfi_info->qry[0] != 'Q')
 793                 return ERROR_FLASH_BANK_NOT_PROBED;
 794
 795         switch(cfi_info->pri_id)
 796         {
 797                 case 1:
 798                 case 3:
 799                         return cfi_intel_erase(bank, first, last);
 800                         break;
 801                 case 2:
 802                         return cfi_spansion_erase(bank, first, last);
 803                         break;
 804                 default:
 805                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 806                         break;
 807         }
 808
 809         return ERROR_OK;
 810 }
 811
 812 static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 813 {
 814         int retval;
 815         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 816         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 817         target_t *target = bank->target;
 818         u8 command[8];
 819         int retry = 0;
 820         int i;
 821
 822         /* if the device supports neither legacy lock/unlock (bit 3) nor
 823          * instant individual block locking (bit 5).
 824          */
 825         if (!(pri_ext->feature_support & 0x28))
 826                 return ERROR_FLASH_OPERATION_FAILED;
 827
 828         cfi_intel_clear_status_register(bank);
 829
 830         for (i = first; i <= last; i++)
 831         {
 832                 cfi_command(bank, 0x60, command);
 833                 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 834                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 835                 {
 836                         return retval;
 837                 }
 838                 if (set)
 839                 {
 840                         cfi_command(bank, 0x01, command);
 841                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 842                         if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 843                         {
 844                                 return retval;
 845                         }
 846                         bank->sectors[i].is_protected = 1;
 847                 }
 848                 else
 849                 {
 850                         cfi_command(bank, 0xd0, command);
 851                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 852                         if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 853                         {
 854                                 return retval;
 855                         }
 856                         bank->sectors[i].is_protected = 0;
 857                 }
 858
 859                 /* instant individual block locking doesn't require reading of the status register */
 860                 if (!(pri_ext->feature_support & 0x20))
 861                 {
 862                         /* Clear lock bits operation may take up to 1.4s */
 863                         cfi_intel_wait_status_busy(bank, 1400);
 864                 }
 865                 else
 866                 {
 867                         u8 block_status;
 868                         /* read block lock bit, to verify status */
 869                         cfi_command(bank, 0x90, command);
 870                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 871                         {
 872                                 return retval;
 873                         }
 874                         block_status = cfi_get_u8(bank, i, 0x2);
 875
 876                         if ((block_status & 0x1) != set)
 877                         {
 878                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 879                                 cfi_command(bank, 0x70, command);
 880                                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 881                                 {
 882                                         return retval;
 883                                 }
 884                                 cfi_intel_wait_status_busy(bank, 10);
 885
 886                                 if (retry > 10)
 887                                         return ERROR_FLASH_OPERATION_FAILED;
 888                                 else
 889                                 {
 890                                         i--;
 891                                         retry++;
 892                                 }
 893                         }
 894                 }
 895         }
 896
 897         /* if the device doesn't support individual block lock bits set/clear,
 898          * all blocks have been unlocked in parallel, so we set those that should be protected
 899          */
 900         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 901         {
 902                 for (i = 0; i < bank->num_sectors; i++)
 903                 {
 904                         if (bank->sectors[i].is_protected == 1)
 905                         {
 906                                 cfi_intel_clear_status_register(bank);
 907
 908                                 cfi_command(bank, 0x60, command);
 909                                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 910                                 {
 911                                         return retval;
 912                                 }
 913
 914                                 cfi_command(bank, 0x01, command);
 915                                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 916                                 {
 917                                         return retval;
 918                                 }
 919
 920                                 cfi_intel_wait_status_busy(bank, 100);
 921                         }
 922                 }
 923         }
 924
 925         cfi_command(bank, 0xff, command);
 926         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 927 }
 928
 929 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 930 {
 931         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 932
 933         if (bank->target->state != TARGET_HALTED)
 934         {
 935                 LOG_ERROR("Target not halted");
 936                 return ERROR_TARGET_NOT_HALTED;
 937         }
 938
 939         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 940         {
 941                 return ERROR_FLASH_SECTOR_INVALID;
 942         }
 943
 944         if (cfi_info->qry[0] != 'Q')
 945                 return ERROR_FLASH_BANK_NOT_PROBED;
 946
 947         switch(cfi_info->pri_id)
 948         {
 949                 case 1:
 950                 case 3:
 951                         cfi_intel_protect(bank, set, first, last);
 952                         break;
 953                 default:
 954                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
 955                         break;
 956         }
 957
 958         return ERROR_OK;
 959 }
 960
 961 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 962 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
 963 {
 964         /* target_t *target = bank->target; */
 965
 966         int i;
 967
 968         /* NOTE:
 969          * The data to flash must not be changed in endian! We write a bytestrem in
 970          * target byte order already. Only the control and status byte lane of the flash
 971          * WSM is interpreted by the CPU in different ways, when read a u16 or u32
 972          * word (data seems to be in the upper or lower byte lane for u16 accesses).
 973          */
 974
 975 #if 0
 976         if (target->endianness == TARGET_LITTLE_ENDIAN)
 977         {
 978 #endif
 979                 /* shift bytes */
 980                 for (i = 0; i < bank->bus_width - 1; i++)
 981                         word[i] = word[i + 1];
 982                 word[bank->bus_width - 1] = byte;
 983 #if 0
 984         }
 985         else
 986         {
 987                 /* shift bytes */
 988                 for (i = bank->bus_width - 1; i > 0; i--)
 989                         word[i] = word[i - 1];
 990                 word[0] = byte;
 991         }
 992 #endif
 993 }
 994
 995 /* Convert code image to target endian */
 996 /* FIXME create general block conversion fcts in target.c?) */
 997 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
 998 {
 999         u32 i;
1000         for (i=0; i< count; i++)
1001         {
1002                 target_buffer_set_u32(target, dest, *src);
1003                 dest+=4;
1004                 src++;
1005         }
1006 }
1007
1008 static u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
1009 {
1010         target_t *target = bank->target;
1011
1012         u8 buf[CFI_MAX_BUS_WIDTH];
1013         cfi_command(bank, cmd, buf);
1014         switch (bank->bus_width)
1015         {
1016         case 1 :
1017                 return buf[0];
1018                 break;
1019         case 2 :
1020                 return target_buffer_get_u16(target, buf);
1021                 break;
1022         case 4 :
1023                 return target_buffer_get_u32(target, buf);
1024                 break;
1025         default :
1026                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1027                 return 0;
1028         }
1029 }
1030
1031 static int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1032 {
1033         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1034         target_t *target = bank->target;
1035         reg_param_t reg_params[7];
1036         armv4_5_algorithm_t armv4_5_info;
1037         working_area_t *source;
1038         u32 buffer_size = 32768;
1039         u32 write_command_val, busy_pattern_val, error_pattern_val;
1040
1041         /* algorithm register usage:
1042          * r0: source address (in RAM)
1043          * r1: target address (in Flash)
1044          * r2: count
1045          * r3: flash write command
1046          * r4: status byte (returned to host)
1047          * r5: busy test pattern
1048          * r6: error test pattern
1049          */
1050
1051         static const u32 word_32_code[] = {
1052                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1053                 0xe5813000,   /*                str r3, [r1] */
1054                 0xe5814000,   /*                str r4, [r1] */
1055                 0xe5914000,   /* busy:  ldr r4, [r1] */
1056                 0xe0047005,   /*                and r7, r4, r5 */
1057                 0xe1570005,   /*                cmp r7, r5 */
1058                 0x1afffffb,   /*                bne busy */
1059                 0xe1140006,   /*                tst r4, r6 */
1060                 0x1a000003,   /*                bne done */
1061                 0xe2522001,   /*                subs r2, r2, #1 */
1062                 0x0a000001,   /*                beq done */
1063                 0xe2811004,   /*                add r1, r1 #4 */
1064                 0xeafffff2,   /*                b loop */
1065                 0xeafffffe    /* done:  b -2 */
1066         };
1067
1068         static const u32 word_16_code[] = {
1069                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1070                 0xe1c130b0,   /*                strh r3, [r1] */
1071                 0xe1c140b0,   /*                strh r4, [r1] */
1072                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1073                 0xe0047005,   /*                and r7, r4, r5 */
1074                 0xe1570005,   /*                cmp r7, r5 */
1075                 0x1afffffb,   /*                bne busy */
1076                 0xe1140006,   /*                tst r4, r6 */
1077                 0x1a000003,   /*                bne done */
1078                 0xe2522001,   /*                subs r2, r2, #1 */
1079                 0x0a000001,   /*                beq done */
1080                 0xe2811002,   /*                add r1, r1 #2 */
1081                 0xeafffff2,   /*                b loop */
1082                 0xeafffffe    /* done:  b -2 */
1083         };
1084
1085         static const u32 word_8_code[] = {
1086                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1087                 0xe5c13000,   /*                strb r3, [r1] */
1088                 0xe5c14000,   /*                strb r4, [r1] */
1089                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1090                 0xe0047005,   /*                and r7, r4, r5 */
1091                 0xe1570005,   /*                cmp r7, r5 */
1092                 0x1afffffb,   /*                bne busy */
1093                 0xe1140006,   /*                tst r4, r6 */
1094                 0x1a000003,   /*                bne done */
1095                 0xe2522001,   /*                subs r2, r2, #1 */
1096                 0x0a000001,   /*                beq done */
1097                 0xe2811001,   /*                add r1, r1 #1 */
1098                 0xeafffff2,   /*                b loop */
1099                 0xeafffffe    /* done:  b -2 */
1100         };
1101         u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1102         const u32 *target_code_src;
1103         u32 target_code_size;
1104         int retval = ERROR_OK;
1105
1106
1107         cfi_intel_clear_status_register(bank);
1108
1109         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1110         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1111         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1112
1113         /* If we are setting up the write_algorith, we need target_code_src */
1114         /* if not we only need target_code_size.                                                                                                                */
1115         /*                                                                                                                                                                                                                                                                      */
1116         /* However, we don't want to create multiple code paths, so we                  */
1117         /* do the unecessary evaluation of target_code_src, which the                   */
1118         /* compiler will probably nicely optimize away if not needed                            */
1119
1120         /* prepare algorithm code for target endian */
1121         switch (bank->bus_width)
1122         {
1123         case 1 :
1124                 target_code_src = word_8_code;
1125                 target_code_size = sizeof(word_8_code);
1126                 break;
1127         case 2 :
1128                 target_code_src = word_16_code;
1129                 target_code_size = sizeof(word_16_code);
1130                 break;
1131         case 4 :
1132                 target_code_src = word_32_code;
1133                 target_code_size = sizeof(word_32_code);
1134                 break;
1135         default:
1136                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1137                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1138         }
1139
1140         /* flash write code */
1141         if (!cfi_info->write_algorithm)
1142         {
1143                 if ( target_code_size > sizeof(target_code) )
1144                 {
1145                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1146                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1147                 }
1148                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1149
1150                 /* Get memory for block write handler */
1151                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1152                 if (retval != ERROR_OK)
1153                 {
1154                         LOG_WARNING("No working area available, can't do block memory writes");
1155                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1156                 };
1157
1158                 /* write algorithm code to working area */
1159                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1160                 if (retval != ERROR_OK)
1161                 {
1162                         LOG_ERROR("Unable to write block write code to target");
1163                         goto cleanup;
1164                 }
1165         }
1166
1167         /* Get a workspace buffer for the data to flash starting with 32k size.
1168            Half size until buffer would be smaller 256 Bytem then fail back */
1169         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1170         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1171         {
1172                 buffer_size /= 2;
1173                 if (buffer_size <= 256)
1174                 {
1175                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1176                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1177                         goto cleanup;
1178                 }
1179         };
1180
1181         /* setup algo registers */
1182         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1183         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1184         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1185         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1186         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1187         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1188         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1189
1190         /* prepare command and status register patterns */
1191         write_command_val = cfi_command_val(bank, 0x40);
1192         busy_pattern_val  = cfi_command_val(bank, 0x80);
1193         error_pattern_val = cfi_command_val(bank, 0x7e);
1194
1195         LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1196
1197         /* Programming main loop */
1198         while (count > 0)
1199         {
1200                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1201                 u32 wsm_error;
1202
1203                 if((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1204                 {
1205                         goto cleanup;
1206                 }
1207
1208                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1209                 buf_set_u32(reg_params[1].value, 0, 32, address);
1210                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1211
1212                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1213                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1214                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1215
1216                 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1217
1218                 /* Execute algorithm, assume breakpoint for last instruction */
1219                 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1220                         cfi_info->write_algorithm->address,
1221                         cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1222                         10000, /* 10s should be enough for max. 32k of data */
1223                         &armv4_5_info);
1224
1225                 /* On failure try a fall back to direct word writes */
1226                 if (retval != ERROR_OK)
1227                 {
1228                         cfi_intel_clear_status_register(bank);
1229                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1230                         retval = ERROR_FLASH_OPERATION_FAILED;
1231                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1232                         /* FIXME To allow fall back or recovery, we must save the actual status
1233                            somewhere, so that a higher level code can start recovery. */
1234                         goto cleanup;
1235                 }
1236
1237                 /* Check return value from algo code */
1238                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1239                 if (wsm_error)
1240                 {
1241                         /* read status register (outputs debug inforation) */
1242                         cfi_intel_wait_status_busy(bank, 100);
1243                         cfi_intel_clear_status_register(bank);
1244                         retval = ERROR_FLASH_OPERATION_FAILED;
1245                         goto cleanup;
1246                 }
1247
1248                 buffer += thisrun_count;
1249                 address += thisrun_count;
1250                 count -= thisrun_count;
1251         }
1252
1253         /* free up resources */
1254 cleanup:
1255         if (source)
1256                 target_free_working_area(target, source);
1257
1258         if (cfi_info->write_algorithm)
1259         {
1260                 target_free_working_area(target, cfi_info->write_algorithm);
1261                 cfi_info->write_algorithm = NULL;
1262         }
1263
1264         destroy_reg_param(&reg_params[0]);
1265         destroy_reg_param(&reg_params[1]);
1266         destroy_reg_param(&reg_params[2]);
1267         destroy_reg_param(&reg_params[3]);
1268         destroy_reg_param(&reg_params[4]);
1269         destroy_reg_param(&reg_params[5]);
1270         destroy_reg_param(&reg_params[6]);
1271
1272         return retval;
1273 }
1274
1275 static int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1276 {
1277         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1278         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1279         target_t *target = bank->target;
1280         reg_param_t reg_params[10];
1281         armv4_5_algorithm_t armv4_5_info;
1282         working_area_t *source;
1283         u32 buffer_size = 32768;
1284         u32 status;
1285         int retval, retvaltemp;
1286         int exit_code = ERROR_OK;
1287
1288         /* input parameters - */
1289         /*      R0 = source address */
1290         /*      R1 = destination address */
1291         /*      R2 = number of writes */
1292         /*      R3 = flash write command */
1293         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1294         /* output parameters - */
1295         /*      R5 = 0x80 ok 0x00 bad */
1296         /* temp registers - */
1297         /*      R6 = value read from flash to test status */
1298         /*      R7 = holding register */
1299         /* unlock registers - */
1300         /*  R8 = unlock1_addr */
1301         /*  R9 = unlock1_cmd */
1302         /*  R10 = unlock2_addr */
1303         /*  R11 = unlock2_cmd */
1304
1305         static const u32 word_32_code[] = {
1306                                                 /* 00008100 <sp_32_code>:               */
1307                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1308                 0xe5889000,     /* str  r9, [r8]                                */
1309                 0xe58ab000,     /* str  r11, [r10]                              */
1310                 0xe5883000,     /* str  r3, [r8]                                */
1311                 0xe5815000,     /* str  r5, [r1]                                */
1312                 0xe1a00000,     /* nop                                                  */
1313                                                 /*                                                              */
1314                                                 /* 00008110 <sp_32_busy>:               */
1315                 0xe5916000,     /* ldr  r6, [r1]                                */
1316                 0xe0257006,     /* eor  r7, r5, r6                              */
1317                 0xe0147007,     /* ands r7, r4, r7                              */
1318                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1319                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1320                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1321                 0xe5916000,     /* ldr  r6, [r1]                                */
1322                 0xe0257006,     /* eor  r7, r5, r6                              */
1323                 0xe0147007,     /* ands r7, r4, r7                              */
1324                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1325                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1326                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1327                                                 /*                                                              */
1328                                 /* 00008140 <sp_32_cont>:                               */
1329                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1330                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1331                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1332                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1333                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1334                                                 /*                                                              */
1335                                                 /* 00008154 <sp_32_done>:               */
1336                 0xeafffffe              /* b    8154 <sp_32_done>               */
1337                 };
1338
1339                 static const u32 word_16_code[] = {
1340                                 /* 00008158 <sp_16_code>:              */
1341                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1342                 0xe1c890b0,     /* strh r9, [r8]                                */
1343                 0xe1cab0b0,     /* strh r11, [r10]                              */
1344                 0xe1c830b0,     /* strh r3, [r8]                                */
1345                 0xe1c150b0,     /* strh r5, [r1]                       */
1346                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1347                                 /*                                     */
1348                                 /* 00008168 <sp_16_busy>:              */
1349                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1350                 0xe0257006,     /* eor  r7, r5, r6                     */
1351                 0xe0147007,     /* ands r7, r4, r7                     */
1352                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1353                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1354                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1355                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1356                 0xe0257006,     /* eor  r7, r5, r6                     */
1357                 0xe0147007,     /* ands r7, r4, r7                     */
1358                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1359                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1360                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1361                                 /*                                     */
1362                                 /* 00008198 <sp_16_cont>:              */
1363                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1364                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1365                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1366                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1367                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1368                                 /*                                     */
1369                                 /* 000081ac <sp_16_done>:              */
1370                 0xeafffffe      /* b    81ac <sp_16_done>              */
1371                 };
1372
1373                 static const u32 word_8_code[] = {
1374                                 /* 000081b0 <sp_16_code_end>:          */
1375                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1376                 0xe5c89000,     /* strb r9, [r8]                                */
1377                 0xe5cab000,     /* strb r11, [r10]                              */
1378                 0xe5c83000,     /* strb r3, [r8]                                */
1379                 0xe5c15000,     /* strb r5, [r1]                       */
1380                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1381                                 /*                                     */
1382                                 /* 000081c0 <sp_8_busy>:               */
1383                 0xe5d16000,     /* ldrb r6, [r1]                       */
1384                 0xe0257006,     /* eor  r7, r5, r6                     */
1385                 0xe0147007,     /* ands r7, r4, r7                     */
1386                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1387                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1388                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1389                 0xe5d16000,     /* ldrb r6, [r1]                       */
1390                 0xe0257006,     /* eor  r7, r5, r6                     */
1391                 0xe0147007,     /* ands r7, r4, r7                     */
1392                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1393                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1394                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1395                                 /*                                     */
1396                                 /* 000081f0 <sp_8_cont>:               */
1397                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1398                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1399                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1400                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1401                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1402                                 /*                                     */
1403                                 /* 00008204 <sp_8_done>:               */
1404                 0xeafffffe      /* b    8204 <sp_8_done>               */
1405         };
1406
1407         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1408         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1409         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1410
1411         /* flash write code */
1412         if (!cfi_info->write_algorithm)
1413         {
1414                 u8 *target_code;
1415                 int target_code_size;
1416                 const u32 *src;
1417
1418                 /* convert bus-width dependent algorithm code to correct endiannes */
1419                 switch (bank->bus_width)
1420                 {
1421                 case 1:
1422                         src = word_8_code;
1423                         target_code_size = sizeof(word_8_code);
1424                         break;
1425                 case 2:
1426                         src = word_16_code;
1427                         target_code_size = sizeof(word_16_code);
1428                         break;
1429                 case 4:
1430                         src = word_32_code;
1431                         target_code_size = sizeof(word_32_code);
1432                         break;
1433                 default:
1434                         LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1435                         return ERROR_FLASH_OPERATION_FAILED;
1436                 }
1437                 target_code = malloc(target_code_size);
1438                 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1439
1440                 /* allocate working area */
1441                 retval=target_alloc_working_area(target, target_code_size,
1442                                 &cfi_info->write_algorithm);
1443                 if (retval != ERROR_OK)
1444                 {
1445                         free(target_code);
1446                         return retval;
1447                 }
1448
1449                 /* write algorithm code to working area */
1450                 if((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1451                                     target_code_size, target_code)) != ERROR_OK)
1452                 {
1453                         free(target_code);
1454                         return retval;
1455                 }
1456
1457                 free(target_code);
1458         }
1459         /* the following code still assumes target code is fixed 24*4 bytes */
1460
1461         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1462         {
1463                 buffer_size /= 2;
1464                 if (buffer_size <= 256)
1465                 {
1466                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1467                         if (cfi_info->write_algorithm)
1468                                 target_free_working_area(target, cfi_info->write_algorithm);
1469
1470                         LOG_WARNING("not enough working area available, can't do block memory writes");
1471                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1472                 }
1473         };
1474
1475         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1476         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1477         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1478         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1479         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1480         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1481         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1482         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1483         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1484         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1485
1486         while (count > 0)
1487         {
1488                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1489
1490                 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1491
1492                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1493                 buf_set_u32(reg_params[1].value, 0, 32, address);
1494                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1495                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1496                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1497                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1498                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1499                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1500                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1501
1502                 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1503                                                      cfi_info->write_algorithm->address,
1504                                                      cfi_info->write_algorithm->address + ((24 * 4) - 4),
1505                                                      10000, &armv4_5_info);
1506
1507                 status = buf_get_u32(reg_params[5].value, 0, 32);
1508
1509                 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1510                 {
1511                         LOG_DEBUG("status: 0x%x", status);
1512                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1513                         break;
1514                 }
1515
1516                 buffer += thisrun_count;
1517                 address += thisrun_count;
1518                 count -= thisrun_count;
1519         }
1520
1521         target_free_working_area(target, source);
1522
1523         destroy_reg_param(&reg_params[0]);
1524         destroy_reg_param(&reg_params[1]);
1525         destroy_reg_param(&reg_params[2]);
1526         destroy_reg_param(&reg_params[3]);
1527         destroy_reg_param(&reg_params[4]);
1528         destroy_reg_param(&reg_params[5]);
1529         destroy_reg_param(&reg_params[6]);
1530         destroy_reg_param(&reg_params[7]);
1531         destroy_reg_param(&reg_params[8]);
1532         destroy_reg_param(&reg_params[9]);
1533
1534         return exit_code;
1535 }
1536
1537 static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1538 {
1539         int retval;
1540         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1541         target_t *target = bank->target;
1542         u8 command[8];
1543
1544         cfi_intel_clear_status_register(bank);
1545         cfi_command(bank, 0x40, command);
1546         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1547         {
1548                 return retval;
1549         }
1550
1551         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1552         {
1553                 return retval;
1554         }
1555
1556         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1557         {
1558                 cfi_command(bank, 0xff, command);
1559                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1560                 {
1561                         return retval;
1562                 }
1563
1564                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1565                 return ERROR_FLASH_OPERATION_FAILED;
1566         }
1567
1568         return ERROR_OK;
1569 }
1570
1571 static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1572 {
1573         int retval;
1574         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1575         target_t *target = bank->target;
1576         u8 command[8];
1577
1578         /* Calculate buffer size and boundary mask */
1579         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1580         u32 buffermask = buffersize-1;
1581         u32 bufferwsize;
1582
1583         /* Check for valid range */
1584         if (address & buffermask)
1585         {
1586                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1587                 return ERROR_FLASH_OPERATION_FAILED;
1588         }
1589         switch(bank->chip_width)
1590         {
1591         case 4 : bufferwsize = buffersize / 4; break;
1592         case 2 : bufferwsize = buffersize / 2; break;
1593         case 1 : bufferwsize = buffersize; break;
1594         default:
1595                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1596                 return ERROR_FLASH_OPERATION_FAILED;
1597         }
1598
1599         bufferwsize/=(bank->bus_width / bank->chip_width);
1600
1601
1602         /* Check for valid size */
1603         if (wordcount > bufferwsize)
1604         {
1605                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1606                 return ERROR_FLASH_OPERATION_FAILED;
1607         }
1608
1609         /* Write to flash buffer */
1610         cfi_intel_clear_status_register(bank);
1611
1612         /* Initiate buffer operation _*/
1613         cfi_command(bank, 0xE8, command);
1614         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1615         {
1616                 return retval;
1617         }
1618         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1619         {
1620                 cfi_command(bank, 0xff, command);
1621                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1622                 {
1623                         return retval;
1624                 }
1625
1626                 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1627                 return ERROR_FLASH_OPERATION_FAILED;
1628         }
1629
1630         /* Write buffer wordcount-1 and data words */
1631         cfi_command(bank, bufferwsize-1, command);
1632         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1633         {
1634                 return retval;
1635         }
1636
1637         if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1638         {
1639                 return retval;
1640         }
1641
1642         /* Commit write operation */
1643         cfi_command(bank, 0xd0, command);
1644         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1645         {
1646                 return retval;
1647         }
1648         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1649         {
1650                 cfi_command(bank, 0xff, command);
1651                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1652                 {
1653                         return retval;
1654                 }
1655
1656                 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1657                 return ERROR_FLASH_OPERATION_FAILED;
1658         }
1659
1660         return ERROR_OK;
1661 }
1662
1663 static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1664 {
1665         int retval;
1666         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1667         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1668         target_t *target = bank->target;
1669         u8 command[8];
1670
1671         cfi_command(bank, 0xaa, command);
1672         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1673         {
1674                 return retval;
1675         }
1676
1677         cfi_command(bank, 0x55, command);
1678         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1679         {
1680                 return retval;
1681         }
1682
1683         cfi_command(bank, 0xa0, command);
1684         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1685         {
1686                 return retval;
1687         }
1688
1689         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1690         {
1691                 return retval;
1692         }
1693
1694         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1695         {
1696                 cfi_command(bank, 0xf0, command);
1697                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1698                 {
1699                         return retval;
1700                 }
1701
1702                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1703                 return ERROR_FLASH_OPERATION_FAILED;
1704         }
1705
1706         return ERROR_OK;
1707 }
1708
1709 static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1710 {
1711         int retval;
1712         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1713         target_t *target = bank->target;
1714         u8 command[8];
1715         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1716
1717         /* Calculate buffer size and boundary mask */
1718         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1719         u32 buffermask = buffersize-1;
1720         u32 bufferwsize;
1721
1722         /* Check for valid range */
1723         if (address & buffermask)
1724         {
1725                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1726                 return ERROR_FLASH_OPERATION_FAILED;
1727         }
1728         switch(bank->chip_width)
1729         {
1730         case 4 : bufferwsize = buffersize / 4; break;
1731         case 2 : bufferwsize = buffersize / 2; break;
1732         case 1 : bufferwsize = buffersize; break;
1733         default:
1734                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1735                 return ERROR_FLASH_OPERATION_FAILED;
1736         }
1737
1738         bufferwsize/=(bank->bus_width / bank->chip_width);
1739
1740         /* Check for valid size */
1741         if (wordcount > bufferwsize)
1742         {
1743                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1744                 return ERROR_FLASH_OPERATION_FAILED;
1745         }
1746
1747         // Unlock
1748         cfi_command(bank, 0xaa, command);
1749         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1750         {
1751                 return retval;
1752         }
1753
1754         cfi_command(bank, 0x55, command);
1755         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1756         {
1757                 return retval;
1758         }
1759
1760         // Buffer load command
1761         cfi_command(bank, 0x25, command);
1762         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1763         {
1764                 return retval;
1765         }
1766
1767         /* Write buffer wordcount-1 and data words */
1768         cfi_command(bank, bufferwsize-1, command);
1769         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1770         {
1771                 return retval;
1772         }
1773
1774         if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1775         {
1776                 return retval;
1777         }
1778
1779         /* Commit write operation */
1780         cfi_command(bank, 0x29, command);
1781         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1782         {
1783                 return retval;
1784         }
1785
1786         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1787         {
1788                 cfi_command(bank, 0xf0, command);
1789                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1790                 {
1791                         return retval;
1792                 }
1793
1794                 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
1795                 return ERROR_FLASH_OPERATION_FAILED;
1796         }
1797
1798         return ERROR_OK;
1799 }
1800
1801 static int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1802 {
1803         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1804
1805         switch(cfi_info->pri_id)
1806         {
1807                 case 1:
1808                 case 3:
1809                         return cfi_intel_write_word(bank, word, address);
1810                         break;
1811                 case 2:
1812                         return cfi_spansion_write_word(bank, word, address);
1813                         break;
1814                 default:
1815                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1816                         break;
1817         }
1818
1819         return ERROR_FLASH_OPERATION_FAILED;
1820 }
1821
1822 static int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1823 {
1824         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1825
1826         switch(cfi_info->pri_id)
1827         {
1828                 case 1:
1829                 case 3:
1830                         return cfi_intel_write_words(bank, word, wordcount, address);
1831                         break;
1832                 case 2:
1833                         return cfi_spansion_write_words(bank, word, wordcount, address);
1834                         break;
1835                 default:
1836                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1837                         break;
1838         }
1839
1840         return ERROR_FLASH_OPERATION_FAILED;
1841 }
1842
1843 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1844 {
1845         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1846         target_t *target = bank->target;
1847         u32 address = bank->base + offset;      /* address of first byte to be programmed */
1848         u32 write_p, copy_p;
1849         int align;      /* number of unaligned bytes */
1850         int blk_count; /* number of bus_width bytes for block copy */
1851         u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1852         int i;
1853         int retval;
1854
1855         if (bank->target->state != TARGET_HALTED)
1856         {
1857                 LOG_ERROR("Target not halted");
1858                 return ERROR_TARGET_NOT_HALTED;
1859         }
1860
1861         if (offset + count > bank->size)
1862                 return ERROR_FLASH_DST_OUT_OF_BANK;
1863
1864         if (cfi_info->qry[0] != 'Q')
1865                 return ERROR_FLASH_BANK_NOT_PROBED;
1866
1867         /* start at the first byte of the first word (bus_width size) */
1868         write_p = address & ~(bank->bus_width - 1);
1869         if ((align = address - write_p) != 0)
1870         {
1871                 LOG_INFO("Fixup %d unaligned head bytes", align );
1872
1873                 for (i = 0; i < bank->bus_width; i++)
1874                         current_word[i] = 0;
1875                 copy_p = write_p;
1876
1877                 /* copy bytes before the first write address */
1878                 for (i = 0; i < align; ++i, ++copy_p)
1879                 {
1880                         u8 byte;
1881                         if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1882                         {
1883                                 return retval;
1884                         }
1885                         cfi_add_byte(bank, current_word, byte);
1886                 }
1887
1888                 /* add bytes from the buffer */
1889                 for (; (i < bank->bus_width) && (count > 0); i++)
1890                 {
1891                         cfi_add_byte(bank, current_word, *buffer++);
1892                         count--;
1893                         copy_p++;
1894                 }
1895
1896                 /* if the buffer is already finished, copy bytes after the last write address */
1897                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1898                 {
1899                         u8 byte;
1900                         if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1901                         {
1902                                 return retval;
1903                         }
1904                         cfi_add_byte(bank, current_word, byte);
1905                 }
1906
1907                 retval = cfi_write_word(bank, current_word, write_p);
1908                 if (retval != ERROR_OK)
1909                         return retval;
1910                 write_p = copy_p;
1911         }
1912
1913         /* handle blocks of bus_size aligned bytes */
1914         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1915         switch(cfi_info->pri_id)
1916         {
1917                 /* try block writes (fails without working area) */
1918                 case 1:
1919                 case 3:
1920                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1921                         break;
1922                 case 2:
1923                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1924                         break;
1925                 default:
1926                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1927                         retval = ERROR_FLASH_OPERATION_FAILED;
1928                         break;
1929         }
1930         if (retval == ERROR_OK)
1931         {
1932                 /* Increment pointers and decrease count on succesful block write */
1933                 buffer += blk_count;
1934                 write_p += blk_count;
1935                 count -= blk_count;
1936         }
1937         else
1938         {
1939                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1940                 {
1941                         //adjust buffersize for chip width
1942                         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1943                         u32 buffermask = buffersize-1;
1944                         u32 bufferwsize;
1945
1946                         switch(bank->chip_width)
1947                         {
1948                         case 4 : bufferwsize = buffersize / 4; break;
1949                         case 2 : bufferwsize = buffersize / 2; break;
1950                         case 1 : bufferwsize = buffersize; break;
1951                         default:
1952                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1953                                 return ERROR_FLASH_OPERATION_FAILED;
1954                         }
1955
1956                         bufferwsize/=(bank->bus_width / bank->chip_width);
1957
1958                         /* fall back to memory writes */
1959                         while (count >= (u32)bank->bus_width)
1960                         {
1961                                 int fallback;
1962                                 if ((write_p & 0xff) == 0)
1963                                 {
1964                                         LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1965                                 }
1966                                 fallback = 1;
1967                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1968                                 {
1969                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1970                                         if (retval == ERROR_OK)
1971                                         {
1972                                                 buffer += buffersize;
1973                                                 write_p += buffersize;
1974                                                 count -= buffersize;
1975                                                 fallback=0;
1976                                         }
1977                                 }
1978                                 /* try the slow way? */
1979                                 if (fallback)
1980                                 {
1981                                         for (i = 0; i < bank->bus_width; i++)
1982                                                 current_word[i] = 0;
1983
1984                                         for (i = 0; i < bank->bus_width; i++)
1985                                         {
1986                                                 cfi_add_byte(bank, current_word, *buffer++);
1987                                         }
1988
1989                                         retval = cfi_write_word(bank, current_word, write_p);
1990                                         if (retval != ERROR_OK)
1991                                                 return retval;
1992
1993                                         write_p += bank->bus_width;
1994                                         count -= bank->bus_width;
1995                                 }
1996                         }
1997                 }
1998                 else
1999                         return retval;
2000         }
2001
2002         /* return to read array mode, so we can read from flash again for padding */
2003         cfi_command(bank, 0xf0, current_word);
2004         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2005         {
2006                 return retval;
2007         }
2008         cfi_command(bank, 0xff, current_word);
2009         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2010         {
2011                 return retval;
2012         }
2013
2014         /* handle unaligned tail bytes */
2015         if (count > 0)
2016         {
2017                 LOG_INFO("Fixup %d unaligned tail bytes", count );
2018
2019                 copy_p = write_p;
2020                 for (i = 0; i < bank->bus_width; i++)
2021                         current_word[i] = 0;
2022
2023                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2024                 {
2025                         cfi_add_byte(bank, current_word, *buffer++);
2026                         count--;
2027                 }
2028                 for (; i < bank->bus_width; ++i, ++copy_p)
2029                 {
2030                         u8 byte;
2031                         if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2032                         {
2033                                 return retval;
2034                         }
2035                         cfi_add_byte(bank, current_word, byte);
2036                 }
2037                 retval = cfi_write_word(bank, current_word, write_p);
2038                 if (retval != ERROR_OK)
2039                         return retval;
2040         }
2041
2042         /* return to read array mode */
2043         cfi_command(bank, 0xf0, current_word);
2044         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2045         {
2046                 return retval;
2047         }
2048         cfi_command(bank, 0xff, current_word);
2049         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2050 }
2051
2052 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2053 {
2054         (void) param;
2055         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2056         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2057
2058         pri_ext->_reversed_geometry = 1;
2059 }
2060
2061 static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2062 {
2063         int i;
2064         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2065         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2066         (void) param;
2067
2068         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2069         {
2070                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2071
2072                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2073                 {
2074                         int j = (cfi_info->num_erase_regions - 1) - i;
2075                         u32 swap;
2076
2077                         swap = cfi_info->erase_region_info[i];
2078                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2079                         cfi_info->erase_region_info[j] = swap;
2080                 }
2081         }
2082 }
2083
2084 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2085 {
2086         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2087         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2088         cfi_unlock_addresses_t *unlock_addresses = param;
2089
2090         pri_ext->_unlock1 = unlock_addresses->unlock1;
2091         pri_ext->_unlock2 = unlock_addresses->unlock2;
2092 }
2093
2094 static int cfi_probe(struct flash_bank_s *bank)
2095 {
2096         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2097         target_t *target = bank->target;
2098         u8 command[8];
2099         int num_sectors = 0;
2100         int i;
2101         int sector = 0;
2102         u32 unlock1 = 0x555;
2103         u32 unlock2 = 0x2aa;
2104         int retval;
2105
2106         if (bank->target->state != TARGET_HALTED)
2107         {
2108                 LOG_ERROR("Target not halted");
2109                 return ERROR_TARGET_NOT_HALTED;
2110         }
2111
2112         cfi_info->probed = 0;
2113
2114         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2115          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2116          */
2117         if (cfi_info->jedec_probe)
2118         {
2119                 unlock1 = 0x5555;
2120                 unlock2 = 0x2aaa;
2121         }
2122
2123         /* switch to read identifier codes mode ("AUTOSELECT") */
2124         cfi_command(bank, 0xaa, command);
2125         if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2126         {
2127                 return retval;
2128         }
2129         cfi_command(bank, 0x55, command);
2130         if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2131         {
2132                 return retval;
2133         }
2134         cfi_command(bank, 0x90, command);
2135         if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2136         {
2137                 return retval;
2138         }
2139
2140         if (bank->chip_width == 1)
2141         {
2142                 u8 manufacturer, device_id;
2143                 if((retval = target_read_u8(target, bank->base + 0x0, &manufacturer)) != ERROR_OK)
2144                 {
2145                         return retval;
2146                 }
2147                 if((retval = target_read_u8(target, bank->base + 0x1, &device_id)) != ERROR_OK)
2148                 {
2149                         return retval;
2150                 }
2151                 cfi_info->manufacturer = manufacturer;
2152                 cfi_info->device_id = device_id;
2153         }
2154         else if (bank->chip_width == 2)
2155         {
2156                 if((retval = target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer)) != ERROR_OK)
2157                 {
2158                         return retval;
2159                 }
2160                 if((retval = target_read_u16(target, bank->base + 0x2, &cfi_info->device_id)) != ERROR_OK)
2161                 {
2162                         return retval;
2163                 }
2164         }
2165
2166         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2167         /* switch back to read array mode */
2168         cfi_command(bank, 0xf0, command);
2169         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2170         {
2171                 return retval;
2172         }
2173         cfi_command(bank, 0xff, command);
2174         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2175         {
2176                 return retval;
2177         }
2178
2179         /* check device/manufacturer ID for known non-CFI flashes. */
2180         cfi_fixup_non_cfi(bank);
2181
2182         /* query only if this is a CFI compatible flash,
2183          * otherwise the relevant info has already been filled in
2184          */
2185         if (cfi_info->not_cfi == 0)
2186         {
2187                 /* enter CFI query mode
2188                  * according to JEDEC Standard No. 68.01,
2189                  * a single bus sequence with address = 0x55, data = 0x98 should put
2190                  * the device into CFI query mode.
2191                  *
2192                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2193                  */
2194                 cfi_command(bank, 0x98, command);
2195                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2196                 {
2197                         return retval;
2198                 }
2199
2200                 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2201                 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2202                 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2203
2204                 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2205
2206                 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2207                 {
2208                         cfi_command(bank, 0xf0, command);
2209                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2210                         {
2211                                 return retval;
2212                         }
2213                         cfi_command(bank, 0xff, command);
2214                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2215                         {
2216                                 return retval;
2217                         }
2218                         LOG_ERROR("Could not probe bank: no QRY");
2219                         return ERROR_FLASH_BANK_INVALID;
2220                 }
2221
2222                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2223                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2224                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2225                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2226
2227                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2228
2229                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2230                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2231                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2232                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2233                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2234                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2235                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2236                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2237                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2238                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2239                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2240                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2241
2242                 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2243                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2244                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2245                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2246                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2247                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2248                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2249                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2250                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2251                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2252                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2253
2254                 cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
2255                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2256                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2257                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2258
2259                 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2260
2261                 if (cfi_info->num_erase_regions)
2262                 {
2263                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2264                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2265                         {
2266                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2267                                 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2268                         }
2269                 }
2270                 else
2271                 {
2272                         cfi_info->erase_region_info = NULL;
2273                 }
2274
2275                 /* We need to read the primary algorithm extended query table before calculating
2276                  * the sector layout to be able to apply fixups
2277                  */
2278                 switch(cfi_info->pri_id)
2279                 {
2280                         /* Intel command set (standard and extended) */
2281                         case 0x0001:
2282                         case 0x0003:
2283                                 cfi_read_intel_pri_ext(bank);
2284                                 break;
2285                         /* AMD/Spansion, Atmel, ... command set */
2286                         case 0x0002:
2287                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2288                                 cfi_read_0002_pri_ext(bank);
2289                                 break;
2290                         default:
2291                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2292                                 break;
2293                 }
2294
2295                 /* return to read array mode
2296                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2297                  */
2298                 cfi_command(bank, 0xf0, command);
2299                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2300                 {
2301                         return retval;
2302                 }
2303                 cfi_command(bank, 0xff, command);
2304                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2305                 {
2306                         return retval;
2307                 }
2308         } /* end CFI case */
2309
2310         /* apply fixups depending on the primary command set */
2311         switch(cfi_info->pri_id)
2312         {
2313                 /* Intel command set (standard and extended) */
2314                 case 0x0001:
2315                 case 0x0003:
2316                         cfi_fixup(bank, cfi_0001_fixups);
2317                         break;
2318                 /* AMD/Spansion, Atmel, ... command set */
2319                 case 0x0002:
2320                         cfi_fixup(bank, cfi_0002_fixups);
2321                         break;
2322                 default:
2323                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2324                         break;
2325         }
2326
2327         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2328         {
2329                 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, cfi_info->dev_size);
2330         }
2331
2332         if (cfi_info->num_erase_regions == 0)
2333         {
2334                 /* a device might have only one erase block, spanning the whole device */
2335                 bank->num_sectors = 1;
2336                 bank->sectors = malloc(sizeof(flash_sector_t));
2337
2338                 bank->sectors[sector].offset = 0x0;
2339                 bank->sectors[sector].size = bank->size;
2340                 bank->sectors[sector].is_erased = -1;
2341                 bank->sectors[sector].is_protected = -1;
2342         }
2343         else
2344         {
2345                 u32 offset = 0;
2346
2347                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2348                 {
2349                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2350                 }
2351
2352                 bank->num_sectors = num_sectors;
2353                 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2354
2355                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2356                 {
2357                         u32 j;
2358                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2359                         {
2360                                 bank->sectors[sector].offset = offset;
2361                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2362                                 offset += bank->sectors[sector].size;
2363                                 bank->sectors[sector].is_erased = -1;
2364                                 bank->sectors[sector].is_protected = -1;
2365                                 sector++;
2366                         }
2367                 }
2368                 if (offset != cfi_info->dev_size)
2369                 {
2370                         LOG_WARNING("CFI size is 0x%x, but total sector size is 0x%x", cfi_info->dev_size, offset);
2371                 }
2372         }
2373
2374         cfi_info->probed = 1;
2375
2376         return ERROR_OK;
2377 }
2378
2379 static int cfi_auto_probe(struct flash_bank_s *bank)
2380 {
2381         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2382         if (cfi_info->probed)
2383                 return ERROR_OK;
2384         return cfi_probe(bank);
2385 }
2386
2387
2388 static int cfi_intel_protect_check(struct flash_bank_s *bank)
2389 {
2390         int retval;
2391         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2392         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2393         target_t *target = bank->target;
2394         u8 command[CFI_MAX_BUS_WIDTH];
2395         int i;
2396
2397         /* check if block lock bits are supported on this device */
2398         if (!(pri_ext->blk_status_reg_mask & 0x1))
2399                 return ERROR_FLASH_OPERATION_FAILED;
2400
2401         cfi_command(bank, 0x90, command);
2402         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2403         {
2404                 return retval;
2405         }
2406
2407         for (i = 0; i < bank->num_sectors; i++)
2408         {
2409                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2410
2411                 if (block_status & 1)
2412                         bank->sectors[i].is_protected = 1;
2413                 else
2414                         bank->sectors[i].is_protected = 0;
2415         }
2416
2417         cfi_command(bank, 0xff, command);
2418         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2419 }
2420
2421 static int cfi_spansion_protect_check(struct flash_bank_s *bank)
2422 {
2423         int retval;
2424         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2425         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2426         target_t *target = bank->target;
2427         u8 command[8];
2428         int i;
2429
2430         cfi_command(bank, 0xaa, command);
2431         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2432         {
2433                 return retval;
2434         }
2435
2436         cfi_command(bank, 0x55, command);
2437         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2438         {
2439                 return retval;
2440         }
2441
2442         cfi_command(bank, 0x90, command);
2443         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2444         {
2445                 return retval;
2446         }
2447
2448         for (i = 0; i < bank->num_sectors; i++)
2449         {
2450                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2451
2452                 if (block_status & 1)
2453                         bank->sectors[i].is_protected = 1;
2454                 else
2455                         bank->sectors[i].is_protected = 0;
2456         }
2457
2458         cfi_command(bank, 0xf0, command);
2459         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2460 }
2461
2462 static int cfi_protect_check(struct flash_bank_s *bank)
2463 {
2464         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2465
2466         if (bank->target->state != TARGET_HALTED)
2467         {
2468                 LOG_ERROR("Target not halted");
2469                 return ERROR_TARGET_NOT_HALTED;
2470         }
2471
2472         if (cfi_info->qry[0] != 'Q')
2473                 return ERROR_FLASH_BANK_NOT_PROBED;
2474
2475         switch(cfi_info->pri_id)
2476         {
2477                 case 1:
2478                 case 3:
2479                         return cfi_intel_protect_check(bank);
2480                         break;
2481                 case 2:
2482                         return cfi_spansion_protect_check(bank);
2483                         break;
2484                 default:
2485                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2486                         break;
2487         }
2488
2489         return ERROR_OK;
2490 }
2491
2492 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2493 {
2494         int printed;
2495         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2496
2497         if (cfi_info->qry[0] == (char)-1)
2498         {
2499                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2500                 return ERROR_OK;
2501         }
2502
2503         if (cfi_info->not_cfi == 0)
2504                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2505         else
2506                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2507         buf += printed;
2508         buf_size -= printed;
2509
2510         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2511                 cfi_info->manufacturer, cfi_info->device_id);
2512         buf += printed;
2513         buf_size -= printed;
2514
2515         if (cfi_info->not_cfi == 0)
2516         {
2517         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2518         buf += printed;
2519         buf_size -= printed;
2520
2521                 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2522                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2523         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2524         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2525         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2526         buf += printed;
2527         buf_size -= printed;
2528
2529                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2530                                    1 << cfi_info->word_write_timeout_typ,
2531                                    1 << cfi_info->buf_write_timeout_typ,
2532                                    1 << cfi_info->block_erase_timeout_typ,
2533                                    1 << cfi_info->chip_erase_timeout_typ);
2534         buf += printed;
2535         buf_size -= printed;
2536
2537                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2538                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2539                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2540                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2541                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2542         buf += printed;
2543         buf_size -= printed;
2544
2545                 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2546                                    cfi_info->dev_size,
2547                                    cfi_info->interface_desc,
2548                                    1 << cfi_info->max_buf_write_size);
2549         buf += printed;
2550         buf_size -= printed;
2551
2552         switch(cfi_info->pri_id)
2553         {
2554                 case 1:
2555                 case 3:
2556                         cfi_intel_info(bank, buf, buf_size);
2557                         break;
2558                 case 2:
2559                         cfi_spansion_info(bank, buf, buf_size);
2560                         break;
2561                 default:
2562                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2563                         break;
2564         }
2565         }
2566
2567         return ERROR_OK;
2568 }