1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
34 copy of the license is included in the section entitled ``GNU Free
35 Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
101 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board connect directly to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD supports only
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
153 USB-based, parallel port-based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
158 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
159 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
161 @b{Flash Programming:} Flash writing is supported for external
162 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
164 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
165 controllers (LPC3180, Orion, S3C24xx, more) is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.org/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
179 @uref{http://openocd.org/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.org/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195 @section OpenOCD User's Mailing List
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
204 Support can also be found on irc:
205 @uref{irc://irc.libera.chat/openocd}
208 @chapter OpenOCD Developer Resources
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
219 @section OpenOCD Git Repository
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a Git repository hosted at SourceForge. The repository URL is:
224 @uref{git://git.code.sf.net/p/openocd/code}
228 @uref{http://git.code.sf.net/p/openocd/code}
230 You may prefer to use a mirror and the HTTP protocol:
232 @uref{http://repo.or.cz/r/openocd.git}
234 With standard Git tools, use @command{git clone} to initialize
235 a local repository, and @command{git pull} to update it.
236 There are also gitweb pages letting you browse the repository
237 with a web browser, or download arbitrary snapshots without
238 needing a Git client:
240 @uref{http://repo.or.cz/w/openocd.git}
242 The @file{README} file contains the instructions for building the project
243 from the repository or a snapshot.
245 Developers that want to contribute patches to the OpenOCD system are
246 @b{strongly} encouraged to work against mainline.
247 Patches created against older versions may require additional
248 work from their submitter in order to be updated for newer releases.
250 @section Doxygen Developer Manual
252 During the 0.2.x release cycle, the OpenOCD project began
253 providing a Doxygen reference manual. This document contains more
254 technical information about the software internals, development
255 processes, and similar documentation:
257 @uref{http://openocd.org/doc/doxygen/html/index.html}
259 This document is a work-in-progress, but contributions would be welcome
260 to fill in the gaps. All of the source files are provided in-tree,
261 listed in the Doxyfile configuration at the top of the source tree.
263 @section Gerrit Review System
265 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 @uref{https://review.openocd.org/}
270 After a one-time registration and repository setup, anyone can push commits
271 from their local Git repository directly into Gerrit.
272 All users and developers are encouraged to review, test, discuss and vote
273 for changes in Gerrit. The feedback provides the basis for a maintainer to
274 eventually submit the change to the main Git repository.
276 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
277 Developer Manual, contains basic information about how to connect a
278 repository to Gerrit, prepare and push patches. Patch authors are expected to
279 maintain their changes while they're in Gerrit, respond to feedback and if
280 necessary rework and push improved versions of the change.
282 @section OpenOCD Developer Mailing List
284 The OpenOCD Developer Mailing List provides the primary means of
285 communication between developers:
287 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
289 @section OpenOCD Bug Tracker
291 The OpenOCD Bug Tracker is hosted on SourceForge:
293 @uref{http://bugs.openocd.org/}
296 @node Debug Adapter Hardware
297 @chapter Debug Adapter Hardware
305 Defined: @b{dongle}: A small device that plugs into a computer and serves as
306 an adapter .... [snip]
308 In the OpenOCD case, this generally refers to @b{a small adapter} that
309 attaches to your computer via USB or the parallel port.
312 @section Choosing a Dongle
314 There are several things you should keep in mind when choosing a dongle.
317 @item @b{Transport} Does it support the kind of communication that you need?
318 OpenOCD focuses mostly on JTAG. Your version may also support
319 other ways to communicate with target devices.
320 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
321 Does your dongle support it? You might need a level converter.
322 @item @b{Pinout} What pinout does your target board use?
323 Does your dongle support it? You may be able to use jumper
324 wires, or an "octopus" connector, to convert pinouts.
325 @item @b{Connection} Does your computer have the USB, parallel, or
326 Ethernet port needed?
327 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
328 RTCK support (also known as ``adaptive clocking'')?
331 @section USB FT2232 Based
333 There are many USB JTAG dongles on the market, many of them based
334 on a chip from ``Future Technology Devices International'' (FTDI)
335 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
336 See: @url{http://www.ftdichip.com} for more information.
337 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
338 chips started to become available in JTAG adapters. Around 2012, a new
339 variant appeared - FT232H - this is a single-channel version of FT2232H.
340 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
343 The FT2232 chips are flexible enough to support some other
344 transport options, such as SWD or the SPI variants used to
345 program some chips. They have two communications channels,
346 and one can be used for a UART adapter at the same time the
347 other one is used to provide a debug adapter.
349 Also, some development boards integrate an FT2232 chip to serve as
350 a built-in low-cost debug adapter and USB-to-serial solution.
354 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
356 @* See: @url{http://www.amontec.com/jtagkey.shtml}
358 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
360 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
362 @* See: @url{http://www.signalyzer.com}
363 @item @b{Stellaris Eval Boards}
364 @* See: @url{http://www.ti.com} - The Stellaris eval boards
365 bundle FT2232-based JTAG and SWD support, which can be used to debug
366 the Stellaris chips. Using separate JTAG adapters is optional.
367 These boards can also be used in a "pass through" mode as JTAG adapters
368 to other target boards, disabling the Stellaris chip.
369 @item @b{TI/Luminary ICDI}
370 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
371 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
372 Evaluation Kits. Like the non-detachable FT2232 support on the other
373 Stellaris eval boards, they can be used to debug other target boards.
374 @item @b{olimex-jtag}
375 @* See: @url{http://www.olimex.com}
376 @item @b{Flyswatter/Flyswatter2}
377 @* See: @url{http://www.tincantools.com}
378 @item @b{turtelizer2}
380 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
381 @url{http://www.ethernut.de}
383 @* Link: @url{http://www.hitex.com/index.php?id=383}
385 @* Link @url{http://www.hitex.com/stm32-stick}
386 @item @b{axm0432_jtag}
387 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
388 to be available anymore as of April 2012.
390 @* Link @url{http://www.hitex.com/index.php?id=cortino}
391 @item @b{dlp-usb1232h}
392 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
393 @item @b{digilent-hs1}
394 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
396 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
398 @item @b{JTAG-lock-pick Tiny 2}
399 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
402 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
406 @section USB-JTAG / Altera USB-Blaster compatibles
408 These devices also show up as FTDI devices, but are not
409 protocol-compatible with the FT2232 devices. They are, however,
410 protocol-compatible among themselves. USB-JTAG devices typically consist
411 of a FT245 followed by a CPLD that understands a particular protocol,
412 or emulates this protocol using some other hardware.
414 They may appear under different USB VID/PID depending on the particular
415 product. The driver can be configured to search for any VID/PID pair
416 (see the section on driver commands).
419 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
420 @* Link: @url{http://ixo-jtag.sourceforge.net/}
421 @item @b{Altera USB-Blaster}
422 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
425 @section USB J-Link based
426 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
427 an example of a microcontroller based JTAG adapter, it uses an
428 AT91SAM764 internally.
431 @item @b{SEGGER J-Link}
432 @* Link: @url{http://www.segger.com/jlink.html}
433 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
434 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
438 @section USB RLINK based
439 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
440 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
441 SWD and not JTAG, thus not supported.
444 @item @b{Raisonance RLink}
445 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
446 @item @b{STM32 Primer}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
448 @item @b{STM32 Primer2}
449 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
452 @section USB ST-LINK based
453 STMicroelectronics has an adapter called @b{ST-LINK}.
454 They only work with STMicroelectronics chips, notably STM32 and STM8.
458 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
459 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
461 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
462 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
464 @* This is available standalone and as part of some kits.
465 @* Link: @url{http://www.st.com/stlink-v3}
468 For info the original ST-LINK enumerates using the mass storage usb class; however,
469 its implementation is completely broken. The result is this causes issues under Linux.
470 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
472 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
473 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
476 @section USB TI/Stellaris ICDI based
477 Texas Instruments has an adapter called @b{ICDI}.
478 It is not to be confused with the FTDI based adapters that were originally fitted to their
479 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
481 @section USB Nuvoton Nu-Link
482 Nuvoton has an adapter called @b{Nu-Link}.
483 It is available either as stand-alone dongle and embedded on development boards.
484 It supports SWD, serial port bridge and mass storage for firmware update.
485 Both Nu-Link v1 and v2 are supported.
487 @section USB CMSIS-DAP based
488 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
489 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
494 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
496 @item @b{USB - Presto}
497 @* Link: @url{http://tools.asix.net/prg_presto.htm}
499 @item @b{Versaloon-Link}
500 @* Link: @url{http://www.versaloon.com}
502 @item @b{ARM-JTAG-EW}
503 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
506 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
509 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
512 @* Link: @url{http://code.google.com/p/estick-jtag/}
514 @item @b{Keil ULINK v1}
515 @* Link: @url{http://www.keil.com/ulink1/}
517 @item @b{TI XDS110 Debug Probe}
518 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
519 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
522 @section IBM PC Parallel Printer Port Based
524 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
525 and the Macraigor Wiggler. There are many clones and variations of
528 Note that parallel ports are becoming much less common, so if you
529 have the choice you should probably avoid these adapters in favor
534 @item @b{Wiggler} - There are many clones of this.
535 @* Link: @url{http://www.macraigor.com/wiggler.htm}
537 @item @b{DLC5} - From XILINX - There are many clones of this
538 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
539 produced, PDF schematics are easily found and it is easy to make.
541 @item @b{Amontec - JTAG Accelerator}
542 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
545 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
547 @item @b{Wiggler_ntrst_inverted}
548 @* Yet another variation - See the source code, src/jtag/parport.c
550 @item @b{old_amt_wiggler}
551 @* Unknown - probably not on the market today
554 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
557 @* Link: @url{http://www.amontec.com/chameleon.shtml}
563 @* ispDownload from Lattice Semiconductor
564 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
567 @* From STMicroelectronics;
568 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
576 @* An EP93xx based Linux machine using the GPIO pins directly.
579 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
581 @item @b{bcm2835gpio}
582 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
585 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
588 @* A JTAG driver acting as a client for the JTAG VPI server interface.
589 @* Link: @url{http://github.com/fjullien/jtag_vpi}
592 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
593 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
594 interface of a hardware model written in SystemVerilog, for example, on an
595 emulation model of target hardware.
597 @item @b{xlnx_pcie_xvc}
598 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
601 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
604 @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
605 This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
610 @chapter About Jim-Tcl
614 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
615 This programming language provides a simple and extensible
618 All commands presented in this Guide are extensions to Jim-Tcl.
619 You can use them as simple commands, without needing to learn
620 much of anything about Tcl.
621 Alternatively, you can write Tcl programs with them.
623 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
624 There is an active and responsive community, get on the mailing list
625 if you have any questions. Jim-Tcl maintainers also lurk on the
626 OpenOCD mailing list.
629 @item @b{Jim vs. Tcl}
630 @* Jim-Tcl is a stripped down version of the well known Tcl language,
631 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
632 fewer features. Jim-Tcl is several dozens of .C files and .H files and
633 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
634 4.2 MB .zip file containing 1540 files.
636 @item @b{Missing Features}
637 @* Our practice has been: Add/clone the real Tcl feature if/when
638 needed. We welcome Jim-Tcl improvements, not bloat. Also there
639 are a large number of optional Jim-Tcl features that are not
643 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
644 command interpreter today is a mixture of (newer)
645 Jim-Tcl commands, and the (older) original command interpreter.
648 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
649 can type a Tcl for() loop, set variables, etc.
650 Some of the commands documented in this guide are implemented
651 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
653 @item @b{Historical Note}
654 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
655 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
656 as a Git submodule, which greatly simplified upgrading Jim-Tcl
657 to benefit from new features and bugfixes in Jim-Tcl.
659 @item @b{Need a crash course in Tcl?}
660 @*@xref{Tcl Crash Course}.
665 @cindex command line options
667 @cindex directory search
669 Properly installing OpenOCD sets up your operating system to grant it access
670 to the debug adapters. On Linux, this usually involves installing a file
671 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
672 that works for many common adapters is shipped with OpenOCD in the
673 @file{contrib} directory. MS-Windows needs
674 complex and confusing driver configuration for every peripheral. Such issues
675 are unique to each operating system, and are not detailed in this User's Guide.
677 Then later you will invoke the OpenOCD server, with various options to
678 tell it how each debug session should work.
679 The @option{--help} option shows:
683 --help | -h display this help
684 --version | -v display OpenOCD version
685 --file | -f use configuration file <name>
686 --search | -s dir to search for config files and scripts
687 --debug | -d set debug level to 3
688 | -d<n> set debug level to <level>
689 --log_output | -l redirect log output to file <name>
690 --command | -c run <command>
693 If you don't give any @option{-f} or @option{-c} options,
694 OpenOCD tries to read the configuration file @file{openocd.cfg}.
695 To specify one or more different
696 configuration files, use @option{-f} options. For example:
699 openocd -f config1.cfg -f config2.cfg -f config3.cfg
702 Configuration files and scripts are searched for in
704 @item the current directory,
705 @item any search dir specified on the command line using the @option{-s} option,
706 @item any search dir specified using the @command{add_script_search_dir} command,
707 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
708 @item @file{%APPDATA%/OpenOCD} (only on Windows),
709 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
710 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
711 @item @file{$HOME/.openocd},
712 @item the site wide script library @file{$pkgdatadir/site} and
713 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
715 The first found file with a matching file name will be used.
718 Don't try to use configuration script names or paths which
719 include the "#" character. That character begins Tcl comments.
722 @section Simple setup, no customization
724 In the best case, you can use two scripts from one of the script
725 libraries, hook up your JTAG adapter, and start the server ... and
726 your JTAG setup will just work "out of the box". Always try to
727 start by reusing those scripts, but assume you'll need more
728 customization even if this works. @xref{OpenOCD Project Setup}.
730 If you find a script for your JTAG adapter, and for your board or
731 target, you may be able to hook up your JTAG adapter then start
732 the server with some variation of one of the following:
735 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
736 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
739 You might also need to configure which reset signals are present,
740 using @option{-c 'reset_config trst_and_srst'} or something similar.
741 If all goes well you'll see output something like
744 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
745 For bug reports, read
746 http://openocd.org/doc/doxygen/bugs.html
747 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
748 (mfg: 0x23b, part: 0xba00, ver: 0x3)
751 Seeing that "tap/device found" message, and no warnings, means
752 the JTAG communication is working. That's a key milestone, but
753 you'll probably need more project-specific setup.
755 @section What OpenOCD does as it starts
757 OpenOCD starts by processing the configuration commands provided
758 on the command line or, if there were no @option{-c command} or
759 @option{-f file.cfg} options given, in @file{openocd.cfg}.
760 @xref{configurationstage,,Configuration Stage}.
761 At the end of the configuration stage it verifies the JTAG scan
762 chain defined using those commands; your configuration should
763 ensure that this always succeeds.
764 Normally, OpenOCD then starts running as a server.
765 Alternatively, commands may be used to terminate the configuration
766 stage early, perform work (such as updating some flash memory),
767 and then shut down without acting as a server.
769 Once OpenOCD starts running as a server, it waits for connections from
770 clients (Telnet, GDB, RPC) and processes the commands issued through
773 If you are having problems, you can enable internal debug messages via
774 the @option{-d} option.
776 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
777 @option{-c} command line switch.
779 To enable debug output (when reporting problems or working on OpenOCD
780 itself), use the @option{-d} command line switch. This sets the
781 @option{debug_level} to "3", outputting the most information,
782 including debug messages. The default setting is "2", outputting only
783 informational messages, warnings and errors. You can also change this
784 setting from within a telnet or gdb session using @command{debug_level<n>}
785 (@pxref{debuglevel,,debug_level}).
787 You can redirect all output from the server to a file using the
788 @option{-l <logfile>} switch.
790 Note! OpenOCD will launch the GDB & telnet server even if it can not
791 establish a connection with the target. In general, it is possible for
792 the JTAG controller to be unresponsive until the target is set up
793 correctly via e.g. GDB monitor commands in a GDB init script.
795 @node OpenOCD Project Setup
796 @chapter OpenOCD Project Setup
798 To use OpenOCD with your development projects, you need to do more than
799 just connect the JTAG adapter hardware (dongle) to your development board
800 and start the OpenOCD server.
801 You also need to configure your OpenOCD server so that it knows
802 about your adapter and board, and helps your work.
803 You may also want to connect OpenOCD to GDB, possibly
804 using Eclipse or some other GUI.
806 @section Hooking up the JTAG Adapter
808 Today's most common case is a dongle with a JTAG cable on one side
809 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
810 and a USB cable on the other.
811 Instead of USB, some dongles use Ethernet;
812 older ones may use a PC parallel port, or even a serial port.
815 @item @emph{Start with power to your target board turned off},
816 and nothing connected to your JTAG adapter.
817 If you're particularly paranoid, unplug power to the board.
818 It's important to have the ground signal properly set up,
819 unless you are using a JTAG adapter which provides
820 galvanic isolation between the target board and the
823 @item @emph{Be sure it's the right kind of JTAG connector.}
824 If your dongle has a 20-pin ARM connector, you need some kind
825 of adapter (or octopus, see below) to hook it up to
826 boards using 14-pin or 10-pin connectors ... or to 20-pin
827 connectors which don't use ARM's pinout.
829 In the same vein, make sure the voltage levels are compatible.
830 Not all JTAG adapters have the level shifters needed to work
831 with 1.2 Volt boards.
833 @item @emph{Be certain the cable is properly oriented} or you might
834 damage your board. In most cases there are only two possible
835 ways to connect the cable.
836 Connect the JTAG cable from your adapter to the board.
837 Be sure it's firmly connected.
839 In the best case, the connector is keyed to physically
840 prevent you from inserting it wrong.
841 This is most often done using a slot on the board's male connector
842 housing, which must match a key on the JTAG cable's female connector.
843 If there's no housing, then you must look carefully and
844 make sure pin 1 on the cable hooks up to pin 1 on the board.
845 Ribbon cables are frequently all grey except for a wire on one
846 edge, which is red. The red wire is pin 1.
848 Sometimes dongles provide cables where one end is an ``octopus'' of
849 color coded single-wire connectors, instead of a connector block.
850 These are great when converting from one JTAG pinout to another,
851 but are tedious to set up.
852 Use these with connector pinout diagrams to help you match up the
853 adapter signals to the right board pins.
855 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
856 A USB, parallel, or serial port connector will go to the host which
857 you are using to run OpenOCD.
858 For Ethernet, consult the documentation and your network administrator.
860 For USB-based JTAG adapters you have an easy sanity check at this point:
861 does the host operating system see the JTAG adapter? If you're running
862 Linux, try the @command{lsusb} command. If that host is an
863 MS-Windows host, you'll need to install a driver before OpenOCD works.
865 @item @emph{Connect the adapter's power supply, if needed.}
866 This step is primarily for non-USB adapters,
867 but sometimes USB adapters need extra power.
869 @item @emph{Power up the target board.}
870 Unless you just let the magic smoke escape,
871 you're now ready to set up the OpenOCD server
872 so you can use JTAG to work with that board.
876 Talk with the OpenOCD server using
877 telnet (@code{telnet localhost 4444} on many systems) or GDB.
878 @xref{GDB and OpenOCD}.
880 @section Project Directory
882 There are many ways you can configure OpenOCD and start it up.
884 A simple way to organize them all involves keeping a
885 single directory for your work with a given board.
886 When you start OpenOCD from that directory,
887 it searches there first for configuration files, scripts,
888 files accessed through semihosting,
889 and for code you upload to the target board.
890 It is also the natural place to write files,
891 such as log files and data you download from the board.
893 @section Configuration Basics
895 There are two basic ways of configuring OpenOCD, and
896 a variety of ways you can mix them.
897 Think of the difference as just being how you start the server:
900 @item Many @option{-f file} or @option{-c command} options on the command line
901 @item No options, but a @dfn{user config file}
902 in the current directory named @file{openocd.cfg}
905 Here is an example @file{openocd.cfg} file for a setup
906 using a Signalyzer FT2232-based JTAG adapter to talk to
907 a board with an Atmel AT91SAM7X256 microcontroller:
910 source [find interface/ftdi/signalyzer.cfg]
912 # GDB can also flash my flash!
913 gdb_memory_map enable
914 gdb_flash_program enable
916 source [find target/sam7x256.cfg]
919 Here is the command line equivalent of that configuration:
922 openocd -f interface/ftdi/signalyzer.cfg \
923 -c "gdb_memory_map enable" \
924 -c "gdb_flash_program enable" \
925 -f target/sam7x256.cfg
928 You could wrap such long command lines in shell scripts,
929 each supporting a different development task.
930 One might re-flash the board with a specific firmware version.
931 Another might set up a particular debugging or run-time environment.
934 At this writing (October 2009) the command line method has
935 problems with how it treats variables.
936 For example, after @option{-c "set VAR value"}, or doing the
937 same in a script, the variable @var{VAR} will have no value
938 that can be tested in a later script.
941 Here we will focus on the simpler solution: one user config
942 file, including basic configuration plus any TCL procedures
943 to simplify your work.
945 @section User Config Files
946 @cindex config file, user
947 @cindex user config file
948 @cindex config file, overview
950 A user configuration file ties together all the parts of a project
952 One of the following will match your situation best:
955 @item Ideally almost everything comes from configuration files
956 provided by someone else.
957 For example, OpenOCD distributes a @file{scripts} directory
958 (probably in @file{/usr/share/openocd/scripts} on Linux).
959 Board and tool vendors can provide these too, as can individual
960 user sites; the @option{-s} command line option lets you say
961 where to find these files. (@xref{Running}.)
962 The AT91SAM7X256 example above works this way.
964 Three main types of non-user configuration file each have their
965 own subdirectory in the @file{scripts} directory:
968 @item @b{interface} -- one for each different debug adapter;
969 @item @b{board} -- one for each different board
970 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
973 Best case: include just two files, and they handle everything else.
974 The first is an interface config file.
975 The second is board-specific, and it sets up the JTAG TAPs and
976 their GDB targets (by deferring to some @file{target.cfg} file),
977 declares all flash memory, and leaves you nothing to do except
981 source [find interface/olimex-jtag-tiny.cfg]
982 source [find board/csb337.cfg]
985 Boards with a single microcontroller often won't need more
986 than the target config file, as in the AT91SAM7X256 example.
987 That's because there is no external memory (flash, DDR RAM), and
988 the board differences are encapsulated by application code.
990 @item Maybe you don't know yet what your board looks like to JTAG.
991 Once you know the @file{interface.cfg} file to use, you may
992 need help from OpenOCD to discover what's on the board.
993 Once you find the JTAG TAPs, you can just search for appropriate
995 configuration files ... or write your own, from the bottom up.
996 @xref{autoprobing,,Autoprobing}.
998 @item You can often reuse some standard config files but
999 need to write a few new ones, probably a @file{board.cfg} file.
1000 You will be using commands described later in this User's Guide,
1001 and working with the guidelines in the next chapter.
1003 For example, there may be configuration files for your JTAG adapter
1004 and target chip, but you need a new board-specific config file
1005 giving access to your particular flash chips.
1006 Or you might need to write another target chip configuration file
1007 for a new chip built around the Cortex-M3 core.
1010 When you write new configuration files, please submit
1011 them for inclusion in the next OpenOCD release.
1012 For example, a @file{board/newboard.cfg} file will help the
1013 next users of that board, and a @file{target/newcpu.cfg}
1014 will help support users of any board using that chip.
1018 You may need to write some C code.
1019 It may be as simple as supporting a new FT2232 or parport
1020 based adapter; a bit more involved, like a NAND or NOR flash
1021 controller driver; or a big piece of work like supporting
1022 a new chip architecture.
1025 Reuse the existing config files when you can.
1026 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1027 You may find a board configuration that's a good example to follow.
1029 When you write config files, separate the reusable parts
1030 (things every user of that interface, chip, or board needs)
1031 from ones specific to your environment and debugging approach.
1035 For example, a @code{gdb-attach} event handler that invokes
1036 the @command{reset init} command will interfere with debugging
1037 early boot code, which performs some of the same actions
1038 that the @code{reset-init} event handler does.
1041 Likewise, the @command{arm9 vector_catch} command (or
1042 @cindex vector_catch
1043 its siblings @command{xscale vector_catch}
1044 and @command{cortex_m vector_catch}) can be a time-saver
1045 during some debug sessions, but don't make everyone use that either.
1046 Keep those kinds of debugging aids in your user config file,
1047 along with messaging and tracing setup.
1048 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1051 You might need to override some defaults.
1052 For example, you might need to move, shrink, or back up the target's
1053 work area if your application needs much SRAM.
1056 TCP/IP port configuration is another example of something which
1057 is environment-specific, and should only appear in
1058 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1061 @section Project-Specific Utilities
1063 A few project-specific utility
1064 routines may well speed up your work.
1065 Write them, and keep them in your project's user config file.
1067 For example, if you are making a boot loader work on a
1068 board, it's nice to be able to debug the ``after it's
1069 loaded to RAM'' parts separately from the finicky early
1070 code which sets up the DDR RAM controller and clocks.
1071 A script like this one, or a more GDB-aware sibling,
1075 proc ramboot @{ @} @{
1076 # Reset, running the target's "reset-init" scripts
1077 # to initialize clocks and the DDR RAM controller.
1078 # Leave the CPU halted.
1081 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1082 load_image u-boot.bin 0x20000000
1089 Then once that code is working you will need to make it
1090 boot from NOR flash; a different utility would help.
1091 Alternatively, some developers write to flash using GDB.
1092 (You might use a similar script if you're working with a flash
1093 based microcontroller application instead of a boot loader.)
1096 proc newboot @{ @} @{
1097 # Reset, leaving the CPU halted. The "reset-init" event
1098 # proc gives faster access to the CPU and to NOR flash;
1099 # "reset halt" would be slower.
1102 # Write standard version of U-Boot into the first two
1103 # sectors of NOR flash ... the standard version should
1104 # do the same lowlevel init as "reset-init".
1105 flash protect 0 0 1 off
1106 flash erase_sector 0 0 1
1107 flash write_bank 0 u-boot.bin 0x0
1108 flash protect 0 0 1 on
1110 # Reboot from scratch using that new boot loader.
1115 You may need more complicated utility procedures when booting
1117 That often involves an extra bootloader stage,
1118 running from on-chip SRAM to perform DDR RAM setup so it can load
1119 the main bootloader code (which won't fit into that SRAM).
1121 Other helper scripts might be used to write production system images,
1122 involving considerably more than just a three stage bootloader.
1124 @section Target Software Changes
1126 Sometimes you may want to make some small changes to the software
1127 you're developing, to help make JTAG debugging work better.
1128 For example, in C or assembly language code you might
1129 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1130 handling issues like:
1134 @item @b{Watchdog Timers}...
1135 Watchdog timers are typically used to automatically reset systems if
1136 some application task doesn't periodically reset the timer. (The
1137 assumption is that the system has locked up if the task can't run.)
1138 When a JTAG debugger halts the system, that task won't be able to run
1139 and reset the timer ... potentially causing resets in the middle of
1140 your debug sessions.
1142 It's rarely a good idea to disable such watchdogs, since their usage
1143 needs to be debugged just like all other parts of your firmware.
1144 That might however be your only option.
1146 Look instead for chip-specific ways to stop the watchdog from counting
1147 while the system is in a debug halt state. It may be simplest to set
1148 that non-counting mode in your debugger startup scripts. You may however
1149 need a different approach when, for example, a motor could be physically
1150 damaged by firmware remaining inactive in a debug halt state. That might
1151 involve a type of firmware mode where that "non-counting" mode is disabled
1152 at the beginning then re-enabled at the end; a watchdog reset might fire
1153 and complicate the debug session, but hardware (or people) would be
1154 protected.@footnote{Note that many systems support a "monitor mode" debug
1155 that is a somewhat cleaner way to address such issues. You can think of
1156 it as only halting part of the system, maybe just one task,
1157 instead of the whole thing.
1158 At this writing, January 2010, OpenOCD based debugging does not support
1159 monitor mode debug, only "halt mode" debug.}
1161 @item @b{ARM Semihosting}...
1162 @cindex ARM semihosting
1163 When linked with a special runtime library provided with many
1164 toolchains@footnote{See chapter 8 "Semihosting" in
1165 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1166 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1167 The CodeSourcery EABI toolchain also includes a semihosting library.},
1168 your target code can use I/O facilities on the debug host. That library
1169 provides a small set of system calls which are handled by OpenOCD.
1170 It can let the debugger provide your system console and a file system,
1171 helping with early debugging or providing a more capable environment
1172 for sometimes-complex tasks like installing system firmware onto
1175 @item @b{ARM Wait-For-Interrupt}...
1176 Many ARM chips synchronize the JTAG clock using the core clock.
1177 Low power states which stop that core clock thus prevent JTAG access.
1178 Idle loops in tasking environments often enter those low power states
1179 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1181 You may want to @emph{disable that instruction} in source code,
1182 or otherwise prevent using that state,
1183 to ensure you can get JTAG access at any time.@footnote{As a more
1184 polite alternative, some processors have special debug-oriented
1185 registers which can be used to change various features including
1186 how the low power states are clocked while debugging.
1187 The STM32 DBGMCU_CR register is an example; at the cost of extra
1188 power consumption, JTAG can be used during low power states.}
1189 For example, the OpenOCD @command{halt} command may not
1190 work for an idle processor otherwise.
1192 @item @b{Delay after reset}...
1193 Not all chips have good support for debugger access
1194 right after reset; many LPC2xxx chips have issues here.
1195 Similarly, applications that reconfigure pins used for
1196 JTAG access as they start will also block debugger access.
1198 To work with boards like this, @emph{enable a short delay loop}
1199 the first thing after reset, before "real" startup activities.
1200 For example, one second's delay is usually more than enough
1201 time for a JTAG debugger to attach, so that
1202 early code execution can be debugged
1203 or firmware can be replaced.
1205 @item @b{Debug Communications Channel (DCC)}...
1206 Some processors include mechanisms to send messages over JTAG.
1207 Many ARM cores support these, as do some cores from other vendors.
1208 (OpenOCD may be able to use this DCC internally, speeding up some
1209 operations like writing to memory.)
1211 Your application may want to deliver various debugging messages
1212 over JTAG, by @emph{linking with a small library of code}
1213 provided with OpenOCD and using the utilities there to send
1214 various kinds of message.
1215 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1219 @section Target Hardware Setup
1221 Chip vendors often provide software development boards which
1222 are highly configurable, so that they can support all options
1223 that product boards may require. @emph{Make sure that any
1224 jumpers or switches match the system configuration you are
1227 Common issues include:
1231 @item @b{JTAG setup} ...
1232 Boards may support more than one JTAG configuration.
1233 Examples include jumpers controlling pullups versus pulldowns
1234 on the nTRST and/or nSRST signals, and choice of connectors
1235 (e.g. which of two headers on the base board,
1236 or one from a daughtercard).
1237 For some Texas Instruments boards, you may need to jumper the
1238 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1240 @item @b{Boot Modes} ...
1241 Complex chips often support multiple boot modes, controlled
1242 by external jumpers. Make sure this is set up correctly.
1243 For example many i.MX boards from NXP need to be jumpered
1244 to "ATX mode" to start booting using the on-chip ROM, when
1245 using second stage bootloader code stored in a NAND flash chip.
1247 Such explicit configuration is common, and not limited to
1248 booting from NAND. You might also need to set jumpers to
1249 start booting using code loaded from an MMC/SD card; external
1250 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1251 flash; some external host; or various other sources.
1254 @item @b{Memory Addressing} ...
1255 Boards which support multiple boot modes may also have jumpers
1256 to configure memory addressing. One board, for example, jumpers
1257 external chipselect 0 (used for booting) to address either
1258 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1259 or NAND flash. When it's jumpered to address NAND flash, that
1260 board must also be told to start booting from on-chip ROM.
1262 Your @file{board.cfg} file may also need to be told this jumper
1263 configuration, so that it can know whether to declare NOR flash
1264 using @command{flash bank} or instead declare NAND flash with
1265 @command{nand device}; and likewise which probe to perform in
1266 its @code{reset-init} handler.
1268 A closely related issue is bus width. Jumpers might need to
1269 distinguish between 8 bit or 16 bit bus access for the flash
1270 used to start booting.
1272 @item @b{Peripheral Access} ...
1273 Development boards generally provide access to every peripheral
1274 on the chip, sometimes in multiple modes (such as by providing
1275 multiple audio codec chips).
1276 This interacts with software
1277 configuration of pin multiplexing, where for example a
1278 given pin may be routed either to the MMC/SD controller
1279 or the GPIO controller. It also often interacts with
1280 configuration jumpers. One jumper may be used to route
1281 signals to an MMC/SD card slot or an expansion bus (which
1282 might in turn affect booting); others might control which
1283 audio or video codecs are used.
1287 Plus you should of course have @code{reset-init} event handlers
1288 which set up the hardware to match that jumper configuration.
1289 That includes in particular any oscillator or PLL used to clock
1290 the CPU, and any memory controllers needed to access external
1291 memory and peripherals. Without such handlers, you won't be
1292 able to access those resources without working target firmware
1293 which can do that setup ... this can be awkward when you're
1294 trying to debug that target firmware. Even if there's a ROM
1295 bootloader which handles a few issues, it rarely provides full
1296 access to all board-specific capabilities.
1299 @node Config File Guidelines
1300 @chapter Config File Guidelines
1302 This chapter is aimed at any user who needs to write a config file,
1303 including developers and integrators of OpenOCD and any user who
1304 needs to get a new board working smoothly.
1305 It provides guidelines for creating those files.
1307 You should find the following directories under
1308 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1309 them as-is where you can; or as models for new files.
1311 @item @file{interface} ...
1312 These are for debug adapters. Files that specify configuration to use
1313 specific JTAG, SWD and other adapters go here.
1314 @item @file{board} ...
1315 Think Circuit Board, PWA, PCB, they go by many names. Board files
1316 contain initialization items that are specific to a board.
1318 They reuse target configuration files, since the same
1319 microprocessor chips are used on many boards,
1320 but support for external parts varies widely. For
1321 example, the SDRAM initialization sequence for the board, or the type
1322 of external flash and what address it uses. Any initialization
1323 sequence to enable that external flash or SDRAM should be found in the
1324 board file. Boards may also contain multiple targets: two CPUs; or
1326 @item @file{target} ...
1327 Think chip. The ``target'' directory represents the JTAG TAPs
1329 which OpenOCD should control, not a board. Two common types of targets
1330 are ARM chips and FPGA or CPLD chips.
1331 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1332 the target config file defines all of them.
1333 @item @emph{more} ... browse for other library files which may be useful.
1334 For example, there are various generic and CPU-specific utilities.
1337 The @file{openocd.cfg} user config
1338 file may override features in any of the above files by
1339 setting variables before sourcing the target file, or by adding
1340 commands specific to their situation.
1342 @section Interface Config Files
1344 The user config file
1345 should be able to source one of these files with a command like this:
1348 source [find interface/FOOBAR.cfg]
1351 A preconfigured interface file should exist for every debug adapter
1352 in use today with OpenOCD.
1353 That said, perhaps some of these config files
1354 have only been used by the developer who created it.
1356 A separate chapter gives information about how to set these up.
1357 @xref{Debug Adapter Configuration}.
1358 Read the OpenOCD source code (and Developer's Guide)
1359 if you have a new kind of hardware interface
1360 and need to provide a driver for it.
1362 @section Board Config Files
1363 @cindex config file, board
1364 @cindex board config file
1366 The user config file
1367 should be able to source one of these files with a command like this:
1370 source [find board/FOOBAR.cfg]
1373 The point of a board config file is to package everything
1374 about a given board that user config files need to know.
1375 In summary the board files should contain (if present)
1378 @item One or more @command{source [find target/...cfg]} statements
1379 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1380 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1381 @item Target @code{reset} handlers for SDRAM and I/O configuration
1382 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1383 @item All things that are not ``inside a chip''
1386 Generic things inside target chips belong in target config files,
1387 not board config files. So for example a @code{reset-init} event
1388 handler should know board-specific oscillator and PLL parameters,
1389 which it passes to target-specific utility code.
1391 The most complex task of a board config file is creating such a
1392 @code{reset-init} event handler.
1393 Define those handlers last, after you verify the rest of the board
1394 configuration works.
1396 @subsection Communication Between Config files
1398 In addition to target-specific utility code, another way that
1399 board and target config files communicate is by following a
1400 convention on how to use certain variables.
1402 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1403 Thus the rule we follow in OpenOCD is this: Variables that begin with
1404 a leading underscore are temporary in nature, and can be modified and
1405 used at will within a target configuration file.
1407 Complex board config files can do the things like this,
1408 for a board with three chips:
1411 # Chip #1: PXA270 for network side, big endian
1412 set CHIPNAME network
1414 source [find target/pxa270.cfg]
1415 # on return: _TARGETNAME = network.cpu
1416 # other commands can refer to the "network.cpu" target.
1417 $_TARGETNAME configure .... events for this CPU..
1419 # Chip #2: PXA270 for video side, little endian
1422 source [find target/pxa270.cfg]
1423 # on return: _TARGETNAME = video.cpu
1424 # other commands can refer to the "video.cpu" target.
1425 $_TARGETNAME configure .... events for this CPU..
1427 # Chip #3: Xilinx FPGA for glue logic
1430 source [find target/spartan3.cfg]
1433 That example is oversimplified because it doesn't show any flash memory,
1434 or the @code{reset-init} event handlers to initialize external DRAM
1435 or (assuming it needs it) load a configuration into the FPGA.
1436 Such features are usually needed for low-level work with many boards,
1437 where ``low level'' implies that the board initialization software may
1438 not be working. (That's a common reason to need JTAG tools. Another
1439 is to enable working with microcontroller-based systems, which often
1440 have no debugging support except a JTAG connector.)
1442 Target config files may also export utility functions to board and user
1443 config files. Such functions should use name prefixes, to help avoid
1446 Board files could also accept input variables from user config files.
1447 For example, there might be a @code{J4_JUMPER} setting used to identify
1448 what kind of flash memory a development board is using, or how to set
1449 up other clocks and peripherals.
1451 @subsection Variable Naming Convention
1452 @cindex variable names
1454 Most boards have only one instance of a chip.
1455 However, it should be easy to create a board with more than
1456 one such chip (as shown above).
1457 Accordingly, we encourage these conventions for naming
1458 variables associated with different @file{target.cfg} files,
1459 to promote consistency and
1460 so that board files can override target defaults.
1462 Inputs to target config files include:
1465 @item @code{CHIPNAME} ...
1466 This gives a name to the overall chip, and is used as part of
1467 tap identifier dotted names.
1468 While the default is normally provided by the chip manufacturer,
1469 board files may need to distinguish between instances of a chip.
1470 @item @code{ENDIAN} ...
1471 By default @option{little} - although chips may hard-wire @option{big}.
1472 Chips that can't change endianness don't need to use this variable.
1473 @item @code{CPUTAPID} ...
1474 When OpenOCD examines the JTAG chain, it can be told verify the
1475 chips against the JTAG IDCODE register.
1476 The target file will hold one or more defaults, but sometimes the
1477 chip in a board will use a different ID (perhaps a newer revision).
1480 Outputs from target config files include:
1483 @item @code{_TARGETNAME} ...
1484 By convention, this variable is created by the target configuration
1485 script. The board configuration file may make use of this variable to
1486 configure things like a ``reset init'' script, or other things
1487 specific to that board and that target.
1488 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1489 @code{_TARGETNAME1}, ... etc.
1492 @subsection The reset-init Event Handler
1493 @cindex event, reset-init
1494 @cindex reset-init handler
1496 Board config files run in the OpenOCD configuration stage;
1497 they can't use TAPs or targets, since they haven't been
1499 This means you can't write memory or access chip registers;
1500 you can't even verify that a flash chip is present.
1501 That's done later in event handlers, of which the target @code{reset-init}
1502 handler is one of the most important.
1504 Except on microcontrollers, the basic job of @code{reset-init} event
1505 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1506 Microcontrollers rarely use boot loaders; they run right out of their
1507 on-chip flash and SRAM memory. But they may want to use one of these
1508 handlers too, if just for developer convenience.
1511 Because this is so very board-specific, and chip-specific, no examples
1513 Instead, look at the board config files distributed with OpenOCD.
1514 If you have a boot loader, its source code will help; so will
1515 configuration files for other JTAG tools
1516 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1519 Some of this code could probably be shared between different boards.
1520 For example, setting up a DRAM controller often doesn't differ by
1521 much except the bus width (16 bits or 32?) and memory timings, so a
1522 reusable TCL procedure loaded by the @file{target.cfg} file might take
1523 those as parameters.
1524 Similarly with oscillator, PLL, and clock setup;
1525 and disabling the watchdog.
1526 Structure the code cleanly, and provide comments to help
1527 the next developer doing such work.
1528 (@emph{You might be that next person} trying to reuse init code!)
1530 The last thing normally done in a @code{reset-init} handler is probing
1531 whatever flash memory was configured. For most chips that needs to be
1532 done while the associated target is halted, either because JTAG memory
1533 access uses the CPU or to prevent conflicting CPU access.
1535 @subsection JTAG Clock Rate
1537 Before your @code{reset-init} handler has set up
1538 the PLLs and clocking, you may need to run with
1539 a low JTAG clock rate.
1540 @xref{jtagspeed,,JTAG Speed}.
1541 Then you'd increase that rate after your handler has
1542 made it possible to use the faster JTAG clock.
1543 When the initial low speed is board-specific, for example
1544 because it depends on a board-specific oscillator speed, then
1545 you should probably set it up in the board config file;
1546 if it's target-specific, it belongs in the target config file.
1548 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1549 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1550 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1551 Consult chip documentation to determine the peak JTAG clock rate,
1552 which might be less than that.
1555 On most ARMs, JTAG clock detection is coupled to the core clock, so
1556 software using a @option{wait for interrupt} operation blocks JTAG access.
1557 Adaptive clocking provides a partial workaround, but a more complete
1558 solution just avoids using that instruction with JTAG debuggers.
1561 If both the chip and the board support adaptive clocking,
1562 use the @command{jtag_rclk}
1563 command, in case your board is used with JTAG adapter which
1564 also supports it. Otherwise use @command{adapter speed}.
1565 Set the slow rate at the beginning of the reset sequence,
1566 and the faster rate as soon as the clocks are at full speed.
1568 @anchor{theinitboardprocedure}
1569 @subsection The init_board procedure
1570 @cindex init_board procedure
1572 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1573 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1574 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1575 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1576 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1577 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1578 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1579 Additionally ``linear'' board config file will most likely fail when target config file uses
1580 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1581 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1582 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1583 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1585 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1586 the original), allowing greater code reuse.
1589 ### board_file.cfg ###
1591 # source target file that does most of the config in init_targets
1592 source [find target/target.cfg]
1594 proc enable_fast_clock @{@} @{
1595 # enables fast on-board clock source
1596 # configures the chip to use it
1599 # initialize only board specifics - reset, clock, adapter frequency
1600 proc init_board @{@} @{
1601 reset_config trst_and_srst trst_pulls_srst
1603 $_TARGETNAME configure -event reset-start @{
1607 $_TARGETNAME configure -event reset-init @{
1614 @section Target Config Files
1615 @cindex config file, target
1616 @cindex target config file
1618 Board config files communicate with target config files using
1619 naming conventions as described above, and may source one or
1620 more target config files like this:
1623 source [find target/FOOBAR.cfg]
1626 The point of a target config file is to package everything
1627 about a given chip that board config files need to know.
1628 In summary the target files should contain
1632 @item Add TAPs to the scan chain
1633 @item Add CPU targets (includes GDB support)
1634 @item CPU/Chip/CPU-Core specific features
1638 As a rule of thumb, a target file sets up only one chip.
1639 For a microcontroller, that will often include a single TAP,
1640 which is a CPU needing a GDB target, and its on-chip flash.
1642 More complex chips may include multiple TAPs, and the target
1643 config file may need to define them all before OpenOCD
1644 can talk to the chip.
1645 For example, some phone chips have JTAG scan chains that include
1646 an ARM core for operating system use, a DSP,
1647 another ARM core embedded in an image processing engine,
1648 and other processing engines.
1650 @subsection Default Value Boiler Plate Code
1652 All target configuration files should start with code like this,
1653 letting board config files express environment-specific
1654 differences in how things should be set up.
1657 # Boards may override chip names, perhaps based on role,
1658 # but the default should match what the vendor uses
1659 if @{ [info exists CHIPNAME] @} @{
1660 set _CHIPNAME $CHIPNAME
1662 set _CHIPNAME sam7x256
1665 # ONLY use ENDIAN with targets that can change it.
1666 if @{ [info exists ENDIAN] @} @{
1672 # TAP identifiers may change as chips mature, for example with
1673 # new revision fields (the "3" here). Pick a good default; you
1674 # can pass several such identifiers to the "jtag newtap" command.
1675 if @{ [info exists CPUTAPID ] @} @{
1676 set _CPUTAPID $CPUTAPID
1678 set _CPUTAPID 0x3f0f0f0f
1681 @c but 0x3f0f0f0f is for an str73x part ...
1683 @emph{Remember:} Board config files may include multiple target
1684 config files, or the same target file multiple times
1685 (changing at least @code{CHIPNAME}).
1687 Likewise, the target configuration file should define
1688 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1689 use it later on when defining debug targets:
1692 set _TARGETNAME $_CHIPNAME.cpu
1693 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1696 @subsection Adding TAPs to the Scan Chain
1697 After the ``defaults'' are set up,
1698 add the TAPs on each chip to the JTAG scan chain.
1699 @xref{TAP Declaration}, and the naming convention
1702 In the simplest case the chip has only one TAP,
1703 probably for a CPU or FPGA.
1704 The config file for the Atmel AT91SAM7X256
1705 looks (in part) like this:
1708 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1711 A board with two such at91sam7 chips would be able
1712 to source such a config file twice, with different
1713 values for @code{CHIPNAME}, so
1714 it adds a different TAP each time.
1716 If there are nonzero @option{-expected-id} values,
1717 OpenOCD attempts to verify the actual tap id against those values.
1718 It will issue error messages if there is mismatch, which
1719 can help to pinpoint problems in OpenOCD configurations.
1722 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1723 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1724 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1725 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1726 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1729 There are more complex examples too, with chips that have
1730 multiple TAPs. Ones worth looking at include:
1733 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1734 plus a JRC to enable them
1735 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1736 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1737 is not currently used)
1740 @subsection Add CPU targets
1742 After adding a TAP for a CPU, you should set it up so that
1743 GDB and other commands can use it.
1744 @xref{CPU Configuration}.
1745 For the at91sam7 example above, the command can look like this;
1746 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1747 to little endian, and this chip doesn't support changing that.
1750 set _TARGETNAME $_CHIPNAME.cpu
1751 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1754 Work areas are small RAM areas associated with CPU targets.
1755 They are used by OpenOCD to speed up downloads,
1756 and to download small snippets of code to program flash chips.
1757 If the chip includes a form of ``on-chip-ram'' - and many do - define
1758 a work area if you can.
1759 Again using the at91sam7 as an example, this can look like:
1762 $_TARGETNAME configure -work-area-phys 0x00200000 \
1763 -work-area-size 0x4000 -work-area-backup 0
1766 @anchor{definecputargetsworkinginsmp}
1767 @subsection Define CPU targets working in SMP
1769 After setting targets, you can define a list of targets working in SMP.
1772 set _TARGETNAME_1 $_CHIPNAME.cpu1
1773 set _TARGETNAME_2 $_CHIPNAME.cpu2
1774 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1775 -coreid 0 -dbgbase $_DAP_DBG1
1776 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1777 -coreid 1 -dbgbase $_DAP_DBG2
1778 #define 2 targets working in smp.
1779 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1781 In the above example on cortex_a, 2 cpus are working in SMP.
1782 In SMP only one GDB instance is created and :
1784 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1785 @item halt command triggers the halt of all targets in the list.
1786 @item resume command triggers the write context and the restart of all targets in the list.
1787 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1788 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1789 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1792 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1793 command have been implemented.
1795 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1796 @item cortex_a smp off : disable SMP mode, the current target is the one
1797 displayed in the GDB session, only this target is now controlled by GDB
1798 session. This behaviour is useful during system boot up.
1799 @item cortex_a smp : display current SMP mode.
1800 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1807 #0 : coreid 0 is displayed to GDB ,
1808 #-> -1 : next resume triggers a real resume
1809 > cortex_a smp_gdb 1
1811 #0 :coreid 0 is displayed to GDB ,
1812 #->1 : next resume displays coreid 1 to GDB
1816 #1 :coreid 1 is displayed to GDB ,
1817 #->1 : next resume displays coreid 1 to GDB
1818 > cortex_a smp_gdb -1
1820 #1 :coreid 1 is displayed to GDB,
1821 #->-1 : next resume triggers a real resume
1825 @subsection Chip Reset Setup
1827 As a rule, you should put the @command{reset_config} command
1828 into the board file. Most things you think you know about a
1829 chip can be tweaked by the board.
1831 Some chips have specific ways the TRST and SRST signals are
1832 managed. In the unusual case that these are @emph{chip specific}
1833 and can never be changed by board wiring, they could go here.
1834 For example, some chips can't support JTAG debugging without
1837 Provide a @code{reset-assert} event handler if you can.
1838 Such a handler uses JTAG operations to reset the target,
1839 letting this target config be used in systems which don't
1840 provide the optional SRST signal, or on systems where you
1841 don't want to reset all targets at once.
1842 Such a handler might write to chip registers to force a reset,
1843 use a JRC to do that (preferable -- the target may be wedged!),
1844 or force a watchdog timer to trigger.
1845 (For Cortex-M targets, this is not necessary. The target
1846 driver knows how to use trigger an NVIC reset when SRST is
1849 Some chips need special attention during reset handling if
1850 they're going to be used with JTAG.
1851 An example might be needing to send some commands right
1852 after the target's TAP has been reset, providing a
1853 @code{reset-deassert-post} event handler that writes a chip
1854 register to report that JTAG debugging is being done.
1855 Another would be reconfiguring the watchdog so that it stops
1856 counting while the core is halted in the debugger.
1858 JTAG clocking constraints often change during reset, and in
1859 some cases target config files (rather than board config files)
1860 are the right places to handle some of those issues.
1861 For example, immediately after reset most chips run using a
1862 slower clock than they will use later.
1863 That means that after reset (and potentially, as OpenOCD
1864 first starts up) they must use a slower JTAG clock rate
1865 than they will use later.
1866 @xref{jtagspeed,,JTAG Speed}.
1868 @quotation Important
1869 When you are debugging code that runs right after chip
1870 reset, getting these issues right is critical.
1871 In particular, if you see intermittent failures when
1872 OpenOCD verifies the scan chain after reset,
1873 look at how you are setting up JTAG clocking.
1876 @anchor{theinittargetsprocedure}
1877 @subsection The init_targets procedure
1878 @cindex init_targets procedure
1880 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1881 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1882 procedure called @code{init_targets}, which will be executed when entering run stage
1883 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1884 Such procedure can be overridden by ``next level'' script (which sources the original).
1885 This concept facilitates code reuse when basic target config files provide generic configuration
1886 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1887 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1888 because sourcing them executes every initialization commands they provide.
1891 ### generic_file.cfg ###
1893 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1894 # basic initialization procedure ...
1897 proc init_targets @{@} @{
1898 # initializes generic chip with 4kB of flash and 1kB of RAM
1899 setup_my_chip MY_GENERIC_CHIP 4096 1024
1902 ### specific_file.cfg ###
1904 source [find target/generic_file.cfg]
1906 proc init_targets @{@} @{
1907 # initializes specific chip with 128kB of flash and 64kB of RAM
1908 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1912 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1913 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1915 For an example of this scheme see LPC2000 target config files.
1917 The @code{init_boards} procedure is a similar concept concerning board config files
1918 (@xref{theinitboardprocedure,,The init_board procedure}.)
1920 @anchor{theinittargeteventsprocedure}
1921 @subsection The init_target_events procedure
1922 @cindex init_target_events procedure
1924 A special procedure called @code{init_target_events} is run just after
1925 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1926 procedure}.) and before @code{init_board}
1927 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1928 to set up default target events for the targets that do not have those
1929 events already assigned.
1931 @subsection ARM Core Specific Hacks
1933 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1934 special high speed download features - enable it.
1936 If present, the MMU, the MPU and the CACHE should be disabled.
1938 Some ARM cores are equipped with trace support, which permits
1939 examination of the instruction and data bus activity. Trace
1940 activity is controlled through an ``Embedded Trace Module'' (ETM)
1941 on one of the core's scan chains. The ETM emits voluminous data
1942 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1943 If you are using an external trace port,
1944 configure it in your board config file.
1945 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1946 configure it in your target config file.
1949 etm config $_TARGETNAME 16 normal full etb
1950 etb config $_TARGETNAME $_CHIPNAME.etb
1953 @subsection Internal Flash Configuration
1955 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1957 @b{Never ever} in the ``target configuration file'' define any type of
1958 flash that is external to the chip. (For example a BOOT flash on
1959 Chip Select 0.) Such flash information goes in a board file - not
1960 the TARGET (chip) file.
1964 @item at91sam7x256 - has 256K flash YES enable it.
1965 @item str912 - has flash internal YES enable it.
1966 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1967 @item pxa270 - again - CS0 flash - it goes in the board file.
1970 @anchor{translatingconfigurationfiles}
1971 @section Translating Configuration Files
1973 If you have a configuration file for another hardware debugger
1974 or toolset (Abatron, BDI2000, BDI3000, CCS,
1975 Lauterbach, SEGGER, Macraigor, etc.), translating
1976 it into OpenOCD syntax is often quite straightforward. The most tricky
1977 part of creating a configuration script is oftentimes the reset init
1978 sequence where e.g. PLLs, DRAM and the like is set up.
1980 One trick that you can use when translating is to write small
1981 Tcl procedures to translate the syntax into OpenOCD syntax. This
1982 can avoid manual translation errors and make it easier to
1983 convert other scripts later on.
1985 Example of transforming quirky arguments to a simple search and
1989 # Lauterbach syntax(?)
1991 # Data.Set c15:0x042f %long 0x40000015
1993 # OpenOCD syntax when using procedure below.
1995 # setc15 0x01 0x00050078
1997 proc setc15 @{regs value@} @{
2000 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2002 arm mcr 15 [expr ($regs>>12)&0x7] \
2003 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2004 [expr ($regs>>8)&0x7] $value
2010 @node Server Configuration
2011 @chapter Server Configuration
2012 @cindex initialization
2013 The commands here are commonly found in the openocd.cfg file and are
2014 used to specify what TCP/IP ports are used, and how GDB should be
2017 @anchor{configurationstage}
2018 @section Configuration Stage
2019 @cindex configuration stage
2020 @cindex config command
2022 When the OpenOCD server process starts up, it enters a
2023 @emph{configuration stage} which is the only time that
2024 certain commands, @emph{configuration commands}, may be issued.
2025 Normally, configuration commands are only available
2026 inside startup scripts.
2028 In this manual, the definition of a configuration command is
2029 presented as a @emph{Config Command}, not as a @emph{Command}
2030 which may be issued interactively.
2031 The runtime @command{help} command also highlights configuration
2032 commands, and those which may be issued at any time.
2034 Those configuration commands include declaration of TAPs,
2036 the interface used for JTAG communication,
2037 and other basic setup.
2038 The server must leave the configuration stage before it
2039 may access or activate TAPs.
2040 After it leaves this stage, configuration commands may no
2043 @anchor{enteringtherunstage}
2044 @section Entering the Run Stage
2046 The first thing OpenOCD does after leaving the configuration
2047 stage is to verify that it can talk to the scan chain
2048 (list of TAPs) which has been configured.
2049 It will warn if it doesn't find TAPs it expects to find,
2050 or finds TAPs that aren't supposed to be there.
2051 You should see no errors at this point.
2052 If you see errors, resolve them by correcting the
2053 commands you used to configure the server.
2054 Common errors include using an initial JTAG speed that's too
2055 fast, and not providing the right IDCODE values for the TAPs
2058 Once OpenOCD has entered the run stage, a number of commands
2060 A number of these relate to the debug targets you may have declared.
2061 For example, the @command{mww} command will not be available until
2062 a target has been successfully instantiated.
2063 If you want to use those commands, you may need to force
2064 entry to the run stage.
2066 @deffn {Config Command} {init}
2067 This command terminates the configuration stage and
2068 enters the run stage. This helps when you need to have
2069 the startup scripts manage tasks such as resetting the target,
2070 programming flash, etc. To reset the CPU upon startup, add "init" and
2071 "reset" at the end of the config script or at the end of the OpenOCD
2072 command line using the @option{-c} command line switch.
2074 If this command does not appear in any startup/configuration file
2075 OpenOCD executes the command for you after processing all
2076 configuration files and/or command line options.
2078 @b{NOTE:} This command normally occurs at or near the end of your
2079 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2080 targets ready. For example: If your openocd.cfg file needs to
2081 read/write memory on your target, @command{init} must occur before
2082 the memory read/write commands. This includes @command{nand probe}.
2085 @deffn {Overridable Procedure} {jtag_init}
2086 This is invoked at server startup to verify that it can talk
2087 to the scan chain (list of TAPs) which has been configured.
2089 The default implementation first tries @command{jtag arp_init},
2090 which uses only a lightweight JTAG reset before examining the
2092 If that fails, it tries again, using a harder reset
2093 from the overridable procedure @command{init_reset}.
2095 Implementations must have verified the JTAG scan chain before
2097 This is done by calling @command{jtag arp_init}
2098 (or @command{jtag arp_init-reset}).
2102 @section TCP/IP Ports
2107 The OpenOCD server accepts remote commands in several syntaxes.
2108 Each syntax uses a different TCP/IP port, which you may specify
2109 only during configuration (before those ports are opened).
2111 For reasons including security, you may wish to prevent remote
2112 access using one or more of these ports.
2113 In such cases, just specify the relevant port number as "disabled".
2114 If you disable all access through TCP/IP, you will need to
2115 use the command line @option{-pipe} option.
2118 @deffn {Config Command} {gdb_port} [number]
2120 Normally gdb listens to a TCP/IP port, but GDB can also
2121 communicate via pipes(stdin/out or named pipes). The name
2122 "gdb_port" stuck because it covers probably more than 90% of
2123 the normal use cases.
2125 No arguments reports GDB port. "pipe" means listen to stdin
2126 output to stdout, an integer is base port number, "disabled"
2127 disables the gdb server.
2129 When using "pipe", also use log_output to redirect the log
2130 output to a file so as not to flood the stdin/out pipes.
2132 Any other string is interpreted as named pipe to listen to.
2133 Output pipe is the same name as input pipe, but with 'o' appended,
2134 e.g. /var/gdb, /var/gdbo.
2136 The GDB port for the first target will be the base port, the
2137 second target will listen on gdb_port + 1, and so on.
2138 When not specified during the configuration stage,
2139 the port @var{number} defaults to 3333.
2140 When @var{number} is not a numeric value, incrementing it to compute
2141 the next port number does not work. In this case, specify the proper
2142 @var{number} for each target by using the option @code{-gdb-port} of the
2143 commands @command{target create} or @command{$target_name configure}.
2144 @xref{gdbportoverride,,option -gdb-port}.
2146 Note: when using "gdb_port pipe", increasing the default remote timeout in
2147 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2148 cause initialization to fail with "Unknown remote qXfer reply: OK".
2151 @deffn {Config Command} {tcl_port} [number]
2152 Specify or query the port used for a simplified RPC
2153 connection that can be used by clients to issue TCL commands and get the
2154 output from the Tcl engine.
2155 Intended as a machine interface.
2156 When not specified during the configuration stage,
2157 the port @var{number} defaults to 6666.
2158 When specified as "disabled", this service is not activated.
2161 @deffn {Config Command} {telnet_port} [number]
2162 Specify or query the
2163 port on which to listen for incoming telnet connections.
2164 This port is intended for interaction with one human through TCL commands.
2165 When not specified during the configuration stage,
2166 the port @var{number} defaults to 4444.
2167 When specified as "disabled", this service is not activated.
2170 @anchor{gdbconfiguration}
2171 @section GDB Configuration
2173 @cindex GDB configuration
2174 You can reconfigure some GDB behaviors if needed.
2175 The ones listed here are static and global.
2176 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2177 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2179 @anchor{gdbbreakpointoverride}
2180 @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
2181 Force breakpoint type for gdb @command{break} commands.
2182 This option supports GDB GUIs which don't
2183 distinguish hard versus soft breakpoints, if the default OpenOCD and
2184 GDB behaviour is not sufficient. GDB normally uses hardware
2185 breakpoints if the memory map has been set up for flash regions.
2188 @anchor{gdbflashprogram}
2189 @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
2190 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2191 vFlash packet is received.
2192 The default behaviour is @option{enable}.
2195 @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
2196 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2197 requested. GDB will then know when to set hardware breakpoints, and program flash
2198 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2199 for flash programming to work.
2200 Default behaviour is @option{enable}.
2201 @xref{gdbflashprogram,,gdb_flash_program}.
2204 @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
2205 Specifies whether data aborts cause an error to be reported
2206 by GDB memory read packets.
2207 The default behaviour is @option{disable};
2208 use @option{enable} see these errors reported.
2211 @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
2212 Specifies whether register accesses requested by GDB register read/write
2213 packets report errors or not.
2214 The default behaviour is @option{disable};
2215 use @option{enable} see these errors reported.
2218 @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
2219 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2220 The default behaviour is @option{enable}.
2223 @deffn {Command} {gdb_save_tdesc}
2224 Saves the target description file to the local file system.
2226 The file name is @i{target_name}.xml.
2229 @anchor{eventpolling}
2230 @section Event Polling
2232 Hardware debuggers are parts of asynchronous systems,
2233 where significant events can happen at any time.
2234 The OpenOCD server needs to detect some of these events,
2235 so it can report them to through TCL command line
2238 Examples of such events include:
2241 @item One of the targets can stop running ... maybe it triggers
2242 a code breakpoint or data watchpoint, or halts itself.
2243 @item Messages may be sent over ``debug message'' channels ... many
2244 targets support such messages sent over JTAG,
2245 for receipt by the person debugging or tools.
2246 @item Loss of power ... some adapters can detect these events.
2247 @item Resets not issued through JTAG ... such reset sources
2248 can include button presses or other system hardware, sometimes
2249 including the target itself (perhaps through a watchdog).
2250 @item Debug instrumentation sometimes supports event triggering
2251 such as ``trace buffer full'' (so it can quickly be emptied)
2252 or other signals (to correlate with code behavior).
2255 None of those events are signaled through standard JTAG signals.
2256 However, most conventions for JTAG connectors include voltage
2257 level and system reset (SRST) signal detection.
2258 Some connectors also include instrumentation signals, which
2259 can imply events when those signals are inputs.
2261 In general, OpenOCD needs to periodically check for those events,
2262 either by looking at the status of signals on the JTAG connector
2263 or by sending synchronous ``tell me your status'' JTAG requests
2264 to the various active targets.
2265 There is a command to manage and monitor that polling,
2266 which is normally done in the background.
2268 @deffn {Command} {poll} [@option{on}|@option{off}]
2269 Poll the current target for its current state.
2270 (Also, @pxref{targetcurstate,,target curstate}.)
2271 If that target is in debug mode, architecture
2272 specific information about the current state is printed.
2273 An optional parameter
2274 allows background polling to be enabled and disabled.
2276 You could use this from the TCL command shell, or
2277 from GDB using @command{monitor poll} command.
2278 Leave background polling enabled while you're using GDB.
2281 background polling: on
2282 target state: halted
2283 target halted in ARM state due to debug-request, \
2284 current mode: Supervisor
2285 cpsr: 0x800000d3 pc: 0x11081bfc
2286 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2291 @node Debug Adapter Configuration
2292 @chapter Debug Adapter Configuration
2293 @cindex config file, interface
2294 @cindex interface config file
2296 Correctly installing OpenOCD includes making your operating system give
2297 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2298 are used to select which one is used, and to configure how it is used.
2301 Because OpenOCD started out with a focus purely on JTAG, you may find
2302 places where it wrongly presumes JTAG is the only transport protocol
2303 in use. Be aware that recent versions of OpenOCD are removing that
2304 limitation. JTAG remains more functional than most other transports.
2305 Other transports do not support boundary scan operations, or may be
2306 specific to a given chip vendor. Some might be usable only for
2307 programming flash memory, instead of also for debugging.
2310 Debug Adapters/Interfaces/Dongles are normally configured
2311 through commands in an interface configuration
2312 file which is sourced by your @file{openocd.cfg} file, or
2313 through a command line @option{-f interface/....cfg} option.
2316 source [find interface/olimex-jtag-tiny.cfg]
2320 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2321 A few cases are so simple that you only need to say what driver to use:
2325 adapter driver jlink
2328 Most adapters need a bit more configuration than that.
2331 @section Adapter Configuration
2333 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2334 using. Depending on the type of adapter, you may need to use one or
2335 more additional commands to further identify or configure the adapter.
2337 @deffn {Config Command} {adapter driver} name
2338 Use the adapter driver @var{name} to connect to the
2342 @deffn {Command} {adapter list}
2343 List the debug adapter drivers that have been built into
2344 the running copy of OpenOCD.
2346 @deffn {Config Command} {adapter transports} transport_name+
2347 Specifies the transports supported by this debug adapter.
2348 The adapter driver builds-in similar knowledge; use this only
2349 when external configuration (such as jumpering) changes what
2350 the hardware can support.
2355 @deffn {Command} {adapter name}
2356 Returns the name of the debug adapter driver being used.
2359 @anchor{adapter_usb_location}
2360 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
2361 Displays or specifies the physical USB port of the adapter to use. The path
2362 roots at @var{bus} and walks down the physical ports, with each
2363 @var{port} option specifying a deeper level in the bus topology, the last
2364 @var{port} denoting where the target adapter is actually plugged.
2365 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2367 This command is only available if your libusb1 is at least version 1.0.16.
2370 @deffn {Config Command} {adapter serial} serial_string
2371 Specifies the @var{serial_string} of the adapter to use.
2372 If this command is not specified, serial strings are not checked.
2373 Only the following adapter drivers use the serial string from this command:
2374 cmsis_dap, ft232r, ftdi, jlink, kitprog, presto, vsllink, xds110.
2375 The following adapters have their own command to specify the serial string:
2379 @section Interface Drivers
2381 Each of the interface drivers listed here must be explicitly
2382 enabled when OpenOCD is configured, in order to be made
2383 available at run time.
2385 @deffn {Interface Driver} {amt_jtagaccel}
2386 Amontec Chameleon in its JTAG Accelerator configuration,
2387 connected to a PC's EPP mode parallel port.
2388 This defines some driver-specific commands:
2390 @deffn {Config Command} {parport port} number
2391 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2392 the number of the @file{/dev/parport} device.
2395 @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
2396 Displays status of RTCK option.
2397 Optionally sets that option first.
2401 @deffn {Interface Driver} {arm-jtag-ew}
2402 Olimex ARM-JTAG-EW USB adapter
2403 This has one driver-specific command:
2405 @deffn {Command} {armjtagew_info}
2410 @deffn {Interface Driver} {at91rm9200}
2411 Supports bitbanged JTAG from the local system,
2412 presuming that system is an Atmel AT91rm9200
2413 and a specific set of GPIOs is used.
2414 @c command: at91rm9200_device NAME
2415 @c chooses among list of bit configs ... only one option
2418 @deffn {Interface Driver} {cmsis-dap}
2419 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
2422 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2423 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2424 the driver will attempt to auto detect the CMSIS-DAP device.
2425 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2427 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2431 @deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
2432 Specifies how to communicate with the adapter:
2435 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
2436 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
2437 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
2438 This is the default if @command{cmsis_dap_backend} is not specified.
2442 @deffn {Config Command} {cmsis_dap_usb interface} [number]
2443 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
2444 In most cases need not to be specified and interfaces are searched by
2445 interface string or for user class interface.
2448 @deffn {Command} {cmsis-dap info}
2449 Display various device information, like hardware version, firmware version, current bus status.
2453 @deffn {Interface Driver} {dummy}
2454 A dummy software-only driver for debugging.
2457 @deffn {Interface Driver} {ep93xx}
2458 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2461 @deffn {Interface Driver} {ftdi}
2462 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2463 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2465 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2466 bypassing intermediate libraries like libftdi.
2468 Support for new FTDI based adapters can be added completely through
2469 configuration files, without the need to patch and rebuild OpenOCD.
2471 The driver uses a signal abstraction to enable Tcl configuration files to
2472 define outputs for one or several FTDI GPIO. These outputs can then be
2473 controlled using the @command{ftdi set_signal} command. Special signal names
2474 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2475 will be used for their customary purpose. Inputs can be read using the
2476 @command{ftdi get_signal} command.
2478 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2479 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2480 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2481 required by the protocol, to tell the adapter to drive the data output onto
2482 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2484 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2485 be controlled differently. In order to support tristateable signals such as
2486 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2487 signal. The following output buffer configurations are supported:
2490 @item Push-pull with one FTDI output as (non-)inverted data line
2491 @item Open drain with one FTDI output as (non-)inverted output-enable
2492 @item Tristate with one FTDI output as (non-)inverted data line and another
2493 FTDI output as (non-)inverted output-enable
2494 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2495 switching data and direction as necessary
2498 These interfaces have several commands, used to configure the driver
2499 before initializing the JTAG scan chain:
2501 @deffn {Config Command} {ftdi vid_pid} [vid pid]+
2502 The vendor ID and product ID of the adapter. Up to eight
2503 [@var{vid}, @var{pid}] pairs may be given, e.g.
2505 ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
2509 @deffn {Config Command} {ftdi device_desc} description
2510 Provides the USB device description (the @emph{iProduct string})
2511 of the adapter. If not specified, the device description is ignored
2512 during device selection.
2515 @deffn {Config Command} {ftdi channel} channel
2516 Selects the channel of the FTDI device to use for MPSSE operations. Most
2517 adapters use the default, channel 0, but there are exceptions.
2520 @deffn {Config Command} {ftdi layout_init} data direction
2521 Specifies the initial values of the FTDI GPIO data and direction registers.
2522 Each value is a 16-bit number corresponding to the concatenation of the high
2523 and low FTDI GPIO registers. The values should be selected based on the
2524 schematics of the adapter, such that all signals are set to safe levels with
2525 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2526 and initially asserted reset signals.
2529 @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2530 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2531 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2532 register bitmasks to tell the driver the connection and type of the output
2533 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2534 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2535 used with inverting data inputs and @option{-data} with non-inverting inputs.
2536 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2537 not-output-enable) input to the output buffer is connected. The options
2538 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2539 with the method @command{ftdi get_signal}.
2541 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2542 simple open-collector transistor driver would be specified with @option{-oe}
2543 only. In that case the signal can only be set to drive low or to Hi-Z and the
2544 driver will complain if the signal is set to drive high. Which means that if
2545 it's a reset signal, @command{reset_config} must be specified as
2546 @option{srst_open_drain}, not @option{srst_push_pull}.
2548 A special case is provided when @option{-data} and @option{-oe} is set to the
2549 same bitmask. Then the FTDI pin is considered being connected straight to the
2550 target without any buffer. The FTDI pin is then switched between output and
2551 input as necessary to provide the full set of low, high and Hi-Z
2552 characteristics. In all other cases, the pins specified in a signal definition
2553 are always driven by the FTDI.
2555 If @option{-alias} or @option{-nalias} is used, the signal is created
2556 identical (or with data inverted) to an already specified signal
2560 @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
2561 Set a previously defined signal to the specified level.
2563 @item @option{0}, drive low
2564 @item @option{1}, drive high
2565 @item @option{z}, set to high-impedance
2569 @deffn {Command} {ftdi get_signal} name
2570 Get the value of a previously defined signal.
2573 @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
2574 Configure TCK edge at which the adapter samples the value of the TDO signal
2576 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2577 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2578 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2579 stability at higher JTAG clocks.
2581 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2582 @item @option{falling}, sample TDO on falling edge of TCK
2586 For example adapter definitions, see the configuration files shipped in the
2587 @file{interface/ftdi} directory.
2591 @deffn {Interface Driver} {ft232r}
2592 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2593 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2594 It currently doesn't support using CBUS pins as GPIO.
2596 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2603 @item DCD(10) - SRST
2606 User can change default pinout by supplying configuration
2607 commands with GPIO numbers or RS232 signal names.
2608 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2609 They differ from physical pin numbers.
2610 For details see actual FTDI chip datasheets.
2611 Every JTAG line must be configured to unique GPIO number
2612 different than any other JTAG line, even those lines
2613 that are sometimes not used like TRST or SRST.
2627 These interfaces have several commands, used to configure the driver
2628 before initializing the JTAG scan chain:
2630 @deffn {Config Command} {ft232r vid_pid} @var{vid} @var{pid}
2631 The vendor ID and product ID of the adapter. If not specified, default
2632 0x0403:0x6001 is used.
2635 @deffn {Config Command} {ft232r jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2636 Set four JTAG GPIO numbers at once.
2637 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2640 @deffn {Config Command} {ft232r tck_num} @var{tck}
2641 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2644 @deffn {Config Command} {ft232r tms_num} @var{tms}
2645 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2648 @deffn {Config Command} {ft232r tdi_num} @var{tdi}
2649 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2652 @deffn {Config Command} {ft232r tdo_num} @var{tdo}
2653 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2656 @deffn {Config Command} {ft232r trst_num} @var{trst}
2657 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2660 @deffn {Config Command} {ft232r srst_num} @var{srst}
2661 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2664 @deffn {Config Command} {ft232r restore_serial} @var{word}
2665 Restore serial port after JTAG. This USB bitmode control word
2666 (16-bit) will be sent before quit. Lower byte should
2667 set GPIO direction register to a "sane" state:
2668 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2669 byte is usually 0 to disable bitbang mode.
2670 When kernel driver reattaches, serial port should continue to work.
2671 Value 0xFFFF disables sending control word and serial port,
2672 then kernel driver will not reattach.
2673 If not specified, default 0xFFFF is used.
2678 @deffn {Interface Driver} {remote_bitbang}
2679 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2680 with a remote process and sends ASCII encoded bitbang requests to that process
2681 instead of directly driving JTAG.
2683 The remote_bitbang driver is useful for debugging software running on
2684 processors which are being simulated.
2686 @deffn {Config Command} {remote_bitbang port} number
2687 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2688 sockets instead of TCP.
2691 @deffn {Config Command} {remote_bitbang host} hostname
2692 Specifies the hostname of the remote process to connect to using TCP, or the
2693 name of the UNIX socket to use if remote_bitbang port is 0.
2696 For example, to connect remotely via TCP to the host foobar you might have
2700 adapter driver remote_bitbang
2701 remote_bitbang port 3335
2702 remote_bitbang host foobar
2705 To connect to another process running locally via UNIX sockets with socket
2709 adapter driver remote_bitbang
2710 remote_bitbang port 0
2711 remote_bitbang host mysocket
2715 @deffn {Interface Driver} {usb_blaster}
2716 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2717 for FTDI chips. These interfaces have several commands, used to
2718 configure the driver before initializing the JTAG scan chain:
2720 @deffn {Config Command} {usb_blaster vid_pid} vid pid
2721 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2722 default values are used.
2723 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2724 Altera USB-Blaster (default):
2726 usb_blaster vid_pid 0x09FB 0x6001
2728 The following VID/PID is for Kolja Waschk's USB JTAG:
2730 usb_blaster vid_pid 0x16C0 0x06AD
2734 @deffn {Command} {usb_blaster pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2735 Sets the state or function of the unused GPIO pins on USB-Blasters
2736 (pins 6 and 8 on the female JTAG header). These pins can be used as
2737 SRST and/or TRST provided the appropriate connections are made on the
2740 For example, to use pin 6 as SRST:
2742 usb_blaster pin pin6 s
2743 reset_config srst_only
2747 @deffn {Config Command} {usb_blaster lowlevel_driver} (@option{ftdi}|@option{ublast2})
2748 Chooses the low level access method for the adapter. If not specified,
2749 @option{ftdi} is selected unless it wasn't enabled during the
2750 configure stage. USB-Blaster II needs @option{ublast2}.
2753 @deffn {Config Command} {usb_blaster firmware} @var{path}
2754 This command specifies @var{path} to access USB-Blaster II firmware
2755 image. To be used with USB-Blaster II only.
2760 @deffn {Interface Driver} {gw16012}
2761 Gateworks GW16012 JTAG programmer.
2762 This has one driver-specific command:
2764 @deffn {Config Command} {parport port} [port_number]
2765 Display either the address of the I/O port
2766 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2767 If a parameter is provided, first switch to use that port.
2768 This is a write-once setting.
2772 @deffn {Interface Driver} {jlink}
2773 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2776 @quotation Compatibility Note
2777 SEGGER released many firmware versions for the many hardware versions they
2778 produced. OpenOCD was extensively tested and intended to run on all of them,
2779 but some combinations were reported as incompatible. As a general
2780 recommendation, it is advisable to use the latest firmware version
2781 available for each hardware version. However the current V8 is a moving
2782 target, and SEGGER firmware versions released after the OpenOCD was
2783 released may not be compatible. In such cases it is recommended to
2784 revert to the last known functional version. For 0.5.0, this is from
2785 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2786 version is from "May 3 2012 18:36:22", packed with 4.46f.
2789 @deffn {Command} {jlink hwstatus}
2790 Display various hardware related information, for example target voltage and pin
2793 @deffn {Command} {jlink freemem}
2794 Display free device internal memory.
2796 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2797 Set the JTAG command version to be used. Without argument, show the actual JTAG
2800 @deffn {Command} {jlink config}
2801 Display the device configuration.
2803 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2804 Set the target power state on JTAG-pin 19. Without argument, show the target
2807 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2808 Set the MAC address of the device. Without argument, show the MAC address.
2810 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2811 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2812 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2815 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2816 Set the USB address of the device. This will also change the USB Product ID
2817 (PID) of the device. Without argument, show the USB address.
2819 @deffn {Command} {jlink config reset}
2820 Reset the current configuration.
2822 @deffn {Command} {jlink config write}
2823 Write the current configuration to the internal persistent storage.
2825 @deffn {Command} {jlink emucom write} <channel> <data>
2826 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2829 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2830 the EMUCOM channel 0x10:
2832 > jlink emucom write 0x10 aa0b23
2835 @deffn {Command} {jlink emucom read} <channel> <length>
2836 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2839 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2841 > jlink emucom read 0x0 4
2845 @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
2846 Set the USB address of the interface, in case more than one adapter is connected
2847 to the host. If not specified, USB addresses are not considered. Device
2848 selection via USB address is not always unambiguous. It is recommended to use
2849 the serial number instead, if possible.
2851 As a configuration command, it can be used only before 'init'.
2855 @deffn {Interface Driver} {kitprog}
2856 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2857 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2858 families, but it is possible to use it with some other devices. If you are using
2859 this adapter with a PSoC or a PRoC, you may need to add
2860 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2861 configuration script.
2863 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2864 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2865 be used with this driver, and must either be used with the cmsis-dap driver or
2866 switched back to KitProg mode. See the Cypress KitProg User Guide for
2867 instructions on how to switch KitProg modes.
2871 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2873 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2874 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2875 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2876 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2877 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2878 SWD sequence must be sent after every target reset in order to re-establish
2879 communications with the target.
2880 @item Due in part to the limitation above, KitProg devices with firmware below
2881 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2882 communicate with PSoC 5LP devices. This is because, assuming debug is not
2883 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2884 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2885 could only be sent with an acquisition sequence.
2888 @deffn {Config Command} {kitprog_init_acquire_psoc}
2889 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2890 Please be aware that the acquisition sequence hard-resets the target.
2893 @deffn {Command} {kitprog acquire_psoc}
2894 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2895 outside of the target-specific configuration scripts since it hard-resets the
2896 target as a side-effect.
2897 This is necessary for "reset halt" on some PSoC 4 series devices.
2900 @deffn {Command} {kitprog info}
2901 Display various adapter information, such as the hardware version, firmware
2902 version, and target voltage.
2906 @deffn {Interface Driver} {parport}
2907 Supports PC parallel port bit-banging cables:
2908 Wigglers, PLD download cable, and more.
2909 These interfaces have several commands, used to configure the driver
2910 before initializing the JTAG scan chain:
2912 @deffn {Config Command} {parport cable} name
2913 Set the layout of the parallel port cable used to connect to the target.
2914 This is a write-once setting.
2915 Currently valid cable @var{name} values include:
2918 @item @b{altium} Altium Universal JTAG cable.
2919 @item @b{arm-jtag} Same as original wiggler except SRST and
2920 TRST connections reversed and TRST is also inverted.
2921 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2922 in configuration mode. This is only used to
2923 program the Chameleon itself, not a connected target.
2924 @item @b{dlc5} The Xilinx Parallel cable III.
2925 @item @b{flashlink} The ST Parallel cable.
2926 @item @b{lattice} Lattice ispDOWNLOAD Cable
2927 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2929 Amontec's Chameleon Programmer. The new version available from
2930 the website uses the original Wiggler layout ('@var{wiggler}')
2931 @item @b{triton} The parallel port adapter found on the
2932 ``Karo Triton 1 Development Board''.
2933 This is also the layout used by the HollyGates design
2934 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2935 @item @b{wiggler} The original Wiggler layout, also supported by
2936 several clones, such as the Olimex ARM-JTAG
2937 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2938 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2942 @deffn {Config Command} {parport port} [port_number]
2943 Display either the address of the I/O port
2944 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2945 If a parameter is provided, first switch to use that port.
2946 This is a write-once setting.
2948 When using PPDEV to access the parallel port, use the number of the parallel port:
2949 @option{parport port 0} (the default). If @option{parport port 0x378} is specified
2950 you may encounter a problem.
2953 @deffn {Config Command} {parport toggling_time} [nanoseconds]
2954 Displays how many nanoseconds the hardware needs to toggle TCK;
2955 the parport driver uses this value to obey the
2956 @command{adapter speed} configuration.
2957 When the optional @var{nanoseconds} parameter is given,
2958 that setting is changed before displaying the current value.
2960 The default setting should work reasonably well on commodity PC hardware.
2961 However, you may want to calibrate for your specific hardware.
2963 To measure the toggling time with a logic analyzer or a digital storage
2964 oscilloscope, follow the procedure below:
2966 > parport toggling_time 1000
2969 This sets the maximum JTAG clock speed of the hardware, but
2970 the actual speed probably deviates from the requested 500 kHz.
2971 Now, measure the time between the two closest spaced TCK transitions.
2972 You can use @command{runtest 1000} or something similar to generate a
2973 large set of samples.
2974 Update the setting to match your measurement:
2976 > parport toggling_time <measured nanoseconds>
2978 Now the clock speed will be a better match for @command{adapter speed}
2979 command given in OpenOCD scripts and event handlers.
2981 You can do something similar with many digital multimeters, but note
2982 that you'll probably need to run the clock continuously for several
2983 seconds before it decides what clock rate to show. Adjust the
2984 toggling time up or down until the measured clock rate is a good
2985 match with the rate you specified in the @command{adapter speed} command;
2990 @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
2991 This will configure the parallel driver to write a known
2992 cable-specific value to the parallel interface on exiting OpenOCD.
2995 For example, the interface configuration file for a
2996 classic ``Wiggler'' cable on LPT2 might look something like this:
2999 adapter driver parport
3001 parport cable wiggler
3005 @deffn {Interface Driver} {presto}
3006 ASIX PRESTO USB JTAG programmer.
3009 @deffn {Interface Driver} {rlink}
3010 Raisonance RLink USB adapter
3013 @deffn {Interface Driver} {usbprog}
3014 usbprog is a freely programmable USB adapter.
3017 @deffn {Interface Driver} {vsllink}
3018 vsllink is part of Versaloon which is a versatile USB programmer.
3021 This defines quite a few driver-specific commands,
3022 which are not currently documented here.
3026 @anchor{hla_interface}
3027 @deffn {Interface Driver} {hla}
3028 This is a driver that supports multiple High Level Adapters.
3029 This type of adapter does not expose some of the lower level api's
3030 that OpenOCD would normally use to access the target.
3032 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3033 and Nuvoton Nu-Link.
3034 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3035 versions of firmware where serial number is reset after first use. Suggest
3036 using ST firmware update utility to upgrade ST-LINK firmware even if current
3037 version reported is V2.J21.S4.
3039 @deffn {Config Command} {hla_device_desc} description
3040 Currently Not Supported.
3043 @deffn {Config Command} {hla_serial} serial
3044 Specifies the serial number of the adapter.
3047 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3048 Specifies the adapter layout to use.
3051 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3052 Pairs of vendor IDs and product IDs of the device.
3055 @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
3056 @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
3057 'shared' mode using ST-Link TCP server (the default port is 7184).
3059 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3060 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3061 ST-LINK server software module}.
3064 @deffn {Command} {hla_command} command
3065 Execute a custom adapter-specific command. The @var{command} string is
3066 passed as is to the underlying adapter layout handler.
3070 @anchor{st_link_dap_interface}
3071 @deffn {Interface Driver} {st-link}
3072 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3073 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3074 directly access the arm ADIv5 DAP.
3076 The new API provide access to multiple AP on the same DAP, but the
3077 maximum number of the AP port is limited by the specific firmware version
3078 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3079 An error is returned for any AP number above the maximum allowed value.
3081 @emph{Note:} Either these same adapters and their older versions are
3082 also supported by @ref{hla_interface, the hla interface driver}.
3084 @deffn {Config Command} {st-link backend} (usb | tcp [port])
3085 Choose between 'exclusive' USB communication (the default backend) or
3086 'shared' mode using ST-Link TCP server (the default port is 7184).
3088 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3089 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3090 ST-LINK server software module}.
3092 @emph{Note:} ST-Link TCP server does not support the SWIM transport.
3095 @deffn {Config Command} {st-link serial} serial
3096 Specifies the serial number of the adapter.
3099 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3100 Pairs of vendor IDs and product IDs of the device.
3103 @deffn {Command} {st-link cmd} rx_n (tx_byte)+
3104 Sends an arbitrary command composed by the sequence of bytes @var{tx_byte}
3105 and receives @var{rx_n} bytes.
3107 For example, the command to read the target's supply voltage is one byte 0xf7 followed
3108 by 15 bytes zero. It returns 8 bytes, where the first 4 bytes represent the ADC sampling
3109 of the reference voltage 1.2V and the last 4 bytes represent the ADC sampling of half
3110 the target's supply voltage.
3112 > st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3113 0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
3115 The result can be converted to Volts (ignoring the most significant bytes, always zero)
3117 > set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
3118 > echo [expr 2*1.2*([lindex $a 4]+256*[lindex $a 5])/([lindex $a 0]+256*[lindex $a 1])]
3124 @deffn {Interface Driver} {opendous}
3125 opendous-jtag is a freely programmable USB adapter.
3128 @deffn {Interface Driver} {ulink}
3129 This is the Keil ULINK v1 JTAG debugger.
3132 @deffn {Interface Driver} {xds110}
3133 The XDS110 is included as the embedded debug probe on many Texas Instruments
3134 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3135 debug probe with the added capability to supply power to the target board. The
3136 following commands are supported by the XDS110 driver:
3138 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3139 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3140 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3141 can be set to any value in the range 1800 to 3600 millivolts.
3144 @deffn {Command} {xds110 info}
3145 Displays information about the connected XDS110 debug probe (e.g. firmware
3150 @deffn {Interface Driver} {xlnx_pcie_xvc}
3151 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3152 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3153 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3154 exposed via extended capability registers in the PCI Express configuration space.
3156 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3158 @deffn {Config Command} {xlnx_pcie_xvc config} device
3159 Specifies the PCI Express device via parameter @var{device} to use.
3161 The correct value for @var{device} can be obtained by looking at the output
3162 of lscpi -D (first column) for the corresponding device.
3164 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3169 @deffn {Interface Driver} {bcm2835gpio}
3170 This SoC is present in Raspberry Pi which is a cheap single-board computer
3171 exposing some GPIOs on its expansion header.
3173 The driver accesses memory-mapped GPIO peripheral registers directly
3174 for maximum performance, but the only possible race condition is for
3175 the pins' modes/muxing (which is highly unlikely), so it should be
3176 able to coexist nicely with both sysfs bitbanging and various
3177 peripherals' kernel drivers. The driver restores the previous
3178 configuration on exit.
3180 GPIO numbers >= 32 can't be used for performance reasons.
3182 See @file{interface/raspberrypi-native.cfg} for a sample config and
3185 @deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3186 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3187 Must be specified to enable JTAG transport. These pins can also be specified
3191 @deffn {Config Command} {bcm2835gpio tck_num} @var{tck}
3192 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3193 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3196 @deffn {Config Command} {bcm2835gpio tms_num} @var{tms}
3197 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3198 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3201 @deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo}
3202 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3203 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3206 @deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi}
3207 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3208 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3211 @deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio}
3212 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3213 specified to enable SWD transport. These pins can also be specified individually.
3216 @deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk}
3217 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3218 specified using the configuration command @command{bcm2835gpio swd_nums}.
3221 @deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio}
3222 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3223 specified using the configuration command @command{bcm2835gpio swd_nums}.
3226 @deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir}
3227 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3228 to control the direction of an external buffer on the SWDIO pin (set=output
3229 mode, clear=input mode). If not specified, this feature is disabled.
3232 @deffn {Config Command} {bcm2835gpio srst_num} @var{srst}
3233 Set SRST GPIO number. Must be specified to enable SRST.
3236 @deffn {Config Command} {bcm2835gpio trst_num} @var{trst}
3237 Set TRST GPIO number. Must be specified to enable TRST.
3240 @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3241 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
3242 speed_coeff defaults to 113714, and speed_offset defaults to 28.
3245 @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
3246 Set the peripheral base register address to access GPIOs. For the RPi1, use
3247 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
3248 list can be found in the
3249 @uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}.
3254 @deffn {Interface Driver} {imx_gpio}
3255 i.MX SoC is present in many community boards. Wandboard is an example
3256 of the one which is most popular.
3258 This driver is mostly the same as bcm2835gpio.
3260 See @file{interface/imx-native.cfg} for a sample config and
3266 @deffn {Interface Driver} {linuxgpiod}
3267 Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6.
3268 The driver emulates either JTAG and SWD transport through bitbanging.
3270 See @file{interface/dln-2-gpiod.cfg} for a sample config.
3274 @deffn {Interface Driver} {sysfsgpio}
3275 Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
3276 Prefer using @b{linuxgpiod}, instead.
3278 See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
3282 @deffn {Interface Driver} {openjtag}
3283 OpenJTAG compatible USB adapter.
3284 This defines some driver-specific commands:
3286 @deffn {Config Command} {openjtag variant} variant
3287 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3288 Currently valid @var{variant} values include:
3291 @item @b{standard} Standard variant (default).
3292 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3293 (see @uref{http://www.cypress.com/?rID=82870}).
3297 @deffn {Config Command} {openjtag device_desc} string
3298 The USB device description string of the adapter.
3299 This value is only used with the standard variant.
3304 @deffn {Interface Driver} {jtag_dpi}
3305 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3306 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3307 DPI server interface.
3309 @deffn {Config Command} {jtag_dpi set_port} port
3310 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3313 @deffn {Config Command} {jtag_dpi set_address} address
3314 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3319 @deffn {Interface Driver} {buspirate}
3321 This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices.
3322 It uses a simple data protocol over a serial port connection.
3324 Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
3325 allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
3327 @deffn {Config Command} {buspirate port} serial_port
3328 Specify the serial port's filename. For example:
3330 buspirate port /dev/ttyUSB0
3334 @deffn {Config Command} {buspirate speed} (normal|fast)
3335 Set the communication speed to 115k (normal) or 1M (fast). For example:
3337 buspirate speed normal
3341 @deffn {Config Command} {buspirate mode} (normal|open-drain)
3342 Set the Bus Pirate output mode.
3344 @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
3345 @item In open drain mode, you will then need to enable the pull-ups.
3349 buspirate mode normal
3353 @deffn {Config Command} {buspirate pullup} (0|1)
3354 Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
3355 to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
3362 @deffn {Config Command} {buspirate vreg} (0|1)
3363 Whether to enable (1) or disable (0) the built-in voltage regulator,
3364 which can be used to supply power to a test circuit through
3365 I/O header pins +3V3 and +5V. For example:
3371 @deffn {Command} {buspirate led} (0|1)
3372 Turns the Bus Pirate's LED on (1) or off (0). For example:
3381 @section Transport Configuration
3383 As noted earlier, depending on the version of OpenOCD you use,
3384 and the debug adapter you are using,
3385 several transports may be available to
3386 communicate with debug targets (or perhaps to program flash memory).
3387 @deffn {Command} {transport list}
3388 displays the names of the transports supported by this
3392 @deffn {Command} {transport select} @option{transport_name}
3393 Select which of the supported transports to use in this OpenOCD session.
3395 When invoked with @option{transport_name}, attempts to select the named
3396 transport. The transport must be supported by the debug adapter
3397 hardware and by the version of OpenOCD you are using (including the
3400 If no transport has been selected and no @option{transport_name} is
3401 provided, @command{transport select} auto-selects the first transport
3402 supported by the debug adapter.
3404 @command{transport select} always returns the name of the session's selected
3408 @subsection JTAG Transport
3410 JTAG is the original transport supported by OpenOCD, and most
3411 of the OpenOCD commands support it.
3412 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3413 each of which must be explicitly declared.
3414 JTAG supports both debugging and boundary scan testing.
3415 Flash programming support is built on top of debug support.
3417 JTAG transport is selected with the command @command{transport select
3418 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3419 driver} (in which case the command is @command{transport select hla_jtag})
3420 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3421 the command is @command{transport select dapdirect_jtag}).
3423 @subsection SWD Transport
3425 @cindex Serial Wire Debug
3426 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3427 Debug Access Point (DAP, which must be explicitly declared.
3428 (SWD uses fewer signal wires than JTAG.)
3429 SWD is debug-oriented, and does not support boundary scan testing.
3430 Flash programming support is built on top of debug support.
3431 (Some processors support both JTAG and SWD.)
3433 SWD transport is selected with the command @command{transport select
3434 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3435 driver} (in which case the command is @command{transport select hla_swd})
3436 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3437 the command is @command{transport select dapdirect_swd}).
3439 @deffn {Config Command} {swd newdap} ...
3440 Declares a single DAP which uses SWD transport.
3441 Parameters are currently the same as "jtag newtap" but this is
3445 @subsection SPI Transport
3447 @cindex Serial Peripheral Interface
3448 The Serial Peripheral Interface (SPI) is a general purpose transport
3449 which uses four wire signaling. Some processors use it as part of a
3450 solution for flash programming.
3452 @anchor{swimtransport}
3453 @subsection SWIM Transport
3455 @cindex Single Wire Interface Module
3456 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3457 by the STMicroelectronics MCU family STM8 and documented in the
3458 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3460 SWIM does not support boundary scan testing nor multiple cores.
3462 The SWIM transport is selected with the command @command{transport select swim}.
3464 The concept of TAPs does not fit in the protocol since SWIM does not implement
3465 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3466 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3467 The TAP definition must precede the target definition command
3468 @command{target create target_name stm8 -chain-position basename.tap_type}.
3472 JTAG clock setup is part of system setup.
3473 It @emph{does not belong with interface setup} since any interface
3474 only knows a few of the constraints for the JTAG clock speed.
3475 Sometimes the JTAG speed is
3476 changed during the target initialization process: (1) slow at
3477 reset, (2) program the CPU clocks, (3) run fast.
3478 Both the "slow" and "fast" clock rates are functions of the
3479 oscillators used, the chip, the board design, and sometimes
3480 power management software that may be active.
3482 The speed used during reset, and the scan chain verification which
3483 follows reset, can be adjusted using a @code{reset-start}
3484 target event handler.
3485 It can then be reconfigured to a faster speed by a
3486 @code{reset-init} target event handler after it reprograms those
3487 CPU clocks, or manually (if something else, such as a boot loader,
3488 sets up those clocks).
3489 @xref{targetevents,,Target Events}.
3490 When the initial low JTAG speed is a chip characteristic, perhaps
3491 because of a required oscillator speed, provide such a handler
3492 in the target config file.
3493 When that speed is a function of a board-specific characteristic
3494 such as which speed oscillator is used, it belongs in the board
3495 config file instead.
3496 In both cases it's safest to also set the initial JTAG clock rate
3497 to that same slow speed, so that OpenOCD never starts up using a
3498 clock speed that's faster than the scan chain can support.
3502 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3505 If your system supports adaptive clocking (RTCK), configuring
3506 JTAG to use that is probably the most robust approach.
3507 However, it introduces delays to synchronize clocks; so it
3508 may not be the fastest solution.
3510 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3511 instead of @command{adapter speed}, but only for (ARM) cores and boards
3512 which support adaptive clocking.
3514 @deffn {Command} {adapter speed} max_speed_kHz
3515 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3516 JTAG interfaces usually support a limited number of
3517 speeds. The speed actually used won't be faster
3518 than the speed specified.
3520 Chip data sheets generally include a top JTAG clock rate.
3521 The actual rate is often a function of a CPU core clock,
3522 and is normally less than that peak rate.
3523 For example, most ARM cores accept at most one sixth of the CPU clock.
3525 Speed 0 (khz) selects RTCK method.
3526 @xref{faqrtck,,FAQ RTCK}.
3527 If your system uses RTCK, you won't need to change the
3528 JTAG clocking after setup.
3529 Not all interfaces, boards, or targets support ``rtck''.
3530 If the interface device can not
3531 support it, an error is returned when you try to use RTCK.
3534 @defun jtag_rclk fallback_speed_kHz
3535 @cindex adaptive clocking
3537 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3538 If that fails (maybe the interface, board, or target doesn't
3539 support it), falls back to the specified frequency.
3541 # Fall back to 3mhz if RTCK is not supported
3546 @node Reset Configuration
3547 @chapter Reset Configuration
3548 @cindex Reset Configuration
3550 Every system configuration may require a different reset
3551 configuration. This can also be quite confusing.
3552 Resets also interact with @var{reset-init} event handlers,
3553 which do things like setting up clocks and DRAM, and
3554 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3555 They can also interact with JTAG routers.
3556 Please see the various board files for examples.
3559 To maintainers and integrators:
3560 Reset configuration touches several things at once.
3561 Normally the board configuration file
3562 should define it and assume that the JTAG adapter supports
3563 everything that's wired up to the board's JTAG connector.
3565 However, the target configuration file could also make note
3566 of something the silicon vendor has done inside the chip,
3567 which will be true for most (or all) boards using that chip.
3568 And when the JTAG adapter doesn't support everything, the
3569 user configuration file will need to override parts of
3570 the reset configuration provided by other files.
3573 @section Types of Reset
3575 There are many kinds of reset possible through JTAG, but
3576 they may not all work with a given board and adapter.
3577 That's part of why reset configuration can be error prone.
3581 @emph{System Reset} ... the @emph{SRST} hardware signal
3582 resets all chips connected to the JTAG adapter, such as processors,
3583 power management chips, and I/O controllers. Normally resets triggered
3584 with this signal behave exactly like pressing a RESET button.
3586 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3587 just the TAP controllers connected to the JTAG adapter.
3588 Such resets should not be visible to the rest of the system; resetting a
3589 device's TAP controller just puts that controller into a known state.
3591 @emph{Emulation Reset} ... many devices can be reset through JTAG
3592 commands. These resets are often distinguishable from system
3593 resets, either explicitly (a "reset reason" register says so)
3594 or implicitly (not all parts of the chip get reset).
3596 @emph{Other Resets} ... system-on-chip devices often support
3597 several other types of reset.
3598 You may need to arrange that a watchdog timer stops
3599 while debugging, preventing a watchdog reset.
3600 There may be individual module resets.
3603 In the best case, OpenOCD can hold SRST, then reset
3604 the TAPs via TRST and send commands through JTAG to halt the
3605 CPU at the reset vector before the 1st instruction is executed.
3606 Then when it finally releases the SRST signal, the system is
3607 halted under debugger control before any code has executed.
3608 This is the behavior required to support the @command{reset halt}
3609 and @command{reset init} commands; after @command{reset init} a
3610 board-specific script might do things like setting up DRAM.
3611 (@xref{resetcommand,,Reset Command}.)
3613 @anchor{srstandtrstissues}
3614 @section SRST and TRST Issues
3616 Because SRST and TRST are hardware signals, they can have a
3617 variety of system-specific constraints. Some of the most
3622 @item @emph{Signal not available} ... Some boards don't wire
3623 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3624 support such signals even if they are wired up.
3625 Use the @command{reset_config} @var{signals} options to say
3626 when either of those signals is not connected.
3627 When SRST is not available, your code might not be able to rely
3628 on controllers having been fully reset during code startup.
3629 Missing TRST is not a problem, since JTAG-level resets can
3630 be triggered using with TMS signaling.
3632 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3633 adapter will connect SRST to TRST, instead of keeping them separate.
3634 Use the @command{reset_config} @var{combination} options to say
3635 when those signals aren't properly independent.
3637 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3638 delay circuit, reset supervisor, or on-chip features can extend
3639 the effect of a JTAG adapter's reset for some time after the adapter
3640 stops issuing the reset. For example, there may be chip or board
3641 requirements that all reset pulses last for at least a
3642 certain amount of time; and reset buttons commonly have
3643 hardware debouncing.
3644 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3645 commands to say when extra delays are needed.
3647 @item @emph{Drive type} ... Reset lines often have a pullup
3648 resistor, letting the JTAG interface treat them as open-drain
3649 signals. But that's not a requirement, so the adapter may need
3650 to use push/pull output drivers.
3651 Also, with weak pullups it may be advisable to drive
3652 signals to both levels (push/pull) to minimize rise times.
3653 Use the @command{reset_config} @var{trst_type} and
3654 @var{srst_type} parameters to say how to drive reset signals.
3656 @item @emph{Special initialization} ... Targets sometimes need
3657 special JTAG initialization sequences to handle chip-specific
3658 issues (not limited to errata).
3659 For example, certain JTAG commands might need to be issued while
3660 the system as a whole is in a reset state (SRST active)
3661 but the JTAG scan chain is usable (TRST inactive).
3662 Many systems treat combined assertion of SRST and TRST as a
3663 trigger for a harder reset than SRST alone.
3664 Such custom reset handling is discussed later in this chapter.
3667 There can also be other issues.
3668 Some devices don't fully conform to the JTAG specifications.
3669 Trivial system-specific differences are common, such as
3670 SRST and TRST using slightly different names.
3671 There are also vendors who distribute key JTAG documentation for
3672 their chips only to developers who have signed a Non-Disclosure
3675 Sometimes there are chip-specific extensions like a requirement to use
3676 the normally-optional TRST signal (precluding use of JTAG adapters which
3677 don't pass TRST through), or needing extra steps to complete a TAP reset.
3679 In short, SRST and especially TRST handling may be very finicky,
3680 needing to cope with both architecture and board specific constraints.
3682 @section Commands for Handling Resets
3684 @deffn {Command} {adapter srst pulse_width} milliseconds
3685 Minimum amount of time (in milliseconds) OpenOCD should wait
3686 after asserting nSRST (active-low system reset) before
3687 allowing it to be deasserted.
3690 @deffn {Command} {adapter srst delay} milliseconds
3691 How long (in milliseconds) OpenOCD should wait after deasserting
3692 nSRST (active-low system reset) before starting new JTAG operations.
3693 When a board has a reset button connected to SRST line it will
3694 probably have hardware debouncing, implying you should use this.
3697 @deffn {Command} {jtag_ntrst_assert_width} milliseconds
3698 Minimum amount of time (in milliseconds) OpenOCD should wait
3699 after asserting nTRST (active-low JTAG TAP reset) before
3700 allowing it to be deasserted.
3703 @deffn {Command} {jtag_ntrst_delay} milliseconds
3704 How long (in milliseconds) OpenOCD should wait after deasserting
3705 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3708 @anchor{reset_config}
3709 @deffn {Command} {reset_config} mode_flag ...
3710 This command displays or modifies the reset configuration
3711 of your combination of JTAG board and target in target
3712 configuration scripts.
3714 Information earlier in this section describes the kind of problems
3715 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3716 As a rule this command belongs only in board config files,
3717 describing issues like @emph{board doesn't connect TRST};
3718 or in user config files, addressing limitations derived
3719 from a particular combination of interface and board.
3720 (An unlikely example would be using a TRST-only adapter
3721 with a board that only wires up SRST.)
3723 The @var{mode_flag} options can be specified in any order, but only one
3724 of each type -- @var{signals}, @var{combination}, @var{gates},
3725 @var{trst_type}, @var{srst_type} and @var{connect_type}
3726 -- may be specified at a time.
3727 If you don't provide a new value for a given type, its previous
3728 value (perhaps the default) is unchanged.
3729 For example, this means that you don't need to say anything at all about
3730 TRST just to declare that if the JTAG adapter should want to drive SRST,
3731 it must explicitly be driven high (@option{srst_push_pull}).
3735 @var{signals} can specify which of the reset signals are connected.
3736 For example, If the JTAG interface provides SRST, but the board doesn't
3737 connect that signal properly, then OpenOCD can't use it.
3738 Possible values are @option{none} (the default), @option{trst_only},
3739 @option{srst_only} and @option{trst_and_srst}.
3742 If your board provides SRST and/or TRST through the JTAG connector,
3743 you must declare that so those signals can be used.
3747 The @var{combination} is an optional value specifying broken reset
3748 signal implementations.
3749 The default behaviour if no option given is @option{separate},
3750 indicating everything behaves normally.
3751 @option{srst_pulls_trst} states that the
3752 test logic is reset together with the reset of the system (e.g. NXP
3753 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3754 the system is reset together with the test logic (only hypothetical, I
3755 haven't seen hardware with such a bug, and can be worked around).
3756 @option{combined} implies both @option{srst_pulls_trst} and
3757 @option{trst_pulls_srst}.
3760 The @var{gates} tokens control flags that describe some cases where
3761 JTAG may be unavailable during reset.
3762 @option{srst_gates_jtag} (default)
3763 indicates that asserting SRST gates the
3764 JTAG clock. This means that no communication can happen on JTAG
3765 while SRST is asserted.
3766 Its converse is @option{srst_nogate}, indicating that JTAG commands
3767 can safely be issued while SRST is active.
3770 The @var{connect_type} tokens control flags that describe some cases where
3771 SRST is asserted while connecting to the target. @option{srst_nogate}
3772 is required to use this option.
3773 @option{connect_deassert_srst} (default)
3774 indicates that SRST will not be asserted while connecting to the target.
3775 Its converse is @option{connect_assert_srst}, indicating that SRST will
3776 be asserted before any target connection.
3777 Only some targets support this feature, STM32 and STR9 are examples.
3778 This feature is useful if you are unable to connect to your target due
3779 to incorrect options byte config or illegal program execution.
3782 The optional @var{trst_type} and @var{srst_type} parameters allow the
3783 driver mode of each reset line to be specified. These values only affect
3784 JTAG interfaces with support for different driver modes, like the Amontec
3785 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3786 relevant signal (TRST or SRST) is not connected.
3790 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3791 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3792 Most boards connect this signal to a pulldown, so the JTAG TAPs
3793 never leave reset unless they are hooked up to a JTAG adapter.
3796 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3797 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3798 Most boards connect this signal to a pullup, and allow the
3799 signal to be pulled low by various events including system
3800 power-up and pressing a reset button.
3804 @section Custom Reset Handling
3807 OpenOCD has several ways to help support the various reset
3808 mechanisms provided by chip and board vendors.
3809 The commands shown in the previous section give standard parameters.
3810 There are also @emph{event handlers} associated with TAPs or Targets.
3811 Those handlers are Tcl procedures you can provide, which are invoked
3812 at particular points in the reset sequence.
3814 @emph{When SRST is not an option} you must set
3815 up a @code{reset-assert} event handler for your target.
3816 For example, some JTAG adapters don't include the SRST signal;
3817 and some boards have multiple targets, and you won't always
3818 want to reset everything at once.
3820 After configuring those mechanisms, you might still
3821 find your board doesn't start up or reset correctly.
3822 For example, maybe it needs a slightly different sequence
3823 of SRST and/or TRST manipulations, because of quirks that
3824 the @command{reset_config} mechanism doesn't address;
3825 or asserting both might trigger a stronger reset, which
3826 needs special attention.
3828 Experiment with lower level operations, such as
3829 @command{adapter assert}, @command{adapter deassert}
3830 and the @command{jtag arp_*} operations shown here,
3831 to find a sequence of operations that works.
3832 @xref{JTAG Commands}.
3833 When you find a working sequence, it can be used to override
3834 @command{jtag_init}, which fires during OpenOCD startup
3835 (@pxref{configurationstage,,Configuration Stage});
3836 or @command{init_reset}, which fires during reset processing.
3838 You might also want to provide some project-specific reset
3839 schemes. For example, on a multi-target board the standard
3840 @command{reset} command would reset all targets, but you
3841 may need the ability to reset only one target at time and
3842 thus want to avoid using the board-wide SRST signal.
3844 @deffn {Overridable Procedure} {init_reset} mode
3845 This is invoked near the beginning of the @command{reset} command,
3846 usually to provide as much of a cold (power-up) reset as practical.
3847 By default it is also invoked from @command{jtag_init} if
3848 the scan chain does not respond to pure JTAG operations.
3849 The @var{mode} parameter is the parameter given to the
3850 low level reset command (@option{halt},
3851 @option{init}, or @option{run}), @option{setup},
3852 or potentially some other value.
3854 The default implementation just invokes @command{jtag arp_init-reset}.
3855 Replacements will normally build on low level JTAG
3856 operations such as @command{adapter assert} and @command{adapter deassert}.
3857 Operations here must not address individual TAPs
3858 (or their associated targets)
3859 until the JTAG scan chain has first been verified to work.
3861 Implementations must have verified the JTAG scan chain before
3863 This is done by calling @command{jtag arp_init}
3864 (or @command{jtag arp_init-reset}).
3867 @deffn {Command} {jtag arp_init}
3868 This validates the scan chain using just the four
3869 standard JTAG signals (TMS, TCK, TDI, TDO).
3870 It starts by issuing a JTAG-only reset.
3871 Then it performs checks to verify that the scan chain configuration
3872 matches the TAPs it can observe.
3873 Those checks include checking IDCODE values for each active TAP,
3874 and verifying the length of their instruction registers using
3875 TAP @code{-ircapture} and @code{-irmask} values.
3876 If these tests all pass, TAP @code{setup} events are
3877 issued to all TAPs with handlers for that event.
3880 @deffn {Command} {jtag arp_init-reset}
3881 This uses TRST and SRST to try resetting
3882 everything on the JTAG scan chain
3883 (and anything else connected to SRST).
3884 It then invokes the logic of @command{jtag arp_init}.
3888 @node TAP Declaration
3889 @chapter TAP Declaration
3890 @cindex TAP declaration
3891 @cindex TAP configuration
3893 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3894 TAPs serve many roles, including:
3897 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3898 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3899 Others do it indirectly, making a CPU do it.
3900 @item @b{Program Download} Using the same CPU support GDB uses,
3901 you can initialize a DRAM controller, download code to DRAM, and then
3902 start running that code.
3903 @item @b{Boundary Scan} Most chips support boundary scan, which
3904 helps test for board assembly problems like solder bridges
3905 and missing connections.
3908 OpenOCD must know about the active TAPs on your board(s).
3909 Setting up the TAPs is the core task of your configuration files.
3910 Once those TAPs are set up, you can pass their names to code
3911 which sets up CPUs and exports them as GDB targets,
3912 probes flash memory, performs low-level JTAG operations, and more.
3914 @section Scan Chains
3917 TAPs are part of a hardware @dfn{scan chain},
3918 which is a daisy chain of TAPs.
3919 They also need to be added to
3920 OpenOCD's software mirror of that hardware list,
3921 giving each member a name and associating other data with it.
3922 Simple scan chains, with a single TAP, are common in
3923 systems with a single microcontroller or microprocessor.
3924 More complex chips may have several TAPs internally.
3925 Very complex scan chains might have a dozen or more TAPs:
3926 several in one chip, more in the next, and connecting
3927 to other boards with their own chips and TAPs.
3929 You can display the list with the @command{scan_chain} command.
3930 (Don't confuse this with the list displayed by the @command{targets}
3931 command, presented in the next chapter.
3932 That only displays TAPs for CPUs which are configured as
3934 Here's what the scan chain might look like for a chip more than one TAP:
3937 TapName Enabled IdCode Expected IrLen IrCap IrMask
3938 -- ------------------ ------- ---------- ---------- ----- ----- ------
3939 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3940 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3941 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3944 OpenOCD can detect some of that information, but not all
3945 of it. @xref{autoprobing,,Autoprobing}.
3946 Unfortunately, those TAPs can't always be autoconfigured,
3947 because not all devices provide good support for that.
3948 JTAG doesn't require supporting IDCODE instructions, and
3949 chips with JTAG routers may not link TAPs into the chain
3950 until they are told to do so.
3952 The configuration mechanism currently supported by OpenOCD
3953 requires explicit configuration of all TAP devices using
3954 @command{jtag newtap} commands, as detailed later in this chapter.
3955 A command like this would declare one tap and name it @code{chip1.cpu}:
3958 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3961 Each target configuration file lists the TAPs provided
3963 Board configuration files combine all the targets on a board,
3965 Note that @emph{the order in which TAPs are declared is very important.}
3966 That declaration order must match the order in the JTAG scan chain,
3967 both inside a single chip and between them.
3968 @xref{faqtaporder,,FAQ TAP Order}.
3970 For example, the STMicroelectronics STR912 chip has
3971 three separate TAPs@footnote{See the ST
3972 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3973 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3974 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3975 To configure those taps, @file{target/str912.cfg}
3976 includes commands something like this:
3979 jtag newtap str912 flash ... params ...
3980 jtag newtap str912 cpu ... params ...
3981 jtag newtap str912 bs ... params ...
3984 Actual config files typically use a variable such as @code{$_CHIPNAME}
3985 instead of literals like @option{str912}, to support more than one chip
3986 of each type. @xref{Config File Guidelines}.
3988 @deffn {Command} {jtag names}
3989 Returns the names of all current TAPs in the scan chain.
3990 Use @command{jtag cget} or @command{jtag tapisenabled}
3991 to examine attributes and state of each TAP.
3993 foreach t [jtag names] @{
3994 puts [format "TAP: %s\n" $t]
3999 @deffn {Command} {scan_chain}
4000 Displays the TAPs in the scan chain configuration,
4002 The set of TAPs listed by this command is fixed by
4003 exiting the OpenOCD configuration stage,
4004 but systems with a JTAG router can
4005 enable or disable TAPs dynamically.
4008 @c FIXME! "jtag cget" should be able to return all TAP
4009 @c attributes, like "$target_name cget" does for targets.
4011 @c Probably want "jtag eventlist", and a "tap-reset" event
4012 @c (on entry to RESET state).
4017 When TAP objects are declared with @command{jtag newtap},
4018 a @dfn{dotted.name} is created for the TAP, combining the
4019 name of a module (usually a chip) and a label for the TAP.
4020 For example: @code{xilinx.tap}, @code{str912.flash},
4021 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
4022 Many other commands use that dotted.name to manipulate or
4023 refer to the TAP. For example, CPU configuration uses the
4024 name, as does declaration of NAND or NOR flash banks.
4026 The components of a dotted name should follow ``C'' symbol
4027 name rules: start with an alphabetic character, then numbers
4028 and underscores are OK; while others (including dots!) are not.
4030 @section TAP Declaration Commands
4032 @deffn {Config Command} {jtag newtap} chipname tapname configparams...
4033 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
4034 and configured according to the various @var{configparams}.
4036 The @var{chipname} is a symbolic name for the chip.
4037 Conventionally target config files use @code{$_CHIPNAME},
4038 defaulting to the model name given by the chip vendor but
4041 @cindex TAP naming convention
4042 The @var{tapname} reflects the role of that TAP,
4043 and should follow this convention:
4046 @item @code{bs} -- For boundary scan if this is a separate TAP;
4047 @item @code{cpu} -- The main CPU of the chip, alternatively
4048 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
4049 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
4050 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
4051 @item @code{flash} -- If the chip has a flash TAP, like the str912;
4052 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
4053 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
4054 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
4056 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
4057 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
4058 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
4059 a JTAG TAP; that TAP should be named @code{sdma}.
4062 Every TAP requires at least the following @var{configparams}:
4065 @item @code{-irlen} @var{NUMBER}
4066 @*The length in bits of the
4067 instruction register, such as 4 or 5 bits.
4070 A TAP may also provide optional @var{configparams}:
4073 @item @code{-disable} (or @code{-enable})
4074 @*Use the @code{-disable} parameter to flag a TAP which is not
4075 linked into the scan chain after a reset using either TRST
4076 or the JTAG state machine's @sc{reset} state.
4077 You may use @code{-enable} to highlight the default state
4078 (the TAP is linked in).
4079 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
4080 @item @code{-expected-id} @var{NUMBER}
4081 @*A non-zero @var{number} represents a 32-bit IDCODE
4082 which you expect to find when the scan chain is examined.
4083 These codes are not required by all JTAG devices.
4084 @emph{Repeat the option} as many times as required if more than one
4085 ID code could appear (for example, multiple versions).
4086 Specify @var{number} as zero to suppress warnings about IDCODE
4087 values that were found but not included in the list.
4089 Provide this value if at all possible, since it lets OpenOCD
4090 tell when the scan chain it sees isn't right. These values
4091 are provided in vendors' chip documentation, usually a technical
4092 reference manual. Sometimes you may need to probe the JTAG
4093 hardware to find these values.
4094 @xref{autoprobing,,Autoprobing}.
4095 @item @code{-ignore-version}
4096 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
4097 option. When vendors put out multiple versions of a chip, or use the same
4098 JTAG-level ID for several largely-compatible chips, it may be more practical
4099 to ignore the version field than to update config files to handle all of
4100 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
4101 @item @code{-ircapture} @var{NUMBER}
4102 @*The bit pattern loaded by the TAP into the JTAG shift register
4103 on entry to the @sc{ircapture} state, such as 0x01.
4104 JTAG requires the two LSBs of this value to be 01.
4105 By default, @code{-ircapture} and @code{-irmask} are set
4106 up to verify that two-bit value. You may provide
4107 additional bits if you know them, or indicate that
4108 a TAP doesn't conform to the JTAG specification.
4109 @item @code{-irmask} @var{NUMBER}
4110 @*A mask used with @code{-ircapture}
4111 to verify that instruction scans work correctly.
4112 Such scans are not used by OpenOCD except to verify that
4113 there seems to be no problems with JTAG scan chain operations.
4114 @item @code{-ignore-syspwrupack}
4115 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4116 register during initial examination and when checking the sticky error bit.
4117 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4118 devices do not set the ack bit until sometime later.
4122 @section Other TAP commands
4124 @deffn {Command} {jtag cget} dotted.name @option{-idcode}
4125 Get the value of the IDCODE found in hardware.
4128 @deffn {Command} {jtag cget} dotted.name @option{-event} event_name
4129 @deffnx {Command} {jtag configure} dotted.name @option{-event} event_name handler
4130 At this writing this TAP attribute
4131 mechanism is limited and used mostly for event handling.
4132 (It is not a direct analogue of the @code{cget}/@code{configure}
4133 mechanism for debugger targets.)
4134 See the next section for information about the available events.
4136 The @code{configure} subcommand assigns an event handler,
4137 a TCL string which is evaluated when the event is triggered.
4138 The @code{cget} subcommand returns that handler.
4145 OpenOCD includes two event mechanisms.
4146 The one presented here applies to all JTAG TAPs.
4147 The other applies to debugger targets,
4148 which are associated with certain TAPs.
4150 The TAP events currently defined are:
4153 @item @b{post-reset}
4154 @* The TAP has just completed a JTAG reset.
4155 The tap may still be in the JTAG @sc{reset} state.
4156 Handlers for these events might perform initialization sequences
4157 such as issuing TCK cycles, TMS sequences to ensure
4158 exit from the ARM SWD mode, and more.
4160 Because the scan chain has not yet been verified, handlers for these events
4161 @emph{should not issue commands which scan the JTAG IR or DR registers}
4162 of any particular target.
4163 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
4165 @* The scan chain has been reset and verified.
4166 This handler may enable TAPs as needed.
4167 @item @b{tap-disable}
4168 @* The TAP needs to be disabled. This handler should
4169 implement @command{jtag tapdisable}
4170 by issuing the relevant JTAG commands.
4171 @item @b{tap-enable}
4172 @* The TAP needs to be enabled. This handler should
4173 implement @command{jtag tapenable}
4174 by issuing the relevant JTAG commands.
4177 If you need some action after each JTAG reset which isn't actually
4178 specific to any TAP (since you can't yet trust the scan chain's
4179 contents to be accurate), you might:
4182 jtag configure CHIP.jrc -event post-reset @{
4183 echo "JTAG Reset done"
4184 ... non-scan jtag operations to be done after reset
4189 @anchor{enablinganddisablingtaps}
4190 @section Enabling and Disabling TAPs
4191 @cindex JTAG Route Controller
4194 In some systems, a @dfn{JTAG Route Controller} (JRC)
4195 is used to enable and/or disable specific JTAG TAPs.
4196 Many ARM-based chips from Texas Instruments include
4197 an ``ICEPick'' module, which is a JRC.
4198 Such chips include DaVinci and OMAP3 processors.
4200 A given TAP may not be visible until the JRC has been
4201 told to link it into the scan chain; and if the JRC
4202 has been told to unlink that TAP, it will no longer
4204 Such routers address problems that JTAG ``bypass mode''
4208 @item The scan chain can only go as fast as its slowest TAP.
4209 @item Having many TAPs slows instruction scans, since all
4210 TAPs receive new instructions.
4211 @item TAPs in the scan chain must be powered up, which wastes
4212 power and prevents debugging some power management mechanisms.
4215 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4216 as implied by the existence of JTAG routers.
4217 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4218 does include a kind of JTAG router functionality.
4220 @c (a) currently the event handlers don't seem to be able to
4221 @c fail in a way that could lead to no-change-of-state.
4223 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4224 shown below, and is implemented using TAP event handlers.
4225 So for example, when defining a TAP for a CPU connected to
4226 a JTAG router, your @file{target.cfg} file
4227 should define TAP event handlers using
4228 code that looks something like this:
4231 jtag configure CHIP.cpu -event tap-enable @{
4232 ... jtag operations using CHIP.jrc
4234 jtag configure CHIP.cpu -event tap-disable @{
4235 ... jtag operations using CHIP.jrc
4239 Then you might want that CPU's TAP enabled almost all the time:
4242 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4245 Note how that particular setup event handler declaration
4246 uses quotes to evaluate @code{$CHIP} when the event is configured.
4247 Using brackets @{ @} would cause it to be evaluated later,
4248 at runtime, when it might have a different value.
4250 @deffn {Command} {jtag tapdisable} dotted.name
4251 If necessary, disables the tap
4252 by sending it a @option{tap-disable} event.
4253 Returns the string "1" if the tap
4254 specified by @var{dotted.name} is enabled,
4255 and "0" if it is disabled.
4258 @deffn {Command} {jtag tapenable} dotted.name
4259 If necessary, enables the tap
4260 by sending it a @option{tap-enable} event.
4261 Returns the string "1" if the tap
4262 specified by @var{dotted.name} is enabled,
4263 and "0" if it is disabled.
4266 @deffn {Command} {jtag tapisenabled} dotted.name
4267 Returns the string "1" if the tap
4268 specified by @var{dotted.name} is enabled,
4269 and "0" if it is disabled.
4272 Humans will find the @command{scan_chain} command more helpful
4273 for querying the state of the JTAG taps.
4277 @anchor{autoprobing}
4278 @section Autoprobing
4280 @cindex JTAG autoprobe
4282 TAP configuration is the first thing that needs to be done
4283 after interface and reset configuration. Sometimes it's
4284 hard finding out what TAPs exist, or how they are identified.
4285 Vendor documentation is not always easy to find and use.
4287 To help you get past such problems, OpenOCD has a limited
4288 @emph{autoprobing} ability to look at the scan chain, doing
4289 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4290 To use this mechanism, start the OpenOCD server with only data
4291 that configures your JTAG interface, and arranges to come up
4292 with a slow clock (many devices don't support fast JTAG clocks
4293 right when they come out of reset).
4295 For example, your @file{openocd.cfg} file might have:
4298 source [find interface/olimex-arm-usb-tiny-h.cfg]
4299 reset_config trst_and_srst
4303 When you start the server without any TAPs configured, it will
4304 attempt to autoconfigure the TAPs. There are two parts to this:
4307 @item @emph{TAP discovery} ...
4308 After a JTAG reset (sometimes a system reset may be needed too),
4309 each TAP's data registers will hold the contents of either the
4310 IDCODE or BYPASS register.
4311 If JTAG communication is working, OpenOCD will see each TAP,
4312 and report what @option{-expected-id} to use with it.
4313 @item @emph{IR Length discovery} ...
4314 Unfortunately JTAG does not provide a reliable way to find out
4315 the value of the @option{-irlen} parameter to use with a TAP
4317 If OpenOCD can discover the length of a TAP's instruction
4318 register, it will report it.
4319 Otherwise you may need to consult vendor documentation, such
4320 as chip data sheets or BSDL files.
4323 In many cases your board will have a simple scan chain with just
4324 a single device. Here's what OpenOCD reported with one board
4325 that's a bit more complex:
4329 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4330 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4331 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4332 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4333 AUTO auto0.tap - use "... -irlen 4"
4334 AUTO auto1.tap - use "... -irlen 4"
4335 AUTO auto2.tap - use "... -irlen 6"
4336 no gdb ports allocated as no target has been specified
4339 Given that information, you should be able to either find some existing
4340 config files to use, or create your own. If you create your own, you
4341 would configure from the bottom up: first a @file{target.cfg} file
4342 with these TAPs, any targets associated with them, and any on-chip
4343 resources; then a @file{board.cfg} with off-chip resources, clocking,
4346 @anchor{dapdeclaration}
4347 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4348 @cindex DAP declaration
4350 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4351 no longer implicitly created together with the target. It must be
4352 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4353 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4354 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4356 The @command{dap} command group supports the following sub-commands:
4358 @deffn {Command} {dap create} dap_name @option{-chain-position} dotted.name configparams...
4359 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4360 @var{dotted.name}. This also creates a new command (@command{dap_name})
4361 which is used for various purposes including additional configuration.
4362 There can only be one DAP for each JTAG tap in the system.
4364 A DAP may also provide optional @var{configparams}:
4367 @item @code{-ignore-syspwrupack}
4368 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4369 register during initial examination and when checking the sticky error bit.
4370 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4371 devices do not set the ack bit until sometime later.
4373 @item @code{-dp-id} @var{number}
4374 @*Debug port identification number for SWD DPv2 multidrop.
4375 The @var{number} is written to bits 0..27 of DP TARGETSEL during DP selection.
4376 To find the id number of a single connected device read DP TARGETID:
4377 @code{device.dap dpreg 0x24}
4378 Use bits 0..27 of TARGETID.
4380 @item @code{-instance-id} @var{number}
4381 @*Instance identification number for SWD DPv2 multidrop.
4382 The @var{number} is written to bits 28..31 of DP TARGETSEL during DP selection.
4383 To find the instance number of a single connected device read DP DLPIDR:
4384 @code{device.dap dpreg 0x34}
4385 The instance number is in bits 28..31 of DLPIDR value.
4389 @deffn {Command} {dap names}
4390 This command returns a list of all registered DAP objects. It it useful mainly
4394 @deffn {Command} {dap info} [num]
4395 Displays the ROM table for MEM-AP @var{num},
4396 defaulting to the currently selected AP of the currently selected target.
4399 @deffn {Command} {dap init}
4400 Initialize all registered DAPs. This command is used internally
4401 during initialization. It can be issued at any time after the
4402 initialization, too.
4405 The following commands exist as subcommands of DAP instances:
4407 @deffn {Command} {$dap_name info} [num]
4408 Displays the ROM table for MEM-AP @var{num},
4409 defaulting to the currently selected AP.
4412 @deffn {Command} {$dap_name apid} [num]
4413 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4416 @anchor{DAP subcommand apreg}
4417 @deffn {Command} {$dap_name apreg} ap_num reg [value]
4418 Displays content of a register @var{reg} from AP @var{ap_num}
4419 or set a new value @var{value}.
4420 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4423 @deffn {Command} {$dap_name apsel} [num]
4424 Select AP @var{num}, defaulting to 0.
4427 @deffn {Command} {$dap_name dpreg} reg [value]
4428 Displays the content of DP register at address @var{reg}, or set it to a new
4431 In case of SWD, @var{reg} is a value in packed format
4432 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4433 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4435 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4436 background activity by OpenOCD while you are operating at such low-level.
4439 @deffn {Command} {$dap_name baseaddr} [num]
4440 Displays debug base address from MEM-AP @var{num},
4441 defaulting to the currently selected AP.
4444 @deffn {Command} {$dap_name memaccess} [value]
4445 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4446 memory bus access [0-255], giving additional time to respond to reads.
4447 If @var{value} is defined, first assigns that.
4450 @deffn {Command} {$dap_name apcsw} [value [mask]]
4451 Displays or changes CSW bit pattern for MEM-AP transfers.
4453 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4454 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4455 and the result is written to the real CSW register. All bits except dynamically
4456 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4457 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4460 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4461 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4464 kx.dap apcsw 0x2000000
4467 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4468 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4469 and leaves the rest of the pattern intact. It configures memory access through
4470 DCache on Cortex-M7.
4472 set CSW_HPROT3_CACHEABLE [expr 1 << 27]
4473 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4476 Another example clears SPROT bit and leaves the rest of pattern intact:
4478 set CSW_SPROT [expr 1 << 30]
4479 samv.dap apcsw 0 $CSW_SPROT
4482 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4483 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4485 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4486 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4487 example with a proper dap name:
4489 xxx.dap apcsw default
4493 @deffn {Config Command} {$dap_name ti_be_32_quirks} [@option{enable}]
4494 Set/get quirks mode for TI TMS450/TMS570 processors
4499 @node CPU Configuration
4500 @chapter CPU Configuration
4503 This chapter discusses how to set up GDB debug targets for CPUs.
4504 You can also access these targets without GDB
4505 (@pxref{Architecture and Core Commands},
4506 and @ref{targetstatehandling,,Target State handling}) and
4507 through various kinds of NAND and NOR flash commands.
4508 If you have multiple CPUs you can have multiple such targets.
4510 We'll start by looking at how to examine the targets you have,
4511 then look at how to add one more target and how to configure it.
4513 @section Target List
4514 @cindex target, current
4515 @cindex target, list
4517 All targets that have been set up are part of a list,
4518 where each member has a name.
4519 That name should normally be the same as the TAP name.
4520 You can display the list with the @command{targets}
4522 This display often has only one CPU; here's what it might
4523 look like with more than one:
4525 TargetName Type Endian TapName State
4526 -- ------------------ ---------- ------ ------------------ ------------
4527 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4528 1 MyTarget cortex_m little mychip.foo tap-disabled
4531 One member of that list is the @dfn{current target}, which
4532 is implicitly referenced by many commands.
4533 It's the one marked with a @code{*} near the target name.
4534 In particular, memory addresses often refer to the address
4535 space seen by that current target.
4536 Commands like @command{mdw} (memory display words)
4537 and @command{flash erase_address} (erase NOR flash blocks)
4538 are examples; and there are many more.
4540 Several commands let you examine the list of targets:
4542 @deffn {Command} {target current}
4543 Returns the name of the current target.
4546 @deffn {Command} {target names}
4547 Lists the names of all current targets in the list.
4549 foreach t [target names] @{
4550 puts [format "Target: %s\n" $t]
4555 @c yep, "target list" would have been better.
4556 @c plus maybe "target setdefault".
4558 @deffn {Command} {targets} [name]
4559 @emph{Note: the name of this command is plural. Other target
4560 command names are singular.}
4562 With no parameter, this command displays a table of all known
4563 targets in a user friendly form.
4565 With a parameter, this command sets the current target to
4566 the given target with the given @var{name}; this is
4567 only relevant on boards which have more than one target.
4570 @section Target CPU Types
4574 Each target has a @dfn{CPU type}, as shown in the output of
4575 the @command{targets} command. You need to specify that type
4576 when calling @command{target create}.
4577 The CPU type indicates more than just the instruction set.
4578 It also indicates how that instruction set is implemented,
4579 what kind of debug support it integrates,
4580 whether it has an MMU (and if so, what kind),
4581 what core-specific commands may be available
4582 (@pxref{Architecture and Core Commands}),
4585 It's easy to see what target types are supported,
4586 since there's a command to list them.
4588 @anchor{targettypes}
4589 @deffn {Command} {target types}
4590 Lists all supported target types.
4591 At this writing, the supported CPU types are:
4594 @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
4595 @item @code{arm11} -- this is a generation of ARMv6 cores.
4596 @item @code{arm720t} -- this is an ARMv4 core with an MMU.
4597 @item @code{arm7tdmi} -- this is an ARMv4 core.
4598 @item @code{arm920t} -- this is an ARMv4 core with an MMU.
4599 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
4600 @item @code{arm946e} -- this is an ARMv5 core with an MMU.
4601 @item @code{arm966e} -- this is an ARMv5 core.
4602 @item @code{arm9tdmi} -- this is an ARMv4 core.
4603 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4604 (Support for this is preliminary and incomplete.)
4605 @item @code{avr32_ap7k} -- this an AVR32 core.
4606 @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
4607 @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
4608 compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
4609 @item @code{cortex_r4} -- this is an ARMv7-R core.
4610 @item @code{dragonite} -- resembles arm966e.
4611 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4612 (Support for this is still incomplete.)
4613 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
4614 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4615 The current implementation supports eSi-32xx cores.
4616 @item @code{fa526} -- resembles arm920 (w/o Thumb).
4617 @item @code{feroceon} -- resembles arm926.
4618 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
4619 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4620 allowing access to physical memory addresses independently of CPU cores.
4621 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without
4622 a CPU, through which bus read and write cycles can be generated; it may be
4623 useful for working with non-CPU hardware behind an AP or during development of
4624 support for new CPUs.
4625 It's possible to connect a GDB client to this target (the GDB port has to be
4626 specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
4627 be emulated to comply to GDB remote protocol.
4628 @item @code{mips_m4k} -- a MIPS core.
4629 @item @code{mips_mips64} -- a MIPS64 core.
4630 @item @code{nds32_v2} -- this is an Andes NDS32 v2 core.
4631 @item @code{nds32_v3} -- this is an Andes NDS32 v3 core.
4632 @item @code{nds32_v3m} -- this is an Andes NDS32 v3m core.
4633 @item @code{or1k} -- this is an OpenRISC 1000 core.
4634 The current implementation supports three JTAG TAP cores:
4636 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4637 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4638 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4640 And two debug interfaces cores:
4642 @item @code{Advanced debug interface}
4643 @*(See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4644 @item @code{SoC Debug Interface}
4645 @*(See: @url{http://opencores.org/project@comma{}dbg_interface})
4647 @item @code{quark_d20xx} -- an Intel Quark D20xx core.
4648 @item @code{quark_x10xx} -- an Intel Quark X10xx core.
4649 @item @code{riscv} -- a RISC-V core.
4650 @item @code{stm8} -- implements an STM8 core.
4651 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
4652 @item @code{xscale} -- this is actually an architecture,
4653 not a CPU type. It is based on the ARMv5 architecture.
4657 To avoid being confused by the variety of ARM based cores, remember
4658 this key point: @emph{ARM is a technology licencing company}.
4659 (See: @url{http://www.arm.com}.)
4660 The CPU name used by OpenOCD will reflect the CPU design that was
4661 licensed, not a vendor brand which incorporates that design.
4662 Name prefixes like arm7, arm9, arm11, and cortex
4663 reflect design generations;
4664 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4665 reflect an architecture version implemented by a CPU design.
4667 @anchor{targetconfiguration}
4668 @section Target Configuration
4670 Before creating a ``target'', you must have added its TAP to the scan chain.
4671 When you've added that TAP, you will have a @code{dotted.name}
4672 which is used to set up the CPU support.
4673 The chip-specific configuration file will normally configure its CPU(s)
4674 right after it adds all of the chip's TAPs to the scan chain.
4676 Although you can set up a target in one step, it's often clearer if you
4677 use shorter commands and do it in two steps: create it, then configure
4679 All operations on the target after it's created will use a new
4680 command, created as part of target creation.
4682 The two main things to configure after target creation are
4683 a work area, which usually has target-specific defaults even
4684 if the board setup code overrides them later;
4685 and event handlers (@pxref{targetevents,,Target Events}), which tend
4686 to be much more board-specific.
4687 The key steps you use might look something like this
4690 dap create mychip.dap -chain-position mychip.cpu
4691 target create MyTarget cortex_m -dap mychip.dap
4692 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4693 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4694 MyTarget configure -event reset-init @{ myboard_reinit @}
4697 You should specify a working area if you can; typically it uses some
4699 Such a working area can speed up many things, including bulk
4700 writes to target memory;
4701 flash operations like checking to see if memory needs to be erased;
4702 GDB memory checksumming;
4706 On more complex chips, the work area can become
4707 inaccessible when application code
4708 (such as an operating system)
4709 enables or disables the MMU.
4710 For example, the particular MMU context used to access the virtual
4711 address will probably matter ... and that context might not have
4712 easy access to other addresses needed.
4713 At this writing, OpenOCD doesn't have much MMU intelligence.
4716 It's often very useful to define a @code{reset-init} event handler.
4717 For systems that are normally used with a boot loader,
4718 common tasks include updating clocks and initializing memory
4720 That may be needed to let you write the boot loader into flash,
4721 in order to ``de-brick'' your board; or to load programs into
4722 external DDR memory without having run the boot loader.
4724 @deffn {Config Command} {target create} target_name type configparams...
4725 This command creates a GDB debug target that refers to a specific JTAG tap.
4726 It enters that target into a list, and creates a new
4727 command (@command{@var{target_name}}) which is used for various
4728 purposes including additional configuration.
4731 @item @var{target_name} ... is the name of the debug target.
4732 By convention this should be the same as the @emph{dotted.name}
4733 of the TAP associated with this target, which must be specified here
4734 using the @code{-chain-position @var{dotted.name}} configparam.
4736 This name is also used to create the target object command,
4737 referred to here as @command{$target_name},
4738 and in other places the target needs to be identified.
4739 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4740 @item @var{configparams} ... all parameters accepted by
4741 @command{$target_name configure} are permitted.
4742 If the target is big-endian, set it here with @code{-endian big}.
4744 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4745 @code{-dap @var{dap_name}} here.
4749 @deffn {Command} {$target_name configure} configparams...
4750 The options accepted by this command may also be
4751 specified as parameters to @command{target create}.
4752 Their values can later be queried one at a time by
4753 using the @command{$target_name cget} command.
4755 @emph{Warning:} changing some of these after setup is dangerous.
4756 For example, moving a target from one TAP to another;
4757 and changing its endianness.
4761 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4762 used to access this target.
4764 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4765 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4766 create and manage DAP instances.
4768 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4769 whether the CPU uses big or little endian conventions
4771 @item @code{-event} @var{event_name} @var{event_body} --
4772 @xref{targetevents,,Target Events}.
4773 Note that this updates a list of named event handlers.
4774 Calling this twice with two different event names assigns
4775 two different handlers, but calling it twice with the
4776 same event name assigns only one handler.
4778 Current target is temporarily overridden to the event issuing target
4779 before handler code starts and switched back after handler is done.
4781 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4782 whether the work area gets backed up; by default,
4783 @emph{it is not backed up.}
4784 When possible, use a working_area that doesn't need to be backed up,
4785 since performing a backup slows down operations.
4786 For example, the beginning of an SRAM block is likely to
4787 be used by most build systems, but the end is often unused.
4789 @item @code{-work-area-size} @var{size} -- specify work are size,
4790 in bytes. The same size applies regardless of whether its physical
4791 or virtual address is being used.
4793 @item @code{-work-area-phys} @var{address} -- set the work area
4794 base @var{address} to be used when no MMU is active.
4796 @item @code{-work-area-virt} @var{address} -- set the work area
4797 base @var{address} to be used when an MMU is active.
4798 @emph{Do not specify a value for this except on targets with an MMU.}
4799 The value should normally correspond to a static mapping for the
4800 @code{-work-area-phys} address, set up by the current operating system.
4803 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4804 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4805 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4806 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
4807 @option{RIOT}, @option{Zephyr}
4808 @xref{gdbrtossupport,,RTOS Support}.
4810 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4811 scan and after a reset. A manual call to arp_examine is required to
4812 access the target for debugging.
4814 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4815 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4816 Use this option with systems where multiple, independent cores are connected
4817 to separate access ports of the same DAP.
4819 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4820 to the target. Currently, only the @code{aarch64} target makes use of this option,
4821 where it is a mandatory configuration for the target run control.
4822 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4823 for instruction on how to declare and control a CTI instance.
4825 @anchor{gdbportoverride}
4826 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4827 possible values of the parameter @var{number}, which are not only numeric values.
4828 Use this option to override, for this target only, the global parameter set with
4829 command @command{gdb_port}.
4830 @xref{gdb_port,,command gdb_port}.
4832 @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum
4833 number of GDB connections that are allowed for the target. Default is 1.
4834 A negative value for @var{number} means unlimited connections.
4835 See @xref{gdbmeminspect,,Using GDB as a non-intrusive memory inspector}.
4839 @section Other $target_name Commands
4840 @cindex object command
4842 The Tcl/Tk language has the concept of object commands,
4843 and OpenOCD adopts that same model for targets.
4845 A good Tk example is a on screen button.
4846 Once a button is created a button
4847 has a name (a path in Tk terms) and that name is useable as a first
4848 class command. For example in Tk, one can create a button and later
4849 configure it like this:
4853 button .foobar -background red -command @{ foo @}
4855 .foobar configure -foreground blue
4857 set x [.foobar cget -background]
4859 puts [format "The button is %s" $x]
4862 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4863 button, and its object commands are invoked the same way.
4866 str912.cpu mww 0x1234 0x42
4867 omap3530.cpu mww 0x5555 123
4870 The commands supported by OpenOCD target objects are:
4872 @deffn {Command} {$target_name arp_examine} @option{allow-defer}
4873 @deffnx {Command} {$target_name arp_halt}
4874 @deffnx {Command} {$target_name arp_poll}
4875 @deffnx {Command} {$target_name arp_reset}
4876 @deffnx {Command} {$target_name arp_waitstate}
4877 Internal OpenOCD scripts (most notably @file{startup.tcl})
4878 use these to deal with specific reset cases.
4879 They are not otherwise documented here.
4882 @deffn {Command} {$target_name array2mem} arrayname width address count
4883 @deffnx {Command} {$target_name mem2array} arrayname width address count
4884 These provide an efficient script-oriented interface to memory.
4885 The @code{array2mem} primitive writes bytes, halfwords, words
4886 or double-words; while @code{mem2array} reads them.
4887 In both cases, the TCL side uses an array, and
4888 the target side uses raw memory.
4890 The efficiency comes from enabling the use of
4891 bulk JTAG data transfer operations.
4892 The script orientation comes from working with data
4893 values that are packaged for use by TCL scripts;
4894 @command{mdw} type primitives only print data they retrieve,
4895 and neither store nor return those values.
4898 @item @var{arrayname} ... is the name of an array variable
4899 @item @var{width} ... is 8/16/32/64 - indicating the memory access size
4900 @item @var{address} ... is the target memory address
4901 @item @var{count} ... is the number of elements to process
4905 @deffn {Command} {$target_name cget} queryparm
4906 Each configuration parameter accepted by
4907 @command{$target_name configure}
4908 can be individually queried, to return its current value.
4909 The @var{queryparm} is a parameter name
4910 accepted by that command, such as @code{-work-area-phys}.
4911 There are a few special cases:
4914 @item @code{-event} @var{event_name} -- returns the handler for the
4915 event named @var{event_name}.
4916 This is a special case because setting a handler requires
4918 @item @code{-type} -- returns the target type.
4919 This is a special case because this is set using
4920 @command{target create} and can't be changed
4921 using @command{$target_name configure}.
4924 For example, if you wanted to summarize information about
4925 all the targets you might use something like this:
4928 foreach name [target names] @{
4929 set y [$name cget -endian]
4930 set z [$name cget -type]
4931 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4937 @anchor{targetcurstate}
4938 @deffn {Command} {$target_name curstate}
4939 Displays the current target state:
4940 @code{debug-running},
4943 @code{running}, or @code{unknown}.
4944 (Also, @pxref{eventpolling,,Event Polling}.)
4947 @deffn {Command} {$target_name eventlist}
4948 Displays a table listing all event handlers
4949 currently associated with this target.
4950 @xref{targetevents,,Target Events}.
4953 @deffn {Command} {$target_name invoke-event} event_name
4954 Invokes the handler for the event named @var{event_name}.
4955 (This is primarily intended for use by OpenOCD framework
4956 code, for example by the reset code in @file{startup.tcl}.)
4959 @deffn {Command} {$target_name mdd} [phys] addr [count]
4960 @deffnx {Command} {$target_name mdw} [phys] addr [count]
4961 @deffnx {Command} {$target_name mdh} [phys] addr [count]
4962 @deffnx {Command} {$target_name mdb} [phys] addr [count]
4963 Display contents of address @var{addr}, as
4964 64-bit doublewords (@command{mdd}),
4965 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4966 or 8-bit bytes (@command{mdb}).
4967 When the current target has an MMU which is present and active,
4968 @var{addr} is interpreted as a virtual address.
4969 Otherwise, or if the optional @var{phys} flag is specified,
4970 @var{addr} is interpreted as a physical address.
4971 If @var{count} is specified, displays that many units.
4972 (If you want to manipulate the data instead of displaying it,
4973 see the @code{mem2array} primitives.)
4976 @deffn {Command} {$target_name mwd} [phys] addr doubleword [count]
4977 @deffnx {Command} {$target_name mww} [phys] addr word [count]
4978 @deffnx {Command} {$target_name mwh} [phys] addr halfword [count]
4979 @deffnx {Command} {$target_name mwb} [phys] addr byte [count]
4980 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
4981 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
4982 at the specified address @var{addr}.
4983 When the current target has an MMU which is present and active,
4984 @var{addr} is interpreted as a virtual address.
4985 Otherwise, or if the optional @var{phys} flag is specified,
4986 @var{addr} is interpreted as a physical address.
4987 If @var{count} is specified, fills that many units of consecutive address.
4990 @anchor{targetevents}
4991 @section Target Events
4992 @cindex target events
4994 At various times, certain things can happen, or you want them to happen.
4997 @item What should happen when GDB connects? Should your target reset?
4998 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4999 @item Is using SRST appropriate (and possible) on your system?
5000 Or instead of that, do you need to issue JTAG commands to trigger reset?
5001 SRST usually resets everything on the scan chain, which can be inappropriate.
5002 @item During reset, do you need to write to certain memory locations
5003 to set up system clocks or
5004 to reconfigure the SDRAM?
5005 How about configuring the watchdog timer, or other peripherals,
5006 to stop running while you hold the core stopped for debugging?
5009 All of the above items can be addressed by target event handlers.
5010 These are set up by @command{$target_name configure -event} or
5011 @command{target create ... -event}.
5013 The programmer's model matches the @code{-command} option used in Tcl/Tk
5014 buttons and events. The two examples below act the same, but one creates
5015 and invokes a small procedure while the other inlines it.
5018 proc my_init_proc @{ @} @{
5019 echo "Disabling watchdog..."
5020 mww 0xfffffd44 0x00008000
5022 mychip.cpu configure -event reset-init my_init_proc
5023 mychip.cpu configure -event reset-init @{
5024 echo "Disabling watchdog..."
5025 mww 0xfffffd44 0x00008000
5029 The following target events are defined:
5032 @item @b{debug-halted}
5033 @* The target has halted for debug reasons (i.e.: breakpoint)
5034 @item @b{debug-resumed}
5035 @* The target has resumed (i.e.: GDB said run)
5036 @item @b{early-halted}
5037 @* Occurs early in the halt process
5038 @item @b{examine-start}
5039 @* Before target examine is called.
5040 @item @b{examine-end}
5041 @* After target examine is called with no errors.
5042 @item @b{examine-fail}
5043 @* After target examine fails.
5044 @item @b{gdb-attach}
5045 @* When GDB connects. Issued before any GDB communication with the target
5046 starts. GDB expects the target is halted during attachment.
5047 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
5048 connect GDB to running target.
5049 The event can be also used to set up the target so it is possible to probe flash.
5050 Probing flash is necessary during GDB connect if you want to use
5051 @pxref{programmingusinggdb,,programming using GDB}.
5052 Another use of the flash memory map is for GDB to automatically choose
5053 hardware or software breakpoints depending on whether the breakpoint
5054 is in RAM or read only memory.
5055 Default is @code{halt}
5056 @item @b{gdb-detach}
5057 @* When GDB disconnects
5059 @* When the target has halted and GDB is not doing anything (see early halt)
5060 @item @b{gdb-flash-erase-start}
5061 @* Before the GDB flash process tries to erase the flash (default is
5063 @item @b{gdb-flash-erase-end}
5064 @* After the GDB flash process has finished erasing the flash
5065 @item @b{gdb-flash-write-start}
5066 @* Before GDB writes to the flash
5067 @item @b{gdb-flash-write-end}
5068 @* After GDB writes to the flash (default is @code{reset halt})
5070 @* Before the target steps, GDB is trying to start/resume the target
5072 @* The target has halted
5073 @item @b{reset-assert-pre}
5074 @* Issued as part of @command{reset} processing
5075 after @command{reset-start} was triggered
5076 but before either SRST alone is asserted on the scan chain,
5077 or @code{reset-assert} is triggered.
5078 @item @b{reset-assert}
5079 @* Issued as part of @command{reset} processing
5080 after @command{reset-assert-pre} was triggered.
5081 When such a handler is present, cores which support this event will use
5082 it instead of asserting SRST.
5083 This support is essential for debugging with JTAG interfaces which
5084 don't include an SRST line (JTAG doesn't require SRST), and for
5085 selective reset on scan chains that have multiple targets.
5086 @item @b{reset-assert-post}
5087 @* Issued as part of @command{reset} processing
5088 after @code{reset-assert} has been triggered.
5089 or the target asserted SRST on the entire scan chain.
5090 @item @b{reset-deassert-pre}
5091 @* Issued as part of @command{reset} processing
5092 after @code{reset-assert-post} has been triggered.
5093 @item @b{reset-deassert-post}
5094 @* Issued as part of @command{reset} processing
5095 after @code{reset-deassert-pre} has been triggered
5096 and (if the target is using it) after SRST has been
5097 released on the scan chain.
5099 @* Issued as the final step in @command{reset} processing.
5100 @item @b{reset-init}
5101 @* Used by @b{reset init} command for board-specific initialization.
5102 This event fires after @emph{reset-deassert-post}.
5104 This is where you would configure PLLs and clocking, set up DRAM so
5105 you can download programs that don't fit in on-chip SRAM, set up pin
5106 multiplexing, and so on.
5107 (You may be able to switch to a fast JTAG clock rate here, after
5108 the target clocks are fully set up.)
5109 @item @b{reset-start}
5110 @* Issued as the first step in @command{reset} processing
5111 before @command{reset-assert-pre} is called.
5113 This is the most robust place to use @command{jtag_rclk}
5114 or @command{adapter speed} to switch to a low JTAG clock rate,
5115 when reset disables PLLs needed to use a fast clock.
5116 @item @b{resume-start}
5117 @* Before any target is resumed
5118 @item @b{resume-end}
5119 @* After all targets have resumed
5121 @* Target has resumed
5122 @item @b{step-start}
5123 @* Before a target is single-stepped
5125 @* After single-step has completed
5126 @item @b{trace-config}
5127 @* After target hardware trace configuration was changed
5131 OpenOCD events are not supposed to be preempt by another event, but this
5132 is not enforced in current code. Only the target event @b{resumed} is
5133 executed with polling disabled; this avoids polling to trigger the event
5134 @b{halted}, reversing the logical order of execution of their handlers.
5135 Future versions of OpenOCD will prevent the event preemption and will
5136 disable the schedule of polling during the event execution. Do not rely
5137 on polling in any event handler; this means, don't expect the status of
5138 a core to change during the execution of the handler. The event handler
5139 will have to enable polling or use @command{$target_name arp_poll} to
5140 check if the core has changed status.
5143 @node Flash Commands
5144 @chapter Flash Commands
5146 OpenOCD has different commands for NOR and NAND flash;
5147 the ``flash'' command works with NOR flash, while
5148 the ``nand'' command works with NAND flash.
5149 This partially reflects different hardware technologies:
5150 NOR flash usually supports direct CPU instruction and data bus access,
5151 while data from a NAND flash must be copied to memory before it can be
5152 used. (SPI flash must also be copied to memory before use.)
5153 However, the documentation also uses ``flash'' as a generic term;
5154 for example, ``Put flash configuration in board-specific files''.
5158 @item Configure via the command @command{flash bank}
5159 @* Do this in a board-specific configuration file,
5160 passing parameters as needed by the driver.
5161 @item Operate on the flash via @command{flash subcommand}
5162 @* Often commands to manipulate the flash are typed by a human, or run
5163 via a script in some automated way. Common tasks include writing a
5164 boot loader, operating system, or other data.
5166 @* Flashing via GDB requires the flash be configured via ``flash
5167 bank'', and the GDB flash features be enabled.
5168 @xref{gdbconfiguration,,GDB Configuration}.
5171 Many CPUs have the ability to ``boot'' from the first flash bank.
5172 This means that misprogramming that bank can ``brick'' a system,
5173 so that it can't boot.
5174 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
5175 board by (re)installing working boot firmware.
5177 @anchor{norconfiguration}
5178 @section Flash Configuration Commands
5179 @cindex flash configuration
5181 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
5182 Configures a flash bank which provides persistent storage
5183 for addresses from @math{base} to @math{base + size - 1}.
5184 These banks will often be visible to GDB through the target's memory map.
5185 In some cases, configuring a flash bank will activate extra commands;
5186 see the driver-specific documentation.
5189 @item @var{name} ... may be used to reference the flash bank
5190 in other flash commands. A number is also available.
5191 @item @var{driver} ... identifies the controller driver
5192 associated with the flash bank being declared.
5193 This is usually @code{cfi} for external flash, or else
5194 the name of a microcontroller with embedded flash memory.
5195 @xref{flashdriverlist,,Flash Driver List}.
5196 @item @var{base} ... Base address of the flash chip.
5197 @item @var{size} ... Size of the chip, in bytes.
5198 For some drivers, this value is detected from the hardware.
5199 @item @var{chip_width} ... Width of the flash chip, in bytes;
5200 ignored for most microcontroller drivers.
5201 @item @var{bus_width} ... Width of the data bus used to access the
5202 chip, in bytes; ignored for most microcontroller drivers.
5203 @item @var{target} ... Names the target used to issue
5204 commands to the flash controller.
5205 @comment Actually, it's currently a controller-specific parameter...
5206 @item @var{driver_options} ... drivers may support, or require,
5207 additional parameters. See the driver-specific documentation
5208 for more information.
5211 This command is not available after OpenOCD initialization has completed.
5212 Use it in board specific configuration files, not interactively.
5216 @comment less confusing would be: "flash list" (like "nand list")
5217 @deffn {Command} {flash banks}
5218 Prints a one-line summary of each device that was
5219 declared using @command{flash bank}, numbered from zero.
5220 Note that this is the @emph{plural} form;
5221 the @emph{singular} form is a very different command.
5224 @deffn {Command} {flash list}
5225 Retrieves a list of associative arrays for each device that was
5226 declared using @command{flash bank}, numbered from zero.
5227 This returned list can be manipulated easily from within scripts.
5230 @deffn {Command} {flash probe} num
5231 Identify the flash, or validate the parameters of the configured flash. Operation
5232 depends on the flash type.
5233 The @var{num} parameter is a value shown by @command{flash banks}.
5234 Most flash commands will implicitly @emph{autoprobe} the bank;
5235 flash drivers can distinguish between probing and autoprobing,
5236 but most don't bother.
5239 @section Preparing a Target before Flash Programming
5241 The target device should be in well defined state before the flash programming
5244 @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
5245 Do not issue another @command{reset} or @command{reset halt} or @command{resume}
5246 until the programming session is finished.
5248 If you use @ref{programmingusinggdb,,Programming using GDB},
5249 the target is prepared automatically in the event gdb-flash-erase-start
5251 The jimtcl script @command{program} calls @command{reset init} explicitly.
5253 @section Erasing, Reading, Writing to Flash
5254 @cindex flash erasing
5255 @cindex flash reading
5256 @cindex flash writing
5257 @cindex flash programming
5258 @anchor{flashprogrammingcommands}
5260 One feature distinguishing NOR flash from NAND or serial flash technologies
5261 is that for read access, it acts exactly like any other addressable memory.
5262 This means you can use normal memory read commands like @command{mdw} or
5263 @command{dump_image} with it, with no special @command{flash} subcommands.
5264 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
5266 Write access works differently. Flash memory normally needs to be erased
5267 before it's written. Erasing a sector turns all of its bits to ones, and
5268 writing can turn ones into zeroes. This is why there are special commands
5269 for interactive erasing and writing, and why GDB needs to know which parts
5270 of the address space hold NOR flash memory.
5273 Most of these erase and write commands leverage the fact that NOR flash
5274 chips consume target address space. They implicitly refer to the current
5275 JTAG target, and map from an address in that target's address space
5276 back to a flash bank.
5277 @comment In May 2009, those mappings may fail if any bank associated
5278 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
5279 A few commands use abstract addressing based on bank and sector numbers,
5280 and don't depend on searching the current target and its address space.
5281 Avoid confusing the two command models.
5284 Some flash chips implement software protection against accidental writes,
5285 since such buggy writes could in some cases ``brick'' a system.
5286 For such systems, erasing and writing may require sector protection to be
5288 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
5289 and AT91SAM7 on-chip flash.
5290 @xref{flashprotect,,flash protect}.
5292 @deffn {Command} {flash erase_sector} num first last
5293 Erase sectors in bank @var{num}, starting at sector @var{first}
5294 up to and including @var{last}.
5295 Sector numbering starts at 0.
5296 Providing a @var{last} sector of @option{last}
5297 specifies "to the end of the flash bank".
5298 The @var{num} parameter is a value shown by @command{flash banks}.
5301 @deffn {Command} {flash erase_address} [@option{pad}] [@option{unlock}] address length
5302 Erase sectors starting at @var{address} for @var{length} bytes.
5303 Unless @option{pad} is specified, @math{address} must begin a
5304 flash sector, and @math{address + length - 1} must end a sector.
5305 Specifying @option{pad} erases extra data at the beginning and/or
5306 end of the specified region, as needed to erase only full sectors.
5307 The flash bank to use is inferred from the @var{address}, and
5308 the specified length must stay within that bank.
5309 As a special case, when @var{length} is zero and @var{address} is
5310 the start of the bank, the whole flash is erased.
5311 If @option{unlock} is specified, then the flash is unprotected
5312 before erase starts.
5315 @deffn {Command} {flash filld} address double-word length
5316 @deffnx {Command} {flash fillw} address word length
5317 @deffnx {Command} {flash fillh} address halfword length
5318 @deffnx {Command} {flash fillb} address byte length
5319 Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
5320 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5321 starting at @var{address} and continuing
5322 for @var{length} units (word/halfword/byte).
5323 No erasure is done before writing; when needed, that must be done
5324 before issuing this command.
5325 Writes are done in blocks of up to 1024 bytes, and each write is
5326 verified by reading back the data and comparing it to what was written.
5327 The flash bank to use is inferred from the @var{address} of
5328 each block, and the specified length must stay within that bank.
5330 @comment no current checks for errors if fill blocks touch multiple banks!
5332 @deffn {Command} {flash mdw} addr [count]
5333 @deffnx {Command} {flash mdh} addr [count]
5334 @deffnx {Command} {flash mdb} addr [count]
5335 Display contents of address @var{addr}, as
5336 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5337 or 8-bit bytes (@command{mdb}).
5338 If @var{count} is specified, displays that many units.
5339 Reads from flash using the flash driver, therefore it enables reading
5340 from a bank not mapped in target address space.
5341 The flash bank to use is inferred from the @var{address} of
5342 each block, and the specified length must stay within that bank.
5345 @deffn {Command} {flash write_bank} num filename [offset]
5346 Write the binary @file{filename} to flash bank @var{num},
5347 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5348 is omitted, start at the beginning of the flash bank.
5349 The @var{num} parameter is a value shown by @command{flash banks}.
5352 @deffn {Command} {flash read_bank} num filename [offset [length]]
5353 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5354 and write the contents to the binary @file{filename}. If @var{offset} is
5355 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5356 read the remaining bytes from the flash bank.
5357 The @var{num} parameter is a value shown by @command{flash banks}.
5360 @deffn {Command} {flash verify_bank} num filename [offset]
5361 Compare the contents of the binary file @var{filename} with the contents of the
5362 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5363 start at the beginning of the flash bank. Fail if the contents do not match.
5364 The @var{num} parameter is a value shown by @command{flash banks}.
5367 @deffn {Command} {flash write_image} [erase] [unlock] filename [offset] [type]
5368 Write the image @file{filename} to the current target's flash bank(s).
5369 Only loadable sections from the image are written.
5370 A relocation @var{offset} may be specified, in which case it is added
5371 to the base address for each section in the image.
5372 The file [@var{type}] can be specified
5373 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5374 @option{elf} (ELF file), @option{s19} (Motorola s19).
5375 @option{mem}, or @option{builder}.
5376 The relevant flash sectors will be erased prior to programming
5377 if the @option{erase} parameter is given. If @option{unlock} is
5378 provided, then the flash banks are unlocked before erase and
5379 program. The flash bank to use is inferred from the address of
5383 Be careful using the @option{erase} flag when the flash is holding
5384 data you want to preserve.
5385 Portions of the flash outside those described in the image's
5386 sections might be erased with no notice.
5389 When a section of the image being written does not fill out all the
5390 sectors it uses, the unwritten parts of those sectors are necessarily
5391 also erased, because sectors can't be partially erased.
5393 Data stored in sector "holes" between image sections are also affected.
5394 For example, "@command{flash write_image erase ...}" of an image with
5395 one byte at the beginning of a flash bank and one byte at the end
5396 erases the entire bank -- not just the two sectors being written.
5398 Also, when flash protection is important, you must re-apply it after
5399 it has been removed by the @option{unlock} flag.
5404 @deffn {Command} {flash verify_image} filename [offset] [type]
5405 Verify the image @file{filename} to the current target's flash bank(s).
5406 Parameters follow the description of 'flash write_image'.
5407 In contrast to the 'verify_image' command, for banks with specific
5408 verify method, that one is used instead of the usual target's read
5409 memory methods. This is necessary for flash banks not readable by
5410 ordinary memory reads.
5411 This command gives only an overall good/bad result for each bank, not
5412 addresses of individual failed bytes as it's intended only as quick
5413 check for successful programming.
5416 @section Other Flash commands
5417 @cindex flash protection
5419 @deffn {Command} {flash erase_check} num
5420 Check erase state of sectors in flash bank @var{num},
5421 and display that status.
5422 The @var{num} parameter is a value shown by @command{flash banks}.
5425 @deffn {Command} {flash info} num [sectors]
5426 Print info about flash bank @var{num}, a list of protection blocks
5427 and their status. Use @option{sectors} to show a list of sectors instead.
5429 The @var{num} parameter is a value shown by @command{flash banks}.
5430 This command will first query the hardware, it does not print cached
5431 and possibly stale information.
5434 @anchor{flashprotect}
5435 @deffn {Command} {flash protect} num first last (@option{on}|@option{off})
5436 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5437 in flash bank @var{num}, starting at protection block @var{first}
5438 and continuing up to and including @var{last}.
5439 Providing a @var{last} block of @option{last}
5440 specifies "to the end of the flash bank".
5441 The @var{num} parameter is a value shown by @command{flash banks}.
5442 The protection block is usually identical to a flash sector.
5443 Some devices may utilize a protection block distinct from flash sector.
5444 See @command{flash info} for a list of protection blocks.
5447 @deffn {Command} {flash padded_value} num value
5448 Sets the default value used for padding any image sections, This should
5449 normally match the flash bank erased value. If not specified by this
5450 command or the flash driver then it defaults to 0xff.
5454 @deffn {Command} {program} filename [preverify] [verify] [reset] [exit] [offset]
5455 This is a helper script that simplifies using OpenOCD as a standalone
5456 programmer. The only required parameter is @option{filename}, the others are optional.
5457 @xref{Flash Programming}.
5460 @anchor{flashdriverlist}
5461 @section Flash Driver List
5462 As noted above, the @command{flash bank} command requires a driver name,
5463 and allows driver-specific options and behaviors.
5464 Some drivers also activate driver-specific commands.
5466 @deffn {Flash Driver} {virtual}
5467 This is a special driver that maps a previously defined bank to another
5468 address. All bank settings will be copied from the master physical bank.
5470 The @var{virtual} driver defines one mandatory parameters,
5473 @item @var{master_bank} The bank that this virtual address refers to.
5476 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5477 the flash bank defined at address 0x1fc00000. Any command executed on
5478 the virtual banks is actually performed on the physical banks.
5480 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5481 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5482 $_TARGETNAME $_FLASHNAME
5483 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5484 $_TARGETNAME $_FLASHNAME
5488 @subsection External Flash
5490 @deffn {Flash Driver} {cfi}
5491 @cindex Common Flash Interface
5493 The ``Common Flash Interface'' (CFI) is the main standard for
5494 external NOR flash chips, each of which connects to a
5495 specific external chip select on the CPU.
5496 Frequently the first such chip is used to boot the system.
5497 Your board's @code{reset-init} handler might need to
5498 configure additional chip selects using other commands (like: @command{mww} to
5499 configure a bus and its timings), or
5500 perhaps configure a GPIO pin that controls the ``write protect'' pin
5502 The CFI driver can use a target-specific working area to significantly
5505 The CFI driver can accept the following optional parameters, in any order:
5508 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5509 like AM29LV010 and similar types.
5510 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5511 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5512 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5513 swapped when writing data values (i.e. not CFI commands).
5516 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5517 wide on a sixteen bit bus:
5520 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5521 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5524 To configure one bank of 32 MBytes
5525 built from two sixteen bit (two byte) wide parts wired in parallel
5526 to create a thirty-two bit (four byte) bus with doubled throughput:
5529 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5532 @c "cfi part_id" disabled
5535 @deffn {Flash Driver} {jtagspi}
5536 @cindex Generic JTAG2SPI driver
5540 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5541 SPI flash connected to them. To access this flash from the host, the device
5542 is first programmed with a special proxy bitstream that
5543 exposes the SPI flash on the device's JTAG interface. The flash can then be
5544 accessed through JTAG.
5546 Since signaling between JTAG and SPI is compatible, all that is required for
5547 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5548 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5549 a bitstream for several Xilinx FPGAs can be found in
5550 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5551 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5553 This flash bank driver requires a target on a JTAG tap and will access that
5554 tap directly. Since no support from the target is needed, the target can be a
5555 "testee" dummy. Since the target does not expose the flash memory
5556 mapping, target commands that would otherwise be expected to access the flash
5557 will not work. These include all @command{*_image} and
5558 @command{$target_name m*} commands as well as @command{program}. Equivalent
5559 functionality is available through the @command{flash write_bank},
5560 @command{flash read_bank}, and @command{flash verify_bank} commands.
5562 According to device size, 1- to 4-byte addresses are sent. However, some
5563 flash chips additionally have to be switched to 4-byte addresses by an extra
5567 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5568 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5569 @var{USER1} instruction.
5573 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5574 set _XILINX_USER1 0x02
5575 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5576 $_TARGETNAME $_XILINX_USER1
5579 @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5580 Sets flash parameters: @var{name} human readable string, @var{total_size}
5581 size in bytes, @var{page_size} is write page size. @var{read_cmd} and @var{pprg_cmd}
5582 are commands for read and page program, respectively. @var{mass_erase_cmd},
5583 @var{sector_size} and @var{sector_erase_cmd} are optional.
5585 jtagspi set 0 w25q128 0x1000000 0x100 0x03 0 0x02 0xC7 0x10000 0xD8
5589 @deffn Command {jtagspi cmd} bank_id resp_num cmd_byte ...
5590 Sends command @var{cmd_byte} and at most 20 following bytes and reads
5591 @var{resp_num} bytes afterwards. E.g. for 'Enter 4-byte address mode'
5593 jtagspi cmd 0 0 0xB7
5597 @deffn Command {jtagspi always_4byte} bank_id [ on | off ]
5598 Some devices use 4-byte addresses for all commands except the legacy 0x03 read
5599 regardless of device size. This command controls the corresponding hack.
5603 @deffn {Flash Driver} {xcf}
5604 @cindex Xilinx Platform flash driver
5606 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5607 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5608 only difference is special registers controlling its FPGA specific behavior.
5609 They must be properly configured for successful FPGA loading using
5610 additional @var{xcf} driver command:
5612 @deffn {Command} {xcf ccb} <bank_id>
5613 command accepts additional parameters:
5615 @item @var{external|internal} ... selects clock source.
5616 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5617 @item @var{slave|master} ... selects slave of master mode for flash device.
5618 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5622 xcf ccb 0 external parallel slave 40
5624 All of them must be specified even if clock frequency is pointless
5625 in slave mode. If only bank id specified than command prints current
5626 CCB register value. Note: there is no need to write this register
5627 every time you erase/program data sectors because it stores in
5631 @deffn {Command} {xcf configure} <bank_id>
5632 Initiates FPGA loading procedure. Useful if your board has no "configure"
5639 Additional driver notes:
5641 @item Only single revision supported.
5642 @item Driver automatically detects need of bit reverse, but
5643 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5644 (Intel hex) file types supported.
5645 @item For additional info check xapp972.pdf and ug380.pdf.
5649 @deffn {Flash Driver} {lpcspifi}
5650 @cindex NXP SPI Flash Interface
5653 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5654 Flash Interface (SPIFI) peripheral that can drive and provide
5655 memory mapped access to external SPI flash devices.
5657 The lpcspifi driver initializes this interface and provides
5658 program and erase functionality for these serial flash devices.
5659 Use of this driver @b{requires} a working area of at least 1kB
5660 to be configured on the target device; more than this will
5661 significantly reduce flash programming times.
5663 The setup command only requires the @var{base} parameter. All
5664 other parameters are ignored, and the flash size and layout
5665 are configured by the driver.
5668 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5673 @deffn {Flash Driver} {stmsmi}
5674 @cindex STMicroelectronics Serial Memory Interface
5677 Some devices from STMicroelectronics (e.g. STR75x MCU family,
5678 SPEAr MPU family) include a proprietary
5679 ``Serial Memory Interface'' (SMI) controller able to drive external
5681 Depending on specific device and board configuration, up to 4 external
5682 flash devices can be connected.
5684 SMI makes the flash content directly accessible in the CPU address
5685 space; each external device is mapped in a memory bank.
5686 CPU can directly read data, execute code and boot from SMI banks.
5687 Normal OpenOCD commands like @command{mdw} can be used to display
5690 The setup command only requires the @var{base} parameter in order
5691 to identify the memory bank.
5692 All other parameters are ignored. Additional information, like
5693 flash size, are detected automatically.
5696 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5701 @deffn {Flash Driver} {stmqspi}
5702 @cindex STMicroelectronics QuadSPI/OctoSPI Interface
5706 Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface''
5707 (e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface'' (e.g. STM32L4+)
5708 controller able to drive one or even two (dual mode) external SPI flash devices.
5709 The OctoSPI is a superset of QuadSPI, its presence is detected automatically.
5710 Currently only the regular command mode is supported, whereas the HyperFlash
5713 QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address
5714 space; in case of dual mode both devices must be of the same type and are
5715 mapped in the same memory bank (even and odd addresses interleaved).
5716 CPU can directly read data, execute code (but not boot) from QuadSPI bank.
5718 The 'flash bank' command only requires the @var{base} parameter and the extra
5719 parameter @var{io_base} in order to identify the memory bank. Both are fixed
5720 by hardware, see datasheet or RM. All other parameters are ignored.
5722 The controller must be initialized after each reset and properly configured
5723 for memory-mapped read operation for the particular flash chip(s), for the full
5724 list of available register settings cf. the controller's RM. This setup is quite
5725 board specific (that's why booting from this memory is not possible). The
5726 flash driver infers all parameters from current controller register values when
5727 'flash probe @var{bank_id}' is executed.
5729 Normal OpenOCD commands like @command{mdw} can be used to display the flash content,
5730 but only after proper controller initialization as described above. However,
5731 due to a silicon bug in some devices, attempting to access the very last word
5734 It is possible to use two (even different) flash chips alternatingly, if individual
5735 bank chip selects are available. For some package variants, this is not the case
5736 due to limited pin count. To switch from one to another, adjust FSEL bit accordingly
5737 and re-issue 'flash probe bank_id'. Note that the bank base address will @emph{not}
5738 change, so the address spaces of both devices will overlap. In dual flash mode
5739 both chips must be identical regarding size and most other properties.
5741 Block or sector protection internal to the flash chip is not handled by this
5742 driver at all, but can be dealt with manually by the 'cmd' command, see below.
5743 The sector protection via 'flash protect' command etc. is completely internal to
5744 openocd, intended only to prevent accidental erase or overwrite and it does not
5745 persist across openocd invocations.
5747 OpenOCD contains a hardcoded list of flash devices with their properties,
5748 these are auto-detected. If a device is not included in this list, SFDP discovery
5749 is attempted. If this fails or gives inappropriate results, manual setting is
5750 required (see 'set' command).
5753 flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
5754 $_TARGETNAME 0xA0001000
5755 flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
5756 $_TARGETNAME 0xA0001400
5759 There are three specific commands
5760 @deffn {Command} {stmqspi mass_erase} bank_id
5761 Clears sector protections and performs a mass erase. Works only if there is no
5762 chip specific write protection engaged.
5765 @deffn {Command} {stmqspi set} bank_id name total_size page_size read_cmd fread_cmd pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5766 Set flash parameters: @var{name} human readable string, @var{total_size} size
5767 in bytes, @var{page_size} is write page size. @var{read_cmd}, @var{fread_cmd} and @var{pprg_cmd}
5768 are commands for reading and page programming. @var{fread_cmd} is used in DPI and QPI modes,
5769 @var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}
5770 and @var{sector_erase_cmd} are optional.
5772 This command is required if chip id is not hardcoded yet and e.g. for EEPROMs or FRAMs
5773 which don't support an id command.
5775 In dual mode parameters of both chips are set identically. The parameters refer to
5776 a single chip, so the whole bank gets twice the specified capacity etc.
5779 @deffn {Command} {stmqspi cmd} bank_id resp_num cmd_byte ...
5780 If @var{resp_num} is zero, sends command @var{cmd_byte} and following data
5781 bytes. In dual mode command byte is sent to @emph{both} chips but data bytes are
5782 sent @emph{alternatingly} to chip 1 and 2, first to flash 1, second to flash 2, etc.,
5783 i.e. the total number of bytes (including cmd_byte) must be odd.
5785 If @var{resp_num} is not zero, cmd and at most four following data bytes are
5786 sent, in dual mode @emph{simultaneously} to both chips. Then @var{resp_num} bytes
5787 are read interleaved from both chips starting with chip 1. In this case
5788 @var{resp_num} must be even.
5790 Note the hardware dictated subtle difference of those two cases in dual-flash mode.
5792 To check basic communication settings, issue
5794 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05
5795 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
5797 for single flash mode or
5799 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05
5800 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
5802 for dual flash mode. This should return the status register contents.
5804 In 8-line mode, @var{cmd_byte} is sent twice - first time as given, second time
5805 complemented. Additionally, in 8-line mode only, some commands (e.g. Read Status)
5806 need a dummy address, e.g.
5808 stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
5810 should return the status register contents.
5816 @deffn {Flash Driver} {mrvlqspi}
5817 This driver supports QSPI flash controller of Marvell's Wireless
5818 Microcontroller platform.
5820 The flash size is autodetected based on the table of known JEDEC IDs
5821 hardcoded in the OpenOCD sources.
5824 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5829 @deffn {Flash Driver} {ath79}
5830 @cindex Atheros ath79 SPI driver
5832 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5834 On reset a SPI flash connected to the first chip select (CS0) is made
5835 directly read-accessible in the CPU address space (up to 16MBytes)
5836 and is usually used to store the bootloader and operating system.
5837 Normal OpenOCD commands like @command{mdw} can be used to display
5838 the flash content while it is in memory-mapped mode (only the first
5839 4MBytes are accessible without additional configuration on reset).
5841 The setup command only requires the @var{base} parameter in order
5842 to identify the memory bank. The actual value for the base address
5843 is not otherwise used by the driver. However the mapping is passed
5844 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5845 address should be the actual memory mapped base address. For unmapped
5846 chipselects (CS1 and CS2) care should be taken to use a base address
5847 that does not overlap with real memory regions.
5848 Additional information, like flash size, are detected automatically.
5849 An optional additional parameter sets the chipselect for the bank,
5850 with the default CS0.
5851 CS1 and CS2 require additional GPIO setup before they can be used
5852 since the alternate function must be enabled on the GPIO pin
5853 CS1/CS2 is routed to on the given SoC.
5856 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
5858 # When using multiple chipselects the base should be different
5859 # for each, otherwise the write_image command is not able to
5860 # distinguish the banks.
5861 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
5862 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
5863 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
5868 @deffn {Flash Driver} {fespi}
5869 @cindex Freedom E SPI
5872 SiFive's Freedom E SPI controller, used in HiFive and other boards.
5875 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
5879 @subsection Internal Flash (Microcontrollers)
5881 @deffn {Flash Driver} {aduc702x}
5882 The ADUC702x analog microcontrollers from Analog Devices
5883 include internal flash and use ARM7TDMI cores.
5884 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5885 The setup command only requires the @var{target} argument
5886 since all devices in this family have the same memory layout.
5889 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5893 @deffn {Flash Driver} {ambiqmicro}
5896 All members of the Apollo microcontroller family from
5897 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
5898 The host connects over USB to an FTDI interface that communicates
5899 with the target using SWD.
5901 The @var{ambiqmicro} driver reads the Chip Information Register detect
5902 the device class of the MCU.
5903 The Flash and SRAM sizes directly follow device class, and are used
5904 to set up the flash banks.
5905 If this fails, the driver will use default values set to the minimum
5906 sizes of an Apollo chip.
5908 All Apollo chips have two flash banks of the same size.
5909 In all cases the first flash bank starts at location 0,
5910 and the second bank starts after the first.
5914 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
5915 # Flash bank 1 - same size as bank0, starts after bank 0.
5916 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
5920 Flash is programmed using custom entry points into the bootloader.
5921 This is the only way to program the flash as no flash control registers
5922 are available to the user.
5924 The @var{ambiqmicro} driver adds some additional commands:
5926 @deffn {Command} {ambiqmicro mass_erase} <bank>
5929 @deffn {Command} {ambiqmicro page_erase} <bank> <first> <last>
5932 @deffn {Command} {ambiqmicro program_otp} <bank> <offset> <count>
5933 Program OTP is a one time operation to create write protected flash.
5934 The user writes sectors to SRAM starting at 0x10000010.
5935 Program OTP will write these sectors from SRAM to flash, and write protect
5941 @deffn {Flash Driver} {at91samd}
5943 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
5944 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
5946 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
5948 The devices have one flash bank:
5951 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
5954 @deffn {Command} {at91samd chip-erase}
5955 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5956 used to erase a chip back to its factory state and does not require the
5957 processor to be halted.
5960 @deffn {Command} {at91samd set-security}
5961 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
5962 to the Flash and can only be undone by using the chip-erase command which
5963 erases the Flash contents and turns off the security bit. Warning: at this
5964 time, openocd will not be able to communicate with a secured chip and it is
5965 therefore not possible to chip-erase it without using another tool.
5968 at91samd set-security enable
5972 @deffn {Command} {at91samd eeprom}
5973 Shows or sets the EEPROM emulation size configuration, stored in the User Row
5974 of the Flash. When setting, the EEPROM size must be specified in bytes and it
5975 must be one of the permitted sizes according to the datasheet. Settings are
5976 written immediately but only take effect on MCU reset. EEPROM emulation
5977 requires additional firmware support and the minimum EEPROM size may not be
5978 the same as the minimum that the hardware supports. Set the EEPROM size to 0
5979 in order to disable this feature.
5983 at91samd eeprom 1024
5987 @deffn {Command} {at91samd bootloader}
5988 Shows or sets the bootloader size configuration, stored in the User Row of the
5989 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5990 must be specified in bytes and it must be one of the permitted sizes according
5991 to the datasheet. Settings are written immediately but only take effect on
5992 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5996 at91samd bootloader 16384
6000 @deffn {Command} {at91samd dsu_reset_deassert}
6001 This command releases internal reset held by DSU
6002 and prepares reset vector catch in case of reset halt.
6003 Command is used internally in event reset-deassert-post.
6006 @deffn {Command} {at91samd nvmuserrow}
6007 Writes or reads the entire 64 bit wide NVM user row register which is located at
6008 0x804000. This register includes various fuses lock-bits and factory calibration
6009 data. Reading the register is done by invoking this command without any
6010 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
6011 is the register value to be written and the second one is an optional changemask.
6012 Every bit which value in changemask is 0 will stay unchanged. The lock- and
6013 reserved-bits are masked out and cannot be changed.
6017 >at91samd nvmuserrow
6018 NVMUSERROW: 0xFFFFFC5DD8E0C788
6019 # Write 0xFFFFFC5DD8E0C788 to user row
6020 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
6021 # Write 0x12300 to user row but leave other bits and low
6023 >at91samd nvmuserrow 0x12345 0xFFF00
6030 @deffn {Flash Driver} {at91sam3}
6032 All members of the AT91SAM3 microcontroller family from
6033 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
6034 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
6035 that the driver was orginaly developed and tested using the
6036 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
6037 the family was cribbed from the data sheet. @emph{Note to future
6038 readers/updaters: Please remove this worrisome comment after other
6039 chips are confirmed.}
6041 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
6042 have one flash bank. In all cases the flash banks are at
6043 the following fixed locations:
6046 # Flash bank 0 - all chips
6047 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
6048 # Flash bank 1 - only 256K chips
6049 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
6052 Internally, the AT91SAM3 flash memory is organized as follows.
6053 Unlike the AT91SAM7 chips, these are not used as parameters
6054 to the @command{flash bank} command:
6057 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
6058 @item @emph{Bank Size:} 128K/64K Per flash bank
6059 @item @emph{Sectors:} 16 or 8 per bank
6060 @item @emph{SectorSize:} 8K Per Sector
6061 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
6064 The AT91SAM3 driver adds some additional commands:
6066 @deffn {Command} {at91sam3 gpnvm}
6067 @deffnx {Command} {at91sam3 gpnvm clear} number
6068 @deffnx {Command} {at91sam3 gpnvm set} number
6069 @deffnx {Command} {at91sam3 gpnvm show} [@option{all}|number]
6070 With no parameters, @command{show} or @command{show all},
6071 shows the status of all GPNVM bits.
6072 With @command{show} @var{number}, displays that bit.
6074 With @command{set} @var{number} or @command{clear} @var{number},
6075 modifies that GPNVM bit.
6078 @deffn {Command} {at91sam3 info}
6079 This command attempts to display information about the AT91SAM3
6080 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
6081 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
6082 document id: doc6430A] and decodes the values. @emph{Second} it reads the
6083 various clock configuration registers and attempts to display how it
6084 believes the chip is configured. By default, the SLOWCLK is assumed to
6085 be 32768 Hz, see the command @command{at91sam3 slowclk}.
6088 @deffn {Command} {at91sam3 slowclk} [value]
6089 This command shows/sets the slow clock frequency used in the
6090 @command{at91sam3 info} command calculations above.
6094 @deffn {Flash Driver} {at91sam4}
6096 All members of the AT91SAM4 microcontroller family from
6097 Atmel include internal flash and use ARM's Cortex-M4 core.
6098 This driver uses the same command names/syntax as @xref{at91sam3}.
6101 @deffn {Flash Driver} {at91sam4l}
6103 All members of the AT91SAM4L microcontroller family from
6104 Atmel include internal flash and use ARM's Cortex-M4 core.
6105 This driver uses the same command names/syntax as @xref{at91sam3}.
6107 The AT91SAM4L driver adds some additional commands:
6108 @deffn {Command} {at91sam4l smap_reset_deassert}
6109 This command releases internal reset held by SMAP
6110 and prepares reset vector catch in case of reset halt.
6111 Command is used internally in event reset-deassert-post.
6116 @deffn {Flash Driver} {atsame5}
6118 All members of the SAM E54, E53, E51 and D51 microcontroller
6119 families from Microchip (former Atmel) include internal flash
6120 and use ARM's Cortex-M4 core.
6122 The devices have two ECC flash banks with a swapping feature.
6123 This driver handles both banks together as it were one.
6124 Bank swapping is not supported yet.
6127 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
6130 @deffn {Command} {atsame5 bootloader}
6131 Shows or sets the bootloader size configuration, stored in the User Page of the
6132 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6133 must be specified in bytes. The nearest bigger protection size is used.
6134 Settings are written immediately but only take effect on MCU reset.
6135 Setting the bootloader size to 0 disables bootloader protection.
6139 atsame5 bootloader 16384
6143 @deffn {Command} {atsame5 chip-erase}
6144 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6145 used to erase a chip back to its factory state and does not require the
6146 processor to be halted.
6149 @deffn {Command} {atsame5 dsu_reset_deassert}
6150 This command releases internal reset held by DSU
6151 and prepares reset vector catch in case of reset halt.
6152 Command is used internally in event reset-deassert-post.
6155 @deffn {Command} {atsame5 userpage}
6156 Writes or reads the first 64 bits of NVM User Page which is located at
6157 0x804000. This field includes various fuses.
6158 Reading is done by invoking this command without any arguments.
6159 Writing is possible by giving 1 or 2 hex values. The first argument
6160 is the value to be written and the second one is an optional bit mask
6161 (a zero bit in the mask means the bit stays unchanged).
6162 The reserved fields are always masked out and cannot be changed.
6167 USER PAGE: 0xAEECFF80FE9A9239
6169 >atsame5 userpage 0xAEECFF80FE9A9239
6170 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other
6171 # bits unchanged (setup SmartEEPROM of virtual size 8192
6173 >atsame5 userpage 0x4200000000 0x7f00000000
6179 @deffn {Flash Driver} {atsamv}
6181 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
6182 Atmel include internal flash and use ARM's Cortex-M7 core.
6183 This driver uses the same command names/syntax as @xref{at91sam3}.
6186 @deffn {Flash Driver} {at91sam7}
6187 All members of the AT91SAM7 microcontroller family from Atmel include
6188 internal flash and use ARM7TDMI cores. The driver automatically
6189 recognizes a number of these chips using the chip identification
6190 register, and autoconfigures itself.
6193 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
6196 For chips which are not recognized by the controller driver, you must
6197 provide additional parameters in the following order:
6200 @item @var{chip_model} ... label used with @command{flash info}
6202 @item @var{sectors_per_bank}
6203 @item @var{pages_per_sector}
6204 @item @var{pages_size}
6205 @item @var{num_nvm_bits}
6206 @item @var{freq_khz} ... required if an external clock is provided,
6207 optional (but recommended) when the oscillator frequency is known
6210 It is recommended that you provide zeroes for all of those values
6211 except the clock frequency, so that everything except that frequency
6212 will be autoconfigured.
6213 Knowing the frequency helps ensure correct timings for flash access.
6215 The flash controller handles erases automatically on a page (128/256 byte)
6216 basis, so explicit erase commands are not necessary for flash programming.
6217 However, there is an ``EraseAll`` command that can erase an entire flash
6218 plane (of up to 256KB), and it will be used automatically when you issue
6219 @command{flash erase_sector} or @command{flash erase_address} commands.
6221 @deffn {Command} {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
6222 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
6223 bit for the processor. Each processor has a number of such bits,
6224 used for controlling features such as brownout detection (so they
6225 are not truly general purpose).
6227 This assumes that the first flash bank (number 0) is associated with
6228 the appropriate at91sam7 target.
6233 @deffn {Flash Driver} {avr}
6234 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
6235 @emph{The current implementation is incomplete.}
6236 @comment - defines mass_erase ... pointless given flash_erase_address
6239 @deffn {Flash Driver} {bluenrg-x}
6240 STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
6241 The driver automatically recognizes these chips using
6242 the chip identification registers, and autoconfigures itself.
6245 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
6248 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
6249 each single sector one by one.
6252 flash erase_sector 0 0 last # It will perform a mass erase
6255 Triggering a mass erase is also useful when users want to disable readout protection.
6258 @deffn {Flash Driver} {cc26xx}
6259 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
6260 Instruments include internal flash. The cc26xx flash driver supports both the
6261 CC13xx and CC26xx family of devices. The driver automatically recognizes the
6262 specific version's flash parameters and autoconfigures itself. The flash bank
6263 starts at address 0.
6266 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
6270 @deffn {Flash Driver} {cc3220sf}
6271 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
6272 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
6273 supports the internal flash. The serial flash on SimpleLink boards is
6274 programmed via the bootloader over a UART connection. Security features of
6275 the CC3220SF may erase the internal flash during power on reset. Refer to
6276 documentation at @url{www.ti.com/cc3220sf} for details on security features
6277 and programming the serial flash.
6280 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
6284 @deffn {Flash Driver} {efm32}
6285 All members of the EFM32 microcontroller family from Energy Micro include
6286 internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
6287 a number of these chips using the chip identification register, and
6288 autoconfigures itself.
6290 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
6292 A special feature of efm32 controllers is that it is possible to completely disable the
6293 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
6294 this via the following command:
6298 The @var{num} parameter is a value shown by @command{flash banks}.
6299 Note that in order for this command to take effect, the target needs to be reset.
6300 @emph{The current implementation is incomplete. Unprotecting flash pages is not
6304 @deffn {Flash Driver} {esirisc}
6305 Members of the eSi-RISC family may optionally include internal flash programmed
6306 via the eSi-TSMC Flash interface. Additional parameters are required to
6307 configure the driver: @option{cfg_address} is the base address of the
6308 configuration register interface, @option{clock_hz} is the expected clock
6309 frequency, and @option{wait_states} is the number of configured read wait states.
6312 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
6313 $_TARGETNAME cfg_address clock_hz wait_states
6316 @deffn {Command} {esirisc flash mass_erase} bank_id
6317 Erase all pages in data memory for the bank identified by @option{bank_id}.
6320 @deffn {Command} {esirisc flash ref_erase} bank_id
6321 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
6322 is an uncommon operation.}
6326 @deffn {Flash Driver} {fm3}
6327 All members of the FM3 microcontroller family from Fujitsu
6328 include internal flash and use ARM Cortex-M3 cores.
6329 The @var{fm3} driver uses the @var{target} parameter to select the
6330 correct bank config, it can currently be one of the following:
6331 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
6332 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
6335 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
6339 @deffn {Flash Driver} {fm4}
6340 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
6341 include internal flash and use ARM Cortex-M4 cores.
6342 The @var{fm4} driver uses a @var{family} parameter to select the
6343 correct bank config, it can currently be one of the following:
6344 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
6345 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
6346 with @code{x} treated as wildcard and otherwise case (and any trailing
6347 characters) ignored.
6350 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
6351 $_TARGETNAME S6E2CCAJ0A
6352 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
6353 $_TARGETNAME S6E2CCAJ0A
6355 @emph{The current implementation is incomplete. Protection is not supported,
6356 nor is Chip Erase (only Sector Erase is implemented).}
6359 @deffn {Flash Driver} {kinetis}
6361 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
6362 from NXP (former Freescale) include
6363 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
6364 recognizes flash size and a number of flash banks (1-4) using the chip
6365 identification register, and autoconfigures itself.
6366 Use kinetis_ke driver for KE0x and KEAx devices.
6368 The @var{kinetis} driver defines option:
6370 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
6374 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
6377 @deffn {Config Command} {kinetis create_banks}
6378 Configuration command enables automatic creation of additional flash banks
6379 based on real flash layout of device. Banks are created during device probe.
6380 Use 'flash probe 0' to force probe.
6383 @deffn {Command} {kinetis fcf_source} [protection|write]
6384 Select what source is used when writing to a Flash Configuration Field.
6385 @option{protection} mode builds FCF content from protection bits previously
6386 set by 'flash protect' command.
6387 This mode is default. MCU is protected from unwanted locking by immediate
6388 writing FCF after erase of relevant sector.
6389 @option{write} mode enables direct write to FCF.
6390 Protection cannot be set by 'flash protect' command. FCF is written along
6391 with the rest of a flash image.
6392 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
6395 @deffn {Command} {kinetis fopt} [num]
6396 Set value to write to FOPT byte of Flash Configuration Field.
6397 Used in kinetis 'fcf_source protection' mode only.
6400 @deffn {Command} {kinetis mdm check_security}
6401 Checks status of device security lock. Used internally in examine-end
6402 and examine-fail event.
6405 @deffn {Command} {kinetis mdm halt}
6406 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
6407 loop when connecting to an unsecured target.
6410 @deffn {Command} {kinetis mdm mass_erase}
6411 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
6412 back to its factory state, removing security. It does not require the processor
6413 to be halted, however the target will remain in a halted state after this
6417 @deffn {Command} {kinetis nvm_partition}
6418 For FlexNVM devices only (KxxDX and KxxFX).
6419 Command shows or sets data flash or EEPROM backup size in kilobytes,
6420 sets two EEPROM blocks sizes in bytes and enables/disables loading
6421 of EEPROM contents to FlexRAM during reset.
6423 For details see device reference manual, Flash Memory Module,
6424 Program Partition command.
6426 Setting is possible only once after mass_erase.
6427 Reset the device after partition setting.
6429 Show partition size:
6431 kinetis nvm_partition info
6434 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
6435 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
6437 kinetis nvm_partition dataflash 32 512 1536 on
6440 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
6441 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
6443 kinetis nvm_partition eebkp 16 1024 1024 off
6447 @deffn {Command} {kinetis mdm reset}
6448 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
6449 RESET pin, which can be used to reset other hardware on board.
6452 @deffn {Command} {kinetis disable_wdog}
6453 For Kx devices only (KLx has different COP watchdog, it is not supported).
6454 Command disables watchdog timer.
6458 @deffn {Flash Driver} {kinetis_ke}
6460 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
6461 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
6462 the KE0x sub-family using the chip identification register, and
6463 autoconfigures itself.
6464 Use kinetis (not kinetis_ke) driver for KE1x devices.
6467 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
6470 @deffn {Command} {kinetis_ke mdm check_security}
6471 Checks status of device security lock. Used internally in examine-end event.
6474 @deffn {Command} {kinetis_ke mdm mass_erase}
6475 Issues a complete Flash erase via the MDM-AP.
6476 This can be used to erase a chip back to its factory state.
6477 Command removes security lock from a device (use of SRST highly recommended).
6478 It does not require the processor to be halted.
6481 @deffn {Command} {kinetis_ke disable_wdog}
6482 Command disables watchdog timer.
6486 @deffn {Flash Driver} {lpc2000}
6487 This is the driver to support internal flash of all members of the
6488 LPC11(x)00 and LPC1300 microcontroller families and most members of
6489 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6490 LPC8Nxx and NHS31xx microcontroller families from NXP.
6493 There are LPC2000 devices which are not supported by the @var{lpc2000}
6495 The LPC2888 is supported by the @var{lpc288x} driver.
6496 The LPC29xx family is supported by the @var{lpc2900} driver.
6499 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6500 which must appear in the following order:
6503 @item @var{variant} ... required, may be
6504 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6505 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6506 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6507 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6509 @option{lpc800} (LPC8xx)
6510 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6511 @option{lpc1500} (LPC15xx)
6512 @option{lpc54100} (LPC541xx)
6513 @option{lpc4000} (LPC40xx)
6514 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6515 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6516 @item @var{clock_kHz} ... the frequency, in kiloHertz,
6517 at which the core is running
6518 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
6519 telling the driver to calculate a valid checksum for the exception vector table.
6521 If you don't provide @option{calc_checksum} when you're writing the vector
6522 table, the boot ROM will almost certainly ignore your flash image.
6523 However, if you do provide it,
6524 with most tool chains @command{verify_image} will fail.
6526 @item @option{iap_entry} ... optional telling the driver to use a different
6527 ROM IAP entry point.
6530 LPC flashes don't require the chip and bus width to be specified.
6533 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
6534 lpc2000_v2 14765 calc_checksum
6537 @deffn {Command} {lpc2000 part_id} bank
6538 Displays the four byte part identifier associated with
6539 the specified flash @var{bank}.
6543 @deffn {Flash Driver} {lpc288x}
6544 The LPC2888 microcontroller from NXP needs slightly different flash
6545 support from its lpc2000 siblings.
6546 The @var{lpc288x} driver defines one mandatory parameter,
6547 the programming clock rate in Hz.
6548 LPC flashes don't require the chip and bus width to be specified.
6551 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
6555 @deffn {Flash Driver} {lpc2900}
6556 This driver supports the LPC29xx ARM968E based microcontroller family
6559 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
6560 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
6561 sector layout are auto-configured by the driver.
6562 The driver has one additional mandatory parameter: The CPU clock rate
6563 (in kHz) at the time the flash operations will take place. Most of the time this
6564 will not be the crystal frequency, but a higher PLL frequency. The
6565 @code{reset-init} event handler in the board script is usually the place where
6568 The driver rejects flashless devices (currently the LPC2930).
6570 The EEPROM in LPC2900 devices is not mapped directly into the address space.
6571 It must be handled much more like NAND flash memory, and will therefore be
6572 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
6574 Sector protection in terms of the LPC2900 is handled transparently. Every time a
6575 sector needs to be erased or programmed, it is automatically unprotected.
6576 What is shown as protection status in the @code{flash info} command, is
6577 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
6578 sector from ever being erased or programmed again. As this is an irreversible
6579 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
6580 and not by the standard @code{flash protect} command.
6582 Example for a 125 MHz clock frequency:
6584 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
6587 Some @code{lpc2900}-specific commands are defined. In the following command list,
6588 the @var{bank} parameter is the bank number as obtained by the
6589 @code{flash banks} command.
6591 @deffn {Command} {lpc2900 signature} bank
6592 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
6593 content. This is a hardware feature of the flash block, hence the calculation is
6594 very fast. You may use this to verify the content of a programmed device against
6599 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
6603 @deffn {Command} {lpc2900 read_custom} bank filename
6604 Reads the 912 bytes of customer information from the flash index sector, and
6605 saves it to a file in binary format.
6608 lpc2900 read_custom 0 /path_to/customer_info.bin
6612 The index sector of the flash is a @emph{write-only} sector. It cannot be
6613 erased! In order to guard against unintentional write access, all following
6614 commands need to be preceded by a successful call to the @code{password}
6617 @deffn {Command} {lpc2900 password} bank password
6618 You need to use this command right before each of the following commands:
6619 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
6620 @code{lpc2900 secure_jtag}.
6622 The password string is fixed to "I_know_what_I_am_doing".
6625 lpc2900 password 0 I_know_what_I_am_doing
6626 Potentially dangerous operation allowed in next command!
6630 @deffn {Command} {lpc2900 write_custom} bank filename type
6631 Writes the content of the file into the customer info space of the flash index
6632 sector. The filetype can be specified with the @var{type} field. Possible values
6633 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
6634 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
6635 contain a single section, and the contained data length must be exactly
6637 @quotation Attention
6638 This cannot be reverted! Be careful!
6642 lpc2900 write_custom 0 /path_to/customer_info.bin bin
6646 @deffn {Command} {lpc2900 secure_sector} bank first last
6647 Secures the sector range from @var{first} to @var{last} (including) against
6648 further program and erase operations. The sector security will be effective
6649 after the next power cycle.
6650 @quotation Attention
6651 This cannot be reverted! Be careful!
6653 Secured sectors appear as @emph{protected} in the @code{flash info} command.
6656 lpc2900 secure_sector 0 1 1
6658 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
6659 # 0: 0x00000000 (0x2000 8kB) not protected
6660 # 1: 0x00002000 (0x2000 8kB) protected
6661 # 2: 0x00004000 (0x2000 8kB) not protected
6665 @deffn {Command} {lpc2900 secure_jtag} bank
6666 Irreversibly disable the JTAG port. The new JTAG security setting will be
6667 effective after the next power cycle.
6668 @quotation Attention
6669 This cannot be reverted! Be careful!
6673 lpc2900 secure_jtag 0
6678 @deffn {Flash Driver} {mdr}
6679 This drivers handles the integrated NOR flash on Milandr Cortex-M
6680 based controllers. A known limitation is that the Info memory can't be
6681 read or verified as it's not memory mapped.
6684 flash bank <name> mdr <base> <size> \
6685 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
6689 @item @var{type} - 0 for main memory, 1 for info memory
6690 @item @var{page_count} - total number of pages
6691 @item @var{sec_count} - number of sector per page count
6696 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
6697 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
6698 0 0 $_TARGETNAME 1 1 4
6700 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
6701 0 0 $_TARGETNAME 0 32 4
6706 @deffn {Flash Driver} {msp432}
6707 All versions of the SimpleLink MSP432 microcontrollers from Texas
6708 Instruments include internal flash. The msp432 flash driver automatically
6709 recognizes the specific version's flash parameters and autoconfigures itself.
6710 Main program flash starts at address 0. The information flash region on
6711 MSP432P4 versions starts at address 0x200000.
6714 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
6717 @deffn {Command} {msp432 mass_erase} bank_id [main|all]
6718 Performs a complete erase of flash. By default, @command{mass_erase} will erase
6719 only the main program flash.
6721 On MSP432P4 versions, using @command{mass_erase all} will erase both the
6722 main program and information flash regions. To also erase the BSL in information
6723 flash, the user must first use the @command{bsl} command.
6726 @deffn {Command} {msp432 bsl} bank_id [unlock|lock]
6727 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
6728 region in information flash so that flash commands can erase or write the BSL.
6729 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
6731 To erase and program the BSL:
6734 flash erase_address 0x202000 0x2000
6735 flash write_image bsl.bin 0x202000
6741 @deffn {Flash Driver} {niietcm4}
6742 This drivers handles the integrated NOR flash on NIIET Cortex-M4
6743 based controllers. Flash size and sector layout are auto-configured by the driver.
6744 Main flash memory is called "Bootflash" and has main region and info region.
6745 Info region is NOT memory mapped by default,
6746 but it can replace first part of main region if needed.
6747 Full erase, single and block writes are supported for both main and info regions.
6748 There is additional not memory mapped flash called "Userflash", which
6749 also have division into regions: main and info.
6750 Purpose of userflash - to store system and user settings.
6751 Driver has special commands to perform operations with this memory.
6754 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
6757 Some niietcm4-specific commands are defined:
6759 @deffn {Command} {niietcm4 uflash_read_byte} bank ('main'|'info') address
6760 Read byte from main or info userflash region.
6763 @deffn {Command} {niietcm4 uflash_write_byte} bank ('main'|'info') address value
6764 Write byte to main or info userflash region.
6767 @deffn {Command} {niietcm4 uflash_full_erase} bank
6768 Erase all userflash including info region.
6771 @deffn {Command} {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
6772 Erase sectors of main or info userflash region, starting at sector first up to and including last.
6775 @deffn {Command} {niietcm4 uflash_protect_check} bank ('main'|'info')
6776 Check sectors protect.
6779 @deffn {Command} {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
6780 Protect sectors of main or info userflash region, starting at sector first up to and including last.
6783 @deffn {Command} {niietcm4 bflash_info_remap} bank ('on'|'off')
6784 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
6787 @deffn {Command} {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
6788 Configure external memory interface for boot.
6791 @deffn {Command} {niietcm4 service_mode_erase} bank
6792 Perform emergency erase of all flash (bootflash and userflash).
6795 @deffn {Command} {niietcm4 driver_info} bank
6796 Show information about flash driver.
6801 @deffn {Flash Driver} {npcx}
6802 All versions of the NPCX microcontroller families from Nuvoton include internal
6803 flash. The NPCX flash driver supports the NPCX family of devices. The driver
6804 automatically recognizes the specific version's flash parameters and
6805 autoconfigures itself. The flash bank starts at address 0x64000000.
6808 flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
6812 @deffn {Flash Driver} {nrf5}
6813 All members of the nRF51 microcontroller families from Nordic Semiconductor
6814 include internal flash and use ARM Cortex-M0 core.
6815 Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
6816 internal flash and use an ARM Cortex-M4F core.
6819 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
6822 Some nrf5-specific commands are defined:
6824 @deffn {Command} {nrf5 mass_erase}
6825 Erases the contents of the code memory and user information
6826 configuration registers as well. It must be noted that this command
6827 works only for chips that do not have factory pre-programmed region 0
6831 @deffn {Command} {nrf5 info}
6832 Decodes and shows information from FICR and UICR registers.
6837 @deffn {Flash Driver} {ocl}
6838 This driver is an implementation of the ``on chip flash loader''
6839 protocol proposed by Pavel Chromy.
6841 It is a minimalistic command-response protocol intended to be used
6842 over a DCC when communicating with an internal or external flash
6843 loader running from RAM. An example implementation for AT91SAM7x is
6844 available in @file{contrib/loaders/flash/at91sam7x/}.
6847 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
6851 @deffn {Flash Driver} {pic32mx}
6852 The PIC32MX microcontrollers are based on the MIPS 4K cores,
6853 and integrate flash memory.
6856 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
6857 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
6860 @comment numerous *disabled* commands are defined:
6861 @comment - chip_erase ... pointless given flash_erase_address
6862 @comment - lock, unlock ... pointless given protect on/off (yes?)
6863 @comment - pgm_word ... shouldn't bank be deduced from address??
6864 Some pic32mx-specific commands are defined:
6865 @deffn {Command} {pic32mx pgm_word} address value bank
6866 Programs the specified 32-bit @var{value} at the given @var{address}
6867 in the specified chip @var{bank}.
6869 @deffn {Command} {pic32mx unlock} bank
6870 Unlock and erase specified chip @var{bank}.
6871 This will remove any Code Protection.
6875 @deffn {Flash Driver} {psoc4}
6876 All members of the PSoC 41xx/42xx microcontroller family from Cypress
6877 include internal flash and use ARM Cortex-M0 cores.
6878 The driver automatically recognizes a number of these chips using
6879 the chip identification register, and autoconfigures itself.
6881 Note: Erased internal flash reads as 00.
6882 System ROM of PSoC 4 does not implement erase of a flash sector.
6885 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
6888 psoc4-specific commands
6889 @deffn {Command} {psoc4 flash_autoerase} num (on|off)
6890 Enables or disables autoerase mode for a flash bank.
6892 If flash_autoerase is off, use mass_erase before flash programming.
6893 Flash erase command fails if region to erase is not whole flash memory.
6895 If flash_autoerase is on, a sector is both erased and programmed in one
6896 system ROM call. Flash erase command is ignored.
6897 This mode is suitable for gdb load.
6899 The @var{num} parameter is a value shown by @command{flash banks}.
6902 @deffn {Command} {psoc4 mass_erase} num
6903 Erases the contents of the flash memory, protection and security lock.
6905 The @var{num} parameter is a value shown by @command{flash banks}.
6909 @deffn {Flash Driver} {psoc5lp}
6910 All members of the PSoC 5LP microcontroller family from Cypress
6911 include internal program flash and use ARM Cortex-M3 cores.
6912 The driver probes for a number of these chips and autoconfigures itself,
6913 apart from the base address.
6916 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
6919 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
6920 @quotation Attention
6921 If flash operations are performed in ECC-disabled mode, they will also affect
6922 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
6923 then also erase the corresponding 2k data bytes in the 0x48000000 area.
6924 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
6927 Commands defined in the @var{psoc5lp} driver:
6929 @deffn {Command} {psoc5lp mass_erase}
6930 Erases all flash data and ECC/configuration bytes, all flash protection rows,
6931 and all row latches in all flash arrays on the device.
6935 @deffn {Flash Driver} {psoc5lp_eeprom}
6936 All members of the PSoC 5LP microcontroller family from Cypress
6937 include internal EEPROM and use ARM Cortex-M3 cores.
6938 The driver probes for a number of these chips and autoconfigures itself,
6939 apart from the base address.
6942 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
6947 @deffn {Flash Driver} {psoc5lp_nvl}
6948 All members of the PSoC 5LP microcontroller family from Cypress
6949 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
6950 The driver probes for a number of these chips and autoconfigures itself.
6953 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
6956 PSoC 5LP chips have multiple NV Latches:
6959 @item Device Configuration NV Latch - 4 bytes
6960 @item Write Once (WO) NV Latch - 4 bytes
6963 @b{Note:} This driver only implements the Device Configuration NVL.
6965 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
6966 @quotation Attention
6967 Switching ECC mode via write to Device Configuration NVL will require a reset
6968 after successful write.
6972 @deffn {Flash Driver} {psoc6}
6973 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
6974 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
6975 the same Flash/RAM/MMIO address space.
6977 Flash in PSoC6 is split into three regions:
6979 @item Main Flash - this is the main storage for user application.
6980 Total size varies among devices, sector size: 256 kBytes, row size:
6981 512 bytes. Supports erase operation on individual rows.
6982 @item Work Flash - intended to be used as storage for user data
6983 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
6984 row size: 512 bytes.
6985 @item Supervisory Flash - special region which contains device-specific
6986 service data. This region does not support erase operation. Only few rows can
6987 be programmed by the user, most of the rows are read only. Programming
6988 operation will erase row automatically.
6991 All three flash regions are supported by the driver. Flash geometry is detected
6992 automatically by parsing data in SPCIF_GEOMETRY register.
6994 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
6997 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 \
6999 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 \
7001 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 \
7003 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 \
7005 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 \
7007 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 \
7010 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 \
7012 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 \
7014 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 \
7016 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 \
7018 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 \
7020 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \
7024 psoc6-specific commands
7025 @deffn {Command} {psoc6 reset_halt}
7026 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
7027 When invoked for CM0+ target, it will set break point at application entry point
7028 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
7029 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
7030 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
7033 @deffn {Command} {psoc6 mass_erase} num
7034 Erases the contents given flash bank. The @var{num} parameter is a value shown
7035 by @command{flash banks}.
7036 Note: only Main and Work flash regions support Erase operation.
7040 @deffn {Flash Driver} {rp2040}
7041 Supports RP2040 "Raspberry Pi Pico" microcontroller.
7042 RP2040 is a dual-core device with two CM0+ cores. Both cores share the same
7043 Flash/RAM/MMIO address space. Non-volatile storage is achieved with an
7044 external QSPI flash; a Boot ROM provides helper functions.
7047 flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
7051 @deffn {Flash Driver} {sim3x}
7052 All members of the SiM3 microcontroller family from Silicon Laboratories
7053 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
7055 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
7056 If this fails, it will use the @var{size} parameter as the size of flash bank.
7059 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
7062 There are 2 commands defined in the @var{sim3x} driver:
7064 @deffn {Command} {sim3x mass_erase}
7065 Erases the complete flash. This is used to unlock the flash.
7066 And this command is only possible when using the SWD interface.
7069 @deffn {Command} {sim3x lock}
7070 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
7074 @deffn {Flash Driver} {stellaris}
7075 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
7076 families from Texas Instruments include internal flash. The driver
7077 automatically recognizes a number of these chips using the chip
7078 identification register, and autoconfigures itself.
7081 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
7084 @deffn {Command} {stellaris recover}
7085 Performs the @emph{Recovering a "Locked" Device} procedure to restore
7086 the flash and its associated nonvolatile registers to their factory
7087 default values (erased). This is the only way to remove flash
7088 protection or re-enable debugging if that capability has been
7091 Note that the final "power cycle the chip" step in this procedure
7092 must be performed by hand, since OpenOCD can't do it.
7094 if more than one Stellaris chip is connected, the procedure is
7095 applied to all of them.
7100 @deffn {Flash Driver} {stm32f1x}
7101 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
7102 from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller
7103 families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores.
7104 The driver automatically recognizes a number of these chips using
7105 the chip identification register, and autoconfigures itself.
7108 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
7111 Note that some devices have been found that have a flash size register that contains
7112 an invalid value, to workaround this issue you can override the probed value used by
7116 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
7119 If you have a target with dual flash banks then define the second bank
7120 as per the following example.
7122 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
7125 Some stm32f1x-specific commands are defined:
7127 @deffn {Command} {stm32f1x lock} num
7128 Locks the entire stm32 device against reading.
7129 The @var{num} parameter is a value shown by @command{flash banks}.
7132 @deffn {Command} {stm32f1x unlock} num
7133 Unlocks the entire stm32 device for reading. This command will cause
7134 a mass erase of the entire stm32 device if previously locked.
7135 The @var{num} parameter is a value shown by @command{flash banks}.
7138 @deffn {Command} {stm32f1x mass_erase} num
7139 Mass erases the entire stm32 device.
7140 The @var{num} parameter is a value shown by @command{flash banks}.
7143 @deffn {Command} {stm32f1x options_read} num
7144 Reads and displays active stm32 option bytes loaded during POR
7145 or upon executing the @command{stm32f1x options_load} command.
7146 The @var{num} parameter is a value shown by @command{flash banks}.
7149 @deffn {Command} {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
7150 Writes the stm32 option byte with the specified values.
7151 The @var{num} parameter is a value shown by @command{flash banks}.
7152 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
7155 @deffn {Command} {stm32f1x options_load} num
7156 Generates a special kind of reset to re-load the stm32 option bytes written
7157 by the @command{stm32f1x options_write} or @command{flash protect} commands
7158 without having to power cycle the target. Not applicable to stm32f1x devices.
7159 The @var{num} parameter is a value shown by @command{flash banks}.
7163 @deffn {Flash Driver} {stm32f2x}
7164 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
7165 include internal flash and use ARM Cortex-M3/M4/M7 cores.
7166 The driver automatically recognizes a number of these chips using
7167 the chip identification register, and autoconfigures itself.
7170 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
7173 If you use OTP (One-Time Programmable) memory define it as a second bank
7174 as per the following example.
7176 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
7179 @deffn {Command} {stm32f2x otp} num (@option{enable}|@option{disable}|@option{show})
7180 Enables or disables OTP write commands for bank @var{num}.
7181 The @var{num} parameter is a value shown by @command{flash banks}.
7184 Note that some devices have been found that have a flash size register that contains
7185 an invalid value, to workaround this issue you can override the probed value used by
7189 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
7192 Some stm32f2x-specific commands are defined:
7194 @deffn {Command} {stm32f2x lock} num
7195 Locks the entire stm32 device.
7196 The @var{num} parameter is a value shown by @command{flash banks}.
7199 @deffn {Command} {stm32f2x unlock} num
7200 Unlocks the entire stm32 device.
7201 The @var{num} parameter is a value shown by @command{flash banks}.
7204 @deffn {Command} {stm32f2x mass_erase} num
7205 Mass erases the entire stm32f2x device.
7206 The @var{num} parameter is a value shown by @command{flash banks}.
7209 @deffn {Command} {stm32f2x options_read} num
7210 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
7211 The @var{num} parameter is a value shown by @command{flash banks}.
7214 @deffn {Command} {stm32f2x options_write} num user_options boot_addr0 boot_addr1
7215 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
7216 Warning: The meaning of the various bits depends on the device, always check datasheet!
7217 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
7218 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
7219 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
7222 @deffn {Command} {stm32f2x optcr2_write} num optcr2
7223 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
7224 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
7228 @deffn {Flash Driver} {stm32h7x}
7229 All members of the STM32H7 microcontroller families from STMicroelectronics
7230 include internal flash and use ARM Cortex-M7 core.
7231 The driver automatically recognizes a number of these chips using
7232 the chip identification register, and autoconfigures itself.
7235 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
7238 Note that some devices have been found that have a flash size register that contains
7239 an invalid value, to workaround this issue you can override the probed value used by
7243 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
7246 Some stm32h7x-specific commands are defined:
7248 @deffn {Command} {stm32h7x lock} num
7249 Locks the entire stm32 device.
7250 The @var{num} parameter is a value shown by @command{flash banks}.
7253 @deffn {Command} {stm32h7x unlock} num
7254 Unlocks the entire stm32 device.
7255 The @var{num} parameter is a value shown by @command{flash banks}.
7258 @deffn {Command} {stm32h7x mass_erase} num
7259 Mass erases the entire stm32h7x device.
7260 The @var{num} parameter is a value shown by @command{flash banks}.
7263 @deffn {Command} {stm32h7x option_read} num reg_offset
7264 Reads an option byte register from the stm32h7x device.
7265 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7266 is the register offset of the option byte to read from the used bank registers' base.
7267 For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2.
7272 stm32h7x option_read 0 0x1c
7274 stm32h7x option_read 0 0x38
7276 stm32h7x option_read 1 0x38
7280 @deffn {Command} {stm32h7x option_write} num reg_offset value [reg_mask]
7281 Writes an option byte register of the stm32h7x device.
7282 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7283 is the register offset of the option byte to write from the used bank register base,
7284 and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1'
7289 # swap bank 1 and bank 2 in dual bank devices
7290 # by setting SWAP_BANK_OPT bit in OPTSR_PRG
7291 stm32h7x option_write 0 0x20 0x8000000 0x8000000
7296 @deffn {Flash Driver} {stm32lx}
7297 All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
7298 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
7299 The driver automatically recognizes a number of these chips using
7300 the chip identification register, and autoconfigures itself.
7303 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
7306 Note that some devices have been found that have a flash size register that contains
7307 an invalid value, to workaround this issue you can override the probed value used by
7308 the flash driver. If you use 0 as the bank base address, it tells the
7309 driver to autodetect the bank location assuming you're configuring the
7313 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
7316 Some stm32lx-specific commands are defined:
7318 @deffn {Command} {stm32lx lock} num
7319 Locks the entire stm32 device.
7320 The @var{num} parameter is a value shown by @command{flash banks}.
7323 @deffn {Command} {stm32lx unlock} num
7324 Unlocks the entire stm32 device.
7325 The @var{num} parameter is a value shown by @command{flash banks}.
7328 @deffn {Command} {stm32lx mass_erase} num
7329 Mass erases the entire stm32lx device (all flash banks and EEPROM
7330 data). This is the only way to unlock a protected flash (unless RDP
7331 Level is 2 which can't be unlocked at all).
7332 The @var{num} parameter is a value shown by @command{flash banks}.
7336 @deffn {Flash Driver} {stm32l4x}
7337 All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
7338 microcontroller families from STMicroelectronics include internal flash
7339 and use ARM Cortex-M0+, M4 and M33 cores.
7340 The driver automatically recognizes a number of these chips using
7341 the chip identification register, and autoconfigures itself.
7344 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
7347 If you use OTP (One-Time Programmable) memory define it as a second bank
7348 as per the following example.
7350 flash bank $_FLASHNAME stm32l4x 0x1FFF7000 0 0 0 $_TARGETNAME
7353 @deffn {Command} {stm32l4x otp} num (@option{enable}|@option{disable}|@option{show})
7354 Enables or disables OTP write commands for bank @var{num}.
7355 The @var{num} parameter is a value shown by @command{flash banks}.
7358 Note that some devices have been found that have a flash size register that contains
7359 an invalid value, to workaround this issue you can override the probed value used by
7360 the flash driver. However, specifying a wrong value might lead to a completely
7361 wrong flash layout, so this feature must be used carefully.
7364 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
7367 Some stm32l4x-specific commands are defined:
7369 @deffn {Command} {stm32l4x lock} num
7370 Locks the entire stm32 device.
7371 The @var{num} parameter is a value shown by @command{flash banks}.
7373 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7376 @deffn {Command} {stm32l4x unlock} num
7377 Unlocks the entire stm32 device.
7378 The @var{num} parameter is a value shown by @command{flash banks}.
7380 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7383 @deffn {Command} {stm32l4x mass_erase} num
7384 Mass erases the entire stm32l4x device.
7385 The @var{num} parameter is a value shown by @command{flash banks}.
7388 @deffn {Command} {stm32l4x option_read} num reg_offset
7389 Reads an option byte register from the stm32l4x device.
7390 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7391 is the register offset of the Option byte to read.
7393 For example to read the FLASH_OPTR register:
7395 stm32l4x option_read 0 0x20
7396 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
7397 # Option Register (for STM32WBx): <0x58004020> = ...
7398 # The correct flash base address will be used automatically
7401 The above example will read out the FLASH_OPTR register which contains the RDP
7402 option byte, Watchdog configuration, BOR level etc.
7405 @deffn {Command} {stm32l4x option_write} num reg_offset reg_mask
7406 Write an option byte register of the stm32l4x device.
7407 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7408 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
7409 to apply when writing the register (only bits with a '1' will be touched).
7411 @emph{Note:} To apply the option bytes change immediately, use @command{stm32l4x option_load}.
7413 For example to write the WRP1AR option bytes:
7415 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
7418 The above example will write the WRP1AR option register configuring the Write protection
7419 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
7420 This will effectively write protect all sectors in flash bank 1.
7423 @deffn {Command} {stm32l4x wrp_info} num [device_bank]
7424 List the protected areas using WRP.
7425 The @var{num} parameter is a value shown by @command{flash banks}.
7426 @var{device_bank} parameter is optional, possible values 'bank1' or 'bank2',
7427 if not specified, the command will display the whole flash protected areas.
7429 @b{Note:} @var{device_bank} is different from banks created using @code{flash bank}.
7430 Devices supported in this flash driver, can have main flash memory organized
7431 in single or dual-banks mode.
7432 Thus the usage of @var{device_bank} is meaningful only in dual-bank mode, to get
7433 write protected areas in a specific @var{device_bank}
7437 @deffn {Command} {stm32l4x option_load} num
7438 Forces a re-load of the option byte registers. Will cause a system reset of the device.
7439 The @var{num} parameter is a value shown by @command{flash banks}.
7442 @deffn Command {stm32l4x trustzone} num [@option{enable} | @option{disable}]
7443 Enables or disables Global TrustZone Security, using the TZEN option bit.
7444 If neither @option{enabled} nor @option{disable} are specified, the command will display
7445 the TrustZone status.
7446 @emph{Note:} This command works only with devices with TrustZone, eg. STM32L5.
7447 @emph{Note:} This command will perform an OBL_Launch after modifying the TZEN.
7451 @deffn {Flash Driver} {str7x}
7452 All members of the STR7 microcontroller family from STMicroelectronics
7453 include internal flash and use ARM7TDMI cores.
7454 The @var{str7x} driver defines one mandatory parameter, @var{variant},
7455 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
7458 flash bank $_FLASHNAME str7x \
7459 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
7462 @deffn {Command} {str7x disable_jtag} bank
7463 Activate the Debug/Readout protection mechanism
7464 for the specified flash bank.
7468 @deffn {Flash Driver} {str9x}
7469 Most members of the STR9 microcontroller family from STMicroelectronics
7470 include internal flash and use ARM966E cores.
7471 The str9 needs the flash controller to be configured using
7472 the @command{str9x flash_config} command prior to Flash programming.
7475 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
7476 str9x flash_config 0 4 2 0 0x80000
7479 @deffn {Command} {str9x flash_config} num bbsr nbbsr bbadr nbbadr
7480 Configures the str9 flash controller.
7481 The @var{num} parameter is a value shown by @command{flash banks}.
7484 @item @var{bbsr} - Boot Bank Size register
7485 @item @var{nbbsr} - Non Boot Bank Size register
7486 @item @var{bbadr} - Boot Bank Start Address register
7487 @item @var{nbbadr} - Boot Bank Start Address register
7493 @deffn {Flash Driver} {str9xpec}
7496 Only use this driver for locking/unlocking the device or configuring the option bytes.
7497 Use the standard str9 driver for programming.
7498 Before using the flash commands the turbo mode must be enabled using the
7499 @command{str9xpec enable_turbo} command.
7501 Here is some background info to help
7502 you better understand how this driver works. OpenOCD has two flash drivers for
7506 Standard driver @option{str9x} programmed via the str9 core. Normally used for
7507 flash programming as it is faster than the @option{str9xpec} driver.
7509 Direct programming @option{str9xpec} using the flash controller. This is an
7510 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
7511 core does not need to be running to program using this flash driver. Typical use
7512 for this driver is locking/unlocking the target and programming the option bytes.
7515 Before we run any commands using the @option{str9xpec} driver we must first disable
7516 the str9 core. This example assumes the @option{str9xpec} driver has been
7517 configured for flash bank 0.
7519 # assert srst, we do not want core running
7520 # while accessing str9xpec flash driver
7522 # turn off target polling
7525 str9xpec enable_turbo 0
7527 str9xpec options_read 0
7528 # re-enable str9 core
7529 str9xpec disable_turbo 0
7533 The above example will read the str9 option bytes.
7534 When performing a unlock remember that you will not be able to halt the str9 - it
7535 has been locked. Halting the core is not required for the @option{str9xpec} driver
7536 as mentioned above, just issue the commands above manually or from a telnet prompt.
7538 Several str9xpec-specific commands are defined:
7540 @deffn {Command} {str9xpec disable_turbo} num
7541 Restore the str9 into JTAG chain.
7544 @deffn {Command} {str9xpec enable_turbo} num
7545 Enable turbo mode, will simply remove the str9 from the chain and talk
7546 directly to the embedded flash controller.
7549 @deffn {Command} {str9xpec lock} num
7550 Lock str9 device. The str9 will only respond to an unlock command that will
7554 @deffn {Command} {str9xpec part_id} num
7555 Prints the part identifier for bank @var{num}.
7558 @deffn {Command} {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
7559 Configure str9 boot bank.
7562 @deffn {Command} {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
7563 Configure str9 lvd source.
7566 @deffn {Command} {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
7567 Configure str9 lvd threshold.
7570 @deffn {Command} {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
7571 Configure str9 lvd reset warning source.
7574 @deffn {Command} {str9xpec options_read} num
7575 Read str9 option bytes.
7578 @deffn {Command} {str9xpec options_write} num
7579 Write str9 option bytes.
7582 @deffn {Command} {str9xpec unlock} num
7588 @deffn {Flash Driver} {swm050}
7590 All members of the swm050 microcontroller family from Foshan Synwit Tech.
7593 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
7596 One swm050-specific command is defined:
7598 @deffn {Command} {swm050 mass_erase} bank_id
7599 Erases the entire flash bank.
7605 @deffn {Flash Driver} {tms470}
7606 Most members of the TMS470 microcontroller family from Texas Instruments
7607 include internal flash and use ARM7TDMI cores.
7608 This driver doesn't require the chip and bus width to be specified.
7610 Some tms470-specific commands are defined:
7612 @deffn {Command} {tms470 flash_keyset} key0 key1 key2 key3
7613 Saves programming keys in a register, to enable flash erase and write commands.
7616 @deffn {Command} {tms470 osc_megahertz} clock_mhz
7617 Reports the clock speed, which is used to calculate timings.
7620 @deffn {Command} {tms470 plldis} (0|1)
7621 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
7626 @deffn {Flash Driver} {w600}
7627 W60x series Wi-Fi SoC from WinnerMicro
7628 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
7629 The @var{w600} driver uses the @var{target} parameter to select the
7630 correct bank config.
7633 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
7637 @deffn {Flash Driver} {xmc1xxx}
7638 All members of the XMC1xxx microcontroller family from Infineon.
7639 This driver does not require the chip and bus width to be specified.
7642 @deffn {Flash Driver} {xmc4xxx}
7643 All members of the XMC4xxx microcontroller family from Infineon.
7644 This driver does not require the chip and bus width to be specified.
7646 Some xmc4xxx-specific commands are defined:
7648 @deffn {Command} {xmc4xxx flash_password} bank_id passwd1 passwd2
7649 Saves flash protection passwords which are used to lock the user flash
7652 @deffn {Command} {xmc4xxx flash_unprotect} bank_id user_level[0-1]
7653 Removes Flash write protection from the selected user bank
7658 @section NAND Flash Commands
7661 Compared to NOR or SPI flash, NAND devices are inexpensive
7662 and high density. Today's NAND chips, and multi-chip modules,
7663 commonly hold multiple GigaBytes of data.
7665 NAND chips consist of a number of ``erase blocks'' of a given
7666 size (such as 128 KBytes), each of which is divided into a
7667 number of pages (of perhaps 512 or 2048 bytes each). Each
7668 page of a NAND flash has an ``out of band'' (OOB) area to hold
7669 Error Correcting Code (ECC) and other metadata, usually 16 bytes
7670 of OOB for every 512 bytes of page data.
7672 One key characteristic of NAND flash is that its error rate
7673 is higher than that of NOR flash. In normal operation, that
7674 ECC is used to correct and detect errors. However, NAND
7675 blocks can also wear out and become unusable; those blocks
7676 are then marked "bad". NAND chips are even shipped from the
7677 manufacturer with a few bad blocks. The highest density chips
7678 use a technology (MLC) that wears out more quickly, so ECC
7679 support is increasingly important as a way to detect blocks
7680 that have begun to fail, and help to preserve data integrity
7681 with techniques such as wear leveling.
7683 Software is used to manage the ECC. Some controllers don't
7684 support ECC directly; in those cases, software ECC is used.
7685 Other controllers speed up the ECC calculations with hardware.
7686 Single-bit error correction hardware is routine. Controllers
7687 geared for newer MLC chips may correct 4 or more errors for
7688 every 512 bytes of data.
7690 You will need to make sure that any data you write using
7691 OpenOCD includes the appropriate kind of ECC. For example,
7692 that may mean passing the @code{oob_softecc} flag when
7693 writing NAND data, or ensuring that the correct hardware
7696 The basic steps for using NAND devices include:
7698 @item Declare via the command @command{nand device}
7699 @* Do this in a board-specific configuration file,
7700 passing parameters as needed by the controller.
7701 @item Configure each device using @command{nand probe}.
7702 @* Do this only after the associated target is set up,
7703 such as in its reset-init script or in procures defined
7704 to access that device.
7705 @item Operate on the flash via @command{nand subcommand}
7706 @* Often commands to manipulate the flash are typed by a human, or run
7707 via a script in some automated way. Common task include writing a
7708 boot loader, operating system, or other data needed to initialize or
7712 @b{NOTE:} At the time this text was written, the largest NAND
7713 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
7714 This is because the variables used to hold offsets and lengths
7715 are only 32 bits wide.
7716 (Larger chips may work in some cases, unless an offset or length
7717 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
7718 Some larger devices will work, since they are actually multi-chip
7719 modules with two smaller chips and individual chipselect lines.
7721 @anchor{nandconfiguration}
7722 @subsection NAND Configuration Commands
7723 @cindex NAND configuration
7725 NAND chips must be declared in configuration scripts,
7726 plus some additional configuration that's done after
7727 OpenOCD has initialized.
7729 @deffn {Config Command} {nand device} name driver target [configparams...]
7730 Declares a NAND device, which can be read and written to
7731 after it has been configured through @command{nand probe}.
7732 In OpenOCD, devices are single chips; this is unlike some
7733 operating systems, which may manage multiple chips as if
7734 they were a single (larger) device.
7735 In some cases, configuring a device will activate extra
7736 commands; see the controller-specific documentation.
7738 @b{NOTE:} This command is not available after OpenOCD
7739 initialization has completed. Use it in board specific
7740 configuration files, not interactively.
7743 @item @var{name} ... may be used to reference the NAND bank
7744 in most other NAND commands. A number is also available.
7745 @item @var{driver} ... identifies the NAND controller driver
7746 associated with the NAND device being declared.
7747 @xref{nanddriverlist,,NAND Driver List}.
7748 @item @var{target} ... names the target used when issuing
7749 commands to the NAND controller.
7750 @comment Actually, it's currently a controller-specific parameter...
7751 @item @var{configparams} ... controllers may support, or require,
7752 additional parameters. See the controller-specific documentation
7753 for more information.
7757 @deffn {Command} {nand list}
7758 Prints a summary of each device declared
7759 using @command{nand device}, numbered from zero.
7760 Note that un-probed devices show no details.
7763 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7764 blocksize: 131072, blocks: 8192
7765 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7766 blocksize: 131072, blocks: 8192
7771 @deffn {Command} {nand probe} num
7772 Probes the specified device to determine key characteristics
7773 like its page and block sizes, and how many blocks it has.
7774 The @var{num} parameter is the value shown by @command{nand list}.
7775 You must (successfully) probe a device before you can use
7776 it with most other NAND commands.
7779 @subsection Erasing, Reading, Writing to NAND Flash
7781 @deffn {Command} {nand dump} num filename offset length [oob_option]
7782 @cindex NAND reading
7783 Reads binary data from the NAND device and writes it to the file,
7784 starting at the specified offset.
7785 The @var{num} parameter is the value shown by @command{nand list}.
7787 Use a complete path name for @var{filename}, so you don't depend
7788 on the directory used to start the OpenOCD server.
7790 The @var{offset} and @var{length} must be exact multiples of the
7791 device's page size. They describe a data region; the OOB data
7792 associated with each such page may also be accessed.
7794 @b{NOTE:} At the time this text was written, no error correction
7795 was done on the data that's read, unless raw access was disabled
7796 and the underlying NAND controller driver had a @code{read_page}
7797 method which handled that error correction.
7799 By default, only page data is saved to the specified file.
7800 Use an @var{oob_option} parameter to save OOB data:
7802 @item no oob_* parameter
7803 @*Output file holds only page data; OOB is discarded.
7804 @item @code{oob_raw}
7805 @*Output file interleaves page data and OOB data;
7806 the file will be longer than "length" by the size of the
7807 spare areas associated with each data page.
7808 Note that this kind of "raw" access is different from
7809 what's implied by @command{nand raw_access}, which just
7810 controls whether a hardware-aware access method is used.
7811 @item @code{oob_only}
7812 @*Output file has only raw OOB data, and will
7813 be smaller than "length" since it will contain only the
7814 spare areas associated with each data page.
7818 @deffn {Command} {nand erase} num [offset length]
7819 @cindex NAND erasing
7820 @cindex NAND programming
7821 Erases blocks on the specified NAND device, starting at the
7822 specified @var{offset} and continuing for @var{length} bytes.
7823 Both of those values must be exact multiples of the device's
7824 block size, and the region they specify must fit entirely in the chip.
7825 If those parameters are not specified,
7826 the whole NAND chip will be erased.
7827 The @var{num} parameter is the value shown by @command{nand list}.
7829 @b{NOTE:} This command will try to erase bad blocks, when told
7830 to do so, which will probably invalidate the manufacturer's bad
7832 For the remainder of the current server session, @command{nand info}
7833 will still report that the block ``is'' bad.
7836 @deffn {Command} {nand write} num filename offset [option...]
7837 @cindex NAND writing
7838 @cindex NAND programming
7839 Writes binary data from the file into the specified NAND device,
7840 starting at the specified offset. Those pages should already
7841 have been erased; you can't change zero bits to one bits.
7842 The @var{num} parameter is the value shown by @command{nand list}.
7844 Use a complete path name for @var{filename}, so you don't depend
7845 on the directory used to start the OpenOCD server.
7847 The @var{offset} must be an exact multiple of the device's page size.
7848 All data in the file will be written, assuming it doesn't run
7849 past the end of the device.
7850 Only full pages are written, and any extra space in the last
7851 page will be filled with 0xff bytes. (That includes OOB data,
7852 if that's being written.)
7854 @b{NOTE:} At the time this text was written, bad blocks are
7855 ignored. That is, this routine will not skip bad blocks,
7856 but will instead try to write them. This can cause problems.
7858 Provide at most one @var{option} parameter. With some
7859 NAND drivers, the meanings of these parameters may change
7860 if @command{nand raw_access} was used to disable hardware ECC.
7862 @item no oob_* parameter
7863 @*File has only page data, which is written.
7864 If raw access is in use, the OOB area will not be written.
7865 Otherwise, if the underlying NAND controller driver has
7866 a @code{write_page} routine, that routine may write the OOB
7867 with hardware-computed ECC data.
7868 @item @code{oob_only}
7869 @*File has only raw OOB data, which is written to the OOB area.
7870 Each page's data area stays untouched. @i{This can be a dangerous
7871 option}, since it can invalidate the ECC data.
7872 You may need to force raw access to use this mode.
7873 @item @code{oob_raw}
7874 @*File interleaves data and OOB data, both of which are written
7875 If raw access is enabled, the data is written first, then the
7877 Otherwise, if the underlying NAND controller driver has
7878 a @code{write_page} routine, that routine may modify the OOB
7879 before it's written, to include hardware-computed ECC data.
7880 @item @code{oob_softecc}
7881 @*File has only page data, which is written.
7882 The OOB area is filled with 0xff, except for a standard 1-bit
7883 software ECC code stored in conventional locations.
7884 You might need to force raw access to use this mode, to prevent
7885 the underlying driver from applying hardware ECC.
7886 @item @code{oob_softecc_kw}
7887 @*File has only page data, which is written.
7888 The OOB area is filled with 0xff, except for a 4-bit software ECC
7889 specific to the boot ROM in Marvell Kirkwood SoCs.
7890 You might need to force raw access to use this mode, to prevent
7891 the underlying driver from applying hardware ECC.
7895 @deffn {Command} {nand verify} num filename offset [option...]
7896 @cindex NAND verification
7897 @cindex NAND programming
7898 Verify the binary data in the file has been programmed to the
7899 specified NAND device, starting at the specified offset.
7900 The @var{num} parameter is the value shown by @command{nand list}.
7902 Use a complete path name for @var{filename}, so you don't depend
7903 on the directory used to start the OpenOCD server.
7905 The @var{offset} must be an exact multiple of the device's page size.
7906 All data in the file will be read and compared to the contents of the
7907 flash, assuming it doesn't run past the end of the device.
7908 As with @command{nand write}, only full pages are verified, so any extra
7909 space in the last page will be filled with 0xff bytes.
7911 The same @var{options} accepted by @command{nand write},
7912 and the file will be processed similarly to produce the buffers that
7913 can be compared against the contents produced from @command{nand dump}.
7915 @b{NOTE:} This will not work when the underlying NAND controller
7916 driver's @code{write_page} routine must update the OOB with a
7917 hardware-computed ECC before the data is written. This limitation may
7918 be removed in a future release.
7921 @subsection Other NAND commands
7922 @cindex NAND other commands
7924 @deffn {Command} {nand check_bad_blocks} num [offset length]
7925 Checks for manufacturer bad block markers on the specified NAND
7926 device. If no parameters are provided, checks the whole
7927 device; otherwise, starts at the specified @var{offset} and
7928 continues for @var{length} bytes.
7929 Both of those values must be exact multiples of the device's
7930 block size, and the region they specify must fit entirely in the chip.
7931 The @var{num} parameter is the value shown by @command{nand list}.
7933 @b{NOTE:} Before using this command you should force raw access
7934 with @command{nand raw_access enable} to ensure that the underlying
7935 driver will not try to apply hardware ECC.
7938 @deffn {Command} {nand info} num
7939 The @var{num} parameter is the value shown by @command{nand list}.
7940 This prints the one-line summary from "nand list", plus for
7941 devices which have been probed this also prints any known
7942 status for each block.
7945 @deffn {Command} {nand raw_access} num (@option{enable}|@option{disable})
7946 Sets or clears an flag affecting how page I/O is done.
7947 The @var{num} parameter is the value shown by @command{nand list}.
7949 This flag is cleared (disabled) by default, but changing that
7950 value won't affect all NAND devices. The key factor is whether
7951 the underlying driver provides @code{read_page} or @code{write_page}
7952 methods. If it doesn't provide those methods, the setting of
7953 this flag is irrelevant; all access is effectively ``raw''.
7955 When those methods exist, they are normally used when reading
7956 data (@command{nand dump} or reading bad block markers) or
7957 writing it (@command{nand write}). However, enabling
7958 raw access (setting the flag) prevents use of those methods,
7959 bypassing hardware ECC logic.
7960 @i{This can be a dangerous option}, since writing blocks
7961 with the wrong ECC data can cause them to be marked as bad.
7964 @anchor{nanddriverlist}
7965 @subsection NAND Driver List
7966 As noted above, the @command{nand device} command allows
7967 driver-specific options and behaviors.
7968 Some controllers also activate controller-specific commands.
7970 @deffn {NAND Driver} {at91sam9}
7971 This driver handles the NAND controllers found on AT91SAM9 family chips from
7972 Atmel. It takes two extra parameters: address of the NAND chip;
7973 address of the ECC controller.
7975 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
7977 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
7978 @code{read_page} methods are used to utilize the ECC hardware unless they are
7979 disabled by using the @command{nand raw_access} command. There are four
7980 additional commands that are needed to fully configure the AT91SAM9 NAND
7981 controller. Two are optional; most boards use the same wiring for ALE/CLE:
7982 @deffn {Config Command} {at91sam9 cle} num addr_line
7983 Configure the address line used for latching commands. The @var{num}
7984 parameter is the value shown by @command{nand list}.
7986 @deffn {Config Command} {at91sam9 ale} num addr_line
7987 Configure the address line used for latching addresses. The @var{num}
7988 parameter is the value shown by @command{nand list}.
7991 For the next two commands, it is assumed that the pins have already been
7992 properly configured for input or output.
7993 @deffn {Config Command} {at91sam9 rdy_busy} num pio_base_addr pin
7994 Configure the RDY/nBUSY input from the NAND device. The @var{num}
7995 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7996 is the base address of the PIO controller and @var{pin} is the pin number.
7998 @deffn {Config Command} {at91sam9 ce} num pio_base_addr pin
7999 Configure the chip enable input to the NAND device. The @var{num}
8000 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8001 is the base address of the PIO controller and @var{pin} is the pin number.
8005 @deffn {NAND Driver} {davinci}
8006 This driver handles the NAND controllers found on DaVinci family
8007 chips from Texas Instruments.
8008 It takes three extra parameters:
8009 address of the NAND chip;
8010 hardware ECC mode to use (@option{hwecc1},
8011 @option{hwecc4}, @option{hwecc4_infix});
8012 address of the AEMIF controller on this processor.
8014 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
8016 All DaVinci processors support the single-bit ECC hardware,
8017 and newer ones also support the four-bit ECC hardware.
8018 The @code{write_page} and @code{read_page} methods are used
8019 to implement those ECC modes, unless they are disabled using
8020 the @command{nand raw_access} command.
8023 @deffn {NAND Driver} {lpc3180}
8024 These controllers require an extra @command{nand device}
8025 parameter: the clock rate used by the controller.
8026 @deffn {Command} {lpc3180 select} num [mlc|slc]
8027 Configures use of the MLC or SLC controller mode.
8028 MLC implies use of hardware ECC.
8029 The @var{num} parameter is the value shown by @command{nand list}.
8032 At this writing, this driver includes @code{write_page}
8033 and @code{read_page} methods. Using @command{nand raw_access}
8034 to disable those methods will prevent use of hardware ECC
8035 in the MLC controller mode, but won't change SLC behavior.
8037 @comment current lpc3180 code won't issue 5-byte address cycles
8039 @deffn {NAND Driver} {mx3}
8040 This driver handles the NAND controller in i.MX31. The mxc driver
8041 should work for this chip as well.
8044 @deffn {NAND Driver} {mxc}
8045 This driver handles the NAND controller found in Freescale i.MX
8046 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
8047 The driver takes 3 extra arguments, chip (@option{mx27},
8048 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
8049 and optionally if bad block information should be swapped between
8050 main area and spare area (@option{biswap}), defaults to off.
8052 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
8054 @deffn {Command} {mxc biswap} bank_num [enable|disable]
8055 Turns on/off bad block information swapping from main area,
8056 without parameter query status.
8060 @deffn {NAND Driver} {orion}
8061 These controllers require an extra @command{nand device}
8062 parameter: the address of the controller.
8064 nand device orion 0xd8000000
8066 These controllers don't define any specialized commands.
8067 At this writing, their drivers don't include @code{write_page}
8068 or @code{read_page} methods, so @command{nand raw_access} won't
8069 change any behavior.
8072 @deffn {NAND Driver} {s3c2410}
8073 @deffnx {NAND Driver} {s3c2412}
8074 @deffnx {NAND Driver} {s3c2440}
8075 @deffnx {NAND Driver} {s3c2443}
8076 @deffnx {NAND Driver} {s3c6400}
8077 These S3C family controllers don't have any special
8078 @command{nand device} options, and don't define any
8079 specialized commands.
8080 At this writing, their drivers don't include @code{write_page}
8081 or @code{read_page} methods, so @command{nand raw_access} won't
8082 change any behavior.
8085 @node Flash Programming
8086 @chapter Flash Programming
8088 OpenOCD implements numerous ways to program the target flash, whether internal or external.
8089 Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB},
8090 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
8092 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
8093 OpenOCD will program/verify/reset the target and optionally shutdown.
8095 The script is executed as follows and by default the following actions will be performed.
8097 @item 'init' is executed.
8098 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
8099 @item @code{flash write_image} is called to erase and write any flash using the filename given.
8100 @item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails.
8101 @item @code{verify_image} is called if @option{verify} parameter is given.
8102 @item @code{reset run} is called if @option{reset} parameter is given.
8103 @item OpenOCD is shutdown if @option{exit} parameter is given.
8106 An example of usage is given below. @xref{program}.
8109 # program and verify using elf/hex/s19. verify and reset
8110 # are optional parameters
8111 openocd -f board/stm32f3discovery.cfg \
8112 -c "program filename.elf verify reset exit"
8114 # binary files need the flash address passing
8115 openocd -f board/stm32f3discovery.cfg \
8116 -c "program filename.bin exit 0x08000000"
8119 @node PLD/FPGA Commands
8120 @chapter PLD/FPGA Commands
8124 Programmable Logic Devices (PLDs) and the more flexible
8125 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
8126 OpenOCD can support programming them.
8127 Although PLDs are generally restrictive (cells are less functional, and
8128 there are no special purpose cells for memory or computational tasks),
8129 they share the same OpenOCD infrastructure.
8130 Accordingly, both are called PLDs here.
8132 @section PLD/FPGA Configuration and Commands
8134 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
8135 OpenOCD maintains a list of PLDs available for use in various commands.
8136 Also, each such PLD requires a driver.
8138 They are referenced by the number shown by the @command{pld devices} command,
8139 and new PLDs are defined by @command{pld device driver_name}.
8141 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
8142 Defines a new PLD device, supported by driver @var{driver_name},
8143 using the TAP named @var{tap_name}.
8144 The driver may make use of any @var{driver_options} to configure its
8148 @deffn {Command} {pld devices}
8149 Lists the PLDs and their numbers.
8152 @deffn {Command} {pld load} num filename
8153 Loads the file @file{filename} into the PLD identified by @var{num}.
8154 The file format must be inferred by the driver.
8157 @section PLD/FPGA Drivers, Options, and Commands
8159 Drivers may support PLD-specific options to the @command{pld device}
8160 definition command, and may also define commands usable only with
8161 that particular type of PLD.
8163 @deffn {FPGA Driver} {virtex2} [no_jstart]
8164 Virtex-II is a family of FPGAs sold by Xilinx.
8165 It supports the IEEE 1532 standard for In-System Configuration (ISC).
8167 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
8168 loading the bitstream. While required for Series2, Series3, and Series6, it
8169 breaks bitstream loading on Series7.
8171 @deffn {Command} {virtex2 read_stat} num
8172 Reads and displays the Virtex-II status register (STAT)
8177 @node General Commands
8178 @chapter General Commands
8181 The commands documented in this chapter here are common commands that
8182 you, as a human, may want to type and see the output of. Configuration type
8183 commands are documented elsewhere.
8187 @item @b{Source Of Commands}
8188 @* OpenOCD commands can occur in a configuration script (discussed
8189 elsewhere) or typed manually by a human or supplied programmatically,
8190 or via one of several TCP/IP Ports.
8192 @item @b{From the human}
8193 @* A human should interact with the telnet interface (default port: 4444)
8194 or via GDB (default port 3333).
8196 To issue commands from within a GDB session, use the @option{monitor}
8197 command, e.g. use @option{monitor poll} to issue the @option{poll}
8198 command. All output is relayed through the GDB session.
8200 @item @b{Machine Interface}
8201 The Tcl interface's intent is to be a machine interface. The default Tcl
8206 @section Server Commands
8208 @deffn {Command} {exit}
8209 Exits the current telnet session.
8212 @deffn {Command} {help} [string]
8213 With no parameters, prints help text for all commands.
8214 Otherwise, prints each helptext containing @var{string}.
8215 Not every command provides helptext.
8217 Configuration commands, and commands valid at any time, are
8218 explicitly noted in parenthesis.
8219 In most cases, no such restriction is listed; this indicates commands
8220 which are only available after the configuration stage has completed.
8223 @deffn {Command} {sleep} msec [@option{busy}]
8224 Wait for at least @var{msec} milliseconds before resuming.
8225 If @option{busy} is passed, busy-wait instead of sleeping.
8226 (This option is strongly discouraged.)
8227 Useful in connection with script files
8228 (@command{script} command and @command{target_name} configuration).
8231 @deffn {Command} {shutdown} [@option{error}]
8232 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
8233 other). If option @option{error} is used, OpenOCD will return a
8234 non-zero exit code to the parent process.
8236 Like any TCL commands, also @command{shutdown} can be redefined, e.g.:
8239 rename shutdown original_shutdown
8240 proc shutdown @{@} @{
8241 puts "This is my implementation of shutdown"
8242 # my own stuff before exit OpenOCD
8246 If user types CTRL-C or kills OpenOCD, either the command @command{shutdown}
8247 or its replacement will be automatically executed before OpenOCD exits.
8251 @deffn {Command} {debug_level} [n]
8252 @cindex message level
8253 Display debug level.
8254 If @var{n} (from 0..4) is provided, then set it to that level.
8255 This affects the kind of messages sent to the server log.
8256 Level 0 is error messages only;
8257 level 1 adds warnings;
8258 level 2 adds informational messages;
8259 level 3 adds debugging messages;
8260 and level 4 adds verbose low-level debug messages.
8261 The default is level 2, but that can be overridden on
8262 the command line along with the location of that log
8263 file (which is normally the server's standard output).
8267 @deffn {Command} {echo} [-n] message
8268 Logs a message at "user" priority.
8269 Option "-n" suppresses trailing newline.
8271 echo "Downloading kernel -- please wait"
8275 @deffn {Command} {log_output} [filename | "default"]
8276 Redirect logging to @var{filename} or set it back to default output;
8277 the default log output channel is stderr.
8280 @deffn {Command} {add_script_search_dir} [directory]
8281 Add @var{directory} to the file/script search path.
8284 @deffn {Config Command} {bindto} [@var{name}]
8285 Specify hostname or IPv4 address on which to listen for incoming
8286 TCP/IP connections. By default, OpenOCD will listen on the loopback
8287 interface only. If your network environment is safe, @code{bindto
8288 0.0.0.0} can be used to cover all available interfaces.
8291 @anchor{targetstatehandling}
8292 @section Target State handling
8295 @cindex target initialization
8297 In this section ``target'' refers to a CPU configured as
8298 shown earlier (@pxref{CPU Configuration}).
8299 These commands, like many, implicitly refer to
8300 a current target which is used to perform the
8301 various operations. The current target may be changed
8302 by using @command{targets} command with the name of the
8303 target which should become current.
8305 @deffn {Command} {reg} [(number|name) [(value|'force')]]
8306 Access a single register by @var{number} or by its @var{name}.
8307 The target must generally be halted before access to CPU core
8308 registers is allowed. Depending on the hardware, some other
8309 registers may be accessible while the target is running.
8311 @emph{With no arguments}:
8312 list all available registers for the current target,
8313 showing number, name, size, value, and cache status.
8314 For valid entries, a value is shown; valid entries
8315 which are also dirty (and will be written back later)
8316 are flagged as such.
8318 @emph{With number/name}: display that register's value.
8319 Use @var{force} argument to read directly from the target,
8320 bypassing any internal cache.
8322 @emph{With both number/name and value}: set register's value.
8323 Writes may be held in a writeback cache internal to OpenOCD,
8324 so that setting the value marks the register as dirty instead
8325 of immediately flushing that value. Resuming CPU execution
8326 (including by single stepping) or otherwise activating the
8327 relevant module will flush such values.
8329 Cores may have surprisingly many registers in their
8330 Debug and trace infrastructure:
8335 (0) r0 (/32): 0x0000D3C2 (dirty)
8336 (1) r1 (/32): 0xFD61F31C
8339 (164) ETM_contextid_comparator_mask (/32)
8344 @deffn {Command} {halt} [ms]
8345 @deffnx {Command} {wait_halt} [ms]
8346 The @command{halt} command first sends a halt request to the target,
8347 which @command{wait_halt} doesn't.
8348 Otherwise these behave the same: wait up to @var{ms} milliseconds,
8349 or 5 seconds if there is no parameter, for the target to halt
8350 (and enter debug mode).
8351 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
8354 On ARM cores, software using the @emph{wait for interrupt} operation
8355 often blocks the JTAG access needed by a @command{halt} command.
8356 This is because that operation also puts the core into a low
8357 power mode by gating the core clock;
8358 but the core clock is needed to detect JTAG clock transitions.
8360 One partial workaround uses adaptive clocking: when the core is
8361 interrupted the operation completes, then JTAG clocks are accepted
8362 at least until the interrupt handler completes.
8363 However, this workaround is often unusable since the processor, board,
8364 and JTAG adapter must all support adaptive JTAG clocking.
8365 Also, it can't work until an interrupt is issued.
8367 A more complete workaround is to not use that operation while you
8368 work with a JTAG debugger.
8369 Tasking environments generally have idle loops where the body is the
8370 @emph{wait for interrupt} operation.
8371 (On older cores, it is a coprocessor action;
8372 newer cores have a @option{wfi} instruction.)
8373 Such loops can just remove that operation, at the cost of higher
8374 power consumption (because the CPU is needlessly clocked).
8379 @deffn {Command} {resume} [address]
8380 Resume the target at its current code position,
8381 or the optional @var{address} if it is provided.
8382 OpenOCD will wait 5 seconds for the target to resume.
8385 @deffn {Command} {step} [address]
8386 Single-step the target at its current code position,
8387 or the optional @var{address} if it is provided.
8390 @anchor{resetcommand}
8391 @deffn {Command} {reset}
8392 @deffnx {Command} {reset run}
8393 @deffnx {Command} {reset halt}
8394 @deffnx {Command} {reset init}
8395 Perform as hard a reset as possible, using SRST if possible.
8396 @emph{All defined targets will be reset, and target
8397 events will fire during the reset sequence.}
8399 The optional parameter specifies what should
8400 happen after the reset.
8401 If there is no parameter, a @command{reset run} is executed.
8402 The other options will not work on all systems.
8403 @xref{Reset Configuration}.
8406 @item @b{run} Let the target run
8407 @item @b{halt} Immediately halt the target
8408 @item @b{init} Immediately halt the target, and execute the reset-init script
8412 @deffn {Command} {soft_reset_halt}
8413 Requesting target halt and executing a soft reset. This is often used
8414 when a target cannot be reset and halted. The target, after reset is
8415 released begins to execute code. OpenOCD attempts to stop the CPU and
8416 then sets the program counter back to the reset vector. Unfortunately
8417 the code that was executed may have left the hardware in an unknown
8421 @deffn {Command} {adapter assert} [signal [assert|deassert signal]]
8422 @deffnx {Command} {adapter deassert} [signal [assert|deassert signal]]
8423 Set values of reset signals.
8424 Without parameters returns current status of the signals.
8425 The @var{signal} parameter values may be
8426 @option{srst}, indicating that srst signal is to be asserted or deasserted,
8427 @option{trst}, indicating that trst signal is to be asserted or deasserted.
8429 The @command{reset_config} command should already have been used
8430 to configure how the board and the adapter treat these two
8431 signals, and to say if either signal is even present.
8432 @xref{Reset Configuration}.
8433 Trying to assert a signal that is not present triggers an error.
8434 If a signal is present on the adapter and not specified in the command,
8435 the signal will not be modified.
8438 TRST is specially handled.
8439 It actually signifies JTAG's @sc{reset} state.
8440 So if the board doesn't support the optional TRST signal,
8441 or it doesn't support it along with the specified SRST value,
8442 JTAG reset is triggered with TMS and TCK signals
8443 instead of the TRST signal.
8444 And no matter how that JTAG reset is triggered, once
8445 the scan chain enters @sc{reset} with TRST inactive,
8446 TAP @code{post-reset} events are delivered to all TAPs
8447 with handlers for that event.
8451 @anchor{memoryaccess}
8452 @section Memory access commands
8453 @cindex memory access
8455 These commands allow accesses of a specific size to the memory
8456 system. Often these are used to configure the current target in some
8457 special way. For example - one may need to write certain values to the
8458 SDRAM controller to enable SDRAM.
8461 @item Use the @command{targets} (plural) command
8462 to change the current target.
8463 @item In system level scripts these commands are deprecated.
8464 Please use their TARGET object siblings to avoid making assumptions
8465 about what TAP is the current target, or about MMU configuration.
8468 @deffn {Command} {mdd} [phys] addr [count]
8469 @deffnx {Command} {mdw} [phys] addr [count]
8470 @deffnx {Command} {mdh} [phys] addr [count]
8471 @deffnx {Command} {mdb} [phys] addr [count]
8472 Display contents of address @var{addr}, as
8473 64-bit doublewords (@command{mdd}),
8474 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
8475 or 8-bit bytes (@command{mdb}).
8476 When the current target has an MMU which is present and active,
8477 @var{addr} is interpreted as a virtual address.
8478 Otherwise, or if the optional @var{phys} flag is specified,
8479 @var{addr} is interpreted as a physical address.
8480 If @var{count} is specified, displays that many units.
8481 (If you want to manipulate the data instead of displaying it,
8482 see the @code{mem2array} primitives.)
8485 @deffn {Command} {mwd} [phys] addr doubleword [count]
8486 @deffnx {Command} {mww} [phys] addr word [count]
8487 @deffnx {Command} {mwh} [phys] addr halfword [count]
8488 @deffnx {Command} {mwb} [phys] addr byte [count]
8489 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
8490 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
8491 at the specified address @var{addr}.
8492 When the current target has an MMU which is present and active,
8493 @var{addr} is interpreted as a virtual address.
8494 Otherwise, or if the optional @var{phys} flag is specified,
8495 @var{addr} is interpreted as a physical address.
8496 If @var{count} is specified, fills that many units of consecutive address.
8499 @anchor{imageaccess}
8500 @section Image loading commands
8501 @cindex image loading
8502 @cindex image dumping
8504 @deffn {Command} {dump_image} filename address size
8505 Dump @var{size} bytes of target memory starting at @var{address} to the
8506 binary file named @var{filename}.
8509 @deffn {Command} {fast_load}
8510 Loads an image stored in memory by @command{fast_load_image} to the
8511 current target. Must be preceded by fast_load_image.
8514 @deffn {Command} {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
8515 Normally you should be using @command{load_image} or GDB load. However, for
8516 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
8517 host), storing the image in memory and uploading the image to the target
8518 can be a way to upload e.g. multiple debug sessions when the binary does not change.
8519 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
8520 memory, i.e. does not affect target. This approach is also useful when profiling
8521 target programming performance as I/O and target programming can easily be profiled
8525 @deffn {Command} {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
8526 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
8527 The file format may optionally be specified
8528 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
8529 In addition the following arguments may be specified:
8530 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
8531 @var{max_length} - maximum number of bytes to load.
8533 proc load_image_bin @{fname foffset address length @} @{
8534 # Load data from fname filename at foffset offset to
8535 # target at address. Load at most length bytes.
8536 load_image $fname [expr $address - $foffset] bin \
8542 @deffn {Command} {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
8543 Displays image section sizes and addresses
8544 as if @var{filename} were loaded into target memory
8545 starting at @var{address} (defaults to zero).
8546 The file format may optionally be specified
8547 (@option{bin}, @option{ihex}, or @option{elf})
8550 @deffn {Command} {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
8551 Verify @var{filename} against target memory starting at @var{address}.
8552 The file format may optionally be specified
8553 (@option{bin}, @option{ihex}, or @option{elf})
8554 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
8557 @deffn {Command} {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
8558 Verify @var{filename} against target memory starting at @var{address}.
8559 The file format may optionally be specified
8560 (@option{bin}, @option{ihex}, or @option{elf})
8561 This perform a comparison using a CRC checksum only
8565 @section Breakpoint and Watchpoint commands
8569 CPUs often make debug modules accessible through JTAG, with
8570 hardware support for a handful of code breakpoints and data
8572 In addition, CPUs almost always support software breakpoints.
8574 @deffn {Command} {bp} [address len [@option{hw}]]
8575 With no parameters, lists all active breakpoints.
8576 Else sets a breakpoint on code execution starting
8577 at @var{address} for @var{length} bytes.
8578 This is a software breakpoint, unless @option{hw} is specified
8579 in which case it will be a hardware breakpoint.
8581 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
8582 for similar mechanisms that do not consume hardware breakpoints.)
8585 @deffn {Command} {rbp} @option{all} | address
8586 Remove the breakpoint at @var{address} or all breakpoints.
8589 @deffn {Command} {rwp} address
8590 Remove data watchpoint on @var{address}
8593 @deffn {Command} {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
8594 With no parameters, lists all active watchpoints.
8595 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
8596 The watch point is an "access" watchpoint unless
8597 the @option{r} or @option{w} parameter is provided,
8598 defining it as respectively a read or write watchpoint.
8599 If a @var{value} is provided, that value is used when determining if
8600 the watchpoint should trigger. The value may be first be masked
8601 using @var{mask} to mark ``don't care'' fields.
8605 @section Real Time Transfer (RTT)
8607 Real Time Transfer (RTT) is an interface specified by SEGGER based on basic
8608 memory reads and writes to transfer data bidirectionally between target and host.
8609 The specification is independent of the target architecture.
8610 Every target that supports so called "background memory access", which means
8611 that the target memory can be accessed by the debugger while the target is
8612 running, can be used.
8613 This interface is especially of interest for targets without
8614 Serial Wire Output (SWO), such as ARM Cortex-M0, or where semihosting is not
8615 applicable because of real-time constraints.
8618 The current implementation supports only single target devices.
8621 The data transfer between host and target device is organized through
8622 unidirectional up/down-channels for target-to-host and host-to-target
8623 communication, respectively.
8626 The current implementation does not respect channel buffer flags.
8627 They are used to determine what happens when writing to a full buffer, for
8631 Channels are exposed via raw TCP/IP connections. One or more RTT servers can be
8632 assigned to each channel to make them accessible to an unlimited number
8633 of TCP/IP connections.
8635 @deffn {Command} {rtt setup} address size ID
8636 Configure RTT for the currently selected target.
8637 Once RTT is started, OpenOCD searches for a control block with the
8638 identifier @var{ID} starting at the memory address @var{address} within the next
8642 @deffn {Command} {rtt start}
8644 If the control block location is not known, OpenOCD starts searching for it.
8647 @deffn {Command} {rtt stop}
8651 @deffn {Command} {rtt polling_interval} [interval]
8652 Display the polling interval.
8653 If @var{interval} is provided, set the polling interval.
8654 The polling interval determines (in milliseconds) how often the up-channels are
8655 checked for new data.
8658 @deffn {Command} {rtt channels}
8659 Display a list of all channels and their properties.
8662 @deffn {Command} {rtt channellist}
8663 Return a list of all channels and their properties as Tcl list.
8664 The list can be manipulated easily from within scripts.
8667 @deffn {Command} {rtt server start} port channel
8668 Start a TCP server on @var{port} for the channel @var{channel}.
8671 @deffn {Command} {rtt server stop} port
8672 Stop the TCP sever with port @var{port}.
8675 The following example shows how to setup RTT using the SEGGER RTT implementation
8676 on the target device.
8681 rtt setup 0x20000000 2048 "SEGGER RTT"
8684 rtt server start 9090 0
8687 In this example, OpenOCD searches the control block with the ID "SEGGER RTT"
8688 starting at 0x20000000 for 2048 bytes. The RTT channel 0 is exposed through the
8692 @section Misc Commands
8695 @deffn {Command} {profile} seconds filename [start end]
8696 Profiling samples the CPU's program counter as quickly as possible,
8697 which is useful for non-intrusive stochastic profiling.
8698 Saves up to 10000 samples in @file{filename} using ``gmon.out''
8699 format. Optional @option{start} and @option{end} parameters allow to
8700 limit the address range.
8703 @deffn {Command} {version}
8704 Displays a string identifying the version of this OpenOCD server.
8707 @deffn {Command} {virt2phys} virtual_address
8708 Requests the current target to map the specified @var{virtual_address}
8709 to its corresponding physical address, and displays the result.
8712 @node Architecture and Core Commands
8713 @chapter Architecture and Core Commands
8714 @cindex Architecture Specific Commands
8715 @cindex Core Specific Commands
8717 Most CPUs have specialized JTAG operations to support debugging.
8718 OpenOCD packages most such operations in its standard command framework.
8719 Some of those operations don't fit well in that framework, so they are
8720 exposed here as architecture or implementation (core) specific commands.
8722 @anchor{armhardwaretracing}
8723 @section ARM Hardware Tracing
8728 CPUs based on ARM cores may include standard tracing interfaces,
8729 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
8730 address and data bus trace records to a ``Trace Port''.
8734 Development-oriented boards will sometimes provide a high speed
8735 trace connector for collecting that data, when the particular CPU
8736 supports such an interface.
8737 (The standard connector is a 38-pin Mictor, with both JTAG
8738 and trace port support.)
8739 Those trace connectors are supported by higher end JTAG adapters
8740 and some logic analyzer modules; frequently those modules can
8741 buffer several megabytes of trace data.
8742 Configuring an ETM coupled to such an external trace port belongs
8743 in the board-specific configuration file.
8745 If the CPU doesn't provide an external interface, it probably
8746 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
8747 dedicated SRAM. 4KBytes is one common ETB size.
8748 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
8749 (target) configuration file, since it works the same on all boards.
8752 ETM support in OpenOCD doesn't seem to be widely used yet.
8755 ETM support may be buggy, and at least some @command{etm config}
8756 parameters should be detected by asking the ETM for them.
8758 ETM trigger events could also implement a kind of complex
8759 hardware breakpoint, much more powerful than the simple
8760 watchpoint hardware exported by EmbeddedICE modules.
8761 @emph{Such breakpoints can be triggered even when using the
8762 dummy trace port driver}.
8764 It seems like a GDB hookup should be possible,
8765 as well as tracing only during specific states
8766 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
8768 There should be GUI tools to manipulate saved trace data and help
8769 analyse it in conjunction with the source code.
8770 It's unclear how much of a common interface is shared
8771 with the current XScale trace support, or should be
8772 shared with eventual Nexus-style trace module support.
8774 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
8775 for ETM modules is available. The code should be able to
8776 work with some newer cores; but not all of them support
8777 this original style of JTAG access.
8780 @subsection ETM Configuration
8781 ETM setup is coupled with the trace port driver configuration.
8783 @deffn {Config Command} {etm config} target width mode clocking driver
8784 Declares the ETM associated with @var{target}, and associates it
8785 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
8787 Several of the parameters must reflect the trace port capabilities,
8788 which are a function of silicon capabilities (exposed later
8789 using @command{etm info}) and of what hardware is connected to
8790 that port (such as an external pod, or ETB).
8791 The @var{width} must be either 4, 8, or 16,
8792 except with ETMv3.0 and newer modules which may also
8793 support 1, 2, 24, 32, 48, and 64 bit widths.
8794 (With those versions, @command{etm info} also shows whether
8795 the selected port width and mode are supported.)
8797 The @var{mode} must be @option{normal}, @option{multiplexed},
8798 or @option{demultiplexed}.
8799 The @var{clocking} must be @option{half} or @option{full}.
8802 With ETMv3.0 and newer, the bits set with the @var{mode} and
8803 @var{clocking} parameters both control the mode.
8804 This modified mode does not map to the values supported by
8805 previous ETM modules, so this syntax is subject to change.
8809 You can see the ETM registers using the @command{reg} command.
8810 Not all possible registers are present in every ETM.
8811 Most of the registers are write-only, and are used to configure
8812 what CPU activities are traced.
8816 @deffn {Command} {etm info}
8817 Displays information about the current target's ETM.
8818 This includes resource counts from the @code{ETM_CONFIG} register,
8819 as well as silicon capabilities (except on rather old modules).
8820 from the @code{ETM_SYS_CONFIG} register.
8823 @deffn {Command} {etm status}
8824 Displays status of the current target's ETM and trace port driver:
8825 is the ETM idle, or is it collecting data?
8826 Did trace data overflow?
8830 @deffn {Command} {etm tracemode} [type context_id_bits cycle_accurate branch_output]
8831 Displays what data that ETM will collect.
8832 If arguments are provided, first configures that data.
8833 When the configuration changes, tracing is stopped
8834 and any buffered trace data is invalidated.
8837 @item @var{type} ... describing how data accesses are traced,
8838 when they pass any ViewData filtering that was set up.
8840 @option{none} (save nothing),
8841 @option{data} (save data),
8842 @option{address} (save addresses),
8843 @option{all} (save data and addresses)
8844 @item @var{context_id_bits} ... 0, 8, 16, or 32
8845 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
8846 cycle-accurate instruction tracing.
8847 Before ETMv3, enabling this causes much extra data to be recorded.
8848 @item @var{branch_output} ... @option{enable} or @option{disable}.
8849 Disable this unless you need to try reconstructing the instruction
8850 trace stream without an image of the code.
8854 @deffn {Command} {etm trigger_debug} (@option{enable}|@option{disable})
8855 Displays whether ETM triggering debug entry (like a breakpoint) is
8856 enabled or disabled, after optionally modifying that configuration.
8857 The default behaviour is @option{disable}.
8858 Any change takes effect after the next @command{etm start}.
8860 By using script commands to configure ETM registers, you can make the
8861 processor enter debug state automatically when certain conditions,
8862 more complex than supported by the breakpoint hardware, happen.
8865 @subsection ETM Trace Operation
8867 After setting up the ETM, you can use it to collect data.
8868 That data can be exported to files for later analysis.
8869 It can also be parsed with OpenOCD, for basic sanity checking.
8871 To configure what is being traced, you will need to write
8872 various trace registers using @command{reg ETM_*} commands.
8873 For the definitions of these registers, read ARM publication
8874 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
8875 Be aware that most of the relevant registers are write-only,
8876 and that ETM resources are limited. There are only a handful
8877 of address comparators, data comparators, counters, and so on.
8879 Examples of scenarios you might arrange to trace include:
8882 @item Code flow within a function, @emph{excluding} subroutines
8883 it calls. Use address range comparators to enable tracing
8884 for instruction access within that function's body.
8885 @item Code flow within a function, @emph{including} subroutines
8886 it calls. Use the sequencer and address comparators to activate
8887 tracing on an ``entered function'' state, then deactivate it by
8888 exiting that state when the function's exit code is invoked.
8889 @item Code flow starting at the fifth invocation of a function,
8890 combining one of the above models with a counter.
8891 @item CPU data accesses to the registers for a particular device,
8892 using address range comparators and the ViewData logic.
8893 @item Such data accesses only during IRQ handling, combining the above
8894 model with sequencer triggers which on entry and exit to the IRQ handler.
8895 @item @emph{... more}
8898 At this writing, September 2009, there are no Tcl utility
8899 procedures to help set up any common tracing scenarios.
8901 @deffn {Command} {etm analyze}
8902 Reads trace data into memory, if it wasn't already present.
8903 Decodes and prints the data that was collected.
8906 @deffn {Command} {etm dump} filename
8907 Stores the captured trace data in @file{filename}.
8910 @deffn {Command} {etm image} filename [base_address] [type]
8911 Opens an image file.
8914 @deffn {Command} {etm load} filename
8915 Loads captured trace data from @file{filename}.
8918 @deffn {Command} {etm start}
8919 Starts trace data collection.
8922 @deffn {Command} {etm stop}
8923 Stops trace data collection.
8926 @anchor{traceportdrivers}
8927 @subsection Trace Port Drivers
8929 To use an ETM trace port it must be associated with a driver.
8931 @deffn {Trace Port Driver} {dummy}
8932 Use the @option{dummy} driver if you are configuring an ETM that's
8933 not connected to anything (on-chip ETB or off-chip trace connector).
8934 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
8935 any trace data collection.}
8936 @deffn {Config Command} {etm_dummy config} target
8937 Associates the ETM for @var{target} with a dummy driver.
8941 @deffn {Trace Port Driver} {etb}
8942 Use the @option{etb} driver if you are configuring an ETM
8943 to use on-chip ETB memory.
8944 @deffn {Config Command} {etb config} target etb_tap
8945 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
8946 You can see the ETB registers using the @command{reg} command.
8948 @deffn {Command} {etb trigger_percent} [percent]
8949 This displays, or optionally changes, ETB behavior after the
8950 ETM's configured @emph{trigger} event fires.
8951 It controls how much more trace data is saved after the (single)
8952 trace trigger becomes active.
8955 @item The default corresponds to @emph{trace around} usage,
8956 recording 50 percent data before the event and the rest
8958 @item The minimum value of @var{percent} is 2 percent,
8959 recording almost exclusively data before the trigger.
8960 Such extreme @emph{trace before} usage can help figure out
8961 what caused that event to happen.
8962 @item The maximum value of @var{percent} is 100 percent,
8963 recording data almost exclusively after the event.
8964 This extreme @emph{trace after} usage might help sort out
8965 how the event caused trouble.
8967 @c REVISIT allow "break" too -- enter debug mode.
8972 @anchor{armcrosstrigger}
8973 @section ARM Cross-Trigger Interface
8976 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
8977 that connects event sources like tracing components or CPU cores with each
8978 other through a common trigger matrix (CTM). For ARMv8 architecture, a
8979 CTI is mandatory for core run control and each core has an individual
8980 CTI instance attached to it. OpenOCD has limited support for CTI using
8981 the @emph{cti} group of commands.
8983 @deffn {Command} {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-baseaddr} base_address
8984 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
8985 @var{apn}. The @var{base_address} must match the base address of the CTI
8986 on the respective MEM-AP. All arguments are mandatory. This creates a
8987 new command @command{$cti_name} which is used for various purposes
8988 including additional configuration.
8991 @deffn {Command} {$cti_name enable} @option{on|off}
8992 Enable (@option{on}) or disable (@option{off}) the CTI.
8995 @deffn {Command} {$cti_name dump}
8996 Displays a register dump of the CTI.
8999 @deffn {Command} {$cti_name write} @var{reg_name} @var{value}
9000 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
9003 @deffn {Command} {$cti_name read} @var{reg_name}
9004 Print the value read from the CTI register with the symbolic name @var{reg_name}.
9007 @deffn {Command} {$cti_name ack} @var{event}
9008 Acknowledge a CTI @var{event}.
9011 @deffn {Command} {$cti_name channel} @var{channel_number} @var{operation}
9012 Perform a specific channel operation, the possible operations are:
9013 gate, ungate, set, clear and pulse
9016 @deffn {Command} {$cti_name testmode} @option{on|off}
9017 Enable (@option{on}) or disable (@option{off}) the integration test mode
9021 @deffn {Command} {cti names}
9022 Prints a list of names of all CTI objects created. This command is mainly
9023 useful in TCL scripting.
9026 @section Generic ARM
9029 These commands should be available on all ARM processors.
9030 They are available in addition to other core-specific
9031 commands that may be available.
9033 @deffn {Command} {arm core_state} [@option{arm}|@option{thumb}]
9034 Displays the core_state, optionally changing it to process
9035 either @option{arm} or @option{thumb} instructions.
9036 The target may later be resumed in the currently set core_state.
9037 (Processors may also support the Jazelle state, but
9038 that is not currently supported in OpenOCD.)
9041 @deffn {Command} {arm disassemble} address [count [@option{thumb}]]
9043 Disassembles @var{count} instructions starting at @var{address}.
9044 If @var{count} is not specified, a single instruction is disassembled.
9045 If @option{thumb} is specified, or the low bit of the address is set,
9046 Thumb2 (mixed 16/32-bit) instructions are used;
9047 else ARM (32-bit) instructions are used.
9048 (Processors may also support the Jazelle state, but
9049 those instructions are not currently understood by OpenOCD.)
9051 Note that all Thumb instructions are Thumb2 instructions,
9052 so older processors (without Thumb2 support) will still
9053 see correct disassembly of Thumb code.
9054 Also, ThumbEE opcodes are the same as Thumb2,
9055 with a handful of exceptions.
9056 ThumbEE disassembly currently has no explicit support.
9059 @deffn {Command} {arm mcr} pX op1 CRn CRm op2 value
9060 Write @var{value} to a coprocessor @var{pX} register
9061 passing parameters @var{CRn},
9062 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9063 and using the MCR instruction.
9064 (Parameter sequence matches the ARM instruction, but omits
9068 @deffn {Command} {arm mrc} pX coproc op1 CRn CRm op2
9069 Read a coprocessor @var{pX} register passing parameters @var{CRn},
9070 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9071 and the MRC instruction.
9072 Returns the result so it can be manipulated by Jim scripts.
9073 (Parameter sequence matches the ARM instruction, but omits
9077 @deffn {Command} {arm reg}
9078 Display a table of all banked core registers, fetching the current value from every
9079 core mode if necessary.
9082 @deffn {Command} {arm semihosting} [@option{enable}|@option{disable}]
9083 @cindex ARM semihosting
9084 Display status of semihosting, after optionally changing that status.
9086 Semihosting allows for code executing on an ARM target to use the
9087 I/O facilities on the host computer i.e. the system where OpenOCD
9088 is running. The target application must be linked against a library
9089 implementing the ARM semihosting convention that forwards operation
9090 requests by using a special SVC instruction that is trapped at the
9091 Supervisor Call vector by OpenOCD.
9094 @deffn {Command} {arm semihosting_cmdline} [@option{enable}|@option{disable}]
9095 @cindex ARM semihosting
9096 Set the command line to be passed to the debugger.
9099 arm semihosting_cmdline argv0 argv1 argv2 ...
9102 This option lets one set the command line arguments to be passed to
9103 the program. The first argument (argv0) is the program name in a
9104 standard C environment (argv[0]). Depending on the program (not much
9105 programs look at argv[0]), argv0 is ignored and can be any string.
9108 @deffn {Command} {arm semihosting_fileio} [@option{enable}|@option{disable}]
9109 @cindex ARM semihosting
9110 Display status of semihosting fileio, after optionally changing that
9113 Enabling this option forwards semihosting I/O to GDB process using the
9114 File-I/O remote protocol extension. This is especially useful for
9115 interacting with remote files or displaying console messages in the
9119 @deffn {Command} {arm semihosting_resexit} [@option{enable}|@option{disable}]
9120 @cindex ARM semihosting
9121 Enable resumable SEMIHOSTING_SYS_EXIT.
9123 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
9124 things are simple, the openocd process calls exit() and passes
9125 the value returned by the target.
9127 When SEMIHOSTING_SYS_EXIT is called during a debug session,
9128 by default execution returns to the debugger, leaving the
9129 debugger in a HALT state, similar to the state entered when
9130 encountering a break.
9132 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
9133 return normally, as any semihosting call, and do not break
9135 The standard allows this to happen, but the condition
9136 to trigger it is a bit obscure ("by performing an RDI_Execute
9137 request or equivalent").
9139 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
9140 this option (default: disabled).
9143 @section ARMv4 and ARMv5 Architecture
9147 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
9148 and introduced core parts of the instruction set in use today.
9149 That includes the Thumb instruction set, introduced in the ARMv4T
9152 @subsection ARM7 and ARM9 specific commands
9156 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
9157 ARM9TDMI, ARM920T or ARM926EJ-S.
9158 They are available in addition to the ARM commands,
9159 and any other core-specific commands that may be available.
9161 @deffn {Command} {arm7_9 dbgrq} [@option{enable}|@option{disable}]
9162 Displays the value of the flag controlling use of the
9163 EmbeddedIce DBGRQ signal to force entry into debug mode,
9164 instead of breakpoints.
9165 If a boolean parameter is provided, first assigns that flag.
9168 safe for all but ARM7TDMI-S cores (like NXP LPC).
9169 This feature is enabled by default on most ARM9 cores,
9170 including ARM9TDMI, ARM920T, and ARM926EJ-S.
9173 @deffn {Command} {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
9175 Displays the value of the flag controlling use of the debug communications
9176 channel (DCC) to write larger (>128 byte) amounts of memory.
9177 If a boolean parameter is provided, first assigns that flag.
9179 DCC downloads offer a huge speed increase, but might be
9180 unsafe, especially with targets running at very low speeds. This command was introduced
9181 with OpenOCD rev. 60, and requires a few bytes of working area.
9184 @deffn {Command} {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
9185 Displays the value of the flag controlling use of memory writes and reads
9186 that don't check completion of the operation.
9187 If a boolean parameter is provided, first assigns that flag.
9189 This provides a huge speed increase, especially with USB JTAG
9190 cables (FT2232), but might be unsafe if used with targets running at very low
9191 speeds, like the 32kHz startup clock of an AT91RM9200.
9194 @subsection ARM9 specific commands
9197 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
9199 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
9201 @c 9-june-2009: tried this on arm920t, it didn't work.
9202 @c no-params always lists nothing caught, and that's how it acts.
9203 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
9204 @c versions have different rules about when they commit writes.
9206 @anchor{arm9vectorcatch}
9207 @deffn {Command} {arm9 vector_catch} [@option{all}|@option{none}|list]
9208 @cindex vector_catch
9209 Vector Catch hardware provides a sort of dedicated breakpoint
9210 for hardware events such as reset, interrupt, and abort.
9211 You can use this to conserve normal breakpoint resources,
9212 so long as you're not concerned with code that branches directly
9213 to those hardware vectors.
9215 This always finishes by listing the current configuration.
9216 If parameters are provided, it first reconfigures the
9217 vector catch hardware to intercept
9218 @option{all} of the hardware vectors,
9219 @option{none} of them,
9220 or a list with one or more of the following:
9221 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
9222 @option{irq} @option{fiq}.
9225 @subsection ARM920T specific commands
9228 These commands are available to ARM920T based CPUs,
9229 which are implementations of the ARMv4T architecture
9230 built using the ARM9TDMI integer core.
9231 They are available in addition to the ARM, ARM7/ARM9,
9234 @deffn {Command} {arm920t cache_info}
9235 Print information about the caches found. This allows to see whether your target
9236 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
9239 @deffn {Command} {arm920t cp15} regnum [value]
9240 Display cp15 register @var{regnum};
9241 else if a @var{value} is provided, that value is written to that register.
9242 This uses "physical access" and the register number is as
9243 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
9244 (Not all registers can be written.)
9247 @deffn {Command} {arm920t read_cache} filename
9248 Dump the content of ICache and DCache to a file named @file{filename}.
9251 @deffn {Command} {arm920t read_mmu} filename
9252 Dump the content of the ITLB and DTLB to a file named @file{filename}.
9255 @subsection ARM926ej-s specific commands
9258 These commands are available to ARM926ej-s based CPUs,
9259 which are implementations of the ARMv5TEJ architecture
9260 based on the ARM9EJ-S integer core.
9261 They are available in addition to the ARM, ARM7/ARM9,
9264 The Feroceon cores also support these commands, although
9265 they are not built from ARM926ej-s designs.
9267 @deffn {Command} {arm926ejs cache_info}
9268 Print information about the caches found.
9271 @subsection ARM966E specific commands
9274 These commands are available to ARM966 based CPUs,
9275 which are implementations of the ARMv5TE architecture.
9276 They are available in addition to the ARM, ARM7/ARM9,
9279 @deffn {Command} {arm966e cp15} regnum [value]
9280 Display cp15 register @var{regnum};
9281 else if a @var{value} is provided, that value is written to that register.
9282 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
9284 There is no current control over bits 31..30 from that table,
9285 as required for BIST support.
9288 @subsection XScale specific commands
9291 Some notes about the debug implementation on the XScale CPUs:
9293 The XScale CPU provides a special debug-only mini-instruction cache
9294 (mini-IC) in which exception vectors and target-resident debug handler
9295 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
9296 must point vector 0 (the reset vector) to the entry of the debug
9297 handler. However, this means that the complete first cacheline in the
9298 mini-IC is marked valid, which makes the CPU fetch all exception
9299 handlers from the mini-IC, ignoring the code in RAM.
9301 To address this situation, OpenOCD provides the @code{xscale
9302 vector_table} command, which allows the user to explicitly write
9303 individual entries to either the high or low vector table stored in
9306 It is recommended to place a pc-relative indirect branch in the vector
9307 table, and put the branch destination somewhere in memory. Doing so
9308 makes sure the code in the vector table stays constant regardless of
9309 code layout in memory:
9312 ldr pc,[pc,#0x100-8]
9313 ldr pc,[pc,#0x100-8]
9314 ldr pc,[pc,#0x100-8]
9315 ldr pc,[pc,#0x100-8]
9316 ldr pc,[pc,#0x100-8]
9317 ldr pc,[pc,#0x100-8]
9318 ldr pc,[pc,#0x100-8]
9319 ldr pc,[pc,#0x100-8]
9321 .long real_reset_vector
9322 .long real_ui_handler
9323 .long real_swi_handler
9325 .long real_data_abort
9326 .long 0 /* unused */
9327 .long real_irq_handler
9328 .long real_fiq_handler
9331 Alternatively, you may choose to keep some or all of the mini-IC
9332 vector table entries synced with those written to memory by your
9333 system software. The mini-IC can not be modified while the processor
9334 is executing, but for each vector table entry not previously defined
9335 using the @code{xscale vector_table} command, OpenOCD will copy the
9336 value from memory to the mini-IC every time execution resumes from a
9337 halt. This is done for both high and low vector tables (although the
9338 table not in use may not be mapped to valid memory, and in this case
9339 that copy operation will silently fail). This means that you will
9340 need to briefly halt execution at some strategic point during system
9341 start-up; e.g., after the software has initialized the vector table,
9342 but before exceptions are enabled. A breakpoint can be used to
9343 accomplish this once the appropriate location in the start-up code has
9344 been identified. A watchpoint over the vector table region is helpful
9345 in finding the location if you're not sure. Note that the same
9346 situation exists any time the vector table is modified by the system
9349 The debug handler must be placed somewhere in the address space using
9350 the @code{xscale debug_handler} command. The allowed locations for the
9351 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
9352 0xfffff800). The default value is 0xfe000800.
9354 XScale has resources to support two hardware breakpoints and two
9355 watchpoints. However, the following restrictions on watchpoint
9356 functionality apply: (1) the value and mask arguments to the @code{wp}
9357 command are not supported, (2) the watchpoint length must be a
9358 power of two and not less than four, and can not be greater than the
9359 watchpoint address, and (3) a watchpoint with a length greater than
9360 four consumes all the watchpoint hardware resources. This means that
9361 at any one time, you can have enabled either two watchpoints with a
9362 length of four, or one watchpoint with a length greater than four.
9364 These commands are available to XScale based CPUs,
9365 which are implementations of the ARMv5TE architecture.
9367 @deffn {Command} {xscale analyze_trace}
9368 Displays the contents of the trace buffer.
9371 @deffn {Command} {xscale cache_clean_address} address
9372 Changes the address used when cleaning the data cache.
9375 @deffn {Command} {xscale cache_info}
9376 Displays information about the CPU caches.
9379 @deffn {Command} {xscale cp15} regnum [value]
9380 Display cp15 register @var{regnum};
9381 else if a @var{value} is provided, that value is written to that register.
9384 @deffn {Command} {xscale debug_handler} target address
9385 Changes the address used for the specified target's debug handler.
9388 @deffn {Command} {xscale dcache} [@option{enable}|@option{disable}]
9389 Enables or disable the CPU's data cache.
9392 @deffn {Command} {xscale dump_trace} filename
9393 Dumps the raw contents of the trace buffer to @file{filename}.
9396 @deffn {Command} {xscale icache} [@option{enable}|@option{disable}]
9397 Enables or disable the CPU's instruction cache.
9400 @deffn {Command} {xscale mmu} [@option{enable}|@option{disable}]
9401 Enables or disable the CPU's memory management unit.
9404 @deffn {Command} {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
9405 Displays the trace buffer status, after optionally
9406 enabling or disabling the trace buffer
9407 and modifying how it is emptied.
9410 @deffn {Command} {xscale trace_image} filename [offset [type]]
9411 Opens a trace image from @file{filename}, optionally rebasing
9412 its segment addresses by @var{offset}.
9413 The image @var{type} may be one of
9414 @option{bin} (binary), @option{ihex} (Intel hex),
9415 @option{elf} (ELF file), @option{s19} (Motorola s19),
9416 @option{mem}, or @option{builder}.
9419 @anchor{xscalevectorcatch}
9420 @deffn {Command} {xscale vector_catch} [mask]
9421 @cindex vector_catch
9422 Display a bitmask showing the hardware vectors to catch.
9423 If the optional parameter is provided, first set the bitmask to that value.
9425 The mask bits correspond with bit 16..23 in the DCSR:
9428 0x02 Trap Undefined Instructions
9429 0x04 Trap Software Interrupt
9430 0x08 Trap Prefetch Abort
9431 0x10 Trap Data Abort
9438 @deffn {Command} {xscale vector_table} [(@option{low}|@option{high}) index value]
9439 @cindex vector_table
9441 Set an entry in the mini-IC vector table. There are two tables: one for
9442 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
9443 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
9444 points to the debug handler entry and can not be overwritten.
9445 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
9447 Without arguments, the current settings are displayed.
9451 @section ARMv6 Architecture
9454 @subsection ARM11 specific commands
9457 @deffn {Command} {arm11 memwrite burst} [@option{enable}|@option{disable}]
9458 Displays the value of the memwrite burst-enable flag,
9459 which is enabled by default.
9460 If a boolean parameter is provided, first assigns that flag.
9461 Burst writes are only used for memory writes larger than 1 word.
9462 They improve performance by assuming that the CPU has read each data
9463 word over JTAG and completed its write before the next word arrives,
9464 instead of polling for a status flag to verify that completion.
9465 This is usually safe, because JTAG runs much slower than the CPU.
9468 @deffn {Command} {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
9469 Displays the value of the memwrite error_fatal flag,
9470 which is enabled by default.
9471 If a boolean parameter is provided, first assigns that flag.
9472 When set, certain memory write errors cause earlier transfer termination.
9475 @deffn {Command} {arm11 step_irq_enable} [@option{enable}|@option{disable}]
9476 Displays the value of the flag controlling whether
9477 IRQs are enabled during single stepping;
9478 they are disabled by default.
9479 If a boolean parameter is provided, first assigns that.
9482 @deffn {Command} {arm11 vcr} [value]
9483 @cindex vector_catch
9484 Displays the value of the @emph{Vector Catch Register (VCR)},
9485 coprocessor 14 register 7.
9486 If @var{value} is defined, first assigns that.
9488 Vector Catch hardware provides dedicated breakpoints
9489 for certain hardware events.
9490 The specific bit values are core-specific (as in fact is using
9491 coprocessor 14 register 7 itself) but all current ARM11
9492 cores @emph{except the ARM1176} use the same six bits.
9495 @section ARMv7 and ARMv8 Architecture
9499 @subsection ARMv7-A specific commands
9502 @deffn {Command} {cortex_a cache_info}
9503 display information about target caches
9506 @deffn {Command} {cortex_a dacrfixup} [@option{on}|@option{off}]
9507 Work around issues with software breakpoints when the program text is
9508 mapped read-only by the operating system. This option sets the CP15 DACR
9509 to "all-manager" to bypass MMU permission checks on memory access.
9513 @deffn {Command} {cortex_a dbginit}
9514 Initialize core debug
9515 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9518 @deffn {Command} {cortex_a smp} [on|off]
9519 Display/set the current SMP mode
9522 @deffn {Command} {cortex_a smp_gdb} [core_id]
9523 Display/set the current core displayed in GDB
9526 @deffn {Command} {cortex_a maskisr} [@option{on}|@option{off}]
9527 Selects whether interrupts will be processed when single stepping
9530 @deffn {Command} {cache_config l2x} [base way]
9534 @deffn {Command} {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
9535 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
9536 memory location @var{address}. When dumping the table from @var{address}, print at most
9537 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
9538 possible (4096) entries are printed.
9541 @subsection ARMv7-R specific commands
9544 @deffn {Command} {cortex_r4 dbginit}
9545 Initialize core debug
9546 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9549 @deffn {Command} {cortex_r4 maskisr} [@option{on}|@option{off}]
9550 Selects whether interrupts will be processed when single stepping
9554 @subsection ARM CoreSight TPIU and SWO specific commands
9560 ARM CoreSight provides several modules to generate debugging
9561 information internally (ITM, DWT and ETM). Their output is directed
9562 through TPIU or SWO modules to be captured externally either on an SWO pin (this
9563 configuration is called SWV) or on a synchronous parallel trace port.
9565 ARM CoreSight provides independent HW blocks named TPIU and SWO each with its
9566 own functionality. Embedded in Cortex-M3 and M4, ARM provides an optional HW
9567 block that includes both TPIU and SWO functionalities and is again named TPIU,
9568 which causes quite some confusion.
9569 The registers map of all the TPIU and SWO implementations allows using a single
9570 driver that detects at runtime the features available.
9572 The @command{tpiu} is used for either TPIU or SWO.
9573 A convenient alias @command{swo} is available to help distinguish, in scripts,
9574 the commands for SWO from the commands for TPIU.
9576 @deffn {Command} {swo} ...
9577 Alias of @command{tpiu ...}. Can be used in scripts to distinguish the commands
9578 for SWO from the commands for TPIU.
9581 @deffn {Command} {tpiu create} tpiu_name configparams...
9582 Creates a TPIU or a SWO object. The two commands are equivalent.
9583 Add the object in a list and add new commands (@command{@var{tpiu_name}})
9584 which are used for various purposes including additional configuration.
9587 @item @var{tpiu_name} -- the name of the TPIU or SWO object.
9588 This name is also used to create the object's command, referred to here
9589 as @command{$tpiu_name}, and in other places where the TPIU or SWO needs to be identified.
9590 @item @var{configparams} -- all parameters accepted by @command{$tpiu_name configure} are permitted.
9592 You @emph{must} set here the AP and MEM_AP base_address through @code{-dap @var{dap_name}},
9593 @code{-ap-num @var{ap_number}} and @code{-baseaddr @var{base_address}}.
9597 @deffn {Command} {tpiu names}
9598 Lists all the TPIU or SWO objects created so far. The two commands are equivalent.
9601 @deffn {Command} {tpiu init}
9602 Initialize all registered TPIU and SWO. The two commands are equivalent.
9603 These commands are used internally during initialization. They can be issued
9604 at any time after the initialization, too.
9607 @deffn {Command} {$tpiu_name cget} queryparm
9608 Each configuration parameter accepted by @command{$tpiu_name configure} can be
9609 individually queried, to return its current value.
9610 The @var{queryparm} is a parameter name accepted by that command, such as @code{-dap}.
9613 @deffn {Command} {$tpiu_name configure} configparams...
9614 The options accepted by this command may also be specified as parameters
9615 to @command{tpiu create}. Their values can later be queried one at a time by
9616 using the @command{$tpiu_name cget} command.
9619 @item @code{-dap} @var{dap_name} -- names the DAP used to access this
9620 TPIU. @xref{dapdeclaration,,DAP declaration}, on how to create and manage DAP instances.
9622 @item @code{-ap-num} @var{ap_number} -- sets DAP access port for TPIU,
9623 @var{ap_number} is the numeric index of the DAP AP the TPIU is connected to.
9625 @item @code{-baseaddr} @var{base_address} -- sets the TPIU @var{base_address} where
9626 to access the TPIU in the DAP AP memory space.
9628 @item @code{-protocol} (@option{sync}|@option{uart}|@option{manchester}) -- sets the
9629 protocol used for trace data:
9631 @item @option{sync} -- synchronous parallel trace output mode, using @var{port_width}
9632 data bits (default);
9633 @item @option{uart} -- use asynchronous SWO mode with NRZ (same as regular UART 8N1) coding;
9634 @item @option{manchester} -- use asynchronous SWO mode with Manchester coding.
9637 @item @code{-event} @var{event_name} @var{event_body} -- assigns an event handler,
9638 a TCL string which is evaluated when the event is triggered. The events
9639 @code{pre-enable}, @code{post-enable}, @code{pre-disable} and @code{post-disable}
9640 are defined for TPIU/SWO.
9641 A typical use case for the event @code{pre-enable} is to enable the trace clock
9644 @item @code{-output} (@option{external}|@option{:}@var{port}|@var{filename}|@option{-}) -- specifies
9645 the destination of the trace data:
9647 @item @option{external} -- configure TPIU/SWO to let user capture trace
9648 output externally, either with an additional UART or with a logic analyzer (default);
9649 @item @option{-} -- configure TPIU/SWO and debug adapter to gather trace data
9650 and forward it to @command{tcl_trace} command;
9651 @item @option{:}@var{port} -- configure TPIU/SWO and debug adapter to gather
9652 trace data, open a TCP server at port @var{port} and send the trace data to
9653 each connected client;
9654 @item @var{filename} -- configure TPIU/SWO and debug adapter to
9655 gather trace data and append it to @var{filename}, which can be
9656 either a regular file or a named pipe.
9659 @item @code{-traceclk} @var{TRACECLKIN_freq} -- mandatory parameter.
9660 Specifies the frequency in Hz of the trace clock. For the TPIU embedded in
9661 Cortex-M3 or M4, this is usually the same frequency as HCLK. For protocol
9662 @option{sync} this is twice the frequency of the pin data rate.
9664 @item @code{-pin-freq} @var{trace_freq} -- specifies the expected data rate
9665 in Hz of the SWO pin. Parameter used only on protocols @option{uart} and
9666 @option{manchester}. Can be omitted to let the adapter driver select the
9667 maximum supported rate automatically.
9669 @item @code{-port-width} @var{port_width} -- sets to @var{port_width} the width
9670 of the synchronous parallel port used for trace output. Parameter used only on
9671 protocol @option{sync}. If not specified, default value is @var{1}.
9673 @item @code{-formatter} (@option{0}|@option{1}) -- specifies if the formatter
9674 should be enabled. Parameter used only on protocol @option{sync}. If not specified,
9675 default value is @var{0}.
9679 @deffn {Command} {$tpiu_name enable}
9680 Uses the parameters specified by the previous @command{$tpiu_name configure}
9681 to configure and enable the TPIU or the SWO.
9682 If required, the adapter is also configured and enabled to receive the trace
9684 This command can be used before @command{init}, but it will take effect only
9685 after the @command{init}.
9688 @deffn {Command} {$tpiu_name disable}
9689 Disable the TPIU or the SWO, terminating the receiving of the trace data.
9696 @item STM32L152 board is programmed with an application that configures
9697 PLL to provide core clock with 24MHz frequency; to use ITM output it's
9700 #include <libopencm3/cm3/itm.h>
9705 (the most obvious way is to use the first stimulus port for printf,
9706 for that this ITM_STIM8 assignment can be used inside _write(); to make it
9707 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
9708 ITM_STIM_FIFOREADY));});
9709 @item An FT2232H UART is connected to the SWO pin of the board;
9710 @item Commands to configure UART for 12MHz baud rate:
9712 $ setserial /dev/ttyUSB1 spd_cust divisor 5
9713 $ stty -F /dev/ttyUSB1 38400
9715 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
9716 baud with our custom divisor to get 12MHz)
9717 @item @code{itmdump -f /dev/ttyUSB1 -d1}
9718 @item OpenOCD invocation line:
9720 openocd -f interface/stlink.cfg \
9721 -c "transport select hla_swd" \
9722 -f target/stm32l1.cfg \
9723 -c "stm32l1.tpiu configure -protocol uart" \
9724 -c "stm32l1.tpiu configure -traceclk 24000000 -pin-freq 12000000" \
9725 -c "stm32l1.tpiu enable"
9729 @subsection ARMv7-M specific commands
9736 @deffn {Command} {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
9737 Enable or disable trace output for ITM stimulus @var{port} (counting
9738 from 0). Port 0 is enabled on target creation automatically.
9741 @deffn {Command} {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
9742 Enable or disable trace output for all ITM stimulus ports.
9745 @subsection Cortex-M specific commands
9748 @deffn {Command} {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
9749 Control masking (disabling) interrupts during target step/resume.
9751 The @option{auto} option handles interrupts during stepping in a way that they
9752 get served but don't disturb the program flow. The step command first allows
9753 pending interrupt handlers to execute, then disables interrupts and steps over
9754 the next instruction where the core was halted. After the step interrupts
9755 are enabled again. If the interrupt handlers don't complete within 500ms,
9756 the step command leaves with the core running.
9758 The @option{steponly} option disables interrupts during single-stepping but
9759 enables them during normal execution. This can be used as a partial workaround
9760 for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
9761 FPU (AT611) Software Developer Errata Notice" from ARM for further details.
9763 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
9764 option. If no breakpoint is available at the time of the step, then the step
9765 is taken with interrupts enabled, i.e. the same way the @option{off} option
9768 Default is @option{auto}.
9771 @deffn {Command} {cortex_m vector_catch} [@option{all}|@option{none}|list]
9772 @cindex vector_catch
9773 Vector Catch hardware provides dedicated breakpoints
9774 for certain hardware events.
9776 Parameters request interception of
9777 @option{all} of these hardware event vectors,
9778 @option{none} of them,
9779 or one or more of the following:
9780 @option{hard_err} for a HardFault exception;
9781 @option{mm_err} for a MemManage exception;
9782 @option{bus_err} for a BusFault exception;
9785 @option{chk_err}, or
9786 @option{nocp_err} for various UsageFault exceptions; or
9788 If NVIC setup code does not enable them,
9789 MemManage, BusFault, and UsageFault exceptions
9790 are mapped to HardFault.
9791 UsageFault checks for
9792 divide-by-zero and unaligned access
9793 must also be explicitly enabled.
9795 This finishes by listing the current vector catch configuration.
9798 @deffn {Command} {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
9799 Control reset handling if hardware srst is not fitted
9800 @xref{reset_config,,reset_config}.
9803 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
9804 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
9807 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
9808 This however has the disadvantage of only resetting the core, all peripherals
9809 are unaffected. A solution would be to use a @code{reset-init} event handler
9810 to manually reset the peripherals.
9811 @xref{targetevents,,Target Events}.
9813 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
9817 @subsection ARMv8-A specific commands
9821 @deffn {Command} {aarch64 cache_info}
9822 Display information about target caches
9825 @deffn {Command} {aarch64 dbginit}
9826 This command enables debugging by clearing the OS Lock and sticky power-down and reset
9827 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
9828 target code relies on. In a configuration file, the command would typically be called from a
9829 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
9830 However, normally it is not necessary to use the command at all.
9833 @deffn {Command} {aarch64 disassemble} address [count]
9835 Disassembles @var{count} instructions starting at @var{address}.
9836 If @var{count} is not specified, a single instruction is disassembled.
9839 @deffn {Command} {aarch64 smp} [on|off]
9840 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
9841 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
9842 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
9843 group. With SMP handling disabled, all targets need to be treated individually.
9846 @deffn {Command} {aarch64 maskisr} [@option{on}|@option{off}]
9847 Selects whether interrupts will be processed when single stepping. The default configuration is
9851 @deffn {Command} {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
9852 Cause @command{$target_name} to halt when an exception is taken. Any combination of
9853 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
9854 @command{$target_name} will halt before taking the exception. In order to resume
9855 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
9856 Issuing the command without options prints the current configuration.
9859 @section EnSilica eSi-RISC Architecture
9861 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
9862 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
9864 @subsection eSi-RISC Configuration
9866 @deffn {Command} {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
9867 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
9868 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
9871 @deffn {Command} {esirisc hwdc} (@option{all}|@option{none}|mask ...)
9872 Configure hardware debug control. The HWDC register controls which exceptions return
9873 control back to the debugger. Possible masks are @option{all}, @option{none},
9874 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
9875 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
9878 @subsection eSi-RISC Operation
9880 @deffn {Command} {esirisc flush_caches}
9881 Flush instruction and data caches. This command requires that the target is halted
9882 when the command is issued and configured with an instruction or data cache.
9885 @subsection eSi-Trace Configuration
9887 eSi-RISC targets may be configured with support for instruction tracing. Trace
9888 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
9889 is typically employed to move trace data off-device using a high-speed
9890 peripheral (eg. SPI). Collected trace data is encoded in one of three different
9891 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
9892 fifo} must be issued along with @command{esirisc trace format} before trace data
9895 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
9896 needed, collected trace data can be dumped to a file and processed by external
9900 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
9901 for this issue is to configure DMA to copy trace data to an in-memory buffer,
9902 which can then be passed to the @command{esirisc trace analyze} and
9903 @command{esirisc trace dump} commands.
9905 It is possible to corrupt trace data when using a FIFO if the peripheral
9906 responsible for draining data from the FIFO is not fast enough. This can be
9907 managed by enabling flow control, however this can impact timing-sensitive
9908 software operation on the CPU.
9911 @deffn {Command} {esirisc trace buffer} address size [@option{wrap}]
9912 Configure trace buffer using the provided address and size. If the @option{wrap}
9913 option is specified, trace collection will continue once the end of the buffer
9914 is reached. By default, wrap is disabled.
9917 @deffn {Command} {esirisc trace fifo} address
9918 Configure trace FIFO using the provided address.
9921 @deffn {Command} {esirisc trace flow_control} (@option{enable}|@option{disable})
9922 Enable or disable stalling the CPU to collect trace data. By default, flow
9923 control is disabled.
9926 @deffn {Command} {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
9927 Configure trace format and number of PC bits to be captured. @option{pc_bits}
9928 must be within 1 and 31 as the LSB is not collected. If external tooling is used
9929 to analyze collected trace data, these values must match.
9931 Supported trace formats:
9933 @item @option{full} capture full trace data, allowing execution history and
9934 timing to be determined.
9935 @item @option{branch} capture taken branch instructions and branch target
9937 @item @option{icache} capture instruction cache misses.
9941 @deffn {Command} {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
9942 Configure trigger start condition using the provided start data and mask. A
9943 brief description of each condition is provided below; for more detail on how
9944 these values are used, see the eSi-RISC Architecture Manual.
9946 Supported conditions:
9948 @item @option{none} manual tracing (see @command{esirisc trace start}).
9949 @item @option{pc} start tracing if the PC matches start data and mask.
9950 @item @option{load} start tracing if the effective address of a load
9951 instruction matches start data and mask.
9952 @item @option{store} start tracing if the effective address of a store
9953 instruction matches start data and mask.
9954 @item @option{exception} start tracing if the EID of an exception matches start
9956 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
9957 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
9958 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
9959 @item @option{high} start tracing when an external signal is a logical high.
9960 @item @option{low} start tracing when an external signal is a logical low.
9964 @deffn {Command} {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
9965 Configure trigger stop condition using the provided stop data and mask. A brief
9966 description of each condition is provided below; for more detail on how these
9967 values are used, see the eSi-RISC Architecture Manual.
9969 Supported conditions:
9971 @item @option{none} manual tracing (see @command{esirisc trace stop}).
9972 @item @option{pc} stop tracing if the PC matches stop data and mask.
9973 @item @option{load} stop tracing if the effective address of a load
9974 instruction matches stop data and mask.
9975 @item @option{store} stop tracing if the effective address of a store
9976 instruction matches stop data and mask.
9977 @item @option{exception} stop tracing if the EID of an exception matches stop
9979 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
9980 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
9981 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
9985 @deffn {Command} {esirisc trace trigger delay} (@option{trigger}) [cycles]
9986 Configure trigger start/stop delay in clock cycles.
9990 @item @option{none} no delay to start or stop collection.
9991 @item @option{start} delay @option{cycles} after trigger to start collection.
9992 @item @option{stop} delay @option{cycles} after trigger to stop collection.
9993 @item @option{both} delay @option{cycles} after both triggers to start or stop
9998 @subsection eSi-Trace Operation
10000 @deffn {Command} {esirisc trace init}
10001 Initialize trace collection. This command must be called any time the
10002 configuration changes. If a trace buffer has been configured, the contents will
10003 be overwritten when trace collection starts.
10006 @deffn {Command} {esirisc trace info}
10007 Display trace configuration.
10010 @deffn {Command} {esirisc trace status}
10011 Display trace collection status.
10014 @deffn {Command} {esirisc trace start}
10015 Start manual trace collection.
10018 @deffn {Command} {esirisc trace stop}
10019 Stop manual trace collection.
10022 @deffn {Command} {esirisc trace analyze} [address size]
10023 Analyze collected trace data. This command may only be used if a trace buffer
10024 has been configured. If a trace FIFO has been configured, trace data must be
10025 copied to an in-memory buffer identified by the @option{address} and
10026 @option{size} options using DMA.
10029 @deffn {Command} {esirisc trace dump} [address size] @file{filename}
10030 Dump collected trace data to file. This command may only be used if a trace
10031 buffer has been configured. If a trace FIFO has been configured, trace data must
10032 be copied to an in-memory buffer identified by the @option{address} and
10033 @option{size} options using DMA.
10036 @section Intel Architecture
10038 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
10039 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
10040 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
10041 software debug and the CLTAP is used for SoC level operations.
10042 Useful docs are here: https://communities.intel.com/community/makers/documentation
10044 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
10045 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
10046 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
10049 @subsection x86 32-bit specific commands
10050 The three main address spaces for x86 are memory, I/O and configuration space.
10051 These commands allow a user to read and write to the 64Kbyte I/O address space.
10053 @deffn {Command} {x86_32 idw} address
10054 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
10057 @deffn {Command} {x86_32 idh} address
10058 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
10061 @deffn {Command} {x86_32 idb} address
10062 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
10065 @deffn {Command} {x86_32 iww} address
10066 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
10069 @deffn {Command} {x86_32 iwh} address
10070 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
10073 @deffn {Command} {x86_32 iwb} address
10074 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
10077 @section OpenRISC Architecture
10079 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
10080 configured with any of the TAP / Debug Unit available.
10082 @subsection TAP and Debug Unit selection commands
10083 @deffn {Command} {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
10084 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
10086 @deffn {Command} {du_select} (@option{adv}|@option{mohor}) [option]
10087 Select between the Advanced Debug Interface and the classic one.
10089 An option can be passed as a second argument to the debug unit.
10091 When using the Advanced Debug Interface, option = 1 means the RTL core is
10092 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
10093 between bytes while doing read or write bursts.
10096 @subsection Registers commands
10097 @deffn {Command} {addreg} [name] [address] [feature] [reg_group]
10098 Add a new register in the cpu register list. This register will be
10099 included in the generated target descriptor file.
10101 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
10103 @strong{[reg_group]} can be anything. The default register list defines "system",
10104 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
10105 and "timer" groups.
10109 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
10114 @section RISC-V Architecture
10116 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
10117 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
10118 harts. (It's possible to increase this limit to 1024 by changing
10119 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
10120 Debug Specification, but there is also support for legacy targets that
10121 implement version 0.11.
10123 @subsection RISC-V Terminology
10125 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
10126 another hart, or may be a separate core. RISC-V treats those the same, and
10127 OpenOCD exposes each hart as a separate core.
10129 @subsection RISC-V Debug Configuration Commands
10131 @deffn {Command} {riscv expose_csrs} n0[-m0][,n1[-m1]]...
10132 Configure a list of inclusive ranges for CSRs to expose in addition to the
10133 standard ones. This must be executed before `init`.
10135 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
10136 and then only if the corresponding extension appears to be implemented. This
10137 command can be used if OpenOCD gets this wrong, or a target implements custom
10141 @deffn {Command} {riscv expose_custom} n0[-m0][,n1[-m1]]...
10142 The RISC-V Debug Specification allows targets to expose custom registers
10143 through abstract commands. (See Section 3.5.1.1 in that document.) This command
10144 configures a list of inclusive ranges of those registers to expose. Number 0
10145 indicates the first custom register, whose abstract command number is 0xc000.
10146 This command must be executed before `init`.
10149 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
10150 Set the wall-clock timeout (in seconds) for individual commands. The default
10151 should work fine for all but the slowest targets (eg. simulators).
10154 @deffn {Command} {riscv set_reset_timeout_sec} [seconds]
10155 Set the maximum time to wait for a hart to come out of reset after reset is
10159 @deffn {Command} {riscv set_prefer_sba} on|off
10160 When on, prefer to use System Bus Access to access memory. When off (default),
10161 prefer to use the Program Buffer to access memory.
10164 @deffn {Command} {riscv set_enable_virtual} on|off
10165 When on, memory accesses are performed on physical or virtual memory depending
10166 on the current system configuration. When off (default), all memory accessses are performed
10167 on physical memory.
10170 @deffn {Command} {riscv set_enable_virt2phys} on|off
10171 When on (default), memory accesses are performed on physical or virtual memory
10172 depending on the current satp configuration. When off, all memory accessses are
10173 performed on physical memory.
10176 @deffn {Command} {riscv resume_order} normal|reversed
10177 Some software assumes all harts are executing nearly continuously. Such
10178 software may be sensitive to the order that harts are resumed in. On harts
10179 that don't support hasel, this option allows the user to choose the order the
10180 harts are resumed in. If you are using this option, it's probably masking a
10181 race condition problem in your code.
10183 Normal order is from lowest hart index to highest. This is the default
10184 behavior. Reversed order is from highest hart index to lowest.
10187 @deffn {Command} {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
10188 Set the IR value for the specified JTAG register. This is useful, for
10189 example, when using the existing JTAG interface on a Xilinx FPGA by
10190 way of BSCANE2 primitives that only permit a limited selection of IR
10193 When utilizing version 0.11 of the RISC-V Debug Specification,
10194 @option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL
10195 and DBUS registers, respectively.
10198 @deffn {Command} {riscv use_bscan_tunnel} value
10199 Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
10200 the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
10203 @deffn {Command} {riscv set_ebreakm} on|off
10204 Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
10205 OpenOCD. When off, they generate a breakpoint exception handled internally.
10208 @deffn {Command} {riscv set_ebreaks} on|off
10209 Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
10210 OpenOCD. When off, they generate a breakpoint exception handled internally.
10213 @deffn {Command} {riscv set_ebreaku} on|off
10214 Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
10215 OpenOCD. When off, they generate a breakpoint exception handled internally.
10218 @subsection RISC-V Authentication Commands
10220 The following commands can be used to authenticate to a RISC-V system. Eg. a
10221 trivial challenge-response protocol could be implemented as follows in a
10222 configuration file, immediately following @command{init}:
10224 set challenge [riscv authdata_read]
10225 riscv authdata_write [expr $challenge + 1]
10228 @deffn {Command} {riscv authdata_read}
10229 Return the 32-bit value read from authdata.
10232 @deffn {Command} {riscv authdata_write} value
10233 Write the 32-bit value to authdata.
10236 @subsection RISC-V DMI Commands
10238 The following commands allow direct access to the Debug Module Interface, which
10239 can be used to interact with custom debug features.
10241 @deffn {Command} {riscv dmi_read} address
10242 Perform a 32-bit DMI read at address, returning the value.
10245 @deffn {Command} {riscv dmi_write} address value
10246 Perform a 32-bit DMI write of value at address.
10249 @section ARC Architecture
10252 Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
10253 designers can optimize for a wide range of uses, from deeply embedded to
10254 high-performance host applications in a variety of market segments. See more
10255 at: @url{http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx}.
10256 OpenOCD currently supports ARC EM processors.
10257 There is a set ARC-specific OpenOCD commands that allow low-level
10258 access to the core and provide necessary support for ARC extensibility and
10259 configurability capabilities. ARC processors has much more configuration
10260 capabilities than most of the other processors and in addition there is an
10261 extension interface that allows SoC designers to add custom registers and
10262 instructions. For the OpenOCD that mostly means that set of core and AUX
10263 registers in target will vary and is not fixed for a particular processor
10264 model. To enable extensibility several TCL commands are provided that allow to
10265 describe those optional registers in OpenOCD configuration files. Moreover
10266 those commands allow for a dynamic target features discovery.
10269 @subsection General ARC commands
10271 @deffn {Config Command} {arc add-reg} configparams
10273 Add a new register to processor target. By default newly created register is
10274 marked as not existing. @var{configparams} must have following required
10279 @item @code{-name} name
10280 @*Name of a register.
10282 @item @code{-num} number
10283 @*Architectural register number: core register number or AUX register number.
10285 @item @code{-feature} XML_feature
10286 @*Name of GDB XML target description feature.
10290 @var{configparams} may have following optional arguments:
10294 @item @code{-gdbnum} number
10295 @*GDB register number. It is recommended to not assign GDB register number
10296 manually, because there would be a risk that two register will have same
10297 number. When register GDB number is not set with this option, then register
10298 will get a previous register number + 1. This option is required only for those
10299 registers that must be at particular address expected by GDB.
10302 @*This option specifies that register is a core registers. If not - this is an
10303 AUX register. AUX registers and core registers reside in different address
10307 @*This options specifies that register is a BCR register. BCR means Build
10308 Configuration Registers - this is a special type of AUX registers that are read
10309 only and non-volatile, that is - they never change their value. Therefore OpenOCD
10310 never invalidates values of those registers in internal caches. Because BCR is a
10311 type of AUX registers, this option cannot be used with @code{-core}.
10313 @item @code{-type} type_name
10314 @*Name of type of this register. This can be either one of the basic GDB types,
10315 or a custom types described with @command{arc add-reg-type-[flags|struct]}.
10318 @* If specified then this is a "general" register. General registers are always
10319 read by OpenOCD on context save (when core has just been halted) and is always
10320 transferred to GDB client in a response to g-packet. Contrary to this,
10321 non-general registers are read and sent to GDB client on-demand. In general it
10322 is not recommended to apply this option to custom registers.
10328 @deffn {Config Command} {arc add-reg-type-flags} -name name flags...
10329 Adds new register type of ``flags'' class. ``Flags'' types can contain only
10330 one-bit fields. Each flag definition looks like @code{-flag name bit-position}.
10333 @anchor{add-reg-type-struct}
10334 @deffn {Config Command} {arc add-reg-type-struct} -name name structs...
10335 Adds new register type of ``struct'' class. ``Struct'' types can contain either
10336 bit-fields or fields of other types, however at the moment only bit fields are
10337 supported. Structure bit field definition looks like @code{-bitfield name
10341 @deffn {Command} {arc get-reg-field} reg-name field-name
10342 Returns value of bit-field in a register. Register must be ``struct'' register
10343 type, @xref{add-reg-type-struct}. command definition.
10346 @deffn {Command} {arc set-reg-exists} reg-names...
10347 Specify that some register exists. Any amount of names can be passed
10348 as an argument for a single command invocation.
10351 @subsection ARC JTAG commands
10353 @deffn {Command} {arc jtag set-aux-reg} regnum value
10354 This command writes value to AUX register via its number. This command access
10355 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10356 therefore it is unsafe to use if that register can be operated by other means.
10360 @deffn {Command} {arc jtag set-core-reg} regnum value
10361 This command is similar to @command{arc jtag set-aux-reg} but is for core
10365 @deffn {Command} {arc jtag get-aux-reg} regnum
10366 This command returns the value storded in AUX register via its number. This commands access
10367 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10368 therefore it is unsafe to use if that register can be operated by other means.
10372 @deffn {Command} {arc jtag get-core-reg} regnum
10373 This command is similar to @command{arc jtag get-aux-reg} but is for core
10377 @section STM8 Architecture
10378 @uref{http://st.com/stm8/, STM8} is a 8-bit microcontroller platform from
10379 STMicroelectronics, based on a proprietary 8-bit core architecture.
10381 OpenOCD supports debugging STM8 through the STMicroelectronics debug
10382 protocol SWIM, @pxref{swimtransport,,SWIM}.
10384 @anchor{softwaredebugmessagesandtracing}
10385 @section Software Debug Messages and Tracing
10386 @cindex Linux-ARM DCC support
10390 OpenOCD can process certain requests from target software, when
10391 the target uses appropriate libraries.
10392 The most powerful mechanism is semihosting, but there is also
10393 a lighter weight mechanism using only the DCC channel.
10395 Currently @command{target_request debugmsgs}
10396 is supported only for @option{arm7_9} and @option{cortex_m} cores.
10397 These messages are received as part of target polling, so
10398 you need to have @command{poll on} active to receive them.
10399 They are intrusive in that they will affect program execution
10400 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
10402 See @file{libdcc} in the contrib dir for more details.
10403 In addition to sending strings, characters, and
10404 arrays of various size integers from the target,
10405 @file{libdcc} also exports a software trace point mechanism.
10406 The target being debugged may
10407 issue trace messages which include a 24-bit @dfn{trace point} number.
10408 Trace point support includes two distinct mechanisms,
10409 each supported by a command:
10412 @item @emph{History} ... A circular buffer of trace points
10413 can be set up, and then displayed at any time.
10414 This tracks where code has been, which can be invaluable in
10415 finding out how some fault was triggered.
10417 The buffer may overflow, since it collects records continuously.
10418 It may be useful to use some of the 24 bits to represent a
10419 particular event, and other bits to hold data.
10421 @item @emph{Counting} ... An array of counters can be set up,
10422 and then displayed at any time.
10423 This can help establish code coverage and identify hot spots.
10425 The array of counters is directly indexed by the trace point
10426 number, so trace points with higher numbers are not counted.
10429 Linux-ARM kernels have a ``Kernel low-level debugging
10430 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
10431 depends on CONFIG_DEBUG_LL) which uses this mechanism to
10432 deliver messages before a serial console can be activated.
10433 This is not the same format used by @file{libdcc}.
10434 Other software, such as the U-Boot boot loader, sometimes
10435 does the same thing.
10437 @deffn {Command} {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
10438 Displays current handling of target DCC message requests.
10439 These messages may be sent to the debugger while the target is running.
10440 The optional @option{enable} and @option{charmsg} parameters
10441 both enable the messages, while @option{disable} disables them.
10443 With @option{charmsg} the DCC words each contain one character,
10444 as used by Linux with CONFIG_DEBUG_ICEDCC;
10445 otherwise the libdcc format is used.
10448 @deffn {Command} {trace history} [@option{clear}|count]
10449 With no parameter, displays all the trace points that have triggered
10450 in the order they triggered.
10451 With the parameter @option{clear}, erases all current trace history records.
10452 With a @var{count} parameter, allocates space for that many
10456 @deffn {Command} {trace point} [@option{clear}|identifier]
10457 With no parameter, displays all trace point identifiers and how many times
10458 they have been triggered.
10459 With the parameter @option{clear}, erases all current trace point counters.
10460 With a numeric @var{identifier} parameter, creates a new a trace point counter
10461 and associates it with that identifier.
10463 @emph{Important:} The identifier and the trace point number
10464 are not related except by this command.
10465 These trace point numbers always start at zero (from server startup,
10466 or after @command{trace point clear}) and count up from there.
10470 @node JTAG Commands
10471 @chapter JTAG Commands
10472 @cindex JTAG Commands
10473 Most general purpose JTAG commands have been presented earlier.
10474 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
10475 Lower level JTAG commands, as presented here,
10476 may be needed to work with targets which require special
10477 attention during operations such as reset or initialization.
10479 To use these commands you will need to understand some
10480 of the basics of JTAG, including:
10483 @item A JTAG scan chain consists of a sequence of individual TAP
10484 devices such as a CPUs.
10485 @item Control operations involve moving each TAP through the same
10486 standard state machine (in parallel)
10487 using their shared TMS and clock signals.
10488 @item Data transfer involves shifting data through the chain of
10489 instruction or data registers of each TAP, writing new register values
10490 while the reading previous ones.
10491 @item Data register sizes are a function of the instruction active in
10492 a given TAP, while instruction register sizes are fixed for each TAP.
10493 All TAPs support a BYPASS instruction with a single bit data register.
10494 @item The way OpenOCD differentiates between TAP devices is by
10495 shifting different instructions into (and out of) their instruction
10499 @section Low Level JTAG Commands
10501 These commands are used by developers who need to access
10502 JTAG instruction or data registers, possibly controlling
10503 the order of TAP state transitions.
10504 If you're not debugging OpenOCD internals, or bringing up a
10505 new JTAG adapter or a new type of TAP device (like a CPU or
10506 JTAG router), you probably won't need to use these commands.
10507 In a debug session that doesn't use JTAG for its transport protocol,
10508 these commands are not available.
10510 @deffn {Command} {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
10511 Loads the data register of @var{tap} with a series of bit fields
10512 that specify the entire register.
10513 Each field is @var{numbits} bits long with
10514 a numeric @var{value} (hexadecimal encouraged).
10515 The return value holds the original value of each
10518 For example, a 38 bit number might be specified as one
10519 field of 32 bits then one of 6 bits.
10520 @emph{For portability, never pass fields which are more
10521 than 32 bits long. Many OpenOCD implementations do not
10522 support 64-bit (or larger) integer values.}
10524 All TAPs other than @var{tap} must be in BYPASS mode.
10525 The single bit in their data registers does not matter.
10527 When @var{tap_state} is specified, the JTAG state machine is left
10529 For example @sc{drpause} might be specified, so that more
10530 instructions can be issued before re-entering the @sc{run/idle} state.
10531 If the end state is not specified, the @sc{run/idle} state is entered.
10534 OpenOCD does not record information about data register lengths,
10535 so @emph{it is important that you get the bit field lengths right}.
10536 Remember that different JTAG instructions refer to different
10537 data registers, which may have different lengths.
10538 Moreover, those lengths may not be fixed;
10539 the SCAN_N instruction can change the length of
10540 the register accessed by the INTEST instruction
10541 (by connecting a different scan chain).
10545 @deffn {Command} {flush_count}
10546 Returns the number of times the JTAG queue has been flushed.
10547 This may be used for performance tuning.
10549 For example, flushing a queue over USB involves a
10550 minimum latency, often several milliseconds, which does
10551 not change with the amount of data which is written.
10552 You may be able to identify performance problems by finding
10553 tasks which waste bandwidth by flushing small transfers too often,
10554 instead of batching them into larger operations.
10557 @deffn {Command} {irscan} [tap instruction]+ [@option{-endstate} tap_state]
10558 For each @var{tap} listed, loads the instruction register
10559 with its associated numeric @var{instruction}.
10560 (The number of bits in that instruction may be displayed
10561 using the @command{scan_chain} command.)
10562 For other TAPs, a BYPASS instruction is loaded.
10564 When @var{tap_state} is specified, the JTAG state machine is left
10566 For example @sc{irpause} might be specified, so the data register
10567 can be loaded before re-entering the @sc{run/idle} state.
10568 If the end state is not specified, the @sc{run/idle} state is entered.
10571 OpenOCD currently supports only a single field for instruction
10572 register values, unlike data register values.
10573 For TAPs where the instruction register length is more than 32 bits,
10574 portable scripts currently must issue only BYPASS instructions.
10578 @deffn {Command} {pathmove} start_state [next_state ...]
10579 Start by moving to @var{start_state}, which
10580 must be one of the @emph{stable} states.
10581 Unless it is the only state given, this will often be the
10582 current state, so that no TCK transitions are needed.
10583 Then, in a series of single state transitions
10584 (conforming to the JTAG state machine) shift to
10585 each @var{next_state} in sequence, one per TCK cycle.
10586 The final state must also be stable.
10589 @deffn {Command} {runtest} @var{num_cycles}
10590 Move to the @sc{run/idle} state, and execute at least
10591 @var{num_cycles} of the JTAG clock (TCK).
10592 Instructions often need some time
10593 to execute before they take effect.
10596 @c tms_sequence (short|long)
10597 @c ... temporary, debug-only, other than USBprog bug workaround...
10599 @deffn {Command} {verify_ircapture} (@option{enable}|@option{disable})
10600 Verify values captured during @sc{ircapture} and returned
10601 during IR scans. Default is enabled, but this can be
10602 overridden by @command{verify_jtag}.
10603 This flag is ignored when validating JTAG chain configuration.
10606 @deffn {Command} {verify_jtag} (@option{enable}|@option{disable})
10607 Enables verification of DR and IR scans, to help detect
10608 programming errors. For IR scans, @command{verify_ircapture}
10609 must also be enabled.
10610 Default is enabled.
10613 @section TAP state names
10614 @cindex TAP state names
10616 The @var{tap_state} names used by OpenOCD in the @command{drscan},
10617 @command{irscan}, and @command{pathmove} commands are the same
10618 as those used in SVF boundary scan documents, except that
10619 SVF uses @sc{idle} instead of @sc{run/idle}.
10622 @item @b{RESET} ... @emph{stable} (with TMS high);
10623 acts as if TRST were pulsed
10624 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
10626 @item @b{DRCAPTURE}
10627 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
10628 through the data register
10630 @item @b{DRPAUSE} ... @emph{stable}; data register ready
10631 for update or more shifting
10635 @item @b{IRCAPTURE}
10636 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
10637 through the instruction register
10639 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
10640 for update or more shifting
10645 Note that only six of those states are fully ``stable'' in the
10646 face of TMS fixed (low except for @sc{reset})
10647 and a free-running JTAG clock. For all the
10648 others, the next TCK transition changes to a new state.
10651 @item From @sc{drshift} and @sc{irshift}, clock transitions will
10652 produce side effects by changing register contents. The values
10653 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
10654 may not be as expected.
10655 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
10656 choices after @command{drscan} or @command{irscan} commands,
10657 since they are free of JTAG side effects.
10658 @item @sc{run/idle} may have side effects that appear at non-JTAG
10659 levels, such as advancing the ARM9E-S instruction pipeline.
10660 Consult the documentation for the TAP(s) you are working with.
10663 @node Boundary Scan Commands
10664 @chapter Boundary Scan Commands
10666 One of the original purposes of JTAG was to support
10667 boundary scan based hardware testing.
10668 Although its primary focus is to support On-Chip Debugging,
10669 OpenOCD also includes some boundary scan commands.
10671 @section SVF: Serial Vector Format
10672 @cindex Serial Vector Format
10675 The Serial Vector Format, better known as @dfn{SVF}, is a
10676 way to represent JTAG test patterns in text files.
10677 In a debug session using JTAG for its transport protocol,
10678 OpenOCD supports running such test files.
10680 @deffn {Command} {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
10681 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
10682 This issues a JTAG reset (Test-Logic-Reset) and then
10683 runs the SVF script from @file{filename}.
10685 Arguments can be specified in any order; the optional dash doesn't
10686 affect their semantics.
10690 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
10691 specified by the SVF file with HIR, TIR, HDR and TDR commands;
10692 instead, calculate them automatically according to the current JTAG
10693 chain configuration, targeting @var{tapname};
10694 @item @option{[-]quiet} do not log every command before execution;
10695 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
10696 on the real interface;
10697 @item @option{[-]progress} enable progress indication;
10698 @item @option{[-]ignore_error} continue execution despite TDO check
10703 @section XSVF: Xilinx Serial Vector Format
10704 @cindex Xilinx Serial Vector Format
10707 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
10708 binary representation of SVF which is optimized for use with
10710 In a debug session using JTAG for its transport protocol,
10711 OpenOCD supports running such test files.
10713 @quotation Important
10714 Not all XSVF commands are supported.
10717 @deffn {Command} {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
10718 This issues a JTAG reset (Test-Logic-Reset) and then
10719 runs the XSVF script from @file{filename}.
10720 When a @var{tapname} is specified, the commands are directed at
10722 When @option{virt2} is specified, the @sc{xruntest} command counts
10723 are interpreted as TCK cycles instead of microseconds.
10724 Unless the @option{quiet} option is specified,
10725 messages are logged for comments and some retries.
10728 The OpenOCD sources also include two utility scripts
10729 for working with XSVF; they are not currently installed
10730 after building the software.
10731 You may find them useful:
10734 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
10735 syntax understood by the @command{xsvf} command; see notes below.
10736 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
10737 understands the OpenOCD extensions.
10740 The input format accepts a handful of non-standard extensions.
10741 These include three opcodes corresponding to SVF extensions
10742 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
10743 two opcodes supporting a more accurate translation of SVF
10744 (XTRST, XWAITSTATE).
10745 If @emph{xsvfdump} shows a file is using those opcodes, it
10746 probably will not be usable with other XSVF tools.
10749 @section IPDBG: JTAG-Host server
10750 @cindex IPDBG JTAG-Host server
10753 IPDBG is a set of tools to debug IP-Cores. It comprises, among others, a logic analyzer and an arbitrary
10754 waveform generator. These are synthesize-able hardware descriptions of
10755 logic circuits in addition to software for control, visualization and further analysis.
10756 In a session using JTAG for its transport protocol, OpenOCD supports the function
10757 of a JTAG-Host. The JTAG-Host is needed to connect the circuit over JTAG to the
10758 control-software. For more details see @url{http://ipdbg.org}.
10760 @deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-tap @var{tapname}} @option{-hub @var{ir_value} [@var{dr_length}]} [@option{-port @var{number}}] [@option{-tool @var{number}}] [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}]
10761 Starts or stops a IPDBG JTAG-Host server. Arguments can be specified in any order.
10765 @item @option{-start|-stop} starts or stops a IPDBG JTAG-Host server (default: start).
10766 @item @option{-tap @var{tapname}} targeting the TAP @var{tapname}.
10767 @item @option{-hub @var{ir_value}} states that the JTAG hub is
10768 reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}.
10769 @item @option{-port @var{number}} tcp port number where the JTAG-Host is listening.
10770 @item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub.
10771 @item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} On some devices, the user data-register is only reachable if there is a
10772 specific value in a second dr. This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an
10773 access to the IPDBG-Hub. The value shifted into the vir is given by the first parameter @var{vir_value} (default: 0x11). The second
10774 parameter @var{length} is the length of the vir data register (default: 5). With the @var{instr_code} (default: 0x00e) parameter the ir value to
10775 shift data through vir can be configured.
10781 ipdbg -start -tap xc6s.tap -hub 0x02 -port 4242 -tool 4
10783 Starts a server listening on tcp-port 4242 which connects to tool 4.
10784 The connection is through the TAP of a Xilinx Spartan 6 on USER1 instruction (tested with a papillion pro board).
10787 ipdbg -start -tap 10m50.tap -hub 0x00C -vir -port 60000 -tool 1
10789 Starts a server listening on tcp-port 60000 which connects to tool 1 (data_up_1/data_down_1).
10790 The connection is through the TAP of a Intel MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is smaller than 5).
10792 @node Utility Commands
10793 @chapter Utility Commands
10794 @cindex Utility Commands
10796 @section RAM testing
10797 @cindex RAM testing
10799 There is often a need to stress-test random access memory (RAM) for
10800 errors. OpenOCD comes with a Tcl implementation of well-known memory
10801 testing procedures allowing the detection of all sorts of issues with
10802 electrical wiring, defective chips, PCB layout and other common
10805 To use them, you usually need to initialise your RAM controller first;
10806 consult your SoC's documentation to get the recommended list of
10807 register operations and translate them to the corresponding
10808 @command{mww}/@command{mwb} commands.
10810 Load the memory testing functions with
10813 source [find tools/memtest.tcl]
10816 to get access to the following facilities:
10818 @deffn {Command} {memTestDataBus} address
10819 Test the data bus wiring in a memory region by performing a walking
10820 1's test at a fixed address within that region.
10823 @deffn {Command} {memTestAddressBus} baseaddress size
10824 Perform a walking 1's test on the relevant bits of the address and
10825 check for aliasing. This test will find single-bit address failures
10826 such as stuck-high, stuck-low, and shorted pins.
10829 @deffn {Command} {memTestDevice} baseaddress size
10830 Test the integrity of a physical memory device by performing an
10831 increment/decrement test over the entire region. In the process every
10832 storage bit in the device is tested as zero and as one.
10835 @deffn {Command} {runAllMemTests} baseaddress size
10836 Run all of the above tests over a specified memory region.
10839 @section Firmware recovery helpers
10840 @cindex Firmware recovery
10842 OpenOCD includes an easy-to-use script to facilitate mass-market
10843 devices recovery with JTAG.
10845 For quickstart instructions run:
10847 openocd -f tools/firmware-recovery.tcl -c firmware_help
10850 @node GDB and OpenOCD
10851 @chapter GDB and OpenOCD
10853 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
10854 to debug remote targets.
10855 Setting up GDB to work with OpenOCD can involve several components:
10858 @item The OpenOCD server support for GDB may need to be configured.
10859 @xref{gdbconfiguration,,GDB Configuration}.
10860 @item GDB's support for OpenOCD may need configuration,
10861 as shown in this chapter.
10862 @item If you have a GUI environment like Eclipse,
10863 that also will probably need to be configured.
10866 Of course, the version of GDB you use will need to be one which has
10867 been built to know about the target CPU you're using. It's probably
10868 part of the tool chain you're using. For example, if you are doing
10869 cross-development for ARM on an x86 PC, instead of using the native
10870 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
10871 if that's the tool chain used to compile your code.
10873 @section Connecting to GDB
10874 @cindex Connecting to GDB
10875 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
10876 instance GDB 6.3 has a known bug that produces bogus memory access
10877 errors, which has since been fixed; see
10878 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
10880 OpenOCD can communicate with GDB in two ways:
10884 A socket (TCP/IP) connection is typically started as follows:
10886 target extended-remote localhost:3333
10888 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
10890 The extended remote protocol is a super-set of the remote protocol and should
10891 be the preferred choice. More details are available in GDB documentation
10892 @url{https://sourceware.org/gdb/onlinedocs/gdb/Connecting.html}
10894 To speed-up typing, any GDB command can be abbreviated, including the extended
10895 remote command above that becomes:
10900 @b{Note:} If any backward compatibility issue requires using the old remote
10901 protocol in place of the extended remote one, the former protocol is still
10902 available through the command:
10904 target remote localhost:3333
10908 A pipe connection is typically started as follows:
10910 target extended-remote | \
10911 openocd -c "gdb_port pipe; log_output openocd.log"
10913 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
10914 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
10915 session. log_output sends the log output to a file to ensure that the pipe is
10916 not saturated when using higher debug level outputs.
10919 To list the available OpenOCD commands type @command{monitor help} on the
10922 @section Sample GDB session startup
10924 With the remote protocol, GDB sessions start a little differently
10925 than they do when you're debugging locally.
10926 Here's an example showing how to start a debug session with a
10928 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
10929 Most programs would be written into flash (address 0) and run from there.
10932 $ arm-none-eabi-gdb example.elf
10933 (gdb) target extended-remote localhost:3333
10934 Remote debugging using localhost:3333
10936 (gdb) monitor reset halt
10939 Loading section .vectors, size 0x100 lma 0x20000000
10940 Loading section .text, size 0x5a0 lma 0x20000100
10941 Loading section .data, size 0x18 lma 0x200006a0
10942 Start address 0x2000061c, load size 1720
10943 Transfer rate: 22 KB/sec, 573 bytes/write.
10949 You could then interrupt the GDB session to make the program break,
10950 type @command{where} to show the stack, @command{list} to show the
10951 code around the program counter, @command{step} through code,
10952 set breakpoints or watchpoints, and so on.
10954 @section Configuring GDB for OpenOCD
10956 OpenOCD supports the gdb @option{qSupported} packet, this enables information
10957 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
10958 packet size and the device's memory map.
10959 You do not need to configure the packet size by hand,
10960 and the relevant parts of the memory map should be automatically
10961 set up when you declare (NOR) flash banks.
10963 However, there are other things which GDB can't currently query.
10964 You may need to set those up by hand.
10965 As OpenOCD starts up, you will often see a line reporting
10969 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
10972 You can pass that information to GDB with these commands:
10975 set remote hardware-breakpoint-limit 6
10976 set remote hardware-watchpoint-limit 4
10979 With that particular hardware (Cortex-M3) the hardware breakpoints
10980 only work for code running from flash memory. Most other ARM systems
10981 do not have such restrictions.
10983 Rather than typing such commands interactively, you may prefer to
10984 save them in a file and have GDB execute them as it starts, perhaps
10985 using a @file{.gdbinit} in your project directory or starting GDB
10986 using @command{gdb -x filename}.
10988 @section Programming using GDB
10989 @cindex Programming using GDB
10990 @anchor{programmingusinggdb}
10992 By default the target memory map is sent to GDB. This can be disabled by
10993 the following OpenOCD configuration option:
10995 gdb_memory_map disable
10997 For this to function correctly a valid flash configuration must also be set
10998 in OpenOCD. For faster performance you should also configure a valid
11001 Informing GDB of the memory map of the target will enable GDB to protect any
11002 flash areas of the target and use hardware breakpoints by default. This means
11003 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
11004 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
11006 To view the configured memory map in GDB, use the GDB command @option{info mem}.
11007 All other unassigned addresses within GDB are treated as RAM.
11009 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
11010 This can be changed to the old behaviour by using the following GDB command
11012 set mem inaccessible-by-default off
11015 If @command{gdb_flash_program enable} is also used, GDB will be able to
11016 program any flash memory using the vFlash interface.
11018 GDB will look at the target memory map when a load command is given, if any
11019 areas to be programmed lie within the target flash area the vFlash packets
11022 If the target needs configuring before GDB programming, set target
11023 event gdb-flash-erase-start:
11025 $_TARGETNAME configure -event gdb-flash-erase-start BODY
11027 @xref{targetevents,,Target Events}, for other GDB programming related events.
11029 To verify any flash programming the GDB command @option{compare-sections}
11032 @section Using GDB as a non-intrusive memory inspector
11033 @cindex Using GDB as a non-intrusive memory inspector
11034 @anchor{gdbmeminspect}
11036 If your project controls more than a blinking LED, let's say a heavy industrial
11037 robot or an experimental nuclear reactor, stopping the controlling process
11038 just because you want to attach GDB is not a good option.
11040 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
11041 Though there is a possible setup where the target does not get stopped
11042 and GDB treats it as it were running.
11043 If the target supports background access to memory while it is running,
11044 you can use GDB in this mode to inspect memory (mainly global variables)
11045 without any intrusion of the target process.
11047 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
11048 Place following command after target configuration:
11050 $_TARGETNAME configure -event gdb-attach @{@}
11053 If any of installed flash banks does not support probe on running target,
11054 switch off gdb_memory_map:
11056 gdb_memory_map disable
11059 Ensure GDB is configured without interrupt-on-connect.
11060 Some GDB versions set it by default, some does not.
11062 set remote interrupt-on-connect off
11065 If you switched gdb_memory_map off, you may want to setup GDB memory map
11066 manually or issue @command{set mem inaccessible-by-default off}
11068 Now you can issue GDB command @command{target extended-remote ...} and inspect memory
11069 of a running target. Do not use GDB commands @command{continue},
11070 @command{step} or @command{next} as they synchronize GDB with your target
11071 and GDB would require stopping the target to get the prompt back.
11073 Do not use this mode under an IDE like Eclipse as it caches values of
11074 previously shown variables.
11076 It's also possible to connect more than one GDB to the same target by the
11077 target's configuration option @code{-gdb-max-connections}. This allows, for
11078 example, one GDB to run a script that continuously polls a set of variables
11079 while other GDB can be used interactively. Be extremely careful in this case,
11080 because the two GDB can easily get out-of-sync.
11082 @section RTOS Support
11083 @cindex RTOS Support
11084 @anchor{gdbrtossupport}
11086 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
11087 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
11089 @xref{Threads, Debugging Programs with Multiple Threads,
11090 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
11093 @* An example setup is below:
11096 $_TARGETNAME configure -rtos auto
11099 This will attempt to auto detect the RTOS within your application.
11101 Currently supported rtos's include:
11103 @item @option{eCos}
11104 @item @option{ThreadX}
11105 @item @option{FreeRTOS}
11106 @item @option{linux}
11107 @item @option{ChibiOS}
11108 @item @option{embKernel}
11110 @item @option{uCOS-III}
11111 @item @option{nuttx}
11112 @item @option{RIOT}
11113 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
11114 @item @option{Zephyr}
11117 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
11118 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
11122 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
11123 @item ThreadX symbols
11124 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
11125 @item FreeRTOS symbols
11127 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
11128 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
11129 uxCurrentNumberOfTasks, uxTopUsedPriority.
11131 @item linux symbols
11133 @item ChibiOS symbols
11134 rlist, ch_debug, chSysInit.
11135 @item embKernel symbols
11136 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
11137 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
11139 _mqx_kernel_data, MQX_init_struct.
11140 @item uC/OS-III symbols
11141 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty.
11142 @item nuttx symbols
11143 g_readytorun, g_tasklisttable.
11146 sched_threads, sched_num_threads, sched_active_pid, max_threads,
11149 @item Zephyr symbols
11150 _kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size
11153 For most RTOS supported the above symbols will be exported by default. However for
11154 some, eg. FreeRTOS, uC/OS-III and Zephyr, extra steps must be taken.
11156 Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols
11157 with information needed in order to build the list of threads.
11159 FreeRTOS and uC/OS-III RTOSes may require additional OpenOCD-specific file to be linked
11160 along with the project:
11164 contrib/rtos-helpers/FreeRTOS-openocd.c
11166 contrib/rtos-helpers/uCOS-III-openocd.c
11169 @anchor{usingopenocdsmpwithgdb}
11170 @section Using OpenOCD SMP with GDB
11174 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
11175 ("hardware threads") in an SMP system as threads to GDB. With this extension,
11176 GDB can be used to inspect the state of an SMP system in a natural way.
11177 After halting the system, using the GDB command @command{info threads} will
11178 list the context of each active CPU core in the system. GDB's @command{thread}
11179 command can be used to switch the view to a different CPU core.
11180 The @command{step} and @command{stepi} commands can be used to step a specific core
11181 while other cores are free-running or remain halted, depending on the
11182 scheduler-locking mode configured in GDB.
11184 @section Legacy SMP core switching support
11186 This method is deprecated in favor of the @emph{hwthread} pseudo RTOS.
11189 For SMP support following GDB serial protocol packet have been defined :
11191 @item j - smp status request
11192 @item J - smp set request
11195 OpenOCD implements :
11197 @item @option{jc} packet for reading core id displayed by
11198 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
11199 @option{E01} for target not smp.
11200 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
11201 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
11202 for target not smp or @option{OK} on success.
11205 Handling of this packet within GDB can be done :
11207 @item by the creation of an internal variable (i.e @option{_core}) by mean
11208 of function allocate_computed_value allowing following GDB command.
11211 #Jc01 packet is sent
11213 #jc packet is sent and result is affected in $
11216 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
11217 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
11220 # toggle0 : force display of coreid 0
11226 # toggle1 : force display of coreid 1
11235 @node Tcl Scripting API
11236 @chapter Tcl Scripting API
11237 @cindex Tcl Scripting API
11238 @cindex Tcl scripts
11241 Tcl commands are stateless; e.g. the @command{telnet} command has
11242 a concept of currently active target, the Tcl API proc's take this sort
11243 of state information as an argument to each proc.
11245 There are three main types of return values: single value, name value
11246 pair list and lists.
11248 Name value pair. The proc 'foo' below returns a name/value pair
11252 > set foo(me) Duane
11253 > set foo(you) Oyvind
11254 > set foo(mouse) Micky
11255 > set foo(duck) Donald
11267 me Duane you Oyvind mouse Micky duck Donald
11270 Thus, to get the names of the associative array is easy:
11273 foreach { name value } [set foo] {
11274 puts "Name: $name, Value: $value"
11278 Lists returned should be relatively small. Otherwise, a range
11279 should be passed in to the proc in question.
11281 @section Internal low-level Commands
11283 By "low-level", we mean commands that a human would typically not
11287 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
11289 Read memory and return as a Tcl array for script processing
11290 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
11292 Convert a Tcl array to memory locations and write the values
11293 @item @b{flash banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
11295 Return information about the flash banks
11297 @item @b{capture} <@var{command}>
11299 Run <@var{command}> and return full log output that was produced during
11300 its execution. Example:
11303 > capture "reset init"
11308 OpenOCD commands can consist of two words, e.g. "flash banks". The
11309 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
11310 called "flash_banks".
11312 @section Tcl RPC server
11315 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
11316 commands and receive the results.
11318 To access it, your application needs to connect to a configured TCP port
11319 (see @command{tcl_port}). Then it can pass any string to the
11320 interpreter terminating it with @code{0x1a} and wait for the return
11321 value (it will be terminated with @code{0x1a} as well). This can be
11322 repeated as many times as desired without reopening the connection.
11324 It is not needed anymore to prefix the OpenOCD commands with
11325 @code{ocd_} to get the results back. But sometimes you might need the
11326 @command{capture} command.
11328 See @file{contrib/rpc_examples/} for specific client implementations.
11330 @section Tcl RPC server notifications
11331 @cindex RPC Notifications
11333 Notifications are sent asynchronously to other commands being executed over
11334 the RPC server, so the port must be polled continuously.
11336 Target event, state and reset notifications are emitted as Tcl associative arrays
11337 in the following format.
11340 type target_event event [event-name]
11341 type target_state state [state-name]
11342 type target_reset mode [reset-mode]
11345 @deffn {Command} {tcl_notifications} [on/off]
11346 Toggle output of target notifications to the current Tcl RPC server.
11347 Only available from the Tcl RPC server.
11352 @section Tcl RPC server trace output
11353 @cindex RPC trace output
11355 Trace data is sent asynchronously to other commands being executed over
11356 the RPC server, so the port must be polled continuously.
11358 Target trace data is emitted as a Tcl associative array in the following format.
11361 type target_trace data [trace-data-hex-encoded]
11364 @deffn {Command} {tcl_trace} [on/off]
11365 Toggle output of target trace data to the current Tcl RPC server.
11366 Only available from the Tcl RPC server.
11369 See an example application here:
11370 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
11379 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
11381 @cindex adaptive clocking
11384 In digital circuit design it is often referred to as ``clock
11385 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
11386 operating at some speed, your CPU target is operating at another.
11387 The two clocks are not synchronised, they are ``asynchronous''
11389 In order for the two to work together they must be synchronised
11390 well enough to work; JTAG can't go ten times faster than the CPU,
11391 for example. There are 2 basic options:
11394 Use a special "adaptive clocking" circuit to change the JTAG
11395 clock rate to match what the CPU currently supports.
11397 The JTAG clock must be fixed at some speed that's enough slower than
11398 the CPU clock that all TMS and TDI transitions can be detected.
11401 @b{Does this really matter?} For some chips and some situations, this
11402 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
11403 the CPU has no difficulty keeping up with JTAG.
11404 Startup sequences are often problematic though, as are other
11405 situations where the CPU clock rate changes (perhaps to save
11408 For example, Atmel AT91SAM chips start operation from reset with
11409 a 32kHz system clock. Boot firmware may activate the main oscillator
11410 and PLL before switching to a faster clock (perhaps that 500 MHz
11412 If you're using JTAG to debug that startup sequence, you must slow
11413 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
11414 JTAG can use a faster clock.
11416 Consider also debugging a 500MHz ARM926 hand held battery powered
11417 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
11418 clock, between keystrokes unless it has work to do. When would
11419 that 5 MHz JTAG clock be usable?
11421 @b{Solution #1 - A special circuit}
11423 In order to make use of this,
11424 your CPU, board, and JTAG adapter must all support the RTCK
11425 feature. Not all of them support this; keep reading!
11427 The RTCK ("Return TCK") signal in some ARM chips is used to help with
11428 this problem. ARM has a good description of the problem described at
11429 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
11430 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
11431 work? / how does adaptive clocking work?''.
11433 The nice thing about adaptive clocking is that ``battery powered hand
11434 held device example'' - the adaptiveness works perfectly all the
11435 time. One can set a break point or halt the system in the deep power
11436 down code, slow step out until the system speeds up.
11438 Note that adaptive clocking may also need to work at the board level,
11439 when a board-level scan chain has multiple chips.
11440 Parallel clock voting schemes are good way to implement this,
11441 both within and between chips, and can easily be implemented
11443 It's not difficult to have logic fan a module's input TCK signal out
11444 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
11445 back with the right polarity before changing the output RTCK signal.
11446 Texas Instruments makes some clock voting logic available
11447 for free (with no support) in VHDL form; see
11448 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
11450 @b{Solution #2 - Always works - but may be slower}
11452 Often this is a perfectly acceptable solution.
11454 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
11455 the target clock speed. But what that ``magic division'' is varies
11456 depending on the chips on your board.
11457 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
11458 ARM11 cores use an 8:1 division.
11459 @b{Xilinx rule of thumb} is 1/12 the clock speed.
11461 Note: most full speed FT2232 based JTAG adapters are limited to a
11462 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
11463 often support faster clock rates (and adaptive clocking).
11465 You can still debug the 'low power' situations - you just need to
11466 either use a fixed and very slow JTAG clock rate ... or else
11467 manually adjust the clock speed at every step. (Adjusting is painful
11468 and tedious, and is not always practical.)
11470 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
11471 have a special debug mode in your application that does a ``high power
11472 sleep''. If you are careful - 98% of your problems can be debugged
11475 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
11476 operation in your idle loops even if you don't otherwise change the CPU
11478 That operation gates the CPU clock, and thus the JTAG clock; which
11479 prevents JTAG access. One consequence is not being able to @command{halt}
11480 cores which are executing that @emph{wait for interrupt} operation.
11482 To set the JTAG frequency use the command:
11485 # Example: 1.234MHz
11490 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
11492 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
11493 around Windows filenames.
11506 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
11508 Make sure you have Cygwin installed, or at least a version of OpenOCD that
11509 claims to come with all the necessary DLLs. When using Cygwin, try launching
11510 OpenOCD from the Cygwin shell.
11512 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
11513 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
11514 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
11516 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
11517 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
11518 software breakpoints consume one of the two available hardware breakpoints.
11520 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
11522 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
11523 clock at the time you're programming the flash. If you've specified the crystal's
11524 frequency, make sure the PLL is disabled. If you've specified the full core speed
11525 (e.g. 60MHz), make sure the PLL is enabled.
11527 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
11528 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
11529 out while waiting for end of scan, rtck was disabled".
11531 Make sure your PC's parallel port operates in EPP mode. You might have to try several
11532 settings in your PC BIOS (ECP, EPP, and different versions of those).
11534 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
11535 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
11536 memory read caused data abort".
11538 The errors are non-fatal, and are the result of GDB trying to trace stack frames
11539 beyond the last valid frame. It might be possible to prevent this by setting up
11540 a proper "initial" stack frame, if you happen to know what exactly has to
11541 be done, feel free to add this here.
11543 @b{Simple:} In your startup code - push 8 registers of zeros onto the
11544 stack before calling main(). What GDB is doing is ``climbing'' the run
11545 time stack by reading various values on the stack using the standard
11546 call frame for the target. GDB keeps going - until one of 2 things
11547 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
11548 stackframes have been processed. By pushing zeros on the stack, GDB
11551 @b{Debugging Interrupt Service Routines} - In your ISR before you call
11552 your C code, do the same - artificially push some zeros onto the stack,
11553 remember to pop them off when the ISR is done.
11555 @b{Also note:} If you have a multi-threaded operating system, they
11556 often do not @b{in the interest of saving memory} waste these few
11560 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
11561 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
11563 This warning doesn't indicate any serious problem, as long as you don't want to
11564 debug your core right out of reset. Your .cfg file specified @option{reset_config
11565 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
11566 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
11567 independently. With this setup, it's not possible to halt the core right out of
11568 reset, everything else should work fine.
11570 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
11571 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
11572 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
11573 quit with an error message. Is there a stability issue with OpenOCD?
11575 No, this is not a stability issue concerning OpenOCD. Most users have solved
11576 this issue by simply using a self-powered USB hub, which they connect their
11577 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
11578 supply stable enough for the Amontec JTAGkey to be operated.
11580 @b{Laptops running on battery have this problem too...}
11582 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
11583 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
11584 What does that mean and what might be the reason for this?
11586 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
11587 has closed the connection to OpenOCD. This might be a GDB issue.
11589 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
11590 are described, there is a parameter for specifying the clock frequency
11591 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
11592 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
11593 specified in kilohertz. However, I do have a quartz crystal of a
11594 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
11595 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
11598 No. The clock frequency specified here must be given as an integral number.
11599 However, this clock frequency is used by the In-Application-Programming (IAP)
11600 routines of the LPC2000 family only, which seems to be very tolerant concerning
11601 the given clock frequency, so a slight difference between the specified clock
11602 frequency and the actual clock frequency will not cause any trouble.
11604 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
11606 Well, yes and no. Commands can be given in arbitrary order, yet the
11607 devices listed for the JTAG scan chain must be given in the right
11608 order (jtag newdevice), with the device closest to the TDO-Pin being
11609 listed first. In general, whenever objects of the same type exist
11610 which require an index number, then these objects must be given in the
11611 right order (jtag newtap, targets and flash banks - a target
11612 references a jtag newtap and a flash bank references a target).
11614 You can use the ``scan_chain'' command to verify and display the tap order.
11616 Also, some commands can't execute until after @command{init} has been
11617 processed. Such commands include @command{nand probe} and everything
11618 else that needs to write to controller registers, perhaps for setting
11619 up DRAM and loading it with code.
11621 @anchor{faqtaporder}
11622 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
11625 Yes; whenever you have more than one, you must declare them in
11626 the same order used by the hardware.
11628 Many newer devices have multiple JTAG TAPs. For example:
11629 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
11630 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
11631 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
11632 connected to the boundary scan TAP, which then connects to the
11633 Cortex-M3 TAP, which then connects to the TDO pin.
11635 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
11636 (2) The boundary scan TAP. If your board includes an additional JTAG
11637 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
11638 place it before or after the STM32 chip in the chain. For example:
11641 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
11642 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
11643 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
11644 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
11645 @item Xilinx TDO Pin -> OpenOCD TDO (input)
11648 The ``jtag device'' commands would thus be in the order shown below. Note:
11651 @item jtag newtap Xilinx tap -irlen ...
11652 @item jtag newtap stm32 cpu -irlen ...
11653 @item jtag newtap stm32 bs -irlen ...
11654 @item # Create the debug target and say where it is
11655 @item target create stm32.cpu -chain-position stm32.cpu ...
11659 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
11660 log file, I can see these error messages: Error: arm7_9_common.c:561
11661 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
11667 @node Tcl Crash Course
11668 @chapter Tcl Crash Course
11671 Not everyone knows Tcl - this is not intended to be a replacement for
11672 learning Tcl, the intent of this chapter is to give you some idea of
11673 how the Tcl scripts work.
11675 This chapter is written with two audiences in mind. (1) OpenOCD users
11676 who need to understand a bit more of how Jim-Tcl works so they can do
11677 something useful, and (2) those that want to add a new command to
11680 @section Tcl Rule #1
11681 There is a famous joke, it goes like this:
11683 @item Rule #1: The wife is always correct
11684 @item Rule #2: If you think otherwise, See Rule #1
11687 The Tcl equal is this:
11690 @item Rule #1: Everything is a string
11691 @item Rule #2: If you think otherwise, See Rule #1
11694 As in the famous joke, the consequences of Rule #1 are profound. Once
11695 you understand Rule #1, you will understand Tcl.
11697 @section Tcl Rule #1b
11698 There is a second pair of rules.
11700 @item Rule #1: Control flow does not exist. Only commands
11701 @* For example: the classic FOR loop or IF statement is not a control
11702 flow item, they are commands, there is no such thing as control flow
11704 @item Rule #2: If you think otherwise, See Rule #1
11705 @* Actually what happens is this: There are commands that by
11706 convention, act like control flow key words in other languages. One of
11707 those commands is the word ``for'', another command is ``if''.
11710 @section Per Rule #1 - All Results are strings
11711 Every Tcl command results in a string. The word ``result'' is used
11712 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
11713 Everything is a string}
11715 @section Tcl Quoting Operators
11716 In life of a Tcl script, there are two important periods of time, the
11717 difference is subtle.
11720 @item Evaluation Time
11723 The two key items here are how ``quoted things'' work in Tcl. Tcl has
11724 three primary quoting constructs, the [square-brackets] the
11725 @{curly-braces@} and ``double-quotes''
11727 By now you should know $VARIABLES always start with a $DOLLAR
11728 sign. BTW: To set a variable, you actually use the command ``set'', as
11729 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
11730 = 1'' statement, but without the equal sign.
11733 @item @b{[square-brackets]}
11734 @* @b{[square-brackets]} are command substitutions. It operates much
11735 like Unix Shell `back-ticks`. The result of a [square-bracket]
11736 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
11737 string}. These two statements are roughly identical:
11741 echo "The Date is: $X"
11744 puts "The Date is: $X"
11746 @item @b{``double-quoted-things''}
11747 @* @b{``double-quoted-things''} are just simply quoted
11748 text. $VARIABLES and [square-brackets] are expanded in place - the
11749 result however is exactly 1 string. @i{Remember Rule #1 - Everything
11753 puts "It is now \"[date]\", $x is in 1 hour"
11755 @item @b{@{Curly-Braces@}}
11756 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
11757 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
11758 'single-quote' operators in BASH shell scripts, with the added
11759 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
11760 nested 3 times@}@}@} NOTE: [date] is a bad example;
11761 at this writing, Jim/OpenOCD does not have a date command.
11764 @section Consequences of Rule 1/2/3/4
11766 The consequences of Rule 1 are profound.
11768 @subsection Tokenisation & Execution.
11770 Of course, whitespace, blank lines and #comment lines are handled in
11773 As a script is parsed, each (multi) line in the script file is
11774 tokenised and according to the quoting rules. After tokenisation, that
11775 line is immediately executed.
11777 Multi line statements end with one or more ``still-open''
11778 @{curly-braces@} which - eventually - closes a few lines later.
11780 @subsection Command Execution
11782 Remember earlier: There are no ``control flow''
11783 statements in Tcl. Instead there are COMMANDS that simply act like
11784 control flow operators.
11786 Commands are executed like this:
11789 @item Parse the next line into (argc) and (argv[]).
11790 @item Look up (argv[0]) in a table and call its function.
11791 @item Repeat until End Of File.
11794 It sort of works like this:
11797 ReadAndParse( &argc, &argv );
11799 cmdPtr = LookupCommand( argv[0] );
11801 (*cmdPtr->Execute)( argc, argv );
11805 When the command ``proc'' is parsed (which creates a procedure
11806 function) it gets 3 parameters on the command line. @b{1} the name of
11807 the proc (function), @b{2} the list of parameters, and @b{3} the body
11808 of the function. Not the choice of words: LIST and BODY. The PROC
11809 command stores these items in a table somewhere so it can be found by
11810 ``LookupCommand()''
11812 @subsection The FOR command
11814 The most interesting command to look at is the FOR command. In Tcl,
11815 the FOR command is normally implemented in C. Remember, FOR is a
11816 command just like any other command.
11818 When the ascii text containing the FOR command is parsed, the parser
11819 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
11823 @item The ascii text 'for'
11824 @item The start text
11825 @item The test expression
11826 @item The next text
11827 @item The body text
11830 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
11831 Remember @i{Rule #1 - Everything is a string.} The key point is this:
11832 Often many of those parameters are in @{curly-braces@} - thus the
11833 variables inside are not expanded or replaced until later.
11835 Remember that every Tcl command looks like the classic ``main( argc,
11836 argv )'' function in C. In JimTCL - they actually look like this:
11840 MyCommand( Jim_Interp *interp,
11842 Jim_Obj * const *argvs );
11845 Real Tcl is nearly identical. Although the newer versions have
11846 introduced a byte-code parser and interpreter, but at the core, it
11847 still operates in the same basic way.
11849 @subsection FOR command implementation
11851 To understand Tcl it is perhaps most helpful to see the FOR
11852 command. Remember, it is a COMMAND not a control flow structure.
11854 In Tcl there are two underlying C helper functions.
11856 Remember Rule #1 - You are a string.
11858 The @b{first} helper parses and executes commands found in an ascii
11859 string. Commands can be separated by semicolons, or newlines. While
11860 parsing, variables are expanded via the quoting rules.
11862 The @b{second} helper evaluates an ascii string as a numerical
11863 expression and returns a value.
11865 Here is an example of how the @b{FOR} command could be
11866 implemented. The pseudo code below does not show error handling.
11868 void Execute_AsciiString( void *interp, const char *string );
11870 int Evaluate_AsciiExpression( void *interp, const char *string );
11873 MyForCommand( void *interp,
11878 SetResult( interp, "WRONG number of parameters");
11882 // argv[0] = the ascii string just like C
11884 // Execute the start statement.
11885 Execute_AsciiString( interp, argv[1] );
11887 // Top of loop test
11889 i = Evaluate_AsciiExpression(interp, argv[2]);
11893 // Execute the body
11894 Execute_AsciiString( interp, argv[3] );
11896 // Execute the LOOP part
11897 Execute_AsciiString( interp, argv[4] );
11901 SetResult( interp, "" );
11906 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
11907 in the same basic way.
11909 @section OpenOCD Tcl Usage
11911 @subsection source and find commands
11912 @b{Where:} In many configuration files
11913 @* Example: @b{ source [find FILENAME] }
11914 @*Remember the parsing rules
11916 @item The @command{find} command is in square brackets,
11917 and is executed with the parameter FILENAME. It should find and return
11918 the full path to a file with that name; it uses an internal search path.
11919 The RESULT is a string, which is substituted into the command line in
11920 place of the bracketed @command{find} command.
11921 (Don't try to use a FILENAME which includes the "#" character.
11922 That character begins Tcl comments.)
11923 @item The @command{source} command is executed with the resulting filename;
11924 it reads a file and executes as a script.
11926 @subsection format command
11927 @b{Where:} Generally occurs in numerous places.
11928 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
11934 puts [format "The answer: %d" [expr $x * $y]]
11937 @item The SET command creates 2 variables, X and Y.
11938 @item The double [nested] EXPR command performs math
11939 @* The EXPR command produces numerical result as a string.
11940 @* Refer to Rule #1
11941 @item The format command is executed, producing a single string
11942 @* Refer to Rule #1.
11943 @item The PUTS command outputs the text.
11945 @subsection Body or Inlined Text
11946 @b{Where:} Various TARGET scripts.
11949 proc someproc @{@} @{
11950 ... multiple lines of stuff ...
11952 $_TARGETNAME configure -event FOO someproc
11953 #2 Good - no variables
11954 $_TARGETNAME configure -event foo "this ; that;"
11955 #3 Good Curly Braces
11956 $_TARGETNAME configure -event FOO @{
11957 puts "Time: [date]"
11959 #4 DANGER DANGER DANGER
11960 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
11963 @item The $_TARGETNAME is an OpenOCD variable convention.
11964 @*@b{$_TARGETNAME} represents the last target created, the value changes
11965 each time a new target is created. Remember the parsing rules. When
11966 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
11967 the name of the target which happens to be a TARGET (object)
11969 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
11970 @*There are 4 examples:
11972 @item The TCLBODY is a simple string that happens to be a proc name
11973 @item The TCLBODY is several simple commands separated by semicolons
11974 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
11975 @item The TCLBODY is a string with variables that get expanded.
11978 In the end, when the target event FOO occurs the TCLBODY is
11979 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
11980 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
11982 Remember the parsing rules. In case #3, @{curly-braces@} mean the
11983 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
11984 and the text is evaluated. In case #4, they are replaced before the
11985 ``Target Object Command'' is executed. This occurs at the same time
11986 $_TARGETNAME is replaced. In case #4 the date will never
11987 change. @{BTW: [date] is a bad example; at this writing,
11988 Jim/OpenOCD does not have a date command@}
11990 @subsection Global Variables
11991 @b{Where:} You might discover this when writing your own procs @* In
11992 simple terms: Inside a PROC, if you need to access a global variable
11993 you must say so. See also ``upvar''. Example:
11995 proc myproc @{ @} @{
11996 set y 0 #Local variable Y
11997 global x #Global variable X
11998 puts [format "X=%d, Y=%d" $x $y]
12001 @section Other Tcl Hacks
12002 @b{Dynamic variable creation}
12004 # Dynamically create a bunch of variables.
12005 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
12007 set vn [format "BIT%d" $x]
12011 set $vn [expr (1 << $x)]
12014 @b{Dynamic proc/command creation}
12016 # One "X" function - 5 uart functions.
12017 foreach who @{A B C D E@}
12018 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
12023 @appendix The GNU Free Documentation License.
12026 @node OpenOCD Concept Index
12027 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
12028 @comment case issue with ``Index.html'' and ``index.html''
12029 @comment Occurs when creating ``--html --no-split'' output
12030 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
12031 @unnumbered OpenOCD Concept Index
12035 @node Command and Driver Index
12036 @unnumbered Command and Driver Index