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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2010 by Spencer Oliver                                  *
   5  *   spen@spen-soft.co.uk                                                  *
   6  *                                                                         *
   7  *   Copyright (C) 2011 Øyvind Harboe                                      *
   8  *   oyvind.harboe@zylin.com                                               *
   9  *                                                                         *
  10  *   Copyright (C) 2011 Clement Burin des Roziers                          *
  11  *   clement.burin-des-roziers@hikob.com                                   *
  12  *                                                                         *
  13  *   Copyright (C) 2017 Armin van der Togt                                 *
  14  *   armin@otheruse.nl                                                     *
  15  ***************************************************************************/
  16
  17         .text
  18         .syntax unified
  19         .cpu cortex-m0
  20         .thumb
  21
  22 /*
  23 Parameters
  24         r0 - destination address
  25         r1 - source address
  26         r2 - half pages
  27         r3 - bytes per half page
  28         r4 - flash base
  29 Variables
  30         r0 - destination write pointer
  31         r1 - source read pointer
  32         r2 - source limit address
  33         r3 - bytes per half page
  34         r4 - flash base
  35         r5 - pages left in current half page
  36         r6 - temporary r/w
  37 */
  38
  39 /* offsets of registers from flash reg base */
  40 #define STM32_FLASH_SR_OFFSET 0x18
  41
  42         .thumb_func
  43         .global _start
  44 _start:
  45         // r2 = source + half pages * bytes per half page
  46         muls r2, r2, r3
  47         add r2, r1, r2
  48         // Go to compare
  49         b test_done
  50 write_half_page:
  51         // initialize pages left in current half page
  52         mov r5, r3
  53 write_word:
  54         // load word from address in r1 and increase r1 by 4
  55         ldmia r1!, {r6}
  56         // store word to address in r0 and increase r0 by 4
  57         stmia r0!, {r6}
  58         // check for end of half page
  59         subs r5, r5, #4
  60         bne write_word
  61 wait_busy:
  62         // read status register into r6, loop while bottom bit is set
  63         ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
  64         lsls r6, r6, #31
  65         bne wait_busy
  66 test_done:
  67         // compare r1 and r2, loop if not equal
  68         cmp     r1, r2
  69         bne     write_half_page
  70
  71         // Set breakpoint to exit
  72         bkpt #0x00