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   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2011 Øyvind Harboe                                      *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2011 Clement Burin des Roziers                          *
   9  *   clement.burin-des-roziers@hikob.com                                   *
  10  *                                                                         *
  11  *   Copyright (C) 2017 Armin van der Togt                                 *
  12  *   armin@otheruse.nl                                                     *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  ***************************************************************************/
  24
  25         .text
  26         .syntax unified
  27         .cpu cortex-m0
  28         .thumb
  29
  30 /*
  31 Parameters
  32         r0 - destination address
  33         r1 - source address
  34         r2 - half pages
  35         r3 - bytes per half page
  36         r4 - flash base
  37 Variables
  38         r0 - destination write pointer
  39         r1 - source read pointer
  40         r2 - source limit address
  41         r3 - bytes per half page
  42         r4 - flash base
  43         r5 - pages left in current half page
  44         r6 - temporary r/w
  45 */
  46
  47 /* offsets of registers from flash reg base */
  48 #define STM32_FLASH_SR_OFFSET 0x18
  49
  50         .thumb_func
  51         .global _start
  52 _start:
  53         // r2 = source + half pages * bytes per half page
  54         muls r2, r2, r3
  55         add r2, r1, r2
  56         // Go to compare
  57         b test_done
  58 write_half_page:
  59         // initialize pages left in current half page
  60         mov r5, r3
  61 write_word:
  62         // load word from address in r1 and increase r1 by 4
  63         ldmia r1!, {r6}
  64         // store word to address in r0 and increase r0 by 4
  65         stmia r0!, {r6}
  66         // check for end of half page
  67         subs r5, r5, #4
  68         bne write_word
  69 wait_busy:
  70         // read status register into r6, loop while bottom bit is set
  71         ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
  72         lsls r6, r6, #31
  73         bne wait_busy
  74 test_done:
  75         // compare r1 and r2, loop if not equal
  76         cmp     r1, r2
  77         bne     write_half_page
  78
  79         // Set breakpoint to exit
  80         bkpt #0x00