1 /***************************************************************************
2 * Copyright (C) 2017 by STMicroelectronics *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc. *
17 ***************************************************************************/
26 * The workarea must have size multiple of 4 bytes, since R/W
27 * operations are all at 32 bits.
28 * The workarea must be big enough to contain rp, wp and data, thus the minimum
29 * workarea size is: min_wa_size = sizeof(rp, wp, data) = 4 + 4 + sizeof(data).
30 * - for 0x450 devices: sizeof(data) = 32 bytes, thus min_wa_size = 40 bytes.
31 * - for 0x480 devices: sizeof(data) = 16 bytes, thus min_wa_size = 24 bytes.
32 * To benefit from concurrent host write-to-buffer and target
33 * write-to-flash, the workarea must be way bigger than the minimum.
35 * To avoid confusions the write word size is got from .block_size member of
36 * struct stm32h7x_part_info defined in stm32h7x.c
41 * r0 = workarea start, status (out)
44 * r3 = count (of write words)
45 * r4 = size of write word
50 * r7 - wp, status, tmp
51 * r8 - loop index, tmp
54 #define STM32_FLASH_CR_OFFSET 0x0C /* offset of CR register in FLASH struct */
55 #define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
56 #define STM32_CR_PROG 0x00000002 /* PG */
57 #define STM32_SR_QW_MASK 0x00000004 /* QW */
58 #define STM32_SR_ERROR_MASK 0x07ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
59 | INCERR | STRBERR | PGSERR | WRPERR */
64 ldr r6, [r0, #4] /* read rp */
67 ldr r7, [r0, #0] /* read wp */
68 cbz r7, exit /* abort if wp == 0, status = 0 */
69 subs r7, r7, r6 /* number of bytes available for read in r7 */
70 ittt mi /* if wrapped around */
71 addmi r7, r1 /* add size of buffer */
74 cmp r7, r4 /* wait until data buffer is full */
77 mov r7, #STM32_CR_PROG
78 str r7, [r5, #STM32_FLASH_CR_OFFSET]
81 udiv r8, r4, r8 /* number of words is size of write word divided by 4*/
84 ldr r7, [r6], #0x04 /* read one word from src, increment ptr */
85 str r7, [r2], #0x04 /* write one word to dst, increment ptr */
87 cmp r6, r1 /* if rp >= end of buffer ... */
89 addcs r6, r0, #8 /* ... then wrap at buffer start */
90 subs r8, r8, #1 /* decrement loop index */
91 bne write_flash /* loop if not done */
94 ldr r7, [r5, #STM32_FLASH_SR_OFFSET]
95 tst r7, #STM32_SR_QW_MASK
96 bne busy /* operation in progress, wait ... */
98 ldr r8, =STM32_SR_ERROR_MASK
100 bne error /* fail... */
102 str r6, [r0, #4] /* store rp */
103 subs r3, r3, #1 /* decrement count */
104 bne wait_fifo /* loop if not done */
109 str r8, [r0, #4] /* set rp = 0 on error */
112 mov r0, r7 /* return status in r0 */