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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2010 by Spencer Oliver                                  *
   5  *   spen@spen-soft.co.uk                                                  *
   6  *                                                                         *
   7  *   Copyright (C) 2011 Øyvind Harboe                                      *
   8  *   oyvind.harboe@zylin.com                                               *
   9  ***************************************************************************/
  10
  11         .text
  12         .syntax unified
  13         .cpu cortex-m3
  14         .thumb
  15
  16 /*
  17  * Params :
  18  * r0 = workarea start, status (out)
  19  * r1 = workarea end
  20  * r2 = target address
  21  * r3 = count (16bit words)
  22  * r4 = flash base
  23  *
  24  * Clobbered:
  25  * r6 - temp
  26  * r7 - rp
  27  * r8 - wp, tmp
  28  */
  29
  30 #define STM32_FLASH_CR_OFFSET   0x10                    /* offset of CR register in FLASH struct */
  31 #define STM32_FLASH_SR_OFFSET   0x0c                    /* offset of SR register in FLASH struct */
  32
  33 #define STM32_PROG16            0x101                   /* PG | PSIZE_16*/
  34
  35         .thumb_func
  36         .global _start
  37 _start:
  38 wait_fifo:
  39         ldr     r8, [r0, #0]    /* read wp */
  40         cmp     r8, #0                  /* abort if wp == 0 */
  41         beq     exit
  42         ldr     r7, [r0, #4]    /* read rp */
  43         cmp     r7, r8                  /* wait until rp != wp */
  44         beq     wait_fifo
  45
  46         ldr             r6, =STM32_PROG16
  47         str             r6, [r4, #STM32_FLASH_CR_OFFSET]
  48         ldrh    r6, [r7], #0x02                                         /* read one half-word from src, increment ptr */
  49         strh    r6, [r2], #0x02                                         /* write one half-word from src, increment ptr */
  50         dsb
  51 busy:
  52         ldr     r6, [r4, #STM32_FLASH_SR_OFFSET]
  53         tst     r6, #0x10000                                            /* BSY (bit16) == 1 => operation in progress */
  54         bne     busy                                                            /* wait more... */
  55         tst             r6, #0xf0                                                       /* PGSERR | PGPERR | PGAERR | WRPERR */
  56         bne             error                                                           /* fail... */
  57
  58         cmp     r7, r1                  /* wrap rp at end of buffer */
  59         it      cs
  60         addcs   r7, r0, #8              /* skip loader args */
  61         str     r7, [r0, #4]    /* store rp */
  62         subs    r3, r3, #1              /* decrement halfword count */
  63         cbz     r3, exit                /* loop if not done */
  64         b               wait_fifo
  65 error:
  66         movs    r1, #0
  67         str             r1, [r0, #4]    /* set rp = 0 on error */
  68 exit:
  69         mov             r0, r6                  /* return status in r0 */
  70         bkpt    #0x00
  71
  72         .pool