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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   5  *   andreas.fritiofson@gmail.com                                          *
   6  ***************************************************************************/
   7
   8         .text
   9         .syntax unified
  10         .cpu cortex-m0
  11         .thumb
  12
  13         /* Params:
  14          * r0 - flash base (in), status (out)
  15          * r1 - count (halfword-16bit)
  16          * r2 - workarea start
  17          * r3 - workarea end
  18          * r4 - target address
  19          * Clobbered:
  20          * r5 - rp
  21          * r6 - wp, tmp
  22          * r7 - tmp
  23          */
  24
  25 #define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
  26
  27         .thumb_func
  28         .global _start
  29 _start:
  30 wait_fifo:
  31         ldr     r6, [r2, #0]    /* read wp */
  32         cmp     r6, #0                  /* abort if wp == 0 */
  33         beq     exit
  34         ldr     r5, [r2, #4]    /* read rp */
  35         cmp     r5, r6                  /* wait until rp != wp */
  36         beq     wait_fifo
  37         ldrh    r6, [r5]        /* "*target_address++ = *rp++" */
  38         strh    r6, [r4]
  39         adds    r5, #2
  40         adds    r4, #2
  41 busy:
  42         ldr     r6, [r0, #STM32_FLASH_SR_OFFSET]        /* wait until BSY flag is reset */
  43         movs    r7, #1
  44         tst     r6, r7
  45         bne     busy
  46         movs    r7, #0x14               /* check the error bits */
  47         tst     r6, r7
  48         bne     error
  49         cmp     r5, r3                  /* wrap rp at end of buffer */
  50         bcc     no_wrap
  51         mov     r5, r2
  52         adds    r5, #8
  53 no_wrap:
  54         str     r5, [r2, #4]    /* store rp */
  55         subs    r1, r1, #1              /* decrement halfword count */
  56         cmp     r1, #0
  57         beq     exit            /* loop if not done */
  58         b       wait_fifo
  59 error:
  60         movs    r0, #0
  61         str     r0, [r2, #4]    /* set rp = 0 on error */
  62 exit:
  63         mov             r0, r6                  /* return status in r0 */
  64         bkpt    #0