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   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   3  *   andreas.fritiofson@gmail.com                                          *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21         .text
  22         .syntax unified
  23         .cpu cortex-m0
  24         .thumb
  25
  26         /* Params:
  27          * r0 - flash base (in), status (out)
  28          * r1 - count (halfword-16bit)
  29          * r2 - workarea start
  30          * r3 - workarea end
  31          * r4 - target address
  32          * Clobbered:
  33          * r5 - rp
  34          * r6 - wp, tmp
  35          * r7 - tmp
  36          */
  37
  38 #define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
  39
  40         .thumb_func
  41         .global _start
  42 _start:
  43 wait_fifo:
  44         ldr     r6, [r2, #0]    /* read wp */
  45         cmp     r6, #0                  /* abort if wp == 0 */
  46         beq     exit
  47         ldr     r5, [r2, #4]    /* read rp */
  48         cmp     r5, r6                  /* wait until rp != wp */
  49         beq     wait_fifo
  50         ldrh    r6, [r5]        /* "*target_address++ = *rp++" */
  51         strh    r6, [r4]
  52         adds    r5, #2
  53         adds    r4, #2
  54 busy:
  55         ldr     r6, [r0, #STM32_FLASH_SR_OFFSET]        /* wait until BSY flag is reset */
  56         movs    r7, #1
  57         tst     r6, r7
  58         bne     busy
  59         movs    r7, #0x14               /* check the error bits */
  60         tst     r6, r7
  61         bne     error
  62         cmp     r5, r3                  /* wrap rp at end of buffer */
  63         bcc     no_wrap
  64         mov     r5, r2
  65         adds    r5, #8
  66 no_wrap:
  67         str     r5, [r2, #4]    /* store rp */
  68         subs    r1, r1, #1              /* decrement halfword count */
  69         cmp     r1, #0
  70         beq     exit            /* loop if not done */
  71         b       wait_fifo
  72 error:
  73         movs    r0, #0
  74         str     r0, [r2, #4]    /* set rp = 0 on error */
  75 exit:
  76         mov             r0, r6                  /* return status in r0 */
  77         bkpt    #0