1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2020 by Nuvoton Technology Corporation
5 * Mulin Chao <mlchao@nuvoton.com>
6 * Wealian Liao <WHLIAO@nuvoton.com>
9 #ifndef OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H
10 #define OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H
12 #include "npcx_flash_config.h"
15 #define NPCX_SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
16 #define NPCX_CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
17 #define NPCX_IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
20 #define NPCX_GET_POS_FIELD(pos, size) (pos)
21 #define NPCX_GET_SIZE_FIELD(pos, size) (size)
22 #define NPCX_FIELD_POS(field) NPCX_GET_POS_##field
23 #define NPCX_FIELD_SIZE(field) NPCX_GET_SIZE_##field
24 /* Read field functions */
25 #define NPCX_GET_FIELD(reg, field) \
26 _NPCX_GET_FIELD_((reg), NPCX_FIELD_POS(field), NPCX_FIELD_SIZE(field))
27 #define _NPCX_GET_FIELD_(reg, f_pos, f_size) \
28 (((reg) >> (f_pos)) & ((1 << (f_size)) - 1))
29 /* Write field functions */
30 #define NPCX_SET_FIELD(reg, field, value) \
31 _NPCX_SET_FIELD_((reg), NPCX_FIELD_POS(field), NPCX_FIELD_SIZE(field), (value))
32 #define _NPCX_SET_FIELD_(reg, f_pos, f_size, value) \
33 ((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | ((value) << (f_pos)))
35 /* Register definitions */
36 #define NPCX_REG32_ADDR(addr) ((volatile uint32_t *)(addr))
37 #define NPCX_REG16_ADDR(addr) ((volatile uint16_t *)(addr))
38 #define NPCX_REG8_ADDR(addr) ((volatile uint8_t *)(addr))
40 #define NPCX_HW_BYTE(addr) (*NPCX_REG8_ADDR(addr))
41 #define NPCX_HW_WORD(addr) (*NPCX_REG16_ADDR(addr))
42 #define NPCX_HW_DWORD(addr) (*NPCX_REG32_ADDR(addr))
45 #define NPCX_SCFG_BASE_ADDR 0x400C3000
46 #define NPCX_DEVCNT NPCX_HW_BYTE(NPCX_SCFG_BASE_ADDR + 0x000)
47 #define NPCX_DEVALT(n) NPCX_HW_BYTE(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
49 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
50 #define NPCX_DEVCNT_JEN0_HEN 4
51 #define NPCX_DEVCNT_JEN1_HEN 5
52 #define NPCX_DEVCNT_F_SPI_TRIS 6
54 /* Pin-mux for SPI/FIU */
55 #define NPCX_DEVALT0_SPIP_SL 0
56 #define NPCX_DEVALT0_GPIO_NO_SPIP 3
57 #define NPCX_DEVALT0_F_SPI_CS1_2 4
58 #define NPCX_DEVALT0_F_SPI_CS1_1 5
59 #define NPCX_DEVALT0_F_SPI_QUAD 6
60 #define NPCX_DEVALT0_NO_F_SPI 7
62 /* Flash Interface Unit (FIU) registers */
63 #define NPCX_FIU_BASE_ADDR 0x40020000
64 #define NPCX_FIU_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x000)
65 #define NPCX_BURST_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x001)
66 #define NPCX_RESP_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x002)
67 #define NPCX_SPI_FL_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x014)
68 #define NPCX_UMA_CODE NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x016)
69 #define NPCX_UMA_AB0 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x017)
70 #define NPCX_UMA_AB1 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x018)
71 #define NPCX_UMA_AB2 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x019)
72 #define NPCX_UMA_DB0 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01A)
73 #define NPCX_UMA_DB1 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01B)
74 #define NPCX_UMA_DB2 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01C)
75 #define NPCX_UMA_DB3 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01D)
76 #define NPCX_UMA_CTS NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01E)
77 #define NPCX_UMA_ECTS NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01F)
78 #define NPCX_UMA_DB0_3 NPCX_HW_DWORD(NPCX_FIU_BASE_ADDR + 0x020)
79 #define NPCX_FIU_RD_CMD NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x030)
80 #define NPCX_FIU_DMM_CYC NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x032)
81 #define NPCX_FIU_EXT_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x033)
82 #define NPCX_FIU_UMA_AB0_3 NPCX_HW_DWORD(NPCX_FIU_BASE_ADDR + 0x034)
84 /* FIU register fields */
85 #define NPCX_RESP_CFG_IAD_EN 0
86 #define NPCX_RESP_CFG_DEV_SIZE_EX 2
87 #define NPCX_UMA_CTS_A_SIZE 3
88 #define NPCX_UMA_CTS_C_SIZE 4
89 #define NPCX_UMA_CTS_RD_WR 5
90 #define NPCX_UMA_CTS_DEV_NUM 6
91 #define NPCX_UMA_CTS_EXEC_DONE 7
92 #define NPCX_UMA_ECTS_SW_CS0 0
93 #define NPCX_UMA_ECTS_SW_CS1 1
94 #define NPCX_UMA_ECTS_SEC_CS 2
95 #define NPCX_UMA_ECTS_UMA_LOCK 3
97 /* Flash UMA commands for npcx internal SPI flash */
98 #define NPCX_CMD_READ_ID 0x9F
99 #define NPCX_CMD_READ_MAN_DEV_ID 0x90
100 #define NPCX_CMD_WRITE_EN 0x06
101 #define NPCX_CMD_WRITE_STATUS 0x50
102 #define NPCX_CMD_READ_STATUS_REG 0x05
103 #define NPCX_CMD_READ_STATUS_REG2 0x35
104 #define NPCX_CMD_WRITE_STATUS_REG 0x01
105 #define NPCX_CMD_FLASH_PROGRAM 0x02
106 #define NPCX_CMD_SECTOR_ERASE 0x20
107 #define NPCX_CMD_PROGRAM_UINT_SIZE 0x08
108 #define NPCX_CMD_PAGE_SIZE 0x00
109 #define NPCX_CMD_READ_ID_TYPE 0x47
110 #define NPCX_CMD_FAST_READ 0x0B
111 #define NPCX_CMD_CHIP_ERASE 0xC7
114 * Status registers for SPI flash
116 #define NPCX_SPI_FLASH_SR2_SUS (1 << 7)
117 #define NPCX_SPI_FLASH_SR2_CMP (1 << 6)
118 #define NPCX_SPI_FLASH_SR2_LB3 (1 << 5)
119 #define NPCX_SPI_FLASH_SR2_LB2 (1 << 4)
120 #define NPCX_SPI_FLASH_SR2_LB1 (1 << 3)
121 #define NPCX_SPI_FLASH_SR2_QE (1 << 1)
122 #define NPCX_SPI_FLASH_SR2_SRP1 (1 << 0)
123 #define NPCX_SPI_FLASH_SR1_SRP0 (1 << 7)
124 #define NPCX_SPI_FLASH_SR1_SEC (1 << 6)
125 #define NPCX_SPI_FLASH_SR1_TB (1 << 5)
126 #define NPCX_SPI_FLASH_SR1_BP2 (1 << 4)
127 #define NPCX_SPI_FLASH_SR1_BP1 (1 << 3)
128 #define NPCX_SPI_FLASH_SR1_BP0 (1 << 2)
129 #define NPCX_SPI_FLASH_SR1_WEL (1 << 1)
130 #define NPCX_SPI_FLASH_SR1_BUSY (1 << 0)
132 #define NPCX_MASK_CMD_ONLY (0xC0)
133 #define NPCX_MASK_CMD_ADR (0xC0 | 0x08)
134 #define NPCX_MASK_CMD_ADR_WR (0xC0 | 0x20 | 0x08 | 0x01)
135 #define NPCX_MASK_RD_1BYTE (0xC0 | 0x10 | 0x01)
136 #define NPCX_MASK_RD_2BYTE (0xC0 | 0x10 | 0x02)
137 #define NPCX_MASK_RD_3BYTE (0xC0 | 0x10 | 0x03)
138 #define NPCX_MASK_RD_4BYTE (0xC0 | 0x10 | 0x04)
139 #define NPCX_MASK_CMD_RD_1BYTE (0xC0 | 0x01)
140 #define NPCX_MASK_CMD_RD_2BYTE (0xC0 | 0x02)
141 #define NPCX_MASK_CMD_RD_3BYTE (0xC0 | 0x03)
142 #define NPCX_MASK_CMD_RD_4BYTE (0xC0 | 0x04)
143 #define NPCX_MASK_CMD_WR_ONLY (0xC0 | 0x20)
144 #define NPCX_MASK_CMD_WR_1BYTE (0xC0 | 0x20 | 0x10 | 0x01)
145 #define NPCX_MASK_CMD_WR_2BYTE (0xC0 | 0x20 | 0x10 | 0x02)
146 #define NPCX_MASK_CMD_WR_ADR (0xC0 | 0x20 | 0x08)
148 /* Flash loader parameters */
149 struct __attribute__((__packed__)) npcx_flash_params {
150 uint32_t addr; /* Address in flash */
151 uint32_t len; /* Number of bytes */
152 uint32_t cmd; /* Command */
153 uint32_t sync; /* Handshake signal */
156 /* Flash trigger signal */
157 enum npcx_flash_handshake {
158 NPCX_FLASH_LOADER_WAIT = 0x0, /* Idle */
159 NPCX_FLASH_LOADER_EXECUTE = 0xFFFFFFFF /* Execute Command */
162 /* Flash loader command */
163 enum npcx_flash_commands {
164 NPCX_FLASH_CMD_NO_ACTION = 0, /* No action, default value */
165 NPCX_FLASH_CMD_GET_FLASH_ID, /* Get the internal flash ID */
166 NPCX_FLASH_CMD_ERASE_SECTORS, /* Erase unprotected sectors */
167 NPCX_FLASH_CMD_ERASE_ALL, /* Erase all */
168 NPCX_FLASH_CMD_PROGRAM, /* Program data */
172 enum npcx_flash_status {
173 NPCX_FLASH_STATUS_OK = 0,
174 NPCX_FLASH_STATUS_FAILED_UNKNOWN_COMMAND,
175 NPCX_FLASH_STATUS_FAILED,
176 NPCX_FLASH_STATUS_FAILED_TIMEOUT,
179 #endif /* OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H */