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   1 /***************************************************************************
   2  *   Copyright (C) 2014 by Angus Gratton                                   *
   3  *   Derived from stm32f1x.S:
   4  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   5  *   andreas.fritiofson@gmail.com                                          *
   6  *   Copyright (C) 2013 by Roman Dmitrienko                                *
   7  *   me@iamroman.org                                                       *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  21  ***************************************************************************/
  22         .text
  23         .syntax unified
  24         .cpu cortex-m0
  25         .thumb
  26         .thumb_func
  27
  28 /* Written for NRF51822 (src/flash/nor/nrf51.c) however the NRF NVMC is
  29  * very generic (CPU blocks during flash writes), so this is actually
  30  * just a generic word-oriented copy routine for Cortex-M0 (also
  31  * suitable for Cortex-M0+/M3/M4.)
  32  *
  33  * To assemble:
  34  * arm-none-eabi-gcc -c cortex-m0.S
  35  *
  36  * To disassemble:
  37  * arm-none-eabi-objdump -o cortex-m0.o
  38  *
  39  * Thanks to Jens Bauer for providing advice on some of the tweaks.
  40  */
  41
  42         /* Params:
  43          * r0 - byte count (in)
  44          * r1 - workarea start
  45          * r2 - workarea end
  46          * r3 - target address
  47          * Clobbered:
  48          * r4 - rp
  49          * r5 - wp, tmp
  50          */
  51
  52 wait_fifo:
  53         ldr     r5, [r1, #0]    /* read wp */
  54         cmp     r5, #0          /* abort if wp == 0 */
  55         beq     exit
  56         ldr     r4, [r1, #4]    /* read rp */
  57         cmp     r4, r5          /* wait until rp != wp */
  58         beq     wait_fifo
  59
  60         ldmia   r4!, {r5}       /* "*target_address++ = *rp++" */
  61         stmia   r3!, {r5}
  62
  63         cmp     r4, r2          /* wrap rp at end of work area buffer */
  64         bcc     no_wrap
  65         mov     r4, r1
  66         adds    r4, #8          /* skip rp,wp at start of work area */
  67 no_wrap:
  68         str     r4, [r1, #4]    /* write back rp */
  69         subs    r0, #4          /* decrement byte count */
  70         bne     wait_fifo       /* loop if not done */
  71 exit:
  72         bkpt    #0