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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *   Copyright (C) 2010 Spencer Oliver                                     *
   7  *   spen@spen-soft.co.uk                                                  *
   8  ***************************************************************************/
   9
  10         .text
  11         .arm
  12         .arch armv4
  13
  14         .section .init
  15
  16 /* algorithm register usage:
  17  * r0: source address (in RAM)
  18  * r1: target address (in Flash)
  19  * r2: count
  20  * r3: flash write command
  21  * r4: status byte (returned to host)
  22  * r5: busy test pattern
  23  * r6: error test pattern
  24  */
  25
  26 loop:
  27         ldrb    r4, [r0], #1
  28         strb    r3, [r1]
  29         strb    r4, [r1]
  30 busy:
  31         ldrb    r4, [r1]
  32         and             r7, r4, r5
  33         cmp             r7, r5
  34         bne             busy
  35         tst             r4, r6
  36         bne             done
  37         subs    r2, r2, #1
  38         beq             done
  39         add             r1, r1, #1
  40         b               loop
  41 done:
  42         b               done
  43
  44         .end