Adjust clock/data phase for spi test

[fw/altos] / target / ee / ee.c

diff --git a/target/ee/ee.c b/target/ee/ee.c
index ab1b54e3eeb0b8c54cfd01f85f6fdf4441265bb5..83dd57ebf32636fc96acc3336dafb06e0afe42ed 100644 (file)
--- a/target/ee/ee.c
+++ b/target/ee/ee.c
@@ -73,6 +73,7 @@ delay (unsigned char n)
 void
 cs(uint8_t b)
 {
+       SCK = 0;
        CS = b;
        delay(1);
 }
@@ -81,10 +82,10 @@ void
 out_bit(uint8_t b)
 {
        MOSI = b;
+       delay(1);
        SCK = 1;
        delay(1);
        SCK = 0;
-       delay(1);
 }
 
 void
@@ -103,11 +104,12 @@ uint8_t
 in_bit(void)
 {
        uint8_t b;
+       
+       delay(1);
        SCK = 1;
        delay(1);
        b = MISO;
        SCK = 0;
-       delay(1);
        return b;
 }
 
@@ -212,7 +214,7 @@ main ()
        CS = 1;
        SCK = 0;
        P1DIR = ((1 << 5) |
-                (1 << 4) |
+                (0 << 4) |
                 (1 << 3) |
                 (1 << 2) |
                 (1 << 1));