extern struct stm_rcc stm_rcc;
-/* Nominal high speed internal oscillator frequency is 16MHz */
-#define STM_HSI_FREQ 16000000
+/* Nominal high speed internal oscillator frequency is 8MHz */
+#define STM_HSI_FREQ 8000000
#define STM_RCC_CR_PLLRDY (25)
#define STM_RCC_CR_PLLON (24)
#define STM_RCC_CFGR_MCO (24)
# define STM_RCC_CFGR_MCO_DISABLE 0
+# define STM_RCC_CFGR_MCO_RC 1
+# define STM_RCC_CFGR_MCO_LSI 2
+# define STM_RCC_CFGR_MCO_LSE 3
+# define STM_RCC_CFGR_MCO_SYSCLK 4
+# define STM_RCC_CFGR_MCO_HSI 5
+# define STM_RCC_CFGR_MCO_HSE 6
+# define STM_RCC_CFGR_MCO_PLLCLK 7
+# define STM_RCC_CFGR_MCO_HSI48 8
+# define STM_RCC_CFGR_MCO_MASK (0xf)
#define STM_RCC_CFGR_PLLMUL (18)
#define STM_RCC_CFGR_PLLMUL_2 0
#define STM_I2C_CCR_CCR 0
#define STM_I2C_CCR_MASK 0x7ff
+struct stm_tim1 {
+ vuint32_t cr1;
+ vuint32_t cr2;
+ vuint32_t smcr;
+ vuint32_t dier;
+
+ vuint32_t sr;
+ vuint32_t egr;
+ vuint32_t ccmr1;
+ vuint32_t ccmr2;
+
+ vuint32_t ccer;
+ vuint32_t cnt;
+ vuint32_t psc;
+ vuint32_t arr;
+
+ vuint32_t rcr;
+ vuint32_t ccr1;
+ vuint32_t ccr2;
+ vuint32_t ccr3;
+
+ vuint32_t ccr4;
+ vuint32_t bdtr;
+ vuint32_t dcr;
+ vuint32_t dmar;
+};
+
+#define STM_TIM1_CR1_CKD 8
+#define STM_TIM1_CR1_CKD_1 0
+#define STM_TIM1_CR1_CKD_2 1
+#define STM_TIM1_CR1_CKD_4 2
+
+#define STM_TIM1_CR1_ARPE 7
+
+#define STM_TIM1_CR1_CMS 5
+#define STM_TIM1_CR1_CMS_EDGE 0
+#define STM_TIM1_CR1_CMS_CENTER_1 1
+#define STM_TIM1_CR1_CMS_CENTER_2 2
+#define STM_TIM1_CR1_CMS_CENTER_3 3
+
+#define STM_TIM1_CR1_DIR 4
+#define STM_TIM1_CR1_DIR_UP 0
+#define STM_TIM1_CR1_DIR_DOWn 1
+#define STM_TIM1_CR1_OPM 3
+#define STM_TIM1_CR1_URS 2
+#define STM_TIM1_CR1_UDIS 1
+#define STM_TIM1_CR1_CEN 0
+
+#define STM_TIM1_CR2_OIS4 14
+#define STM_TIM1_CR2_OIS3N 13
+#define STM_TIM1_CR2_OIS3 12
+#define STM_TIM1_CR2_OIS2N 11
+#define STM_TIM1_CR2_OIS2 10
+#define STM_TIM1_CR2_OIS1N 9
+#define STM_TIM1_CR2_OSI1 8
+#define STM_TIM1_CR2_TI1S 7
+#define STM_TIM1_CR2_MMS 4
+#define STM_TIM1_CR2_MMS_RESET 0
+#define STM_TIM1_CR2_MMS_ENABLE 1
+#define STM_TIM1_CR2_MMS_UPDATE 2
+#define STM_TIM1_CR2_MMS_COMPARE_PULSE 3
+#define STM_TIM1_CR2_MMS_COMPARE_OC1REF 4
+#define STM_TIM1_CR2_MMS_COMPARE_OC2REF 5
+#define STM_TIM1_CR2_MMS_COMPARE_OC3REF 6
+#define STM_TIM1_CR2_MMS_COMPARE_OC4REF 7
+#define STM_TIM1_CR2_CCDS 3
+#define STM_TIM1_CR2_CCUS 2
+#define STM_TIM1_CR2_CCPC 0
+
+#define STM_TIM1_SMCR_ETP 15
+#define STM_TIM1_SMCR_ECE 14
+#define STM_TIM1_SMCR_ETPS 12
+#define STM_TIM1_SMCR_ETPS_OFF 0
+#define STM_TIM1_SMCR_ETPS_DIV_2 1
+#define STM_TIM1_SMCR_ETPS_DIV_4 2
+#define STM_TIM1_SMCR_ETPS_DIV_8 3
+
+#define STM_TIM1_SMCR_ETF 8
+#define STM_TIM1_SMCR_ETF_NONE 0
+#define STM_TIM1_SMCR_ETF_DIV_1_N_2 1
+#define STM_TIM1_SMCR_ETF_DIV_1_N_4 2
+#define STM_TIM1_SMCR_ETF_DIV_1_N_8 3
+#define STM_TIM1_SMCR_ETF_DIV_2_N_6 4
+#define STM_TIM1_SMCR_ETF_DIV_2_N_8 5
+#define STM_TIM1_SMCR_ETF_DIV_4_N_6 6
+#define STM_TIM1_SMCR_ETF_DIV_4_N_8 7
+#define STM_TIM1_SMCR_ETF_DIV_8_N_6 8
+#define STM_TIM1_SMCR_ETF_DIV_8_N_8 9
+#define STM_TIM1_SMCR_ETF_DIV_16_N_5 10
+#define STM_TIM1_SMCR_ETF_DIV_16_N_6 11
+#define STM_TIM1_SMCR_ETF_DIV_16_N_8 12
+#define STM_TIM1_SMCR_ETF_DIV_32_N_5 13
+#define STM_TIM1_SMCR_ETF_DIV_32_N_6 14
+#define STM_TIM1_SMCR_ETF_DIV_32_N_8 15
+
+#define STM_TIM1_SMCR_MSM 7
+#define STM_TIM1_SMCR_TS 4
+#define STM_TIM1_SMCR_TS_ITR0 0
+#define STM_TIM1_SMCR_TS_ITR1 1
+#define STM_TIM1_SMCR_TS_ITR2 2
+#define STM_TIM1_SMCR_TS_ITR3 3
+#define STM_TIM1_SMCR_TS_TI1F_ED 4
+#define STM_TIM1_SMCR_TS_TI1FP1 5
+#define STM_TIM1_SMCR_TS_TI2FP2 6
+#define STM_TIM1_SMCR_TS_ETRF 7
+
+#define STM_TIM1_SMCR_OCCS 3
+#define STM_TIM1_SMCR_SMS 0
+#define STM_TIM1_SMCR_SMS_DISABLE 0
+#define STM_TIM1_SMCR_SMS_ENCODER_1 1
+#define STM_TIM1_SMCR_SMS_ENCODER_2 2
+#define STM_TIM1_SMCR_SMS_ENCODER_3 3
+#define STM_TIM1_SMCR_SMS_RESET 4
+#define STM_TIM1_SMCR_SMS_GATED 5
+#define STM_TIM1_SMCR_SMS_TRIGGER 6
+#define STM_TIM1_SMCR_SMS_EXTERNAL 7
+
+#define STM_TIM1_DIER_TDE 14
+#define STM_TIM1_DIER_COMDE 13
+#define STM_TIM1_DIER_CC4DE 12
+#define STM_TIM1_DIER_CC3DE 11
+#define STM_TIM1_DIER_CC2DE 10
+#define STM_TIM1_DIER_CC1DE 9
+#define STM_TIM1_DIER_UDE 8
+#define STM_TIM1_DIER_BIE 7
+#define STM_TIM1_DIER_TIE 6
+#define STM_TIM1_DIER_COMIE 5
+#define STM_TIM1_DIER_CC4IE 4
+#define STM_TIM1_DIER_CC3IE 3
+#define STM_TIM1_DIER_CC2IE 2
+#define STM_TIM1_DIER_CC1IE 1
+#define STM_TIM1_DIER_UIE 0
+
+#define STM_TIM1_SR_CC4OF 12
+#define STM_TIM1_SR_CC3OF 11
+#define STM_TIM1_SR_CC2OF 10
+#define STM_TIM1_SR_CC1OF 9
+#define STM_TIM1_SR_BIF 7
+#define STM_TIM1_SR_TIF 6
+#define STM_TIM1_SR_COMIF 5
+#define STM_TIM1_SR_CC4IF 4
+#define STM_TIM1_SR_CC3IF 3
+#define STM_TIM1_SR_CC2IF 2
+#define STM_TIM1_SR_CC1IF 1
+#define STM_TIM1_SR_UIF 0
+
+#define STM_TIM1_EGR_BG 7
+#define STM_TIM1_EGR_TG 6
+#define STM_TIM1_EGR_COMG 5
+#define STM_TIM1_EGR_CC4G 4
+#define STM_TIM1_EGR_CC3G 3
+#define STM_TIM1_EGR_CC2G 2
+#define STM_TIM1_EGR_CC1G 1
+#define STM_TIM1_EGR_UG 0
+
+#define STM_TIM1_CCMR1_OC2CE 15
+#define STM_TIM1_CCMR1_OC2M 12
+#define STM_TIM1_CCMR1_OC2PE 11
+#define STM_TIM1_CCMR1_OC2FE 10
+#define STM_TIM1_CCMR1_CC2S 8
+#define STM_TIM1_CCMR1_OC1CE 7
+#define STM_TIM1_CCMR1_OC1M 4
+#define STM_TIM1_CCMR_OCM_FROZEN 0
+#define STM_TIM1_CCMR_OCM_1_HIGH_MATCH 1
+#define STM_TIM1_CCMR_OCM_1_LOW_MATCH 2
+#define STM_TIM1_CCMR_OCM_TOGGLE 3
+#define STM_TIM1_CCMR_OCM_FORCE_LOW 4
+#define STM_TIM1_CCMR_OCM_FORCE_HIGH 5
+#define STM_TIM1_CCMR_OCM_PWM_MODE_1 6
+#define STM_TIM1_CCMR_OCM_PWM_MODE_2 7
+
+#define STM_TIM1_CCMR1_OC1PE 3
+#define STM_TIM1_CCMR1_OC1FE 2
+#define STM_TIM1_CCMR1_CC1S 0
+#define STM_TIM1_CCMR_CCS_OUTPUT 0
+#define STM_TIM1_CCMR_CCS_INPUT_TI1 1
+#define STM_TIM1_CCMR_CCS_INPUT_TI2 2
+#define STM_TIM1_CCMR_CCS_INPUT_TRC 3
+
+#define STM_TIM1_CCMR1_IC2F 12
+#define STM_TIM1_CCMR1_IC2PSC 10
+#define STM_TIM1_CCMR1_CC2S 8
+#define STM_TIM1_CCMR1_IC1F 4
+#define STM_TIM1_CCMR1_IC1F_NONE 0
+#define STM_TIM1_CCMR1_IC1F_DIV_1_N_2 1
+#define STM_TIM1_CCMR1_IC1F_DIV_1_N_4 2
+#define STM_TIM1_CCMR1_IC1F_DIV_1_N_8 3
+#define STM_TIM1_CCMR1_IC1F_DIV_2_N_6 4
+#define STM_TIM1_CCMR1_IC1F_DIV_2_N_8 5
+#define STM_TIM1_CCMR1_IC1F_DIV_4_N_6 6
+#define STM_TIM1_CCMR1_IC1F_DIV_4_N_8 7
+#define STM_TIM1_CCMR1_IC1F_DIV_8_N_6 8
+#define STM_TIM1_CCMR1_IC1F_DIV_8_N_8 9
+#define STM_TIM1_CCMR1_IC1F_DIV_16_N_5 10
+#define STM_TIM1_CCMR1_IC1F_DIV_16_N_6 11
+#define STM_TIM1_CCMR1_IC1F_DIV_16_N_8 12
+#define STM_TIM1_CCMR1_IC1F_DIV_32_N_5 13
+#define STM_TIM1_CCMR1_IC1F_DIV_32_N_6 14
+#define STM_TIM1_CCMR1_IC1F_DIV_32_N_8 15
+
+#define STM_TIM1_CCMR1_IC1PSC 2
+#define STM_TIM1_CCMR1_IC1PSC_NONE 0
+#define STM_TIM1_CCMR1_IC1PSC_2 1
+#define STM_TIM1_CCMR1_IC1PSC_4 2
+#define STM_TIM1_CCMR1_IC1PSC_8 3
+
+#define STM_TIM1_CCMR1_CC1S 0
+#define STM_TIM1_CCMR1_CC1S_OUTPUT 0
+#define STM_TIM1_CCMR1_CC1S_TI1 1
+#define STM_TIM1_CCMR1_CC1S_TI2 2
+#define STM_TIM1_CCMR1_CC1S_TRC 3
+
+#define STM_TIM1_CCMR2_OC4CE 15
+#define STM_TIM1_CCMR2_OC4M 12
+#define STM_TIM1_CCMR2_OC4PE 11
+#define STM_TIM1_CCMR2_OC4FE 10
+#define STM_TIM1_CCMR2_CC4S 8
+#define STM_TIM1_CCMR2_CCS_OUTPUT 0
+#define STM_TIM1_CCMR2_CCS_INPUT_TI3 1
+#define STM_TIM1_CCMR2_CCS_INPUT_TI4 2
+#define STM_TIM1_CCMR2_CCS_INPUT_TRC 3
+#define STM_TIM1_CCMR2_OC3CE 7
+#define STM_TIM1_CCMR2_OC3M 4
+#define STM_TIM1_CCMR2_OC3PE 3
+#define STM_TIM1_CCMR2_OC3FE 2
+#define STM_TIM1_CCMR2_CC3S 0
+
+#define STM_TIM1_CCMR2_IC4F 12
+#define STM_TIM1_CCMR2_IC2PSC 10
+#define STM_TIM1_CCMR2_CC4S 8
+#define STM_TIM1_CCMR2_IC3F 4
+#define STM_TIM1_CCMR2_IC1F_NONE 0
+#define STM_TIM1_CCMR2_IC1F_DIV_1_N_2 1
+#define STM_TIM1_CCMR2_IC1F_DIV_1_N_4 2
+#define STM_TIM1_CCMR2_IC1F_DIV_1_N_8 3
+#define STM_TIM1_CCMR2_IC1F_DIV_2_N_6 4
+#define STM_TIM1_CCMR2_IC1F_DIV_2_N_8 5
+#define STM_TIM1_CCMR2_IC1F_DIV_4_N_6 6
+#define STM_TIM1_CCMR2_IC1F_DIV_4_N_8 7
+#define STM_TIM1_CCMR2_IC1F_DIV_8_N_6 8
+#define STM_TIM1_CCMR2_IC1F_DIV_8_N_8 9
+#define STM_TIM1_CCMR2_IC1F_DIV_16_N_5 10
+#define STM_TIM1_CCMR2_IC1F_DIV_16_N_6 11
+#define STM_TIM1_CCMR2_IC1F_DIV_16_N_8 12
+#define STM_TIM1_CCMR2_IC1F_DIV_32_N_5 13
+#define STM_TIM1_CCMR2_IC1F_DIV_32_N_6 14
+#define STM_TIM1_CCMR2_IC1F_DIV_32_N_8 15
+
+#define STM_TIM1_CCER_CC4P 13
+#define STM_TIM1_CCER_CC4E 12
+#define STM_TIM1_CCER_CC3NP 11
+#define STM_TIM1_CCER_CC3NE 10
+#define STM_TIM1_CCER_CC3P 9
+#define STM_TIM1_CCER_CC3E 8
+#define STM_TIM1_CCER_CC2NP 7
+#define STM_TIM1_CCER_CC2NE 6
+#define STM_TIM1_CCER_CC2P 5
+#define STM_TIM1_CCER_CC2E 4
+#define STM_TIM1_CCER_CC1BP 3
+#define STM_TIM1_CCER_CC1NE 2
+#define STM_TIM1_CCER_CC1P 1
+#define STM_TIM1_CCER_CC1E 0
+
+#define STM_TIM1_BDTR_MOE 15
+#define STM_TIM1_BDTR_AOE 14
+#define STM_TIM1_BDTR_BKP 13
+#define STM_TIM1_BDTR_BKE 12
+#define STM_TIM1_BDTR_OSSR 11
+#define STM_TIM1_BDTR_OSSI 10
+#define STM_TIM1_BDTR_LOCK 8
+#define STM_TIM1_BDTR_LOCK_OFF 0
+#define STM_TIM1_BDTR_LOCK_LEVEL_1 1
+#define STM_TIM1_BDTR_LOCK_LEVEL_2 2
+#define STM_TIM1_BDTR_LOCK_LEVEL_3 3
+
+#define STM_TIM1_BDTR_DTG 0
+
+#define STM_TIM1_DCR_DBL 8
+#define STM_TIM1_DCR_DBA 0
+
+extern struct stm_tim1 stm_tim1;
+
+#define stm_tim1 (*(struct stm_tim1 *)0x40012c00)
+
struct stm_tim23 {
vuint32_t cr1;
vuint32_t cr2;
#define STM_USB_EPR_CTR_RX 15
#define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
#define STM_USB_EPR_DTOG_RX 14
+#define STM_USB_EPR_SW_BUF_TX 14
#define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
#define STM_USB_EPR_STAT_RX 12
#define STM_USB_EPR_STAT_RX_DISABLED 0
#define STM_USB_EPR_EP_TYPE_INTERRUPT 3
#define STM_USB_EPR_EP_TYPE_MASK 3
#define STM_USB_EPR_EP_KIND 8
+#define STM_USB_EPR_EP_KIND_SNGL_BUF 0 /* Bulk */
#define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
+#define STM_USB_EPR_EP_KIND_NO_STATUS_OUT 0 /* Control */
#define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
#define STM_USB_EPR_CTR_TX 7
#define STM_USB_CTR_TX_WRITE_INVARIANT 1
#define STM_USB_EPR_DTOG_TX 6
+#define STM_USB_EPR_SW_BUF_RX 6
#define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
#define STM_USB_EPR_STAT_TX 4
#define STM_USB_EPR_STAT_TX_DISABLED 0
#define STM_USB_BDT_SIZE 8
-extern uint8_t stm_usb_sram[];
+/* We'll use the first block of usb SRAM for the BDT */
+extern uint8_t stm_usb_sram[] __attribute__((aligned(4)));
+extern union stm_usb_bdt stm_usb_bdt[STM_USB_BDT_SIZE] __attribute__((aligned(4)));
+
+#define stm_usb_sram ((uint8_t *) 0x40006000)
+#define stm_usb_bdt ((union stm_usb_bdt *) 0x40006000)
struct stm_exti {
vuint32_t imr;
extern struct stm_exti stm_exti;
+struct stm_usart {
+ vuint32_t cr1; /* control register 1 */
+ vuint32_t cr2; /* control register 2 */
+ vuint32_t cr3; /* control register 3 */
+ vuint32_t brr; /* baud rate register */
+
+ vuint32_t gtpr; /* guard time and prescaler */
+ vuint32_t rtor; /* receiver timeout register */
+ vuint32_t rqr; /* request register */
+ vuint32_t isr; /* interrupt and status register */
+
+ vuint32_t icr; /* interrupt flag clear register */
+ vuint32_t rdr; /* receive data register */
+ vuint32_t tdr; /* transmit data register */
+};
+
+#define STM_USART_CR1_M1 28
+#define STM_USART_CR1_EOBIE 27
+#define STM_USART_CR1_RTOIE 26
+#define STM_USART_CR1_DEAT 21
+#define STM_USART_CR1_DEDT 16
+#define STM_USART_CR1_OVER8 15
+#define STM_USART_CR1_CMIE 14
+#define STM_USART_CR1_MME 13
+#define STM_USART_CR1_M0 12
+#define STM_USART_CR1_WAKE 11
+#define STM_USART_CR1_PCE 10
+#define STM_USART_CR1_PS 9
+#define STM_USART_CR1_PEIE 8
+#define STM_USART_CR1_TXEIE 7
+#define STM_USART_CR1_TCIE 6
+#define STM_USART_CR1_RXNEIE 5
+#define STM_USART_CR1_IDLEIE 4
+#define STM_USART_CR1_TE 3
+#define STM_USART_CR1_RE 2
+#define STM_USART_CR1_UESM 1
+#define STM_USART_CR1_UE 0
+
+#define STM_USART_CR2_ADD 24
+#define STM_USART_CR2_RTOEN 23
+#define STM_USART_CR2_ABRMOD 21
+#define STM_USART_CR2_ABREN 20
+#define STM_USART_CR2_MSBFIRST 19
+#define STM_USART_CR2_DATAINV 18
+#define STM_USART_CR2_TXINV 17
+#define STM_USART_CR2_RXINV 16
+#define STM_USART_CR2_SWAP 15
+#define STM_USART_CR2_LINEN 14
+#define STM_USART_CR2_STOP 12
+#define STM_USART_CR2_CLKEN 11
+#define STM_USART_CR2_CPOL 10
+#define STM_USART_CR2_CHPA 9
+#define STM_USART_CR2_LBCL 8
+#define STM_USART_CR2_LBDIE 6
+#define STM_USART_CR2_LBDL 5
+#define STM_USART_CR2_ADDM7 4
+
+#define STM_USART_CR3_WUFIE 22
+#define STM_USART_CR3_WUS 20
+#define STM_USART_CR3_SCARCNT 17
+#define STM_USART_CR3_DEP 15
+#define STM_USART_CR3_DEM 14
+#define STM_USART_CR3_DDRE 13
+#define STM_USART_CR3_OVRDIS 12
+#define STM_USART_CR3_ONEBIT 11
+#define STM_USART_CR3_CTIIE 10
+#define STM_USART_CR3_CTSE 9
+#define STM_USART_CR3_RTSE 8
+#define STM_USART_CR3_DMAT 7
+#define STM_USART_CR3_DMAR 6
+#define STM_USART_CR3_SCEN 5
+#define STM_USART_CR3_NACK 4
+#define STM_USART_CR3_HDSEL 3
+#define STM_USART_CR3_IRLP 2
+#define STM_USART_CR3_IREN 1
+#define STM_USART_CR3_EIE 0
+
+#define STM_USART_GTPR_GT 8
+#define STM_USART_GTPR_PSC 0
+
+#define STM_USART_RQR_TXFRQ 4
+#define STM_USART_RQR_RXFRQ 3
+#define STM_USART_RQR_MMRQ 2
+#define STM_USART_RQR_SBKRQ 1
+#define STM_USART_RQR_ABRRQ 0
+
+#define STM_USART_ISR_REACK 22
+#define STM_USART_ISR_TEACK 21
+#define STM_USART_ISR_WUF 20
+#define STM_USART_ISR_RWU 19
+#define STM_USART_ISR_SBKF 18
+#define STM_USART_ISR_CMF 17
+#define STM_USART_ISR_BUSY 16
+#define STM_USART_ISR_ABRF 15
+#define STM_USART_ISR_ABRE 14
+#define STM_USART_ISR_EOBF 12
+#define STM_USART_ISR_RTOF 11
+#define STM_USART_ISR_CTS 10
+#define STM_USART_ISR_CTSIF 9
+#define STM_USART_ISR_LBDF 8
+#define STM_USART_ISR_TXE 7
+#define STM_USART_ISR_TC 6
+#define STM_USART_ISR_RXNE 5
+#define STM_USART_ISR_IDLE 4
+#define STM_USART_ISR_ORE 3
+#define STM_USART_ISR_NF 2
+#define STM_USART_ISR_FE 1
+#define STM_USART_ISR_PE 0
+
+#define STM_USART_ICR_WUCF 20
+#define STM_USART_ICR_CMCF 17
+#define STM_USART_ICR_EOBCF 12
+#define STM_USART_ICR_RTOCF 11
+#define STM_USART_ICR_CTSCF 9
+#define STM_USART_ICR_LBDCF 8
+#define STM_USART_ICR_TCCF 6
+#define STM_USART_ICR_IDLECF 4
+#define STM_USART_ICR_ORECF 3
+#define STM_USART_ICR_NCF 2
+#define STM_USART_ICR_FECF 1
+#define STM_USART_ICR_PECF 0
+
+extern struct stm_usart stm_usart1;
+extern struct stm_usart stm_usart2;
+
+#define isr_decl(name) \
+ void __attribute__ ((weak)) stm_ ## name ## _isr(void);
+
+isr_decl(nmi)
+isr_decl(hardfault)
+isr_decl(memmanage)
+isr_decl(busfault)
+isr_decl(usagefault)
+isr_decl(svc)
+isr_decl(debugmon)
+isr_decl(pendsv)
+isr_decl(systick)
+isr_decl(wwdg)
+isr_decl(pvd)
+isr_decl(rtc)
+isr_decl(flash)
+isr_decl(rcc_crs)
+isr_decl(exti0_1)
+isr_decl(exti2_3)
+isr_decl(exti4_15)
+isr_decl(tsc)
+isr_decl(dma_ch1)
+isr_decl(dma_ch2_3)
+isr_decl(dma_ch4_5_6)
+isr_decl(adc_comp)
+isr_decl(tim1_brk_up_trg_com)
+isr_decl(tim1_cc)
+isr_decl(tim2)
+isr_decl(tim3)
+isr_decl(tim6_dac)
+isr_decl(tim7)
+isr_decl(tim14)
+isr_decl(tim15)
+isr_decl(tim16)
+isr_decl(tim17)
+isr_decl(i2c1)
+isr_decl(i2c2)
+isr_decl(spi1)
+isr_decl(spi2)
+isr_decl(usart1)
+isr_decl(usart2)
+isr_decl(usart3_4_5_6_7_8)
+isr_decl(cec_can)
+isr_decl(usb)
+
#endif /* _STM32F0_H_ */
projects / fw / altos / blobdiff