extern struct stm_rcc stm_rcc;
-/* Nominal high speed internal oscillator frequency is 16MHz */
-#define STM_HSI_FREQ 16000000
+/* Nominal high speed internal oscillator frequency is 8MHz */
+#define STM_HSI_FREQ 8000000
#define STM_RCC_CR_PLLRDY (25)
#define STM_RCC_CR_PLLON (24)
#define STM_TIM23_CCMR2_OC4CE 15
#define STM_TIM23_CCMR2_OC4M 12
-#define STM_TIM23_CCMR2_OCM_FROZEN 0
-#define STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH 1
-#define STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH 2
-#define STM_TIM23_CCMR2_OCM_TOGGLE 3
-#define STM_TIM23_CCMR2_OCM_FORCE_LOW 4
-#define STM_TIM23_CCMR2_OCM_FORCE_HIGH 5
-#define STM_TIM23_CCMR2_OCM_PWM_MODE_1 6
-#define STM_TIM23_CCMR2_OCM_PWM_MODE_2 7
-#define STM_TIM23_CCMR2_OCM_MASK 7
+#define STM_TIM23_CCMR2_OC4M_FROZEN 0
+#define STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
+#define STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH 2
+#define STM_TIM23_CCMR2_OC4M_TOGGLE 3
+#define STM_TIM23_CCMR2_OC4M_FORCE_LOW 4
+#define STM_TIM23_CCMR2_OC4M_FORCE_HIGH 5
+#define STM_TIM23_CCMR2_OC4M_PWM_MODE_1 6
+#define STM_TIM23_CCMR2_OC4M_PWM_MODE_2 7
+#define STM_TIM23_CCMR2_OC4M_MASK 7
#define STM_TIM23_CCMR2_OC4PE 11
#define STM_TIM23_CCMR2_OC4FE 10
#define STM_TIM23_CCMR2_CC4S 8
#define STM_TIM23_CCMR2_OC3CE 7
#define STM_TIM23_CCMR2_OC3M 4
-#define STM_TIM23_CCMR2_OCM_FROZEN 0
-#define STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH 1
-#define STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH 2
-#define STM_TIM23_CCMR2_OCM_TOGGLE 3
-#define STM_TIM23_CCMR2_OCM_FORCE_LOW 4
-#define STM_TIM23_CCMR2_OCM_FORCE_HIGH 5
+#define STM_TIM23_CCMR2_OC3M_FROZEN 0
+#define STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
+#define STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH 2
+#define STM_TIM23_CCMR2_OC3M_TOGGLE 3
+#define STM_TIM23_CCMR2_OC3M_FORCE_LOW 4
+#define STM_TIM23_CCMR2_OC3M_FORCE_HIGH 5
#define STM_TIM23_CCMR2_OC3M_PWM_MODE_1 6
-#define STM_TIM23_CCMR2_OCM_PWM_MODE_2 7
-#define STM_TIM23_CCMR2_OCM_MASK 7
+#define STM_TIM23_CCMR2_OC3M_PWM_MODE_2 7
+#define STM_TIM23_CCMR2_OC3M_MASK 7
#define STM_TIM23_CCMR2_OC3PE 11
#define STM_TIM23_CCMR2_OC3FE 2
#define STM_TIM23_CCMR2_CC3S 0
#define STM_USB_EPR_CTR_RX 15
#define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
#define STM_USB_EPR_DTOG_RX 14
+#define STM_USB_EPR_SW_BUF_TX 14
#define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
#define STM_USB_EPR_STAT_RX 12
#define STM_USB_EPR_STAT_RX_DISABLED 0
#define STM_USB_EPR_EP_TYPE_INTERRUPT 3
#define STM_USB_EPR_EP_TYPE_MASK 3
#define STM_USB_EPR_EP_KIND 8
+#define STM_USB_EPR_EP_KIND_SNGL_BUF 0 /* Bulk */
#define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
+#define STM_USB_EPR_EP_KIND_NO_STATUS_OUT 0 /* Control */
#define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
#define STM_USB_EPR_CTR_TX 7
#define STM_USB_CTR_TX_WRITE_INVARIANT 1
#define STM_USB_EPR_DTOG_TX 6
+#define STM_USB_EPR_SW_BUF_RX 6
#define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
#define STM_USB_EPR_STAT_TX 4
#define STM_USB_EPR_STAT_TX_DISABLED 0
#define STM_USB_BDT_SIZE 8
-extern uint8_t stm_usb_sram[];
+/* We'll use the first block of usb SRAM for the BDT */
+extern uint8_t stm_usb_sram[] __attribute__((aligned(4)));
+extern union stm_usb_bdt stm_usb_bdt[STM_USB_BDT_SIZE] __attribute__((aligned(4)));
+
+#define stm_usb_sram ((uint8_t *) 0x40006000)
+#define stm_usb_bdt ((union stm_usb_bdt *) 0x40006000)
struct stm_exti {
vuint32_t imr;
extern struct stm_usart stm_usart1;
extern struct stm_usart stm_usart2;
+#define isr_decl(name) \
+ void __attribute__ ((weak)) stm_ ## name ## _isr(void);
+
+isr_decl(nmi)
+isr_decl(hardfault)
+isr_decl(memmanage)
+isr_decl(busfault)
+isr_decl(usagefault)
+isr_decl(svc)
+isr_decl(debugmon)
+isr_decl(pendsv)
+isr_decl(systick)
+isr_decl(wwdg)
+isr_decl(pvd)
+isr_decl(rtc)
+isr_decl(flash)
+isr_decl(rcc_crs)
+isr_decl(exti0_1)
+isr_decl(exti2_3)
+isr_decl(exti4_15)
+isr_decl(tsc)
+isr_decl(dma_ch1)
+isr_decl(dma_ch2_3)
+isr_decl(dma_ch4_5_6)
+isr_decl(adc_comp)
+isr_decl(tim1_brk_up_trg_com)
+isr_decl(tim1_cc)
+isr_decl(tim2)
+isr_decl(tim3)
+isr_decl(tim6_dac)
+isr_decl(tim7)
+isr_decl(tim14)
+isr_decl(tim15)
+isr_decl(tim16)
+isr_decl(tim17)
+isr_decl(i2c1)
+isr_decl(i2c2)
+isr_decl(spi1)
+isr_decl(spi2)
+isr_decl(usart1)
+isr_decl(usart2)
+isr_decl(usart3_4_5_6_7_8)
+isr_decl(cec_can)
+isr_decl(usb)
+
#endif /* _STM32F0_H_ */