};
#define STM_MODER_SHIFT(pin) ((pin) << 1)
-#define STM_MODER_MASK 3
+#define STM_MODER_MASK 3UL
#define STM_MODER_INPUT 0
#define STM_MODER_OUTPUT 1
#define STM_MODER_ALTERNATE 2
}
#define STM_OTYPER_SHIFT(pin) (pin)
-#define STM_OTYPER_MASK 1
+#define STM_OTYPER_MASK 1UL
#define STM_OTYPER_PUSH_PULL 0
#define STM_OTYPER_OPEN_DRAIN 1
}
#define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
-#define STM_OSPEEDR_MASK 3
+#define STM_OSPEEDR_MASK 3UL
#define STM_OSPEEDR_LOW 0 /* 2MHz */
#define STM_OSPEEDR_MEDIUM 1 /* 10MHz */
#define STM_OSPEEDR_HIGH 3 /* 10-50MHz */
}
#define STM_PUPDR_SHIFT(pin) ((pin) << 1)
-#define STM_PUPDR_MASK 3
+#define STM_PUPDR_MASK 3UL
#define STM_PUPDR_NONE 0
#define STM_PUPDR_PULL_UP 1
#define STM_PUPDR_PULL_DOWN 2
}
#define STM_AFR_SHIFT(pin) ((pin) << 2)
-#define STM_AFR_MASK 0xf
+#define STM_AFR_MASK 0xfUL
#define STM_AFR_NONE 0
#define STM_AFR_AF0 0x0
#define STM_AFR_AF1 0x1
static inline uint16_t
stm_gpio_get_all(struct stm_gpio *gpio) {
- return gpio->idr;
+ return (uint16_t) gpio->idr;
}
/*
#define STM_FLASH_ACR_LATENCY_0 0
#define STM_FLASH_ACR_LATENCY_1 1
-#define STM_FLASH_PECR_OBL_LAUNCH 18
-#define STM_FLASH_PECR_ERRIE 17
-#define STM_FLASH_PECR_EOPIE 16
-#define STM_FLASH_PECR_FPRG 10
-#define STM_FLASH_PECR_ERASE 9
-#define STM_FLASH_PECR_FTDW 8
-#define STM_FLASH_PECR_DATA 4
-#define STM_FLASH_PECR_PROG 3
-#define STM_FLASH_PECR_OPTLOCK 2
-#define STM_FLASH_PECR_PRGLOCK 1
-#define STM_FLASH_PECR_PELOCK 0
-
#define STM_FLASH_SR_EOP 5
#define STM_FLASH_SR_WRPRTERR 4
#define STM_FLASH_SR_PGERR 2
extern struct stm_rcc stm_rcc;
-/* Nominal high speed internal oscillator frequency is 16MHz */
-#define STM_HSI_FREQ 16000000
+/* Nominal high speed internal oscillator frequency is 8MHz */
+#define STM_HSI_FREQ 8000000
#define STM_RCC_CR_PLLRDY (25)
#define STM_RCC_CR_PLLON (24)
#define STM_RCC_CFGR_MCOPRE_DIV_32 5
#define STM_RCC_CFGR_MCOPRE_DIV_64 6
#define STM_RCC_CFGR_MCOPRE_DIV_128 7
-#define STM_RCC_CFGR_MCOPRE_DIV_MASK 7
+#define STM_RCC_CFGR_MCOPRE_DIV_MASK 7UL
#define STM_RCC_CFGR_MCO (24)
# define STM_RCC_CFGR_MCO_DISABLE 0
+# define STM_RCC_CFGR_MCO_RC 1
+# define STM_RCC_CFGR_MCO_LSI 2
+# define STM_RCC_CFGR_MCO_LSE 3
+# define STM_RCC_CFGR_MCO_SYSCLK 4
+# define STM_RCC_CFGR_MCO_HSI 5
+# define STM_RCC_CFGR_MCO_HSE 6
+# define STM_RCC_CFGR_MCO_PLLCLK 7
+# define STM_RCC_CFGR_MCO_HSI48 8
+# define STM_RCC_CFGR_MCO_MASK (0xfUL)
#define STM_RCC_CFGR_PLLMUL (18)
#define STM_RCC_CFGR_PLLMUL_2 0
#define STM_RCC_CFGR_PLLMUL_14 12
#define STM_RCC_CFGR_PLLMUL_15 13
#define STM_RCC_CFGR_PLLMUL_16 14
-#define STM_RCC_CFGR_PLLMUL_MASK 0xf
+#define STM_RCC_CFGR_PLLMUL_MASK 0xfUL
#define STM_RCC_CFGR_PLLXTPRE (17)
#define STM_RCC_CFGR_PPRE_DIV_4 5
#define STM_RCC_CFGR_PPRE_DIV_8 6
#define STM_RCC_CFGR_PPRE_DIV_16 7
-#define STM_RCC_CFGR_PPRE_MASK 7
+#define STM_RCC_CFGR_PPRE_MASK 7UL
#define STM_RCC_CFGR_HPRE (4)
#define STM_RCC_CFGR_HPRE_DIV_1 0
#define STM_RCC_CFGR_HPRE_DIV_128 0xd
#define STM_RCC_CFGR_HPRE_DIV_256 0xe
#define STM_RCC_CFGR_HPRE_DIV_512 0xf
-#define STM_RCC_CFGR_HPRE_MASK 0xf
+#define STM_RCC_CFGR_HPRE_MASK 0xfUL
#define STM_RCC_CFGR_SWS (2)
#define STM_RCC_CFGR_SWS_HSI 0
#define STM_RCC_CFGR_SWS_HSE 1
#define STM_RCC_CFGR_SWS_PLL 2
#define STM_RCC_CFGR_SWS_HSI48 3
-#define STM_RCC_CFGR_SWS_MASK 3
+#define STM_RCC_CFGR_SWS_MASK 3UL
#define STM_RCC_CFGR_SW (0)
#define STM_RCC_CFGR_SW_HSI 0
#define STM_RCC_CFGR_SW_HSE 1
#define STM_RCC_CFGR_SW_PLL 2
#define STM_RCC_CFGR_SW_HSI48 3
-#define STM_RCC_CFGR_SW_MASK 3
+#define STM_RCC_CFGR_SW_MASK 3UL
#define STM_RCC_APB2RSTR_DBGMCURST 22
#define STM_RCC_APB2RSTR_TIM17RST 18
extern struct stm_pwr stm_pwr;
+#define stm_pwr (*(struct stm_pwr *) 0x40007000)
+
#define STM_PWR_CR_DBP (8)
#define STM_PWR_CR_PLS (5)
#define STM_PWR_CR_CSBF (3)
#define STM_PWR_CR_CWUF (2)
#define STM_PWR_CR_PDDS (1)
-#define STM_PWR_CR_LPSDSR (0)
+#define STM_PWR_CR_LPDS (0)
#define STM_PWR_CSR_EWUP3 (10)
#define STM_PWR_CSR_EWUP2 (9)
#define IRQ_PRIO_REG(irq) ((irq) >> 2)
#define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
-#define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
+#define IRQ_PRIO_MASK(irq) (0xffUL << IRQ_PRIO_BIT(irq))
static inline void
stm_nvic_set_priority(int irq, uint8_t prio) {
extern struct stm_scb stm_scb;
+#define stm_scb (*(struct stm_scb *) 0xe000ed00)
+
#define STM_SCB_AIRCR_VECTKEY 16
#define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
#define STM_SCB_AIRCR_PRIGROUP 8
#define STM_SCB_AIRCR_VECTCLRACTIVE 1
#define STM_SCB_AIRCR_VECTRESET 0
-#define isr(name) void stm_ ## name ## _isr(void);
-
-isr(nmi)
-isr(hardfault)
-isr(memmanage)
-isr(busfault)
-isr(usagefault)
-isr(svc)
-isr(debugmon)
-isr(pendsv)
-isr(systick)
-isr(wwdg)
-isr(pvd)
-isr(tamper_stamp)
-isr(rtc_wkup)
-isr(flash)
-isr(rcc)
-isr(exti0)
-isr(exti1)
-isr(exti2)
-isr(exti3)
-isr(exti4)
-isr(dma1_channel1)
-isr(dma1_channel2)
-isr(dma1_channel3)
-isr(dma1_channel4)
-isr(dma1_channel5)
-isr(dma1_channel6)
-isr(dma1_channel7)
-isr(adc1)
-isr(usb_hp)
-isr(usb_lp)
-isr(dac)
-isr(comp)
-isr(exti9_5)
-isr(lcd)
-isr(tim9)
-isr(tim10)
-isr(tim11)
-isr(tim2)
-isr(tim3)
-isr(tim4)
-isr(i2c1_ev)
-isr(i2c1_er)
-isr(i2c2_ev)
-isr(i2c2_er)
-isr(spi1)
-isr(spi2)
-isr(usart1)
-isr(usart2)
-isr(usart3)
-isr(exti15_10)
-isr(rtc_alarm)
-isr(usb_fs_wkup)
-isr(tim6)
-isr(tim7)
-
-#undef isr
+#define STM_SCB_SCR_SEVONPEND 4
+#define STM_SCB_SCR_SLEEPDEEP 2
+#define STM_SCB_SCR_SLEEPONEXIT 1
#define STM_ISR_WWDG_POS 0
#define STM_ISR_PVD_VDDIO2_POS 1
#define STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH 0
#define STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
#define STM_SYSCFG_CFGR1_MEM_MODE_SRAM 3
-#define STM_SYSCFG_CFGR1_MEM_MODE_MASK 3
+#define STM_SYSCFG_CFGR1_MEM_MODE_MASK 3UL
#define STM_SYSCFG_EXTICR_PA 0
#define STM_SYSCFG_EXTICR_PB 1
static inline void
stm_exticr_set(struct stm_gpio *gpio, int pin) {
- uint8_t reg = pin >> 2;
- uint8_t shift = (pin & 3) << 2;
+ uint8_t reg = (uint8_t) pin >> 2;
+ uint8_t shift = ((uint8_t) pin & 3) << 2;
uint8_t val = 0;
/* Enable SYSCFG */
else if (gpio == &stm_gpiof)
val = STM_SYSCFG_EXTICR_PF;
- stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
+ stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xfUL << shift)) | val << shift;
}
struct stm_dma_channel {
#define STM_DMA_INDEX(channel) ((channel) - 1)
#define STM_DMA_ISR(index) ((index) << 2)
-#define STM_DMA_ISR_MASK 0xf
+#define STM_DMA_ISR_MASK 0xfUL
#define STM_DMA_ISR_TEIF 3
#define STM_DMA_ISR_HTIF 2
#define STM_DMA_ISR_TCIF 1
#define STM_DMA_ISR_GIF 0
#define STM_DMA_IFCR(index) ((index) << 2)
-#define STM_DMA_IFCR_MASK 0xf
+#define STM_DMA_IFCR_MASK 0xfUL
#define STM_DMA_IFCR_CTEIF 3
#define STM_DMA_IFCR_CHTIF 2
#define STM_DMA_IFCR_CTCIF 1
#define STM_DMA_CCR_PL_MEDIUM (1)
#define STM_DMA_CCR_PL_HIGH (2)
#define STM_DMA_CCR_PL_VERY_HIGH (3)
-#define STM_DMA_CCR_PL_MASK (3)
+#define STM_DMA_CCR_PL_MASK (3UL)
#define STM_DMA_CCR_MSIZE (10)
#define STM_DMA_CCR_MSIZE_8 (0)
#define STM_DMA_CCR_MSIZE_16 (1)
#define STM_DMA_CCR_MSIZE_32 (2)
-#define STM_DMA_CCR_MSIZE_MASK (3)
+#define STM_DMA_CCR_MSIZE_MASK (3UL)
#define STM_DMA_CCR_PSIZE (8)
#define STM_DMA_CCR_PSIZE_8 (0)
#define STM_DMA_CCR_PSIZE_16 (1)
#define STM_DMA_CCR_PSIZE_32 (2)
-#define STM_DMA_CCR_PSIZE_MASK (3)
+#define STM_DMA_CCR_PSIZE_MASK (3UL)
#define STM_DMA_CCR_MINC (7)
#define STM_DMA_CCR_PINC (6)
#define STM_SPI_CR1_BR_PCLK_64 5
#define STM_SPI_CR1_BR_PCLK_128 6
#define STM_SPI_CR1_BR_PCLK_256 7
-#define STM_SPI_CR1_BR_MASK 7
+#define STM_SPI_CR1_BR_MASK 7UL
#define STM_SPI_CR1_MSTR 2
#define STM_SPI_CR1_CPOL 1
#define STM_ADC_CFGR1_EXTEN_RISING 1
#define STM_ADC_CFGR1_EXTEN_FALLING 2
#define STM_ADC_CFGR1_EXTEN_BOTH 3
-#define STM_ADC_CFGR1_EXTEN_MASK 3
+#define STM_ADC_CFGR1_EXTEN_MASK 3UL
#define STM_ADC_CFGR1_EXTSEL 6
#define STM_ADC_CFGR1_ALIGN 5
#define STM_ADC_CFGR1_RES_10 1
#define STM_ADC_CFGR1_RES_8 2
#define STM_ADC_CFGR1_RES_6 3
-#define STM_ADC_CFGR1_RES_MASK 3
+#define STM_ADC_CFGR1_RES_MASK 3UL
#define STM_ADC_CFGR1_SCANDIR 2
#define STM_ADC_CFGR1_SCANDIR_UP 0
#define STM_ADC_CFGR1_SCANDIR_DOWN 1
#define STM_I2C_CR2_FREQ_8_MHZ 8
#define STM_I2C_CR2_FREQ_16_MHZ 16
#define STM_I2C_CR2_FREQ_32_MHZ 32
-#define STM_I2C_CR2_FREQ_MASK 0x3f
+#define STM_I2C_CR2_FREQ_MASK 0x3fUL
#define STM_I2C_SR1_SMBALERT 15
#define STM_I2C_SR1_TIMEOUT 14
#define STM_I2C_SR1_SB 0
#define STM_I2C_SR2_PEC 8
-#define STM_I2C_SR2_PEC_MASK 0xff00
+#define STM_I2C_SR2_PEC_MASK 0xff00UL
#define STM_I2C_SR2_DUALF 7
#define STM_I2C_SR2_SMBHOST 6
#define STM_I2C_SR2_SMBDEFAULT 5
#define STM_I2C_CCR_FS 15
#define STM_I2C_CCR_DUTY 14
#define STM_I2C_CCR_CCR 0
-#define STM_I2C_CCR_MASK 0x7ff
+#define STM_I2C_CCR_MASK 0x7ffUL
struct stm_tim1 {
vuint32_t cr1;
#define STM_TIM23_CR1_CKD_1 0
#define STM_TIM23_CR1_CKD_2 1
#define STM_TIM23_CR1_CKD_4 2
-#define STM_TIM23_CR1_CKD_MASK 3
+#define STM_TIM23_CR1_CKD_MASK 3UL
#define STM_TIM23_CR1_ARPE 7
#define STM_TIM23_CR1_CMS 5
#define STM_TIM23_CR1_CMS_EDGE 0
#define STM_TIM23_CR1_CMS_CENTER_1 1
#define STM_TIM23_CR1_CMS_CENTER_2 2
#define STM_TIM23_CR1_CMS_CENTER_3 3
-#define STM_TIM23_CR1_CMS_MASK 3
+#define STM_TIM23_CR1_CMS_MASK 3UL
#define STM_TIM23_CR1_DIR 4
#define STM_TIM23_CR1_DIR_UP 0
#define STM_TIM23_CR1_DIR_DOWN 1
#define STM_TIM23_CR2_MMS_COMPARE_OC2REF 5
#define STM_TIM23_CR2_MMS_COMPARE_OC3REF 6
#define STM_TIM23_CR2_MMS_COMPARE_OC4REF 7
-#define STM_TIM23_CR2_MMS_MASK 7
+#define STM_TIM23_CR2_MMS_MASK 7UL
#define STM_TIM23_CR2_CCDS 3
#define STM_TIM23_SMCR_ETP 15
#define STM_TIM23_SMCR_ETPS_DIV_2 1
#define STM_TIM23_SMCR_ETPS_DIV_4 2
#define STM_TIM23_SMCR_ETPS_DIV_8 3
-#define STM_TIM23_SMCR_ETPS_MASK 3
+#define STM_TIM23_SMCR_ETPS_MASK 3UL
#define STM_TIM23_SMCR_ETF 8
#define STM_TIM23_SMCR_ETF_NONE 0
#define STM_TIM23_SMCR_ETF_INT_N_2 1
#define STM_TIM23_CCMR2_OC4CE 15
#define STM_TIM23_CCMR2_OC4M 12
-#define STM_TIM23_CCMR2_OCM_FROZEN 0
-#define STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH 1
-#define STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH 2
-#define STM_TIM23_CCMR2_OCM_TOGGLE 3
-#define STM_TIM23_CCMR2_OCM_FORCE_LOW 4
-#define STM_TIM23_CCMR2_OCM_FORCE_HIGH 5
-#define STM_TIM23_CCMR2_OCM_PWM_MODE_1 6
-#define STM_TIM23_CCMR2_OCM_PWM_MODE_2 7
-#define STM_TIM23_CCMR2_OCM_MASK 7
+#define STM_TIM23_CCMR2_OC4M_FROZEN 0
+#define STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
+#define STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH 2
+#define STM_TIM23_CCMR2_OC4M_TOGGLE 3
+#define STM_TIM23_CCMR2_OC4M_FORCE_LOW 4
+#define STM_TIM23_CCMR2_OC4M_FORCE_HIGH 5
+#define STM_TIM23_CCMR2_OC4M_PWM_MODE_1 6
+#define STM_TIM23_CCMR2_OC4M_PWM_MODE_2 7
+#define STM_TIM23_CCMR2_OC4M_MASK 7
#define STM_TIM23_CCMR2_OC4PE 11
#define STM_TIM23_CCMR2_OC4FE 10
#define STM_TIM23_CCMR2_CC4S 8
#define STM_TIM23_CCMR2_OC3CE 7
#define STM_TIM23_CCMR2_OC3M 4
-#define STM_TIM23_CCMR2_OCM_FROZEN 0
-#define STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH 1
-#define STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH 2
-#define STM_TIM23_CCMR2_OCM_TOGGLE 3
-#define STM_TIM23_CCMR2_OCM_FORCE_LOW 4
-#define STM_TIM23_CCMR2_OCM_FORCE_HIGH 5
+#define STM_TIM23_CCMR2_OC3M_FROZEN 0
+#define STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
+#define STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH 2
+#define STM_TIM23_CCMR2_OC3M_TOGGLE 3
+#define STM_TIM23_CCMR2_OC3M_FORCE_LOW 4
+#define STM_TIM23_CCMR2_OC3M_FORCE_HIGH 5
#define STM_TIM23_CCMR2_OC3M_PWM_MODE_1 6
-#define STM_TIM23_CCMR2_OCM_PWM_MODE_2 7
-#define STM_TIM23_CCMR2_OCM_MASK 7
+#define STM_TIM23_CCMR2_OC3M_PWM_MODE_2 7
+#define STM_TIM23_CCMR2_OC3M_MASK 7
#define STM_TIM23_CCMR2_OC3PE 11
#define STM_TIM23_CCMR2_OC3FE 2
#define STM_TIM23_CCMR2_CC3S 0
#define STM_USB_EPR_CTR_RX 15
#define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
#define STM_USB_EPR_DTOG_RX 14
+#define STM_USB_EPR_SW_BUF_TX 14
#define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
#define STM_USB_EPR_STAT_RX 12
#define STM_USB_EPR_STAT_RX_DISABLED 0
#define STM_USB_EPR_EP_TYPE_INTERRUPT 3
#define STM_USB_EPR_EP_TYPE_MASK 3
#define STM_USB_EPR_EP_KIND 8
+#define STM_USB_EPR_EP_KIND_SNGL_BUF 0 /* Bulk */
#define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
+#define STM_USB_EPR_EP_KIND_NO_STATUS_OUT 0 /* Control */
#define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
#define STM_USB_EPR_CTR_TX 7
#define STM_USB_CTR_TX_WRITE_INVARIANT 1
#define STM_USB_EPR_DTOG_TX 6
+#define STM_USB_EPR_SW_BUF_RX 6
#define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
#define STM_USB_EPR_STAT_TX 4
#define STM_USB_EPR_STAT_TX_DISABLED 0
#define STM_USB_BDT_SIZE 8
-extern uint8_t stm_usb_sram[];
+/* We'll use the first block of usb SRAM for the BDT */
+extern uint8_t stm_usb_sram[] __attribute__((aligned(4)));
+extern union stm_usb_bdt stm_usb_bdt[STM_USB_BDT_SIZE] __attribute__((aligned(4)));
+
+#define stm_usb_sram ((uint8_t *) 0x40006000)
+#define stm_usb_bdt ((union stm_usb_bdt *) 0x40006000)
struct stm_exti {
vuint32_t imr;
extern struct stm_exti stm_exti;
+struct stm_usart {
+ vuint32_t cr1; /* control register 1 */
+ vuint32_t cr2; /* control register 2 */
+ vuint32_t cr3; /* control register 3 */
+ vuint32_t brr; /* baud rate register */
+
+ vuint32_t gtpr; /* guard time and prescaler */
+ vuint32_t rtor; /* receiver timeout register */
+ vuint32_t rqr; /* request register */
+ vuint32_t isr; /* interrupt and status register */
+
+ vuint32_t icr; /* interrupt flag clear register */
+ vuint32_t rdr; /* receive data register */
+ vuint32_t tdr; /* transmit data register */
+};
+
+#define STM_USART_CR1_M1 28
+#define STM_USART_CR1_EOBIE 27
+#define STM_USART_CR1_RTOIE 26
+#define STM_USART_CR1_DEAT 21
+#define STM_USART_CR1_DEDT 16
+#define STM_USART_CR1_OVER8 15
+#define STM_USART_CR1_CMIE 14
+#define STM_USART_CR1_MME 13
+#define STM_USART_CR1_M0 12
+#define STM_USART_CR1_WAKE 11
+#define STM_USART_CR1_PCE 10
+#define STM_USART_CR1_PS 9
+#define STM_USART_CR1_PEIE 8
+#define STM_USART_CR1_TXEIE 7
+#define STM_USART_CR1_TCIE 6
+#define STM_USART_CR1_RXNEIE 5
+#define STM_USART_CR1_IDLEIE 4
+#define STM_USART_CR1_TE 3
+#define STM_USART_CR1_RE 2
+#define STM_USART_CR1_UESM 1
+#define STM_USART_CR1_UE 0
+
+#define STM_USART_CR2_ADD 24
+#define STM_USART_CR2_RTOEN 23
+#define STM_USART_CR2_ABRMOD 21
+#define STM_USART_CR2_ABREN 20
+#define STM_USART_CR2_MSBFIRST 19
+#define STM_USART_CR2_DATAINV 18
+#define STM_USART_CR2_TXINV 17
+#define STM_USART_CR2_RXINV 16
+#define STM_USART_CR2_SWAP 15
+#define STM_USART_CR2_LINEN 14
+#define STM_USART_CR2_STOP 12
+#define STM_USART_CR2_CLKEN 11
+#define STM_USART_CR2_CPOL 10
+#define STM_USART_CR2_CHPA 9
+#define STM_USART_CR2_LBCL 8
+#define STM_USART_CR2_LBDIE 6
+#define STM_USART_CR2_LBDL 5
+#define STM_USART_CR2_ADDM7 4
+
+#define STM_USART_CR3_WUFIE 22
+#define STM_USART_CR3_WUS 20
+#define STM_USART_CR3_SCARCNT 17
+#define STM_USART_CR3_DEP 15
+#define STM_USART_CR3_DEM 14
+#define STM_USART_CR3_DDRE 13
+#define STM_USART_CR3_OVRDIS 12
+#define STM_USART_CR3_ONEBIT 11
+#define STM_USART_CR3_CTIIE 10
+#define STM_USART_CR3_CTSE 9
+#define STM_USART_CR3_RTSE 8
+#define STM_USART_CR3_DMAT 7
+#define STM_USART_CR3_DMAR 6
+#define STM_USART_CR3_SCEN 5
+#define STM_USART_CR3_NACK 4
+#define STM_USART_CR3_HDSEL 3
+#define STM_USART_CR3_IRLP 2
+#define STM_USART_CR3_IREN 1
+#define STM_USART_CR3_EIE 0
+
+#define STM_USART_GTPR_GT 8
+#define STM_USART_GTPR_PSC 0
+
+#define STM_USART_RQR_TXFRQ 4
+#define STM_USART_RQR_RXFRQ 3
+#define STM_USART_RQR_MMRQ 2
+#define STM_USART_RQR_SBKRQ 1
+#define STM_USART_RQR_ABRRQ 0
+
+#define STM_USART_ISR_REACK 22
+#define STM_USART_ISR_TEACK 21
+#define STM_USART_ISR_WUF 20
+#define STM_USART_ISR_RWU 19
+#define STM_USART_ISR_SBKF 18
+#define STM_USART_ISR_CMF 17
+#define STM_USART_ISR_BUSY 16
+#define STM_USART_ISR_ABRF 15
+#define STM_USART_ISR_ABRE 14
+#define STM_USART_ISR_EOBF 12
+#define STM_USART_ISR_RTOF 11
+#define STM_USART_ISR_CTS 10
+#define STM_USART_ISR_CTSIF 9
+#define STM_USART_ISR_LBDF 8
+#define STM_USART_ISR_TXE 7
+#define STM_USART_ISR_TC 6
+#define STM_USART_ISR_RXNE 5
+#define STM_USART_ISR_IDLE 4
+#define STM_USART_ISR_ORE 3
+#define STM_USART_ISR_NF 2
+#define STM_USART_ISR_FE 1
+#define STM_USART_ISR_PE 0
+
+#define STM_USART_ICR_WUCF 20
+#define STM_USART_ICR_CMCF 17
+#define STM_USART_ICR_EOBCF 12
+#define STM_USART_ICR_RTOCF 11
+#define STM_USART_ICR_CTSCF 9
+#define STM_USART_ICR_LBDCF 8
+#define STM_USART_ICR_TCCF 6
+#define STM_USART_ICR_IDLECF 4
+#define STM_USART_ICR_ORECF 3
+#define STM_USART_ICR_NCF 2
+#define STM_USART_ICR_FECF 1
+#define STM_USART_ICR_PECF 0
+
+extern struct stm_usart stm_usart1;
+extern struct stm_usart stm_usart2;
+
+#define isr_decl(name) \
+ void stm_ ## name ## _isr(void)
+
+isr_decl(halt);
+isr_decl(ignore);
+isr_decl(nmi);
+isr_decl(hardfault);
+isr_decl(memmanage);
+isr_decl(busfault);
+isr_decl(usagefault);
+isr_decl(svc);
+isr_decl(debugmon);
+isr_decl(pendsv);
+isr_decl(systick);
+isr_decl(wwdg);
+isr_decl(pvd);
+isr_decl(rtc);
+isr_decl(flash);
+isr_decl(rcc_crs);
+isr_decl(exti0_1);
+isr_decl(exti2_3);
+isr_decl(exti4_15);
+isr_decl(tsc);
+isr_decl(dma_ch1);
+isr_decl(dma_ch2_3);
+isr_decl(dma_ch4_5_6);
+isr_decl(adc_comp);
+isr_decl(tim1_brk_up_trg_com);
+isr_decl(tim1_cc);
+isr_decl(tim2);
+isr_decl(tim3);
+isr_decl(tim6_dac);
+isr_decl(tim7);
+isr_decl(tim14);
+isr_decl(tim15);
+isr_decl(tim16);
+isr_decl(tim17);
+isr_decl(i2c1);
+isr_decl(i2c2);
+isr_decl(spi1);
+isr_decl(spi2);
+isr_decl(usart1);
+isr_decl(usart2);
+isr_decl(usart3_4_5_6_7_8);
+isr_decl(cec_can);
+isr_decl(usb);
+
#endif /* _STM32F0_H_ */
projects / fw / altos / blobdiff