*/
/* Buffer description tables */
-static union stm_usb_bdt *ao_usb_bdt;
-/* USB address of end of allocated storage */
-#if AO_USB_DIRECTIO
-static uint16_t ao_usb_sram_addr;
-#endif
+
+#define ao_usb_bdt ((union stm_usb_bdt *) (intptr_t) (void *) stm_usb_sram)
/* Pointer to ep0 tx/rx buffers in USB memory */
-static uint16_t *ao_usb_ep0_tx_buffer;
-static uint16_t *ao_usb_ep0_rx_buffer;
+static uint16_t ao_usb_ep0_tx_offset;
+static uint16_t ao_usb_ep0_rx_offset;
#if AO_USB_HAS_INT
/* Pointer to interrupt buffer in USB memory */
/* Pointer to bulk data tx/rx buffers in USB memory */
#if AO_USB_HAS_IN
-static uint16_t ao_usb_in_tx_offset[2];
-static uint16_t *ao_usb_in_tx_buffer[2];
+static uint16_t ao_usb_in_tx_offset;
static uint8_t ao_usb_in_tx_which;
static uint8_t ao_usb_tx_count;
#endif
#if AO_USB_HAS_OUT
-static uint16_t ao_usb_out_rx_offset[2];
-static uint16_t *ao_usb_out_rx_buffer[2];
+static uint16_t ao_usb_out_rx_offset;
static uint8_t ao_usb_out_rx_which;
static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
#endif
#if AO_USB_HAS_IN2
-static uint16_t ao_usb_in2_tx_offset[2];
-static uint16_t *ao_usb_in2_tx_buffer[2];
+static uint16_t ao_usb_in_tx2_offset;
static uint8_t ao_usb_in_tx2_which;
static uint8_t ao_usb_tx2_count;
#endif
+#if AO_USB_HAS_IN3
+static uint16_t ao_usb_in_tx3_offset;
+static uint8_t ao_usb_in_tx3_which;
+static uint8_t ao_usb_tx3_count;
+#endif
+
/*
* End point register indices
*/
#define AO_USB_OUT_EPR 2
#define AO_USB_IN_EPR 3
#define AO_USB_IN2_EPR 4
+#define AO_USB_IN3_EPR 5
/* Marks when we don't need to send an IN packet.
* This happens only when the last IN packet is not full,
static uint8_t ao_usb_in2_flushed;
#endif
+#if AO_USB_HAS_IN3
+/* Marks when we have delivered an IN packet to the hardware
+ * and it has not been received yet. ao_sleep on this address
+ * to wait for it to be delivered.
+ */
+static uint8_t ao_usb_in3_pending;
+static uint16_t in3_count;
+static uint8_t ao_usb_in3_flushed;
+#endif
+
/* Marks when an OUT packet has been received by the hardware
* but not pulled to the shadow buffer.
*/
return (uint16_t *) (void *) (stm_usb_sram + sram_addr);
}
+static inline uint16_t ao_usb_packet_get(uint16_t sram_addr)
+{
+ return ao_usb_packet_buffer_addr(sram_addr)[0];
+}
+
+static inline void ao_usb_packet_put(uint16_t sram_addr, uint16_t val)
+{
+ ao_usb_packet_buffer_addr(sram_addr)[0] = val;
+}
+
static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
{
return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
* Set current device address and mark the
* interface as active
*/
-void
+static void
ao_usb_set_address(uint8_t address)
{
debug("ao_usb_set_address %02x\n", address);
{
uint16_t sram_addr = 0;
- ao_usb_bdt = (void *) stm_usb_sram;
+ /* allocate space for BDT, which is at the start of SRAM */
sram_addr += 8 * STM_USB_BDT_SIZE;
- ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(sram_addr);
+ ao_usb_ep0_tx_offset = sram_addr;
sram_addr += AO_USB_CONTROL_SIZE;
- ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(sram_addr);
+ ao_usb_ep0_rx_offset = sram_addr;
sram_addr += AO_USB_CONTROL_SIZE;
-
#if AO_USB_HAS_INT
sram_addr += (sram_addr & 1);
ao_usb_int_tx_offset = sram_addr;
#if AO_USB_HAS_OUT
sram_addr += (sram_addr & 1);
- ao_usb_out_rx_buffer[0] = ao_usb_packet_buffer_addr(sram_addr);
- ao_usb_out_rx_offset[0] = sram_addr;
- sram_addr += AO_USB_OUT_SIZE;
- sram_addr += (sram_addr & 1);
- ao_usb_out_rx_buffer[1] = ao_usb_packet_buffer_addr(sram_addr);
- ao_usb_out_rx_offset[1] = sram_addr;
- sram_addr += AO_USB_OUT_SIZE;
- ao_usb_out_rx_which = 1;
+ ao_usb_out_rx_offset = sram_addr;
+ sram_addr += AO_USB_OUT_SIZE * 2;
#endif
#if AO_USB_HAS_IN
sram_addr += (sram_addr & 1);
- ao_usb_in_tx_buffer[0] = ao_usb_packet_buffer_addr(sram_addr);
- ao_usb_in_tx_offset[0] = sram_addr;
- sram_addr += AO_USB_IN_SIZE;
- ao_usb_in_tx_buffer[1] = ao_usb_packet_buffer_addr(sram_addr);
- ao_usb_in_tx_offset[1] = sram_addr;
- sram_addr += AO_USB_IN_SIZE;
- ao_usb_in_tx_which = 0;
+ ao_usb_in_tx_offset = sram_addr;
+ sram_addr += AO_USB_IN_SIZE * 2;
#endif
#if AO_USB_HAS_IN2
sram_addr += (sram_addr & 1);
- ao_usb_in2_tx_buffer[0] = ao_usb_packet_buffer_addr(sram_addr);
- ao_usb_in2_tx_offset[0] = sram_addr;
- sram_addr += AO_USB_IN_SIZE;
-
- sram_addr += (sram_addr & 1);
- ao_usb_in2_tx_buffer[1] = ao_usb_packet_buffer_addr(sram_addr);
- ao_usb_in2_tx_offset[1] = sram_addr;
- sram_addr += AO_USB_IN_SIZE;
- ao_usb_in2_tx_which = 0;
+ ao_usb_in_tx2_offset = sram_addr;
+ sram_addr += AO_USB_IN_SIZE * 2;
#endif
-
-#if AO_USB_DIRECTIO
+#if AO_USB_HAS_IN3
sram_addr += (sram_addr & 1);
- ao_usb_sram_addr = sram_addr;
+ ao_usb_in_tx3_offset = sram_addr;
+ sram_addr += AO_USB_IN_SIZE * 2;
#endif
}
{
/* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
- ao_usb_bdt[0].single.addr_tx = ao_usb_packet_buffer_offset(ao_usb_ep0_tx_buffer);
- ao_usb_bdt[0].single.count_tx = 0;
+ stm_usb_bdt[0].single.addr_tx = ao_usb_ep0_tx_offset;
+ stm_usb_bdt[0].single.count_tx = 0;
- ao_usb_bdt[0].single.addr_rx = ao_usb_packet_buffer_offset(ao_usb_ep0_rx_buffer);
- ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
+ stm_usb_bdt[0].single.addr_rx = ao_usb_ep0_rx_offset;
+ stm_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
(((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
}
#if AO_USB_HAS_INT
/* Set up the INT end point */
- ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_int_tx_offset;
- ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
+ stm_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_int_tx_offset;
+ stm_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
ao_usb_init_ep(AO_USB_INT_EPR,
AO_USB_INT_EP,
#if AO_USB_HAS_OUT
/* Set up the OUT end point */
- ao_usb_bdt[AO_USB_OUT_EPR].double_rx[0].addr = ao_usb_out_rx_offset[0];
- ao_usb_bdt[AO_USB_OUT_EPR].double_rx[0].count = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
+ stm_usb_bdt[AO_USB_OUT_EPR].double_rx[0].addr = ao_usb_out_rx_offset;
+ stm_usb_bdt[AO_USB_OUT_EPR].double_rx[0].count = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
(((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
- ao_usb_bdt[AO_USB_OUT_EPR].double_rx[1].addr = ao_usb_out_rx_offset[1];
- ao_usb_bdt[AO_USB_OUT_EPR].double_rx[1].count = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
+ stm_usb_bdt[AO_USB_OUT_EPR].double_rx[1].addr = ao_usb_out_rx_offset + AO_USB_OUT_SIZE;
+ stm_usb_bdt[AO_USB_OUT_EPR].double_rx[1].count = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
(((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
/* set 'our' buffer to one, and the device buffer to 0 */
STM_USB_EPR_STAT_RX_VALID,
STM_USB_EPR_STAT_TX_DISABLED,
STM_USB_EPR_EP_KIND_DBL_BUF, 0, 1);
+
+ /* At first receive, we'll flip this back to 0 */
+ ao_usb_out_rx_which = 1;
#endif
#if AO_USB_HAS_IN
/* Set up the IN end point */
- ao_usb_bdt[AO_USB_IN_EPR].double_tx[0].addr = ao_usb_in_tx_offset[0];
- ao_usb_bdt[AO_USB_IN_EPR].double_tx[0].count = 0;
- ao_usb_bdt[AO_USB_IN_EPR].double_tx[1].addr = ao_usb_in_tx_offset[1];
- ao_usb_bdt[AO_USB_IN_EPR].double_tx[1].count = 0;
+ stm_usb_bdt[AO_USB_IN_EPR].double_tx[0].addr = ao_usb_in_tx_offset;
+ stm_usb_bdt[AO_USB_IN_EPR].double_tx[0].count = 0;
+ stm_usb_bdt[AO_USB_IN_EPR].double_tx[1].addr = ao_usb_in_tx_offset + AO_USB_IN_SIZE;
+ stm_usb_bdt[AO_USB_IN_EPR].double_tx[1].count = 0;
/* set 'our' buffer to 0, and the device buffer to 1 */
ao_usb_init_ep(AO_USB_IN_EPR,
STM_USB_EPR_STAT_TX_NAK,
STM_USB_EPR_EP_KIND_DBL_BUF,
0, 1);
+
+ /* First transmit data goes to buffer 0 */
+ ao_usb_in_tx_which = 0;
#endif
#if AO_USB_HAS_IN2
/* Set up the IN2 end point */
- ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = 0;
- ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = 0;
+ stm_usb_bdt[AO_USB_IN2_EPR].double_tx[0].addr = ao_usb_in_tx2_offset;
+ stm_usb_bdt[AO_USB_IN2_EPR].double_tx[0].count = 0;
+ stm_usb_bdt[AO_USB_IN2_EPR].double_tx[1].addr = ao_usb_in_tx2_offset + AO_USB_IN_SIZE;
+ stm_usb_bdt[AO_USB_IN2_EPR].double_tx[1].count = 0;
ao_usb_init_ep(AO_USB_IN2_EPR,
AO_USB_IN2_EP,
STM_USB_EPR_STAT_TX_NAK,
STM_USB_EPR_EP_KIND_DBL_BUF,
0, 1);
+
+ /* First transmit data goes to buffer 0 */
+ ao_usb_in_tx2_which = 0;
+#endif
+
+#if AO_USB_HAS_IN3
+ /* Set up the IN3 end point */
+ stm_usb_bdt[AO_USB_IN3_EPR].double_tx[0].addr = ao_usb_in_tx3_offset;
+ stm_usb_bdt[AO_USB_IN3_EPR].double_tx[0].count = 0;
+ stm_usb_bdt[AO_USB_IN3_EPR].double_tx[1].addr = ao_usb_in_tx3_offset + AO_USB_IN_SIZE;
+ stm_usb_bdt[AO_USB_IN3_EPR].double_tx[1].count = 0;
+
+ ao_usb_init_ep(AO_USB_IN3_EPR,
+ AO_USB_IN3_EP,
+ STM_USB_EPR_EP_TYPE_BULK,
+ STM_USB_EPR_STAT_RX_DISABLED,
+ STM_USB_EPR_STAT_TX_NAK,
+ STM_USB_EPR_EP_KIND_DBL_BUF,
+ 0, 1);
+
+ /* First transmit data goes to buffer 0 */
+ ao_usb_in_tx3_which = 0;
#endif
ao_usb_in_flushed = 0;
ao_wakeup(&ao_usb_in2_pending);
#endif
+#if AO_USB_HAS_IN3
+ ao_usb_in3_flushed = 0;
+ ao_usb_in3_pending = 0;
+ ao_wakeup(&ao_usb_in3_pending);
+#endif
+
ao_usb_out_avail = 0;
ao_usb_configuration = 0;
*/
static void
-ao_usb_copy_tx(const uint8_t *src, uint16_t *base, uint16_t bytes)
+ao_usb_tx_byte(uint16_t offset, uint8_t byte)
{
- while (bytes >= 2) {
- *base++ = src[0] | (src[1] << 8);
- src += 2;
- bytes -= 2;
- }
- if (bytes)
- *base = *src;
+ if (offset & 1)
+ ao_usb_packet_put(offset - 1,
+ ao_usb_packet_get(offset - 1) | ((uint16_t) byte) << 8);
+ else
+ ao_usb_packet_put(offset, (uint16_t) byte);
}
-static void
-ao_usb_copy_rx(uint8_t *dst, uint16_t *base, uint16_t bytes)
+static uint8_t
+ao_usb_rx_byte(uint16_t offset)
{
- while (bytes >= 2) {
- uint16_t s = *base++;
- dst[0] = s;
- dst[1] = s >> 8;
- dst += 2;
- bytes -= 2;
- }
- if (bytes)
- *dst = *base;
+ if (offset & 1)
+ return (uint8_t) ((ao_usb_packet_get(offset - 1)) >> 8);
+ else
+ return (uint8_t) ao_usb_packet_get(offset);
}
-static inline void
-ao_usb_tx_byte(uint16_t *base, uint8_t tx_count, char byte)
+static void
+ao_usb_copy_tx(const uint8_t *src, uint16_t offset, uint16_t bytes)
{
- if (tx_count & 1)
- base[tx_count >> 1] |= ((uint16_t) byte) << 8;
- else
- base[tx_count >> 1] = (uint16_t) (uint8_t) byte;
+ while (bytes--)
+ ao_usb_tx_byte(offset++, *src++);
}
-static inline char
-ao_usb_rx_byte(uint16_t *base, uint8_t rx_count)
+static void
+ao_usb_copy_rx(uint8_t *dst, uint16_t offset, uint16_t bytes)
{
- if (rx_count & 1)
- return (char) (base[rx_count>>1] >> 8);
- else
- return (char) base[rx_count>>1];
+ while (bytes--)
+ *dst++ = ao_usb_rx_byte(offset++);
}
/* Send an IN data packet */
ao_usb_ep0_in_len -= this_len;
debug_data ("Flush EP0 len %d:", this_len);
- ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
+ ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_offset, this_len);
debug_data ("\n");
ao_usb_ep0_in_data += this_len;
/* Mark the endpoint as TX valid to send the packet */
- ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
+ stm_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
}
static void
ao_usb_ep0_fill(void)
{
- uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
+ uint16_t len = stm_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
if (len > ao_usb_ep0_out_len)
len = ao_usb_ep0_out_len;
/* Pull all of the data out of the packet */
debug_data ("Fill EP0 len %d:", len);
- ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
+ ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_offset, len);
debug_data ("\n");
ao_usb_ep0_out_data += len;
}
#if AO_POWER_MANAGEMENT
-void
+static void
ao_usb_suspend(void)
{
stm_usb.cntr |= (1 << STM_USB_CNTR_FSUSP);
ao_clock_suspend();
}
-void
+static void
ao_usb_wakeup(void)
{
ao_clock_resume();
ao_wakeup(&ao_usb_in2_pending);
}
break;
+#endif
+#if AO_USB_HAS_IN3
+ case AO_USB_IN3_EPR:
+ ++in3_count;
+ _tx_dbg1("TX3 ISR", epr);
+ if (ao_usb_epr_ctr_tx(epr)) {
+ ao_usb_in3_pending = 0;
+ ao_wakeup(&ao_usb_in3_pending);
+ }
+ break;
#endif
case AO_USB_INT_EPR:
#if USB_STATUS
ao_usb_in_pending = 1;
if (ao_usb_tx_count != AO_USB_IN_SIZE)
ao_usb_in_flushed = 1;
- ao_usb_bdt[AO_USB_IN_EPR].double_tx[ao_usb_in_tx_which].count = ao_usb_tx_count;
+ stm_usb_bdt[AO_USB_IN_EPR].double_tx[ao_usb_in_tx_which].count = ao_usb_tx_count;
ao_usb_tx_count = 0;
/* Toggle our usage */
_ao_usb_in_wait();
ao_usb_in_flushed = 0;
- ao_usb_tx_byte(ao_usb_in_tx_buffer[ao_usb_in_tx_which], ao_usb_tx_count++, c);
+ ao_usb_tx_byte(ao_usb_in_tx_offset + AO_USB_IN_SIZE * ao_usb_in_tx_which + ao_usb_tx_count++, c);
/* Send the packet when full */
if (ao_usb_tx_count == AO_USB_IN_SIZE) {
ao_usb_in2_pending = 1;
if (ao_usb_tx2_count != AO_USB_IN_SIZE)
ao_usb_in2_flushed = 1;
- ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_in2_tx_offset[ao_usb_in2_tx_which];
- ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = ao_usb_tx2_count;
+ stm_usb_bdt[AO_USB_IN2_EPR].double_tx[ao_usb_in_tx2_which].count = ao_usb_tx2_count;
ao_usb_tx2_count = 0;
- ao_usb_in2_tx_which = 1 - ao_usb_in2_tx_which;
+
+ /* Toggle our usage */
+ ao_usb_in_tx2_which = 1 - ao_usb_in_tx2_which;
+
+ /* Toggle the SW_BUF flag */
+ _ao_usb_toggle_dtog(AO_USB_IN2_EPR, 1, 0);
+
+ /* Mark the outgoing buffer as valid */
_ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
+
_tx_dbg0("in2_send end");
}
_ao_usb_in2_wait();
ao_usb_in2_flushed = 0;
- ao_usb_tx_byte(ao_usb_in2_tx_buffer[ao_usb_in2_tx_which], ao_usb_tx2_count, c);
- ao_usb_tx2_count++;
+ ao_usb_tx_byte(ao_usb_in_tx2_offset + AO_USB_IN_SIZE * ao_usb_in_tx2_which + ao_usb_tx2_count++, c);
/* Send the packet when full */
if (ao_usb_tx2_count == AO_USB_IN_SIZE) {
}
#endif
+#if AO_USB_HAS_IN3
+/* Queue the current IN buffer for transmission */
+static void
+_ao_usb_in3_send(void)
+{
+ _tx_dbg0("in3_send start");
+ debug ("send3 %d\n", ao_usb_tx3_count);
+ while (ao_usb_in3_pending)
+ ao_sleep(&ao_usb_in3_pending);
+ ao_usb_in3_pending = 1;
+ if (ao_usb_tx3_count != AO_USB_IN_SIZE)
+ ao_usb_in3_flushed = 1;
+ stm_usb_bdt[AO_USB_IN3_EPR].double_tx[ao_usb_in_tx3_which].count = ao_usb_tx3_count;
+ ao_usb_tx3_count = 0;
+
+ /* Toggle our usage */
+ ao_usb_in_tx3_which = 1 - ao_usb_in_tx3_which;
+
+ /* Toggle the SW_BUF flag */
+ _ao_usb_toggle_dtog(AO_USB_IN3_EPR, 1, 0);
+
+ /* Mark the outgoing buffer as valid */
+ _ao_usb_set_stat_tx(AO_USB_IN3_EPR, STM_USB_EPR_STAT_TX_VALID);
+
+ _tx_dbg0("in3_send end");
+}
+
+/* Wait for a free IN buffer. Interrupts are blocked */
+static void
+_ao_usb_in3_wait(void)
+{
+ for (;;) {
+ /* Check if the current buffer is writable */
+ if (ao_usb_tx3_count < AO_USB_IN_SIZE)
+ break;
+
+ _tx_dbg0("in3_wait top");
+ /* Wait for an IN buffer to be ready */
+ while (ao_usb_in3_pending)
+ ao_sleep(&ao_usb_in3_pending);
+ _tx_dbg0("in_wait bottom");
+ }
+}
+
+void
+ao_usb_flush3(void)
+{
+ if (!ao_usb_running)
+ return;
+
+ /* Anytime we've sent a character since
+ * the last time we flushed, we'll need
+ * to send a packet -- the only other time
+ * we would send a packet is when that
+ * packet was full, in which case we now
+ * want to send an empty packet
+ */
+ ao_arch_block_interrupts();
+ while (!ao_usb_in3_flushed) {
+ _tx_dbg0("flush3 top");
+ _ao_usb_in3_send();
+ _tx_dbg0("flush3 end");
+ }
+ ao_arch_release_interrupts();
+}
+
+void
+ao_usb_putchar3(char c)
+{
+ if (!ao_usb_running)
+ return;
+
+ ao_arch_block_interrupts();
+ _ao_usb_in3_wait();
+
+ ao_usb_in3_flushed = 0;
+ ao_usb_tx_byte(ao_usb_in_tx3_offset + AO_USB_IN_SIZE * ao_usb_in_tx3_which + ao_usb_tx3_count++, c);
+
+ /* Send the packet when full */
+ if (ao_usb_tx3_count == AO_USB_IN_SIZE) {
+ _tx_dbg0("putchar3 full");
+ _ao_usb_in3_send();
+ _tx_dbg0("putchar3 flushed");
+ }
+ ao_arch_release_interrupts();
+}
+#endif
+
#if AO_USB_HAS_OUT
static void
_ao_usb_out_recv(void)
/* Switch to new buffer */
ao_usb_out_rx_which = 1 - ao_usb_out_rx_which;
- ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].double_rx[ao_usb_out_rx_which].count & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
+ ao_usb_rx_count = stm_usb_bdt[AO_USB_OUT_EPR].double_rx[ao_usb_out_rx_which].count & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
ao_usb_rx_pos = 0;
/* Toggle the SW_BUF_RX bit */
_rx_dbg1("out_recv count", ao_usb_rx_count);
}
-int
+static int
_ao_usb_pollchar(void)
{
uint8_t c;
}
/* Pull a character out of the fifo */
- c = ao_usb_rx_byte(ao_usb_out_rx_buffer[ao_usb_out_rx_which], ao_usb_rx_pos++);
+ c = ao_usb_rx_byte(ao_usb_out_rx_offset + ao_usb_out_rx_which * AO_USB_OUT_SIZE + ao_usb_rx_pos++);
_rx_dbg1("char", c);
return c;
}
#endif
#if AO_USB_DIRECTIO
-uint16_t *
-ao_usb_alloc(void)
-{
- uint16_t *buffer;
- buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
- ao_usb_sram_addr += AO_USB_IN_SIZE;
- return buffer;
+#if AO_USB_HAS_IN
+uint8_t
+ao_usb_alloc(uint16_t *buffers[2])
+{
+ buffers[0] = ao_usb_packet_buffer_addr(ao_usb_in_tx_offset);
+ buffers[1] = ao_usb_packet_buffer_addr(ao_usb_in_tx_offset + AO_USB_IN_SIZE);
+ return ao_usb_in_tx_which;
}
-void
-ao_usb_write(uint16_t *buffer, uint16_t len)
+uint8_t
+ao_usb_write(uint16_t len)
{
ao_arch_block_interrupts();
continue;
}
- /* Flush any pending regular I/O */
- if (ao_usb_tx_count) {
- _ao_usb_in_send();
- continue;
- }
-
/* Wait for an idle IN buffer */
if (ao_usb_in_pending) {
ao_sleep(&ao_usb_in_pending);
ao_usb_in_pending = 1;
ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
- ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
- ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = len;
+
+ stm_usb_bdt[AO_USB_IN_EPR].double_tx[ao_usb_in_tx_which].count = len;
+
+ /* Toggle our usage */
+ ao_usb_in_tx_which = 1 - ao_usb_in_tx_which;
+
+ /* Toggle the SW_BUF flag */
+ _ao_usb_toggle_dtog(AO_USB_IN_EPR, 1, 0);
+
+ /* Mark the outgoing buffer as valid */
_ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
+
ao_arch_release_interrupts();
+ return ao_usb_in_tx_which;
}
+#endif
#if AO_USB_HAS_IN2
-void
-ao_usb_write2(uint16_t *buffer, uint16_t len)
+
+uint8_t
+ao_usb_alloc2(uint16_t *buffers[2])
+{
+ buffers[0] = ao_usb_packet_buffer_addr(ao_usb_in_tx2_offset);
+ buffers[1] = ao_usb_packet_buffer_addr(ao_usb_in_tx2_offset + AO_USB_IN_SIZE);
+ return ao_usb_in_tx2_which;
+}
+
+uint8_t
+ao_usb_write2(uint16_t len)
{
ao_arch_block_interrupts();
continue;
}
- /* Flush any pending regular I/O */
- if (ao_usb_tx2_count) {
- _ao_usb_in2_send();
- continue;
- }
-
/* Wait for an idle IN buffer */
if (ao_usb_in2_pending) {
ao_sleep(&ao_usb_in2_pending);
ao_usb_in2_pending = 1;
ao_usb_in2_flushed = (len != AO_USB_IN_SIZE);
- ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
- ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = len;
+
+ stm_usb_bdt[AO_USB_IN2_EPR].double_tx[ao_usb_in_tx2_which].count = len;
+
+ /* Toggle our usage */
+ ao_usb_in_tx2_which = 1 - ao_usb_in_tx2_which;
+
+ /* Toggle the SW_BUF flag */
+ _ao_usb_toggle_dtog(AO_USB_IN2_EPR, 1, 0);
+
+ /* Mark the outgoing buffer as valid */
_ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
ao_arch_release_interrupts();
+
+ return ao_usb_in_tx2_which;
}
#endif
#endif
ao_arch_release_interrupts();
- for (t = 0; t < 1000; t++)
+ for (t = 0; t < 50000; t++)
ao_arch_nop();
/* Enable USB pull-up */
control_count, out_count, in_count, int_count, reset_count);
}
-__code struct ao_cmds ao_usb_cmds[] = {
+const struct ao_cmds ao_usb_cmds[] = {
{ ao_usb_irq, "I\0Show USB interrupt counts" },
{ 0, NULL }
};
#endif
};
-#define NUM_USB_DBG 128
+#define NUM_USB_DBG 16
-struct ao_usb_dbg dbg[128];
+struct ao_usb_dbg dbg[NUM_USB_DBG];
int dbg_i;
static void _dbg(int line, char *msg, uint32_t value)
asm("mrs %0,primask" : "=&r" (primask));
dbg[dbg_i].primask = primask;
#if TX_DBG
- dbg[dbg_i].in_count = in_count;
- dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
- dbg[dbg_i].in_pending = ao_usb_in_pending;
- dbg[dbg_i].tx_count = ao_usb_tx_count;
- dbg[dbg_i].in_flushed = ao_usb_in_flushed;
+ dbg[dbg_i].in_count = in3_count;
+ dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN3_EPR].r;
+ dbg[dbg_i].in_pending = ao_usb_in3_pending;
+ dbg[dbg_i].tx_count = ao_usb_tx3_count;
+ dbg[dbg_i].in_flushed = ao_usb_in3_flushed;
#endif
#if RX_DBG
dbg[dbg_i].rx_count = ao_usb_rx_count;
projects / fw / altos / blobdiff