altos/stm32f1: Add STM_RCC_CFGR_PLLXTPRE_MASK value

[fw/altos] / src / stm32f1 / stm32f1.h

diff --git a/src/stm32f1/stm32f1.h b/src/stm32f1/stm32f1.h
index 9d59ebe53069e71edcf67feedbf880752736214c..196c8753d71da3ca8dd26962c447b5fe233638a1 100644 (file)
--- a/src/stm32f1/stm32f1.h
+++ b/src/stm32f1/stm32f1.h
@@ -68,14 +68,6 @@ extern struct stm_rcc stm_rcc;
 #define STM_RCC_CR_HSIRDY      (1)
 #define STM_RCC_CR_HSION       (0)
 
-#define STM_RCC_CFGR_MCOPRE    (28)
-#define  STM_RCC_CFGR_MCOPRE_DIV_1     0
-#define  STM_RCC_CFGR_MCOPRE_DIV_2     1
-#define  STM_RCC_CFGR_MCOPRE_DIV_4     2
-#define  STM_RCC_CFGR_MCOPRE_DIV_8     3
-#define  STM_RCC_CFGR_MCOPRE_DIV_16    4
-#define  STM_RCC_CFGR_MCOPRE_MASK      7UL
-
 #define STM_RCC_CFGR_MCO       (24)
 #define  STM_RCC_CFGR_MCO_DISABLE      0
 #define  STM_RCC_CFGR_MCO_SYSCLK       4
@@ -109,6 +101,7 @@ extern struct stm_rcc stm_rcc;
 #define STM_RCC_CFGR_PLLXTPRE  (17)
 #define  STM_RCC_CFGR_PLLXTPRE_1       0
 #define  STM_RCC_CFGR_PLLXTPRE_2       1
+#define  STM_RCC_CFGR_PLLXTPRE_MASK    1UL
 
 #define STM_RCC_CFGR_PLLSRC    (16)
 #define  STM_RCC_CFGR_PLLSRC_HSI_2     0