altos: Replace __critical usage with ao_arch_critical as needed

[fw/altos] / src / stm / stm32l.h

diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h
index ff8dddffc2bb1cbb95947f5fb995a917020f0288..e950d09bf5b8b905b6b32d7e37c290ce549ba696 100644 (file)
--- a/src/stm/stm32l.h
+++ b/src/stm/stm32l.h
@@ -167,7 +167,7 @@ stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 }
 
 static inline uint8_t
-stm_gpio_isset(struct stm_gpio *gpio, int pin) {
+stm_gpio_get(struct stm_gpio *gpio, int pin) {
        return (gpio->idr >> pin) & 1;
 }
 
@@ -254,8 +254,138 @@ struct stm_tim {
 };
 
 extern struct stm_tim stm_tim9;
-extern struct stm_tim stm_tim10;
-extern struct stm_tim stm_tim11;
+
+struct stm_tim1011 {
+       vuint32_t       cr1;
+       uint32_t        unused_4;
+       vuint32_t       smcr;
+       vuint32_t       dier;
+       vuint32_t       sr;
+       vuint32_t       egr;
+       vuint32_t       ccmr1;
+       uint32_t        unused_1c;
+       vuint32_t       ccer;
+       vuint32_t       cnt;
+       vuint32_t       psc;
+       vuint32_t       arr;
+       uint32_t        unused_30;
+       vuint32_t       ccr1;
+       uint32_t        unused_38;
+       uint32_t        unused_3c;
+       uint32_t        unused_40;
+       uint32_t        unused_44;
+       uint32_t        unused_48;
+       uint32_t        unused_4c;
+       vuint32_t       or;
+};
+
+extern struct stm_tim1011 stm_tim10;
+extern struct stm_tim1011 stm_tim11;
+
+#define STM_TIM1011_CR1_CKD    8
+#define  STM_TIM1011_CR1_CKD_1         0
+#define  STM_TIM1011_CR1_CKD_2         1
+#define  STM_TIM1011_CR1_CKD_4         2
+#define  STM_TIM1011_CR1_CKD_MASK      3
+#define STM_TIM1011_CR1_ARPE   7
+#define STM_TIM1011_CR1_URS    2
+#define STM_TIM1011_CR1_UDIS   1
+#define STM_TIM1011_CR1_CEN    0
+
+#define STM_TIM1011_SMCR_ETP   15
+#define STM_TIM1011_SMCR_ECE   14
+#define STM_TIM1011_SMCR_ETPS  12
+#define  STM_TIM1011_SMCR_ETPS_OFF     0
+#define  STM_TIM1011_SMCR_ETPS_2       1
+#define  STM_TIM1011_SMCR_ETPS_4       2
+#define  STM_TIM1011_SMCR_ETPS_8       3
+#define  STM_TIM1011_SMCR_ETPS_MASK    3
+#define STM_TIM1011_SMCR_ETF   8
+#define  STM_TIM1011_SMCR_ETF_NONE             0
+#define  STM_TIM1011_SMCR_ETF_CK_INT_2         1
+#define  STM_TIM1011_SMCR_ETF_CK_INT_4         2
+#define  STM_TIM1011_SMCR_ETF_CK_INT_8         3
+#define  STM_TIM1011_SMCR_ETF_DTS_2_6          4
+#define  STM_TIM1011_SMCR_ETF_DTS_2_8          5
+#define  STM_TIM1011_SMCR_ETF_DTS_4_6          6
+#define  STM_TIM1011_SMCR_ETF_DTS_4_8          7
+#define  STM_TIM1011_SMCR_ETF_DTS_8_6          8
+#define  STM_TIM1011_SMCR_ETF_DTS_8_8          9
+#define  STM_TIM1011_SMCR_ETF_DTS_16_5         10
+#define  STM_TIM1011_SMCR_ETF_DTS_16_6         11
+#define  STM_TIM1011_SMCR_ETF_DTS_16_8         12
+#define  STM_TIM1011_SMCR_ETF_DTS_32_5         13
+#define  STM_TIM1011_SMCR_ETF_DTS_32_6         14
+#define  STM_TIM1011_SMCR_ETF_DTS_32_8         15
+#define  STM_TIM1011_SMCR_ETF_MASK             15
+
+#define STM_TIM1011_DIER_CC1E  1
+#define STM_TIM1011_DIER_UIE   0
+
+#define STM_TIM1011_SR_CC1OF   9
+#define STM_TIM1011_SR_CC1IF   1
+#define STM_TIM1011_SR_UIF     0
+
+#define STM_TIM1011_EGR_CC1G   1
+#define STM_TIM1011_EGR_UG     0
+
+#define STM_TIM1011_CCMR1_OC1CE        7
+#define STM_TIM1011_CCMR1_OC1M 4
+#define  STM_TIM1011_CCMR1_OC1M_FROZEN                 0
+#define  STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH  1
+#define  STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH        2
+#define  STM_TIM1011_CCMR1_OC1M_TOGGLE                 3
+#define  STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE         4
+#define  STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE           5
+#define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_1             6
+#define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_2             7
+#define  STM_TIM1011_CCMR1_OC1M_MASK                   7
+#define STM_TIM1011_CCMR1_OC1PE        3
+#define STM_TIM1011_CCMR1_OC1FE        2
+#define STM_TIM1011_CCMR1_CC1S 0
+#define  STM_TIM1011_CCMR1_CC1S_OUTPUT                 0
+#define  STM_TIM1011_CCMR1_CC1S_INPUT_TI1              1
+#define  STM_TIM1011_CCMR1_CC1S_INPUT_TI2              2
+#define  STM_TIM1011_CCMR1_CC1S_INPUT_TRC              3
+#define  STM_TIM1011_CCMR1_CC1S_MASK                   3
+
+#define  STM_TIM1011_CCMR1_IC1F_NONE           0
+#define  STM_TIM1011_CCMR1_IC1F_CK_INT_2       1
+#define  STM_TIM1011_CCMR1_IC1F_CK_INT_4       2
+#define  STM_TIM1011_CCMR1_IC1F_CK_INT_8       3
+#define  STM_TIM1011_CCMR1_IC1F_DTS_2_6                4
+#define  STM_TIM1011_CCMR1_IC1F_DTS_2_8                5
+#define  STM_TIM1011_CCMR1_IC1F_DTS_4_6                6
+#define  STM_TIM1011_CCMR1_IC1F_DTS_4_8                7
+#define  STM_TIM1011_CCMR1_IC1F_DTS_8_6                8
+#define  STM_TIM1011_CCMR1_IC1F_DTS_8_8                9
+#define  STM_TIM1011_CCMR1_IC1F_DTS_16_5       10
+#define  STM_TIM1011_CCMR1_IC1F_DTS_16_6       11
+#define  STM_TIM1011_CCMR1_IC1F_DTS_16_8       12
+#define  STM_TIM1011_CCMR1_IC1F_DTS_32_5       13
+#define  STM_TIM1011_CCMR1_IC1F_DTS_32_6       14
+#define  STM_TIM1011_CCMR1_IC1F_DTS_32_8       15
+#define  STM_TIM1011_CCMR1_IC1F_MASK           15
+#define STM_TIM1011_CCMR1_IC1PSC       2
+#define  STM_TIM1011_CCMR1_IC1PSC_1            0
+#define  STM_TIM1011_CCMR1_IC1PSC_2            1
+#define  STM_TIM1011_CCMR1_IC1PSC_4            2
+#define  STM_TIM1011_CCMR1_IC1PSC_8            3
+#define  STM_TIM1011_CCMR1_IC1PSC_MASK         3
+#define STM_TIM1011_CCMR1_CC1S         0
+
+#define STM_TIM1011_CCER_CC1NP         3
+#define STM_TIM1011_CCER_CC1P          1
+#define STM_TIM1011_CCER_CC1E          0
+
+#define STM_TIM1011_OR_TI1_RMP_RI      3
+#define STM_TIM1011_ETR_RMP            2
+#define STM_TIM1011_TI1_RMP            0
+#define  STM_TIM1011_TI1_RMP_GPIO              0
+#define  STM_TIM1011_TI1_RMP_LSI               1
+#define  STM_TIM1011_TI1_RMP_LSE               2
+#define  STM_TIM1011_TI1_RMP_RTC               3
+#define  STM_TIM1011_TI1_RMP_MASK              3
 
 /* Flash interface */
 
@@ -281,6 +411,30 @@ extern struct stm_flash    stm_flash;
 #define STM_FLASH_ACR_PRFEN    (1)
 #define STM_FLASH_ACR_LATENCY  (0)
 
+#define STM_FLASH_PECR_OBL_LAUNCH      18
+#define STM_FLASH_PECR_ERRIE           17
+#define STM_FLASH_PECR_EOPIE           16
+#define STM_FLASH_PECR_FPRG            10
+#define STM_FLASH_PECR_ERASE           9
+#define STM_FLASH_PECR_FTDW            8
+#define STM_FLASH_PECR_DATA            4
+#define STM_FLASH_PECR_PROG            3
+#define STM_FLASH_PECR_OPTLOCK         2
+#define STM_FLASH_PECR_PRGLOCK         1
+#define STM_FLASH_PECR_PELOCK          0
+
+#define STM_FLASH_SR_OPTVERR           11
+#define STM_FLASH_SR_SIZERR            10
+#define STM_FLASH_SR_PGAERR            9
+#define STM_FLASH_SR_WRPERR            8
+#define STM_FLASH_SR_READY             3
+#define STM_FLASH_SR_ENDHV             2
+#define STM_FLASH_SR_EOP               1
+#define STM_FLASH_SR_BSY               0
+
+#define STM_FLASH_PEKEYR_PEKEY1        0x89ABCDEF
+#define STM_FLASH_PEKEYR_PEKEY2 0x02030405
+
 struct stm_rcc {
        vuint32_t       cr;
        vuint32_t       icscr;
@@ -881,6 +1035,9 @@ stm_exticr_set(struct stm_gpio *gpio, int pin) {
        uint8_t shift = (pin & 3) << 2;
        uint8_t val = 0;
 
+       /* Enable SYSCFG */
+       stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
+
        if (gpio == &stm_gpioa)
                val = STM_SYSCFG_EXTICR_PA;
        else if (gpio == &stm_gpiob)