altos/stm: Figure out available flash space based on chip id registers

[fw/altos] / src / stm / stm32l.h

diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h
index 0dbfae39814c0fd4a5e43805bbbe66c120800ce9..9226e9cb0f39a4ea6d1ffc27986000ce94a5100a 100644 (file)
--- a/src/stm/stm32l.h
+++ b/src/stm/stm32l.h
@@ -52,7 +52,7 @@ stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
                       value << STM_MODER_SHIFT(pin));
 }
        
-static inline vuint32_t
+static inline uint32_t
 stm_moder_get(struct stm_gpio *gpio, int pin) {
        return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
 }
@@ -69,7 +69,7 @@ stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
                        value << STM_OTYPER_SHIFT(pin));
 }
        
-static inline vuint32_t
+static inline uint32_t
 stm_otyper_get(struct stm_gpio *gpio, int pin) {
        return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
 }
@@ -88,7 +88,7 @@ stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
                       value << STM_OSPEEDR_SHIFT(pin));
 }
        
-static inline vuint32_t
+static inline uint32_t
 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
        return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
 }
@@ -171,6 +171,11 @@ stm_gpio_get(struct stm_gpio *gpio, int pin) {
        return (gpio->idr >> pin) & 1;
 }
 
+static inline uint16_t
+stm_gpio_get_all(struct stm_gpio *gpio) {
+       return gpio->idr;
+}
+
 extern struct stm_gpio stm_gpioa;
 extern struct stm_gpio stm_gpiob;
 extern struct stm_gpio stm_gpioc;
@@ -435,6 +440,9 @@ extern struct stm_flash     stm_flash;
 #define STM_FLASH_PEKEYR_PEKEY1        0x89ABCDEF
 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
 
+#define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
+#define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
+
 struct stm_rcc {
        vuint32_t       cr;
        vuint32_t       icscr;
@@ -811,30 +819,59 @@ extern struct stm_lcd stm_lcd;
 #define STM_LCD_CLR_UDDC               (3)
 #define STM_LCD_CLR_SOFC               (1)
 
+/* The SYSTICK starts at 0xe000e010 */
+
+struct stm_systick {
+       vuint32_t       csr;
+       vuint32_t       rvr;
+       vuint32_t       cvr;
+       vuint32_t       calib;
+};
+
+extern struct stm_systick stm_systick;
+
+#define STM_SYSTICK_CSR_ENABLE         0
+#define STM_SYSTICK_CSR_TICKINT                1
+#define STM_SYSTICK_CSR_CLKSOURCE      2
+#define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8              0
+#define  STM_SYSTICK_CSR_CLKSOURCE_HCLK                        1
+#define STM_SYSTICK_CSR_COUNTFLAG      16
+
+/* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
+
 struct stm_nvic {
-       vuint32_t       iser[3];        /* 0x000 */
+       vuint32_t       iser[8];        /* 0x000 0xe000e100 Set Enable Register */
+
+       uint8_t         _unused020[0x080 - 0x020];
 
-       uint8_t         _unused00c[0x080 - 0x00c];
+       vuint32_t       icer[8];        /* 0x080 0xe000e180 Clear Enable Register */
 
-       vuint32_t       icer[3];        /* 0x080 */
+       uint8_t         _unused0a0[0x100 - 0x0a0];
 
-       uint8_t         _unused08c[0x100 - 0x08c];
+       vuint32_t       ispr[8];        /* 0x100 0xe000e200 Set Pending Register */
 
-       vuint32_t       ispr[3];        /* 0x100 */
+       uint8_t         _unused120[0x180 - 0x120];
 
-       uint8_t         _unused10c[0x180 - 0x10c];
+       vuint32_t       icpr[8];        /* 0x180 0xe000e280 Clear Pending Register */
 
-       vuint32_t       icpr[3];        /* 0x180 */
+       uint8_t         _unused1a0[0x200 - 0x1a0];
 
-       uint8_t         _unused18c[0x200 - 0x18c];
+       vuint32_t       iabr[8];        /* 0x200 0xe000e300 Active Bit Register */
 
-       vuint32_t       iabr[3];        /* 0x200 */
+       uint8_t         _unused220[0x300 - 0x220];
 
-       uint8_t         _unused20c[0x300 - 0x20c];
+       vuint32_t       ipr[60];        /* 0x300 0xe000e400 Priority Register */
 
-       vuint32_t       ipr[21];        /* 0x300 */
+       uint8_t         _unused3f0[0xc00 - 0x3f0];
 
-       uint8_t         _unused324[0xe00 - 0x324];
+       vuint32_t       cpuid_base;     /* 0xc00 0xe000ed00 CPUID Base Register */
+       vuint32_t       ics;            /* 0xc04 0xe000ed04 Interrupt Control State Register */
+       vuint32_t       vto;            /* 0xc08 0xe000ed08 Vector Table Offset Register */
+       vuint32_t       ai_rc;          /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
+       vuint32_t       sc;             /* 0xc10 0xe000ed10 System Control Register */
+       vuint32_t       cc;             /* 0xc14 0xe000ed14 Configuration Control Register */
+
+       uint8_t         _unusedc18[0xe00 - 0xc18];
 
        vuint32_t       stir;           /* 0xe00 */
 };
@@ -1455,6 +1492,36 @@ extern struct stm_temp_cal       stm_temp_cal;
 #define stm_temp_cal_cold      25
 #define stm_temp_cal_hot       110
 
+struct stm_dbg_mcu {
+       uint32_t        idcode;
+};
+
+extern struct stm_dbg_mcu      stm_dbg_mcu;
+
+static inline uint16_t
+stm_dev_id(void) {
+       return stm_dbg_mcu.idcode & 0xfff;
+}
+
+struct stm_flash_size {
+       uint16_t        f_size;
+};
+
+extern struct stm_flash_size   stm_flash_size_medium;
+extern struct stm_flash_size   stm_flash_size_large;
+
+/* Returns flash size in bytes */
+extern uint32_t
+stm_flash_size(void);
+
+struct stm_device_id {
+       uint32_t        u_id0;
+       uint32_t        u_id1;
+       uint32_t        u_id2;
+};
+
+extern struct stm_device_id    stm_device_id;
+
 #define STM_NUM_I2C    2
 
 #define STM_I2C_INDEX(channel) ((channel) - 1)
@@ -1702,7 +1769,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC               3
 #define  STM_TIM234_CCMR1_CC1S_MASK                    3
 
-#define STM_TIM234_CCMR2_OC2CE 15
+#define STM_TIM234_CCMR2_OC4CE 15
 #define STM_TIM234_CCMR2_OC4M  12
 #define  STM_TIM234_CCMR2_OC4M_FROZEN                  0
 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH       1