/* SPI controller mode */
#define SAMD21_SERCOM_CTRLA_DOPO 16
+#define SAMD21_SERCOM_CTRLA_DOPO_MOSI_0_SCLK_1 0UL
+#define SAMD21_SERCOM_CTRLA_DOPO_MOSI_2_SCLK_3 1UL
+#define SAMD21_SERCOM_CTRLA_DOPO_MOSI_3_SCLK_1 2UL
+#define SAMD21_SERCOM_CTRLA_DOPO_MOSI_0_SCLK_3 3UL
+#define SAMD21_SERCOM_CTRLA_DOPO_MASK 3UL
+
#define SAMD21_SERCOM_CTRLA_DIPO 20
+#define SAMD21_SERCOM_CTRLA_DIPO_MISO_0 0UL
+#define SAMD21_SERCOM_CTRLA_DIPO_MISO_1 1UL
+#define SAMD21_SERCOM_CTRLA_DIPO_MISO_2 2UL
+#define SAMD21_SERCOM_CTRLA_DIPO_MISO_3 3UL
+#define SAMD21_SERCOM_CTRLA_DIPO_MASK 3UL
+
#define SAMD21_SERCOM_CTRLA_FORM 24
#define SAMD21_SERCOM_CTRLA_CPHA 28
#define SAMD21_SERCOM_CTRLA_CPOL 29