*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
};
extern struct lpc_ioconf lpc_ioconf;
+#define lpc_ioconf (*(struct lpc_ioconf *) 0x40044000)
#define LPC_IOCONF_FUNC 0
#define LPC_IOCONF_FUNC_PIO0_3 0
#define LPC_IOCONF_FUNC_USB_VBUS 1
-/* PIO0_4
+/* PIO0_4 */
#define LPC_IOCONF_FUNC_PIO0_4 0
#define LPC_IOCONF_FUNC_I2C_SCL 1
/* PIO0_6 */
#define LPC_IOCONF_FUNC_PIO0_6 0
#define LPC_IOCONF_FUNC_USB_CONNECT 1
-#define LPC_IOCONF_FUNC_SCK0 2
+#define LPC_IOCONF_FUNC_PIO0_6_SCK0 2
/* PIO0_7 */
#define LPC_IOCONF_FUNC_PIO0_7 0
/* PIO0_10 */
#define LPC_IOCONF_FUNC_SWCLK 0
#define LPC_IOCONF_FUNC_PIO0_10 1
-#define LPC_IOCONF_FUNC_SCK0 2
+#define LPC_IOCONF_FUNC_PIO0_10_SCK0 2
#define LPC_IOCONF_FUNC_CT16B0_MAT2 3
/* PIO0_11 */
vuint32_t mainclksel; /* 0x70 */
vuint32_t mainclkuen;
vuint32_t sysahbclkdiv;
- uint32_t r7c;
+ uint32_t r7c;
vuint32_t sysahbclkctrl; /* 0x80 */
uint32_t r84[3];
uint32_t rcc;
uint32_t rd0[4];
-
+
vuint32_t clkoutsel; /* 0xe0 */
vuint32_t clkoutuen;
vuint32_t clkoutdiv;
uint32_t rec;
-
+
uint32_t rf0[4]; /* 0xf0 */
-
+
vuint32_t pioporcap0; /* 0x100 */
vuint32_t pioporcap1;
uint32_t r102[2];
uint32_t r120[4]; /* 0x120 */
uint32_t r130[4]; /* 0x130 */
uint32_t r140[4]; /* 0x140 */
-
+
vuint32_t bodctrl; /* 0x150 */
vuint32_t systckcal;
uint32_t r158[2];
vuint32_t irqlatency; /* 0x170 */
vuint32_t nmisrc;
- vuint32_t pintsel0;
- vuint32_t pintsel1;
+ vuint32_t pintsel[8];
- vuint32_t pintsel2; /* 0x180 */
- vuint32_t pintsel3;
- vuint32_t pintsel4;
- vuint32_t pintsel5;
-
- vuint32_t pintsel6; /* 0x190 */
- vuint32_t pintsel7;
- vuint32_t usbclkctrl;
+ vuint32_t usbclkctrl; /* 0x198 */
vuint32_t usbclkst;
uint32_t r1a0[6*4]; /* 0x1a0 */
uint32_t r240[12 * 4]; /* 0x240 */
uint32_t r300[15 * 4]; /* 0x300 */
-
+
uint32_t r3f0; /* 0x3f0 */
vuint32_t device_id;
};
extern struct lpc_scb lpc_scb;
+#define lpc_scb (*(struct lpc_scb *) 0x40048000)
+
+#define LPC_SCB_SYSMEMREMAP_MAP 0
+# define LPC_SCB_SYSMEMREMAP_MAP_BOOT_LOADER 0
+# define LPC_SCB_SYSMEMREMAP_MAP_RAM 1
+# define LPC_SCB_SYSMEMREMAP_MAP_FLASH 2
#define LPC_SCB_PRESETCTRL_SSP0_RST_N 0
#define LPC_SCB_PRESETCTRL_I2C_RST_N 1
#define LPC_SCB_CLKOUTUEN_ENA 0
+#define LPC_SCB_BOD_BODRSTLEV 0
+# define LPC_SCB_BOD_BODRSTLEV_1_46 0
+# define LPC_SCB_BOD_BODRSTLEV_2_06 1
+# define LPC_SCB_BOD_BODRSTLEV_2_35 2
+# define LPC_SCB_BOD_BODRSTLEV_2_63 3
+#define LPC_SCB_BOD_BODINTVAL 2
+# define LPC_SCB_BOD_BODINTVAL_RESERVED 0
+# define LPC_SCB_BOD_BODINTVAL_2_22 1
+# define LPC_SCB_BOD_BODINTVAL_2_52 2
+# define LPC_SCB_BOD_BODINTVAL_2_80 3
+#define LPC_SCB_BOD_BODRSTENA 4
+
#define LPC_SCB_PDRUNCFG_IRCOUT_PD 0
#define LPC_SCB_PDRUNCFG_IRC_PD 1
#define LPC_SCB_PDRUNCFG_FLASH_PD 2
};
extern struct lpc_flash lpc_flash;
+#define lpc_flash (*(struct lpc_flash *) 0x4003c000)
struct lpc_gpio_pin {
+ vuint32_t isel; /* 0x00 */
+ vuint32_t ienr;
+ vuint32_t sienr;
+ vuint32_t cienr;
+
+ vuint32_t ienf; /* 0x10 */
+ vuint32_t sienf;
+ vuint32_t cienf;
+ vuint32_t rise;
+
+ vuint32_t fall; /* 0x20 */
+ vuint32_t ist;
};
extern struct lpc_gpio_pin lpc_gpio_pin;
+#define lpc_gpio_pin (*(struct lpc_gpio_pin *) 0x4004c000)
struct lpc_gpio_group0 {
};
vuint32_t word[0x40]; /* 0x1000 */
uint8_t r1100[0x2000 - 0x1100];
-
+
vuint32_t dir[2]; /* 0x2000 */
uint8_t r2008[0x2080 - 0x2008];
};
extern struct lpc_gpio lpc_gpio;
+#define lpc_gpio (*(struct lpc_gpio *) 0x50000000)
struct lpc_systick {
uint8_t r0000[0x10]; /* 0x0000 */
};
extern struct lpc_systick lpc_systick;
+#define lpc_systick (*(struct lpc_systick *) 0xe000e000)
#define LPC_SYSTICK_CSR_ENABLE 0
#define LPC_SYSTICK_CSR_TICKINT 1
};
extern struct lpc_usart lpc_usart;
+#define lpc_usart (*(struct lpc_usart *) 0x40008000)
#define LPC_USART_IER_RBRINTEN 0
#define LPC_USART_IER_THREINTEN 1
vuint32_t introuting;
uint32_t r30;
vuint32_t eptoggle;
-} lpc_usb;
+};
extern struct lpc_usb lpc_usb;
+#define lpc_usb (*(struct lpc_usb *) 0x40080000)
#define LPC_USB_DEVCMDSTAT_DEV_ADDR 0
#define LPC_USB_DEVCMDSTAT_DEV_ADDR_MASK 0x7f
vuint32_t reserved_0c;
struct lpc_usb_epn epn[4];
};
+#define lpc_usb_endpoint (*(struct lpc_usb_endpoint *) 0x20004700)
/* Assigned in registers.ld to point at the base
* of USB ram
*/
extern uint8_t lpc_usb_sram[];
+#define lpc_usb_sram ((uint8_t*) 0x20004000)
#define LPC_USB_EP_ACTIVE 31
#define LPC_USB_EP_DISABLED 30
};
extern struct lpc_nvic lpc_nvic;
+#define lpc_nvic (*(struct lpc_nvic *) 0xe000e100)
static inline void
lpc_nvic_set_enable(int irq) {
- lpc_nvic.iser |= (1 << irq);
+ lpc_nvic.iser = (1 << irq);
}
static inline void
lpc_nvic_clear_enable(int irq) {
- lpc_nvic.icer |= (1 << irq);
+ lpc_nvic.icer = (1 << irq);
}
static inline int
return (lpc_nvic.iser >> irq) & 1;
}
-
+
static inline void
lpc_nvic_set_pending(int irq) {
lpc_nvic.ispr = (1 << irq);
};
extern struct arm_scb arm_scb;
+#define arm_scb (*(struct arm_scb *) 0xe000ed00)
+
+struct lpc_ssp {
+ vuint32_t cr0; /* 0x00 */
+ vuint32_t cr1;
+ vuint32_t dr;
+ vuint32_t sr;
+
+ vuint32_t cpsr; /* 0x10 */
+ vuint32_t imsc;
+ vuint32_t ris;
+ vuint32_t mis;
+
+ vuint32_t icr; /* 0x20 */
+};
+
+extern struct lpc_ssp lpc_ssp0, lpc_ssp1;
+#define lpc_ssp0 (*(struct lpc_ssp *) 0x40040000)
+#define lpc_ssp1 (*(struct lpc_ssp *) 0x40058000)
+
+#define LPC_NUM_SPI 2
+
+#define LPC_SSP_FIFOSIZE 8
+
+#define LPC_SSP_CR0_DSS 0
+#define LPC_SSP_CR0_DSS_4 0x3
+#define LPC_SSP_CR0_DSS_5 0x4
+#define LPC_SSP_CR0_DSS_6 0x5
+#define LPC_SSP_CR0_DSS_7 0x6
+#define LPC_SSP_CR0_DSS_8 0x7
+#define LPC_SSP_CR0_DSS_9 0x8
+#define LPC_SSP_CR0_DSS_10 0x9
+#define LPC_SSP_CR0_DSS_11 0xa
+#define LPC_SSP_CR0_DSS_12 0xb
+#define LPC_SSP_CR0_DSS_13 0xc
+#define LPC_SSP_CR0_DSS_14 0xd
+#define LPC_SSP_CR0_DSS_15 0xe
+#define LPC_SSP_CR0_DSS_16 0xf
+#define LPC_SSP_CR0_FRF 4
+#define LPC_SSP_CR0_FRF_SPI 0
+#define LPC_SSP_CR0_FRF_TI 1
+#define LPC_SSP_CR0_FRF_MICROWIRE 2
+#define LPC_SSP_CR0_CPOL 6
+#define LPC_SSP_CR0_CPOL_LOW 0
+#define LPC_SSP_CR0_CPOL_HIGH 1
+#define LPC_SSP_CR0_CPHA 7
+#define LPC_SSP_CR0_CPHA_FIRST 0
+#define LPC_SSP_CR0_CPHA_SECOND 1
+#define LPC_SSP_CR0_SCR 8
+
+#define LPC_SSP_CR1_LBM 0
+#define LPC_SSP_CR1_SSE 1
+#define LPC_SSP_CR1_MS 2
+#define LPC_SSP_CR1_MS_MASTER 0
+#define LPC_SSP_CR1_MS_SLAVE 1
+#define LPC_SSP_CR1_SOD 3
+
+#define LPC_SSP_SR_TFE 0
+#define LPC_SSP_SR_TNF 1
+#define LPC_SSP_SR_RNE 2
+#define LPC_SSP_SR_RFF 3
+#define LPC_SSP_SR_BSY 4
+
+#define LPC_SSP_IMSC_RORIM 0
+#define LPC_SSP_IMSC_RTIM 1
+#define LPC_SSP_IMSC_RXIM 2
+#define LPC_SSP_IMSC_TXIM 3
+
+#define LPC_SSP_RIS_RORRIS 0
+#define LPC_SSP_RIS_RTRIS 1
+#define LPC_SSP_RIS_RXRIS 2
+#define LPC_SSP_RIS_TXRIS 3
+
+#define LPC_SSP_MIS_RORMIS 0
+#define LPC_SSP_MIS_RTMIS 1
+#define LPC_SSP_MIS_RXMIS 2
+#define LPC_SSP_MIS_TXMIS 3
+
+#define LPC_SSP_ICR_RORIC 0
+#define LPC_SSP_ICR_RTIC 1
+
+struct lpc_adc {
+ vuint32_t cr; /* 0x00 */
+ vuint32_t gdr;
+ uint32_t r08;
+ vuint32_t inten;
+
+ vuint32_t dr[8]; /* 0x10 */
+
+ vuint32_t stat; /* 0x30 */
+};
+
+extern struct lpc_adc lpc_adc;
+#define lpc_adc (*(struct lpc_adc *) 0x4001c000)
+
+#define LPC_ADC_CR_SEL 0
+#define LPC_ADC_CR_CLKDIV 8
+#define LPC_ADC_CR_BURST 16
+#define LPC_ADC_CR_CLKS 17
+#define LPC_ADC_CR_CLKS_11 0
+#define LPC_ADC_CR_CLKS_10 1
+#define LPC_ADC_CR_CLKS_9 2
+#define LPC_ADC_CR_CLKS_8 3
+#define LPC_ADC_CR_CLKS_7 4
+#define LPC_ADC_CR_CLKS_6 5
+#define LPC_ADC_CR_CLKS_5 6
+#define LPC_ADC_CR_CLKS_4 7
+#define LPC_ADC_CR_START 24
+#define LPC_ADC_CR_START_NONE 0
+#define LPC_ADC_CR_START_NOW 1
+
+#define LPC_ADC_GDR_CHN 24
+#define LPC_ADC_GDR_OVERRUN 30
+#define LPC_ADC_GDR_DONE 31
+
+#define LPC_ADC_INTEN_ADINTEN 0
+#define LPC_ADC_INTEN_ADGINTEN 8
+
+#define LPC_ADC_STAT_DONE 0
+#define LPC_ADC_STAT_OVERRUN 8
+#define LPC_ADC_STAT_ADINT 16
+
+struct lpc_ct16b {
+ vuint32_t ir; /* 0x00 */
+ vuint32_t tcr;
+ vuint32_t tc;
+ vuint32_t pr;
+
+ vuint32_t pc; /* 0x10 */
+ vuint32_t mcr;
+ vuint32_t mr[4]; /* 0x18 */
+ vuint32_t ccr; /* 0x28 */
+ vuint32_t cr0;
+
+ vuint32_t cr1_0; /* 0x30 (only for ct16b0 */
+ vuint32_t cr1_1; /* 0x34 (only for ct16b1 */
+ uint32_t r38;
+ vuint32_t emr;
+
+ uint8_t r40[0x70 - 0x40];
+
+ vuint32_t ctcr; /* 0x70 */
+ vuint32_t pwmc;
+};
+
+extern struct lpc_ct16b lpc_ct16b0, lpc_ct16b1;
+#define lpc_ct16b0 (*(struct lpc_ct16b *) 0x4000c000)
+#define lpc_ct16b1 (*(struct lpc_ct16b *) 0x40010000)
+
+#define LPC_CT16B_IR_MR0INT 0
+#define LPC_CT16B_IR_MR1INT 1
+#define LPC_CT16B_IR_MR2INT 2
+#define LPC_CT16B_IR_MR3INT 3
+#define LPC_CT16B_IR_CR0INT 4
+#define LPC_CT16B0_IR_CR1INT 6
+#define LPC_CT16B1_IR_CR1INT 5
+
+#define LPC_CT16B_TCR_CEN 0
+#define LPC_CT16B_TCR_CRST 1
+
+#define LPC_CT16B_MCR_MR0I 0
+#define LPC_CT16B_MCR_MR0R 1
+#define LPC_CT16B_MCR_MR0S 2
+#define LPC_CT16B_MCR_MR1I 3
+#define LPC_CT16B_MCR_MR1R 4
+#define LPC_CT16B_MCR_MR1S 5
+#define LPC_CT16B_MCR_MR2I 6
+#define LPC_CT16B_MCR_MR2R 7
+#define LPC_CT16B_MCR_MR2S 8
+#define LPC_CT16B_MCR_MR3I 9
+#define LPC_CT16B_MCR_MR3R 10
+#define LPC_CT16B_MCR_MR3S 11
+
+#define LPC_CT16B_CCR_CAP0RE 0
+#define LPC_CT16B_CCR_CAP0FE 1
+#define LPC_CT16B_CCR_CAP0I 2
+#define LPC_CT16B0_CCR_CAP1RE 6
+#define LPC_CT16B0_CCR_CAP1FE 7
+#define LPC_CT16B0_CCR_CAP1I 8
+#define LPC_CT16B1_CCR_CAP1RE 3
+#define LPC_CT16B1_CCR_CAP1FE 4
+#define LPC_CT16B1_CCR_CAP1I 5
+
+#define LPC_CT16B_EMR_EM0 0
+#define LPC_CT16B_EMR_EM1 1
+#define LPC_CT16B_EMR_EM2 2
+#define LPC_CT16B_EMR_EM3 3
+#define LPC_CT16B_EMR_EMC0 4
+#define LPC_CT16B_EMR_EMC1 6
+#define LPC_CT16B_EMR_EMC2 8
+#define LPC_CT16B_EMR_EMC3 10
+
+#define LPC_CT16B_EMR_EMC_NOTHING 0
+#define LPC_CT16B_EMR_EMC_CLEAR 1
+#define LPC_CT16B_EMR_EMC_SET 2
+#define LPC_CT16B_EMR_EMC_TOGGLE 3
+
+#define LPC_CT16B_CCR_CTM 0
+#define LPC_CT16B_CCR_CTM_TIMER 0
+#define LPC_CT16B_CCR_CTM_COUNTER_RISING 1
+#define LPC_CT16B_CCR_CTM_COUNTER_FALLING 2
+#define LPC_CT16B_CCR_CTM_COUNTER_BOTH 3
+#define LPC_CT16B_CCR_CIS 2
+#define LPC_CT16B_CCR_CIS_CAP0 0
+#define LPC_CT16B0_CCR_CIS_CAP1 2
+#define LPC_CT16B1_CCR_CIS_CAP1 1
+#define LPC_CT16B_CCR_ENCC 4
+#define LPC_CT16B_CCR_SELCC 5
+#define LPC_CT16B_CCR_SELCC_RISING_CAP0 0
+#define LPC_CT16B_CCR_SELCC_FALLING_CAP0 1
+#define LPC_CT16B0_CCR_SELCC_RISING_CAP1 4
+#define LPC_CT16B0_CCR_SELCC_FALLING_CAP1 5
+#define LPC_CT16B1_CCR_SELCC_RISING_CAP1 2
+#define LPC_CT16B1_CCR_SELCC_FALLING_CAP1 3
+#define LPC_CT16B_CCR_
+
+#define LPC_CT16B_PWMC_PWMEN0 0
+#define LPC_CT16B_PWMC_PWMEN1 1
+#define LPC_CT16B_PWMC_PWMEN2 2
+#define LPC_CT16B_PWMC_PWMEN3 3
+
+struct lpc_ct32b {
+ vuint32_t ir; /* 0x00 */
+ vuint32_t tcr;
+ vuint32_t tc;
+ vuint32_t pr;
+
+ vuint32_t pc; /* 0x10 */
+ vuint32_t mcr;
+ vuint32_t mr[4]; /* 0x18 */
+ vuint32_t ccr; /* 0x28 */
+ vuint32_t cr0;
+
+ vuint32_t cr1_0; /* 0x30 (only for ct32b0 */
+ vuint32_t cr1_1; /* 0x34 (only for ct32b1 */
+ uint32_t r38;
+ vuint32_t emr;
+
+ uint32_t r40[12];
+
+ vuint32_t ctcr; /* 0x70 */
+ vuint32_t pwmc;
+};
+
+extern struct lpc_ct32b lpc_ct32b0, lpc_ct32b1;
+#define lpc_ct32b0 (*(struct lpc_ct32b *) 0x40014000)
+#define lpc_ct32b1 (*(struct lpc_ct32b *) 0x40018000)
+
+#define LPC_CT32B_TCR_CEN 0
+#define LPC_CT32B_TCR_CRST 1
+
+#define LPC_CT32B_MCR_MR0R 1
+
+#define LPC_CT32B_PWMC_PWMEN0 0
+#define LPC_CT32B_PWMC_PWMEN1 1
+#define LPC_CT32B_PWMC_PWMEN2 2
+#define LPC_CT32B_PWMC_PWMEN3 3
+
+#define LPC_CT32B_EMR_EMC0 4
+#define LPC_CT32B_EMR_EMC1 6
+#define LPC_CT32B_EMR_EMC2 8
+#define LPC_CT32B_EMR_EMC3 10
+
+#define LPC_CT32B_EMR_EMC_NOTHING 0
+#define LPC_CT32B_EMR_EMC_CLEAR 1
+#define LPC_CT32B_EMR_EMC_SET 2
+#define LPC_CT32B_EMR_EMC_TOGGLE 3
+
+#define isr_decl(name) \
+ void lpc_ ## name ## _isr(void)
+
+isr_decl(halt);
+isr_decl(ignore);
+
+isr_decl(nmi);
+isr_decl(hardfault);
+isr_decl(memmanage);
+isr_decl(busfault);
+isr_decl(usagefault);
+isr_decl(svc);
+isr_decl(debugmon);
+isr_decl(pendsv);
+isr_decl(systick);
+
+isr_decl(pin_int0); /* IRQ0 */
+isr_decl(pin_int1);
+isr_decl(pin_int2);
+isr_decl(pin_int3);
+isr_decl(pin_int4); /* IRQ4 */
+isr_decl(pin_int5);
+isr_decl(pin_int6);
+isr_decl(pin_int7);
+
+isr_decl(gint0); /* IRQ8 */
+isr_decl(gint1);
+isr_decl(ssp1);
+isr_decl(i2c);
+
+isr_decl(ct16b0); /* IRQ16 */
+isr_decl(ct16b1);
+isr_decl(ct32b0);
+isr_decl(ct32b1);
+isr_decl(ssp0); /* IRQ20 */
+isr_decl(usart);
+isr_decl(usb_irq);
+isr_decl(usb_fiq);
+
+isr_decl(adc); /* IRQ24 */
+isr_decl(wwdt);
+isr_decl(bod);
+isr_decl(flash);
+
+isr_decl(usb_wakeup);
#endif /* _LPC_H_ */
projects / fw / altos / blobdiff