altos/easymega-v3.0: Switch to STM32F103

[fw/altos] / src / easymega-v3.0 / flash-loader / ao_pins.h

diff --git a/src/easymega-v3.0/flash-loader/ao_pins.h b/src/easymega-v3.0/flash-loader/ao_pins.h
index 324b0eb9d406c5342b73e63dfe214b02ecbf2077..c60f620762b9cec061ae6b6a21484e77628b5e61 100644 (file)
--- a/src/easymega-v3.0/flash-loader/ao_pins.h
+++ b/src/easymega-v3.0/flash-loader/ao_pins.h
@@ -19,8 +19,34 @@
 #ifndef _AO_PINS_H_
 #define _AO_PINS_H_
 
-/* External crystal at 16MHz */
-#define AO_HSE         16000000
+/* 16MHz crystal */
+
+#define AO_HSE         1
+#define AO_HSE_BYPASS  0
+
+#define AO_SYSCLK      72000000
+#define AO_HCLK                72000000
+#define AO_APB1CLK     36000000
+#define AO_APB2CLK     72000000
+#define AO_ADCCLK      12000000
+
+/* PLLMUL is 9, PLLXTPRE (pre divider) is 2, so the
+ * overall PLLCLK is 16 * 9/2 = 72MHz (used as SYSCLK)
+ *
+ * HCLK is SYSCLK / 1 (HPRE_DIV) = 72MHz (72MHz max)
+ * USB is PLLCLK / 1.5 (USBPRE)= 48MHz (must be 48MHz)
+ * APB2 is HCLK / 1 (PPRE2_DIV) = 72MHz (72MHz max)
+ * APB1 is HCLK / 2 (PPRE1_DIV) = 36MHz (36MHz max)
+ * ADC is APB2 / 6 (ADCPRE) = 12MHz (14MHz max)
+ */
+
+#define AO_RCC_CFGR_USBPRE     STM_RCC_CFGR_USBPRE_1_5
+#define AO_RCC_CFGR_PLLMUL     STM_RCC_CFGR_PLLMUL_9
+#define AO_RCC_CFGR_PLLXTPRE   STM_RCC_CFGR_PLLXTPRE_2
+#define AO_RCC_CFGR_PPRE2_DIV  STM_RCC_CFGR_PPRE2_DIV_1
+#define AO_RCC_CFGR_PPRE1_DIV  STM_RCC_CFGR_PPRE1_DIV_2
+#define AO_RCC_CFGR_HPRE_DIV   STM_RCC_CFGR_HPRE_DIV_1
+#define AO_RCC_CFGR_ADCPRE     STM_RCC_CFGR_ADCPRE_6
 
 #include <ao_flash_stm_pins.h>
 
@@ -32,4 +58,8 @@
 #define AO_BOOT_APPLICATION_VALUE      1
 #define AO_BOOT_APPLICATION_MODE       AO_EXTI_MODE_PULL_UP
 
+#define HAS_USB_PULLUP 1
+#define AO_USB_PULLUP_PORT     (&stm_gpioa)
+#define AO_USB_PULLUP_PIN      8
+
 #endif /* _AO_PINS_H_ */